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Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands */ class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def *(t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def *(t: UInt) = self * t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros | ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def *(t: SInt) = self * t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros | ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid || output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def *(t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def *(t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }
module MacUnit_3( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [19:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54] assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }
module AsyncResetSynchronizerShiftReg_w1_d3_i0_155( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_267 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands */ class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def *(t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def *(t: UInt) = self * t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros | ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def *(t: SInt) = self * t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros | ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid || output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def *(t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def *(t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }
module MacUnit_175( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File issue-unit-age-ordered.scala: //****************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Issue Logic //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v4.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util.Str import boom.v4.common._ class IssueUnitCollapsing( params: IssueParams, numWakeupPorts: Int) (implicit p: Parameters) extends IssueUnit(params, numWakeupPorts) { //------------------------------------------------------------- // Set up the dispatch uops // special case "storing" 2 uops within one issue slot. val dis_uops = Array.fill(dispatchWidth) {Wire(new MicroOp())} for (w <- 0 until dispatchWidth) { dis_uops(w) := io.dis_uops(w).bits dis_uops(w).iw_issued := false.B dis_uops(w).iw_issued_partial_agen := false.B dis_uops(w).iw_issued_partial_dgen := false.B dis_uops(w).iw_p1_bypass_hint := false.B dis_uops(w).iw_p2_bypass_hint := false.B dis_uops(w).iw_p3_bypass_hint := false.B // Handle wakeups on dispatch val prs1_matches = io.wakeup_ports.map { wu => wu.bits.uop.pdst === io.dis_uops(w).bits.prs1 } val prs2_matches = io.wakeup_ports.map { wu => wu.bits.uop.pdst === io.dis_uops(w).bits.prs2 } val prs3_matches = io.wakeup_ports.map { wu => wu.bits.uop.pdst === io.dis_uops(w).bits.prs3 } val prs1_wakeups = (io.wakeup_ports zip prs1_matches).map { case (wu,m) => wu.valid && m } val prs2_wakeups = (io.wakeup_ports zip prs2_matches).map { case (wu,m) => wu.valid && m } val prs3_wakeups = (io.wakeup_ports zip prs3_matches).map { case (wu,m) => wu.valid && m } val prs1_rebusys = (io.wakeup_ports zip prs1_matches).map { case (wu,m) => wu.bits.rebusy && m } val prs2_rebusys = (io.wakeup_ports zip prs2_matches).map { case (wu,m) => wu.bits.rebusy && m } val bypassables = io.wakeup_ports.map { wu => wu.bits.bypassable } val speculative_masks = io.wakeup_ports.map { wu => wu.bits.speculative_mask } when (prs1_wakeups.reduce(_||_)) { dis_uops(w).prs1_busy := false.B dis_uops(w).iw_p1_speculative_child := Mux1H(prs1_wakeups, speculative_masks) dis_uops(w).iw_p1_bypass_hint := Mux1H(prs1_wakeups, bypassables) } when (prs1_rebusys.reduce(_||_) || ((io.child_rebusys & io.dis_uops(w).bits.iw_p1_speculative_child) =/= 0.U)) { dis_uops(w).prs1_busy := io.dis_uops(w).bits.lrs1_rtype === RT_FIX } when (prs2_wakeups.reduce(_||_)) { dis_uops(w).prs2_busy := false.B dis_uops(w).iw_p2_speculative_child := Mux1H(prs2_wakeups, speculative_masks) dis_uops(w).iw_p2_bypass_hint := Mux1H(prs2_wakeups, bypassables) } when (prs2_rebusys.reduce(_||_) || ((io.child_rebusys & io.dis_uops(w).bits.iw_p2_speculative_child) =/= 0.U)) { dis_uops(w).prs2_busy := io.dis_uops(w).bits.lrs2_rtype === RT_FIX } when (prs3_wakeups.reduce(_||_)) { dis_uops(w).prs3_busy := false.B dis_uops(w).iw_p3_bypass_hint := Mux1H(prs3_wakeups, bypassables) } when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === io.dis_uops(w).bits.ppred) { dis_uops(w).ppred_busy := false.B } if (iqType == IQ_UNQ) { when (io.dis_uops(w).bits.fu_code(FC_I2F)) { dis_uops(w).prs2 := Cat(io.dis_uops(w).bits.fp_rm, io.dis_uops(w).bits.fp_typ) } when (io.dis_uops(w).bits.is_sfence) { dis_uops(w).pimm := io.dis_uops(w).bits.mem_size } } if (iqType == IQ_MEM) { // For store addr gen for FP, rs2 is the FP register, and we don't wait for that here when (io.dis_uops(w).bits.uses_stq && io.dis_uops(w).bits.lrs2_rtype === RT_FLT) { dis_uops(w).lrs2_rtype := RT_X dis_uops(w).prs2_busy := false.B } dis_uops(w).prs3_busy := false.B } else if (iqType == IQ_FP) { // FP "StoreAddrGen" is really storeDataGen, and rs1 is the integer address register when (io.dis_uops(w).bits.uses_stq) { dis_uops(w).lrs1_rtype := RT_X dis_uops(w).prs1_busy := false.B } } if (iqType != IQ_ALU) { assert(!(io.dis_uops(w).bits.ppred_busy && io.dis_uops(w).valid)) dis_uops(w).ppred_busy := false.B } } //------------------------------------------------------------- // Issue Table val slots = (0 until numIssueSlots) map { w => Module(new IssueSlot(numWakeupPorts, iqType == IQ_MEM, iqType == IQ_FP)) } val issue_slots = VecInit(slots.map(_.io)) for (i <- 0 until numIssueSlots) { issue_slots(i).wakeup_ports := io.wakeup_ports issue_slots(i).pred_wakeup_port := io.pred_wakeup_port issue_slots(i).child_rebusys := io.child_rebusys issue_slots(i).squash_grant := io.squash_grant issue_slots(i).brupdate := io.brupdate issue_slots(i).kill := io.flush_pipeline } for (w <- 0 until issueWidth) { io.iss_uops(w).valid := false.B } //------------------------------------------------------------- assert (PopCount(issue_slots.map(s => s.grant)) <= issueWidth.U, "[issue] window giving out too many grants.") //------------------------------------------------------------- // Figure out how much to shift entries by // Slow slots only shift 1 per cycle, these reduce critical path val nSlowSlots = params.numSlowEntries // Fast slots can shift up to dispatchWidth per cycle, so they can handle full dispatch throughput val nFastSlots = numIssueSlots - nSlowSlots require (nFastSlots >= dispatchWidth) require (nFastSlots <= numIssueSlots) val vacants = issue_slots.map(s => !(s.valid)) ++ io.dis_uops.map(_.valid).map(!_.asBool) val shamts_oh = Wire(Vec(numIssueSlots+dispatchWidth, UInt(width=dispatchWidth.W))) // track how many to shift up this entry by by counting previous vacant spots def SaturatingCounterOH(count_oh:UInt, inc: Bool, max: Int): UInt = { val next = Wire(UInt(width=max.W)) next := count_oh when (count_oh === 0.U && inc) { next := 1.U } .elsewhen (!count_oh(max-1) && inc) { next := (count_oh << 1.U) } next } shamts_oh(0) := 0.U for (i <- 1 until numIssueSlots + dispatchWidth) { val shift = if (i < nSlowSlots) (dispatchWidth min 1 + (i * (dispatchWidth-1)/nSlowSlots).toInt) else dispatchWidth if (dispatchWidth == 1 || shift == 1) { shamts_oh(i) := vacants.take(i).reduce(_||_) } else { shamts_oh(i) := SaturatingCounterOH(shamts_oh(i-1), vacants(i-1), shift) } } //------------------------------------------------------------- // which entries' uops will still be next cycle? (not being issued and vacated) val will_be_valid = (0 until numIssueSlots).map(i => issue_slots(i).will_be_valid) ++ (0 until dispatchWidth).map(i => io.dis_uops(i).valid && !dis_uops(i).exception && !dis_uops(i).is_fence && !dis_uops(i).is_fencei) val uops = issue_slots.map(s=>s.out_uop) ++ dis_uops.map(s=>s) for (i <- 0 until numIssueSlots) { issue_slots(i).in_uop.valid := false.B issue_slots(i).in_uop.bits := uops(i+1) for (j <- 1 to dispatchWidth by 1) { when (shamts_oh(i+j) === (1 << (j-1)).U) { issue_slots(i).in_uop.valid := will_be_valid(i+j) issue_slots(i).in_uop.bits := uops(i+j) } } issue_slots(i).clear := shamts_oh(i) =/= 0.U } //------------------------------------------------------------- // Dispatch/Entry Logic // did we find a spot to slide the new dispatched uops into? // Only look at the fast slots to determine readiness to dispatch. // Slow slot do not compact fast enough to make this calculation valid val is_available = Reg(Vec(nFastSlots, Bool())) is_available := VecInit((nSlowSlots until numIssueSlots).map(i => (!issue_slots(i).will_be_valid || issue_slots(i).clear) && !(issue_slots(i).in_uop.valid))) for (w <- 0 until dispatchWidth) { io.dis_uops(w).ready := RegNext(PopCount(is_available) > w.U(log2Ceil(nFastSlots).W) + PopCount(io.dis_uops.map(_.fire))) // io.dis_uops(w).ready := RegNext(PopCount(will_be_available) > w.U) assert (!io.dis_uops(w).ready || (shamts_oh(w+numIssueSlots) >> w) =/= 0.U) } //------------------------------------------------------------- // Issue Select Logic val requests = issue_slots.map(s => s.request) val port_issued = Array.fill(issueWidth){Bool()} for (w <- 0 until issueWidth) { port_issued(w) = false.B } val iss_select_mask = Array.ofDim[Boolean](issueWidth, numIssueSlots) if (params.useFullIssueSel) { for (w <- 0 until issueWidth) { for (i <- 0 until numIssueSlots) { iss_select_mask(w)(i) = true } } } else { for (w <- 0 until issueWidth) { for (i <- 0 until numIssueSlots) { iss_select_mask(w)(i) = (w % 2) == (i % 2) } iss_select_mask(w)(0) = true } } val iss_uops = Wire(Vec(issueWidth, Valid(new MicroOp))) for (w <- 0 until issueWidth) { iss_uops(w).valid := false.B iss_uops(w).bits := DontCare } for (i <- 0 until numIssueSlots) { issue_slots(i).grant := false.B var uop_issued = false.B for (w <- 0 until issueWidth) { val fu_code_match = (issue_slots(i).iss_uop.fu_code zip io.fu_types(w)).map { case (r,c) => r && c } .reduce(_||_) val can_allocate = fu_code_match && iss_select_mask(w)(i).B when (requests(i) && !uop_issued && can_allocate && !port_issued(w)) { issue_slots(i).grant := true.B iss_uops(w).valid := true.B iss_uops(w).bits := issue_slots(i).iss_uop } val was_port_issued_yet = port_issued(w) port_issued(w) = (requests(i) && !uop_issued && can_allocate) | port_issued(w) uop_issued = (requests(i) && can_allocate && !was_port_issued_yet) | uop_issued } } io.iss_uops := iss_uops when (io.squash_grant) { io.iss_uops.map { u => u.valid := false.B } } } File issue-unit.scala: //****************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Issue Logic //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v4.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util.{Str} import boom.v4.common._ import boom.v4.util.{BoolToChar} case class IssueParams( dispatchWidth: Int = 1, issueWidth: Int = 1, numEntries: Int = 8, useFullIssueSel: Boolean = true, numSlowEntries: Int = 0, iqType: Int ) abstract class IssueUnit( val params: IssueParams, val numWakeupPorts: Int )(implicit p: Parameters) extends BoomModule { val numIssueSlots = params.numEntries val issueWidth = params.issueWidth val iqType = params.iqType val dispatchWidth = params.dispatchWidth val io = IO(new Bundle { val dis_uops = Vec(dispatchWidth, Flipped(Decoupled(new MicroOp))) val iss_uops = Output(Vec(issueWidth, Valid(new MicroOp()))) val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new Wakeup))) val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W))) val child_rebusys = Input(UInt(aluWidth.W)) // tell the issue unit what each execution pipeline has in terms of functional units val fu_types = Input(Vec(issueWidth, Vec(FC_SZ, Bool()))) val brupdate = Input(new BrUpdateInfo()) val flush_pipeline = Input(Bool()) val squash_grant = Input(Bool()) val tsc_reg = Input(UInt(xLen.W)) }) //------------------------------------------------------------- def getType: String = if (iqType == IQ_ALU) "alu" else if (iqType == IQ_MEM) "mem" else if (iqType == IQ_FP) " fp" else if (iqType == IQ_UNQ) "unique" else "unknown" } object IssueUnit { def apply(params: IssueParams, numWakeupPorts: Int, useColumnIssueUnit: Boolean, useSingleWideDispatch: Boolean)(implicit p: Parameters): IssueUnit = { if (useColumnIssueUnit) Module(new IssueUnitBanked(params, numWakeupPorts, useSingleWideDispatch)) else Module(new IssueUnitCollapsing(params, numWakeupPorts)) } }
module IssueUnitCollapsing_2( // @[issue-unit-age-ordered.scala:22:7] input clock, // @[issue-unit-age-ordered.scala:22:7] input reset, // @[issue-unit-age-ordered.scala:22:7] output io_dis_uops_0_ready, // @[issue-unit.scala:44:14] input io_dis_uops_0_valid, // @[issue-unit.scala:44:14] input [31:0] io_dis_uops_0_bits_inst, // @[issue-unit.scala:44:14] input [31:0] io_dis_uops_0_bits_debug_inst, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_rvc, // @[issue-unit.scala:44:14] input [39:0] io_dis_uops_0_bits_debug_pc, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iq_type_0, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iq_type_1, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iq_type_2, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iq_type_3, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_0, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_1, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_2, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_3, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_4, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_5, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_6, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_7, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_8, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_9, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iw_issued, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iw_issued_partial_agen, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iw_issued_partial_dgen, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_iw_p1_speculative_child, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_iw_p2_speculative_child, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iw_p1_bypass_hint, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iw_p2_bypass_hint, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iw_p3_bypass_hint, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_dis_col_sel, // @[issue-unit.scala:44:14] input [11:0] io_dis_uops_0_bits_br_mask, // @[issue-unit.scala:44:14] input [3:0] io_dis_uops_0_bits_br_tag, // @[issue-unit.scala:44:14] input [3:0] io_dis_uops_0_bits_br_type, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_sfb, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_fence, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_fencei, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_sfence, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_amo, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_eret, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_sys_pc2epc, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_rocc, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_mov, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_0_bits_ftq_idx, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_edge_inst, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_0_bits_pc_lob, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_taken, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_imm_rename, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_0_bits_imm_sel, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_0_bits_pimm, // @[issue-unit.scala:44:14] input [19:0] io_dis_uops_0_bits_imm_packed, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_op1_sel, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_0_bits_op2_sel, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_ldst, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_wen, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_ren1, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_ren2, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_ren3, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_swap12, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_swap23, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_fromint, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_toint, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_fma, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_div, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_sqrt, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_wflags, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_vec, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_0_bits_rob_idx, // @[issue-unit.scala:44:14] input [3:0] io_dis_uops_0_bits_ldq_idx, // @[issue-unit.scala:44:14] input [3:0] io_dis_uops_0_bits_stq_idx, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_rxq_idx, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_0_bits_pdst, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_0_bits_prs1, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_0_bits_prs2, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_0_bits_prs3, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_0_bits_ppred, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_prs1_busy, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_prs2_busy, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_prs3_busy, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_ppred_busy, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_0_bits_stale_pdst, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_exception, // @[issue-unit.scala:44:14] input [63:0] io_dis_uops_0_bits_exc_cause, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_0_bits_mem_cmd, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_mem_size, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_mem_signed, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_uses_ldq, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_uses_stq, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_unique, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_flush_on_commit, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_0_bits_csr_cmd, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_ldst_is_rs1, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_0_bits_ldst, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_0_bits_lrs1, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_0_bits_lrs2, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_0_bits_lrs3, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_dst_rtype, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_lrs1_rtype, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_lrs2_rtype, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_frs3_en, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fcn_dw, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_0_bits_fcn_op, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_val, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_0_bits_fp_rm, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_fp_typ, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_xcpt_pf_if, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_xcpt_ae_if, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_xcpt_ma_if, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_bp_debug_if, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_bp_xcpt_if, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_0_bits_debug_fsrc, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_0_bits_debug_tsrc, // @[issue-unit.scala:44:14] output io_dis_uops_1_ready, // @[issue-unit.scala:44:14] input io_dis_uops_1_valid, // @[issue-unit.scala:44:14] input [31:0] io_dis_uops_1_bits_inst, // @[issue-unit.scala:44:14] input [31:0] io_dis_uops_1_bits_debug_inst, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_rvc, // @[issue-unit.scala:44:14] input [39:0] io_dis_uops_1_bits_debug_pc, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iq_type_0, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iq_type_1, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iq_type_2, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iq_type_3, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_0, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_1, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_2, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_3, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_4, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_5, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_6, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_7, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_8, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_9, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iw_issued, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iw_issued_partial_agen, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iw_issued_partial_dgen, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_iw_p1_speculative_child, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_iw_p2_speculative_child, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iw_p1_bypass_hint, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iw_p2_bypass_hint, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iw_p3_bypass_hint, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_dis_col_sel, // @[issue-unit.scala:44:14] input [11:0] io_dis_uops_1_bits_br_mask, // @[issue-unit.scala:44:14] input [3:0] io_dis_uops_1_bits_br_tag, // @[issue-unit.scala:44:14] input [3:0] io_dis_uops_1_bits_br_type, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_sfb, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_fence, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_fencei, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_sfence, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_amo, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_eret, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_sys_pc2epc, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_rocc, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_mov, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_1_bits_ftq_idx, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_edge_inst, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_1_bits_pc_lob, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_taken, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_imm_rename, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_1_bits_imm_sel, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_1_bits_pimm, // @[issue-unit.scala:44:14] input [19:0] io_dis_uops_1_bits_imm_packed, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_op1_sel, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_1_bits_op2_sel, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_ldst, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_wen, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_ren1, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_ren2, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_ren3, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_swap12, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_swap23, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_fromint, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_toint, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_fma, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_div, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_sqrt, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_wflags, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_vec, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_1_bits_rob_idx, // @[issue-unit.scala:44:14] input [3:0] io_dis_uops_1_bits_ldq_idx, // @[issue-unit.scala:44:14] input [3:0] io_dis_uops_1_bits_stq_idx, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_rxq_idx, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_1_bits_pdst, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_1_bits_prs1, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_1_bits_prs2, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_1_bits_prs3, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_1_bits_ppred, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_prs1_busy, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_prs2_busy, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_prs3_busy, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_ppred_busy, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_1_bits_stale_pdst, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_exception, // @[issue-unit.scala:44:14] input [63:0] io_dis_uops_1_bits_exc_cause, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_1_bits_mem_cmd, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_mem_size, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_mem_signed, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_uses_ldq, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_uses_stq, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_unique, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_flush_on_commit, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_1_bits_csr_cmd, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_ldst_is_rs1, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_1_bits_ldst, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_1_bits_lrs1, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_1_bits_lrs2, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_1_bits_lrs3, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_dst_rtype, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_lrs1_rtype, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_lrs2_rtype, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_frs3_en, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fcn_dw, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_1_bits_fcn_op, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_val, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_1_bits_fp_rm, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_fp_typ, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_xcpt_pf_if, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_xcpt_ae_if, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_xcpt_ma_if, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_bp_debug_if, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_bp_xcpt_if, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_1_bits_debug_fsrc, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_1_bits_debug_tsrc, // @[issue-unit.scala:44:14] output io_iss_uops_0_valid, // @[issue-unit.scala:44:14] output [31:0] io_iss_uops_0_bits_inst, // @[issue-unit.scala:44:14] output [31:0] io_iss_uops_0_bits_debug_inst, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_rvc, // @[issue-unit.scala:44:14] output [39:0] io_iss_uops_0_bits_debug_pc, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_iq_type_0, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_iq_type_1, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_iq_type_2, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_iq_type_3, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_0, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_1, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_2, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_3, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_4, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_5, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_6, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_7, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_8, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_9, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_iw_issued, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_iw_p1_speculative_child, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_iw_p2_speculative_child, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_iw_p1_bypass_hint, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_iw_p2_bypass_hint, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_iw_p3_bypass_hint, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_dis_col_sel, // @[issue-unit.scala:44:14] output [11:0] io_iss_uops_0_bits_br_mask, // @[issue-unit.scala:44:14] output [3:0] io_iss_uops_0_bits_br_tag, // @[issue-unit.scala:44:14] output [3:0] io_iss_uops_0_bits_br_type, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_sfb, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_fence, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_fencei, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_sfence, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_amo, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_eret, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_sys_pc2epc, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_rocc, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_mov, // @[issue-unit.scala:44:14] output [4:0] io_iss_uops_0_bits_ftq_idx, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_edge_inst, // @[issue-unit.scala:44:14] output [5:0] io_iss_uops_0_bits_pc_lob, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_taken, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_imm_rename, // @[issue-unit.scala:44:14] output [2:0] io_iss_uops_0_bits_imm_sel, // @[issue-unit.scala:44:14] output [4:0] io_iss_uops_0_bits_pimm, // @[issue-unit.scala:44:14] output [19:0] io_iss_uops_0_bits_imm_packed, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_op1_sel, // @[issue-unit.scala:44:14] output [2:0] io_iss_uops_0_bits_op2_sel, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_ldst, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_wen, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_ren1, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_ren2, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_ren3, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_swap12, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_swap23, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_fromint, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_toint, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_fma, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_div, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_sqrt, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_wflags, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_vec, // @[issue-unit.scala:44:14] output [5:0] io_iss_uops_0_bits_rob_idx, // @[issue-unit.scala:44:14] output [3:0] io_iss_uops_0_bits_ldq_idx, // @[issue-unit.scala:44:14] output [3:0] io_iss_uops_0_bits_stq_idx, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_rxq_idx, // @[issue-unit.scala:44:14] output [6:0] io_iss_uops_0_bits_pdst, // @[issue-unit.scala:44:14] output [6:0] io_iss_uops_0_bits_prs1, // @[issue-unit.scala:44:14] output [6:0] io_iss_uops_0_bits_prs2, // @[issue-unit.scala:44:14] output [6:0] io_iss_uops_0_bits_prs3, // @[issue-unit.scala:44:14] output [4:0] io_iss_uops_0_bits_ppred, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_prs1_busy, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_prs2_busy, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_prs3_busy, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_ppred_busy, // @[issue-unit.scala:44:14] output [6:0] io_iss_uops_0_bits_stale_pdst, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_exception, // @[issue-unit.scala:44:14] output [63:0] io_iss_uops_0_bits_exc_cause, // @[issue-unit.scala:44:14] output [4:0] io_iss_uops_0_bits_mem_cmd, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_mem_size, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_mem_signed, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_uses_ldq, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_uses_stq, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_unique, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_flush_on_commit, // @[issue-unit.scala:44:14] output [2:0] io_iss_uops_0_bits_csr_cmd, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_ldst_is_rs1, // @[issue-unit.scala:44:14] output [5:0] io_iss_uops_0_bits_ldst, // @[issue-unit.scala:44:14] output [5:0] io_iss_uops_0_bits_lrs1, // @[issue-unit.scala:44:14] output [5:0] io_iss_uops_0_bits_lrs2, // @[issue-unit.scala:44:14] output [5:0] io_iss_uops_0_bits_lrs3, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_dst_rtype, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_lrs1_rtype, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_lrs2_rtype, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_frs3_en, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fcn_dw, // @[issue-unit.scala:44:14] output [4:0] io_iss_uops_0_bits_fcn_op, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_val, // @[issue-unit.scala:44:14] output [2:0] io_iss_uops_0_bits_fp_rm, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_fp_typ, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_xcpt_pf_if, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_xcpt_ae_if, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_xcpt_ma_if, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_bp_debug_if, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_bp_xcpt_if, // @[issue-unit.scala:44:14] output [2:0] io_iss_uops_0_bits_debug_fsrc, // @[issue-unit.scala:44:14] output [2:0] io_iss_uops_0_bits_debug_tsrc, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_valid, // @[issue-unit.scala:44:14] input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-unit.scala:44:14] input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-unit.scala:44:14] input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-unit.scala:44:14] input [11:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-unit.scala:44:14] input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-unit.scala:44:14] input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_taken, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-unit.scala:44:14] input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-unit.scala:44:14] input [3:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-unit.scala:44:14] input [3:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_exception, // @[issue-unit.scala:44:14] input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_bypassable, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_speculative_mask, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_rebusy, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_valid, // @[issue-unit.scala:44:14] input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-unit.scala:44:14] input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-unit.scala:44:14] input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-unit.scala:44:14] input [11:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-unit.scala:44:14] input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-unit.scala:44:14] input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_taken, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-unit.scala:44:14] input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-unit.scala:44:14] input [3:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-unit.scala:44:14] input [3:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_exception, // @[issue-unit.scala:44:14] input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_valid, // @[issue-unit.scala:44:14] input [31:0] io_wakeup_ports_2_bits_uop_inst, // @[issue-unit.scala:44:14] input [31:0] io_wakeup_ports_2_bits_uop_debug_inst, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_is_rvc, // @[issue-unit.scala:44:14] input [39:0] io_wakeup_ports_2_bits_uop_debug_pc, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_iq_type_0, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_iq_type_1, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_iq_type_2, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_iq_type_3, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fu_code_0, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fu_code_1, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fu_code_2, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fu_code_3, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fu_code_4, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fu_code_5, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fu_code_6, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fu_code_7, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fu_code_8, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fu_code_9, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_iw_issued, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_2_bits_uop_dis_col_sel, // @[issue-unit.scala:44:14] input [11:0] io_wakeup_ports_2_bits_uop_br_mask, // @[issue-unit.scala:44:14] input [3:0] io_wakeup_ports_2_bits_uop_br_tag, // @[issue-unit.scala:44:14] input [3:0] io_wakeup_ports_2_bits_uop_br_type, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_is_sfb, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_is_fence, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_is_fencei, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_is_sfence, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_is_amo, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_is_eret, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_is_sys_pc2epc, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_is_rocc, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_is_mov, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_2_bits_uop_ftq_idx, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_edge_inst, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_2_bits_uop_pc_lob, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_taken, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_imm_rename, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_2_bits_uop_imm_sel, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_2_bits_uop_pimm, // @[issue-unit.scala:44:14] input [19:0] io_wakeup_ports_2_bits_uop_imm_packed, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_2_bits_uop_op1_sel, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_2_bits_uop_op2_sel, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ldst, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wen, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren1, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren2, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren3, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap12, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap23, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fromint, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_toint, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fma, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_div, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wflags, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_vec, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_2_bits_uop_rob_idx, // @[issue-unit.scala:44:14] input [3:0] io_wakeup_ports_2_bits_uop_ldq_idx, // @[issue-unit.scala:44:14] input [3:0] io_wakeup_ports_2_bits_uop_stq_idx, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_2_bits_uop_rxq_idx, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_2_bits_uop_pdst, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_2_bits_uop_prs1, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_2_bits_uop_prs2, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_2_bits_uop_prs3, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_2_bits_uop_ppred, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_prs1_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_prs2_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_prs3_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_ppred_busy, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_2_bits_uop_stale_pdst, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_exception, // @[issue-unit.scala:44:14] input [63:0] io_wakeup_ports_2_bits_uop_exc_cause, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_2_bits_uop_mem_cmd, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_2_bits_uop_mem_size, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_mem_signed, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_uses_ldq, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_uses_stq, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_is_unique, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_flush_on_commit, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_2_bits_uop_csr_cmd, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_ldst_is_rs1, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_2_bits_uop_ldst, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs1, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs2, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs3, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_2_bits_uop_dst_rtype, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_frs3_en, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fcn_dw, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_2_bits_uop_fcn_op, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fp_val, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_2_bits_uop_fp_rm, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_typ, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_xcpt_pf_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_xcpt_ae_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_xcpt_ma_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_bp_debug_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_bp_xcpt_if, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_valid, // @[issue-unit.scala:44:14] input [31:0] io_wakeup_ports_3_bits_uop_inst, // @[issue-unit.scala:44:14] input [31:0] io_wakeup_ports_3_bits_uop_debug_inst, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_is_rvc, // @[issue-unit.scala:44:14] input [39:0] io_wakeup_ports_3_bits_uop_debug_pc, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_iq_type_0, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_iq_type_1, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_iq_type_2, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_iq_type_3, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fu_code_0, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fu_code_1, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fu_code_2, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fu_code_3, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fu_code_4, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fu_code_5, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fu_code_6, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fu_code_7, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fu_code_8, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fu_code_9, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_iw_issued, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_3_bits_uop_dis_col_sel, // @[issue-unit.scala:44:14] input [11:0] io_wakeup_ports_3_bits_uop_br_mask, // @[issue-unit.scala:44:14] input [3:0] io_wakeup_ports_3_bits_uop_br_tag, // @[issue-unit.scala:44:14] input [3:0] io_wakeup_ports_3_bits_uop_br_type, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_is_sfb, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_is_fence, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_is_fencei, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_is_sfence, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_is_amo, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_is_eret, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_is_sys_pc2epc, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_is_rocc, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_is_mov, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_3_bits_uop_ftq_idx, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_edge_inst, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_3_bits_uop_pc_lob, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_taken, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_imm_rename, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_3_bits_uop_imm_sel, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_3_bits_uop_pimm, // @[issue-unit.scala:44:14] input [19:0] io_wakeup_ports_3_bits_uop_imm_packed, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_3_bits_uop_op1_sel, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_3_bits_uop_op2_sel, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ldst, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wen, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren1, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren2, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren3, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap12, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap23, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fromint, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_toint, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fma, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_div, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wflags, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_vec, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_3_bits_uop_rob_idx, // @[issue-unit.scala:44:14] input [3:0] io_wakeup_ports_3_bits_uop_ldq_idx, // @[issue-unit.scala:44:14] input [3:0] io_wakeup_ports_3_bits_uop_stq_idx, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_3_bits_uop_rxq_idx, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_3_bits_uop_pdst, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_3_bits_uop_prs1, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_3_bits_uop_prs2, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_3_bits_uop_prs3, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_3_bits_uop_ppred, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_prs1_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_prs2_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_prs3_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_ppred_busy, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_3_bits_uop_stale_pdst, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_exception, // @[issue-unit.scala:44:14] input [63:0] io_wakeup_ports_3_bits_uop_exc_cause, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_3_bits_uop_mem_cmd, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_3_bits_uop_mem_size, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_mem_signed, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_uses_ldq, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_uses_stq, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_is_unique, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_flush_on_commit, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_3_bits_uop_csr_cmd, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_ldst_is_rs1, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_3_bits_uop_ldst, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs1, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs2, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs3, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_3_bits_uop_dst_rtype, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_frs3_en, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fcn_dw, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_3_bits_uop_fcn_op, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fp_val, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_3_bits_uop_fp_rm, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_typ, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_xcpt_pf_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_xcpt_ae_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_xcpt_ma_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_bp_debug_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_bp_xcpt_if, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc, // @[issue-unit.scala:44:14] input [1:0] io_child_rebusys, // @[issue-unit.scala:44:14] input io_fu_types_0_4, // @[issue-unit.scala:44:14] input io_fu_types_0_8, // @[issue-unit.scala:44:14] input [11:0] io_brupdate_b1_resolve_mask, // @[issue-unit.scala:44:14] input [11:0] io_brupdate_b1_mispredict_mask, // @[issue-unit.scala:44:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-unit.scala:44:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_rvc, // @[issue-unit.scala:44:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iq_type_0, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iq_type_1, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iq_type_2, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iq_type_3, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_0, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_1, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_2, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_3, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_4, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_5, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_6, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_7, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_8, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_9, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iw_issued, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-unit.scala:44:14] input [11:0] io_brupdate_b2_uop_br_mask, // @[issue-unit.scala:44:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-unit.scala:44:14] input [3:0] io_brupdate_b2_uop_br_type, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_sfb, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_fence, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_fencei, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_sfence, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_amo, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_eret, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_rocc, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_mov, // @[issue-unit.scala:44:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_edge_inst, // @[issue-unit.scala:44:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_taken, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_imm_rename, // @[issue-unit.scala:44:14] input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-unit.scala:44:14] input [4:0] io_brupdate_b2_uop_pimm, // @[issue-unit.scala:44:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-unit.scala:44:14] input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-unit.scala:44:14] input [5:0] io_brupdate_b2_uop_rob_idx, // @[issue-unit.scala:44:14] input [3:0] io_brupdate_b2_uop_ldq_idx, // @[issue-unit.scala:44:14] input [3:0] io_brupdate_b2_uop_stq_idx, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-unit.scala:44:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-unit.scala:44:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-unit.scala:44:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-unit.scala:44:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-unit.scala:44:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-unit.scala:44:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_exception, // @[issue-unit.scala:44:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-unit.scala:44:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_mem_signed, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_uses_stq, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_unique, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-unit.scala:44:14] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-unit.scala:44:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-unit.scala:44:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-unit.scala:44:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-unit.scala:44:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_frs3_en, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fcn_dw, // @[issue-unit.scala:44:14] input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_val, // @[issue-unit.scala:44:14] input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-unit.scala:44:14] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-unit.scala:44:14] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-unit.scala:44:14] input io_brupdate_b2_mispredict, // @[issue-unit.scala:44:14] input io_brupdate_b2_taken, // @[issue-unit.scala:44:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-unit.scala:44:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-unit.scala:44:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-unit.scala:44:14] input io_flush_pipeline, // @[issue-unit.scala:44:14] input io_squash_grant, // @[issue-unit.scala:44:14] input [63:0] io_tsc_reg // @[issue-unit.scala:44:14] ); wire issue_slots_11_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire io_dis_uops_0_valid_0 = io_dis_uops_0_valid; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_dis_uops_0_bits_inst_0 = io_dis_uops_0_bits_inst; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_dis_uops_0_bits_debug_inst_0 = io_dis_uops_0_bits_debug_inst; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_rvc_0 = io_dis_uops_0_bits_is_rvc; // @[issue-unit-age-ordered.scala:22:7] wire [39:0] io_dis_uops_0_bits_debug_pc_0 = io_dis_uops_0_bits_debug_pc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iq_type_0_0 = io_dis_uops_0_bits_iq_type_0; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iq_type_1_0 = io_dis_uops_0_bits_iq_type_1; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iq_type_2_0 = io_dis_uops_0_bits_iq_type_2; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iq_type_3_0 = io_dis_uops_0_bits_iq_type_3; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_0_0 = io_dis_uops_0_bits_fu_code_0; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_1_0 = io_dis_uops_0_bits_fu_code_1; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_2_0 = io_dis_uops_0_bits_fu_code_2; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_3_0 = io_dis_uops_0_bits_fu_code_3; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_4_0 = io_dis_uops_0_bits_fu_code_4; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_5_0 = io_dis_uops_0_bits_fu_code_5; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_6_0 = io_dis_uops_0_bits_fu_code_6; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_7_0 = io_dis_uops_0_bits_fu_code_7; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_8_0 = io_dis_uops_0_bits_fu_code_8; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_9_0 = io_dis_uops_0_bits_fu_code_9; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iw_issued_0 = io_dis_uops_0_bits_iw_issued; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iw_issued_partial_agen_0 = io_dis_uops_0_bits_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iw_issued_partial_dgen_0 = io_dis_uops_0_bits_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_iw_p1_speculative_child_0 = io_dis_uops_0_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_iw_p2_speculative_child_0 = io_dis_uops_0_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iw_p1_bypass_hint_0 = io_dis_uops_0_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iw_p2_bypass_hint_0 = io_dis_uops_0_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iw_p3_bypass_hint_0 = io_dis_uops_0_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_dis_col_sel_0 = io_dis_uops_0_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7] wire [11:0] io_dis_uops_0_bits_br_mask_0 = io_dis_uops_0_bits_br_mask; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_dis_uops_0_bits_br_tag_0 = io_dis_uops_0_bits_br_tag; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_dis_uops_0_bits_br_type_0 = io_dis_uops_0_bits_br_type; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_sfb_0 = io_dis_uops_0_bits_is_sfb; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_fence_0 = io_dis_uops_0_bits_is_fence; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_fencei_0 = io_dis_uops_0_bits_is_fencei; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_sfence_0 = io_dis_uops_0_bits_is_sfence; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_amo_0 = io_dis_uops_0_bits_is_amo; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_eret_0 = io_dis_uops_0_bits_is_eret; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_sys_pc2epc_0 = io_dis_uops_0_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_rocc_0 = io_dis_uops_0_bits_is_rocc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_mov_0 = io_dis_uops_0_bits_is_mov; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_0_bits_ftq_idx_0 = io_dis_uops_0_bits_ftq_idx; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_edge_inst_0 = io_dis_uops_0_bits_edge_inst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_0_bits_pc_lob_0 = io_dis_uops_0_bits_pc_lob; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_taken_0 = io_dis_uops_0_bits_taken; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_imm_rename_0 = io_dis_uops_0_bits_imm_rename; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_0_bits_imm_sel_0 = io_dis_uops_0_bits_imm_sel; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_0_bits_pimm_0 = io_dis_uops_0_bits_pimm; // @[issue-unit-age-ordered.scala:22:7] wire [19:0] io_dis_uops_0_bits_imm_packed_0 = io_dis_uops_0_bits_imm_packed; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_op1_sel_0 = io_dis_uops_0_bits_op1_sel; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_0_bits_op2_sel_0 = io_dis_uops_0_bits_op2_sel; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_ldst_0 = io_dis_uops_0_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_wen_0 = io_dis_uops_0_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_ren1_0 = io_dis_uops_0_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_ren2_0 = io_dis_uops_0_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_ren3_0 = io_dis_uops_0_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_swap12_0 = io_dis_uops_0_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_swap23_0 = io_dis_uops_0_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_fp_ctrl_typeTagIn_0 = io_dis_uops_0_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_fp_ctrl_typeTagOut_0 = io_dis_uops_0_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_fromint_0 = io_dis_uops_0_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_toint_0 = io_dis_uops_0_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_fastpipe_0 = io_dis_uops_0_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_fma_0 = io_dis_uops_0_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_div_0 = io_dis_uops_0_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_sqrt_0 = io_dis_uops_0_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_wflags_0 = io_dis_uops_0_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_vec_0 = io_dis_uops_0_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_0_bits_rob_idx_0 = io_dis_uops_0_bits_rob_idx; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_dis_uops_0_bits_ldq_idx_0 = io_dis_uops_0_bits_ldq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_dis_uops_0_bits_stq_idx_0 = io_dis_uops_0_bits_stq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_rxq_idx_0 = io_dis_uops_0_bits_rxq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_0_bits_pdst_0 = io_dis_uops_0_bits_pdst; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_0_bits_prs1_0 = io_dis_uops_0_bits_prs1; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_0_bits_prs2_0 = io_dis_uops_0_bits_prs2; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_0_bits_prs3_0 = io_dis_uops_0_bits_prs3; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_0_bits_ppred_0 = io_dis_uops_0_bits_ppred; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_prs1_busy_0 = io_dis_uops_0_bits_prs1_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_prs2_busy_0 = io_dis_uops_0_bits_prs2_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_prs3_busy_0 = io_dis_uops_0_bits_prs3_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_ppred_busy_0 = io_dis_uops_0_bits_ppred_busy; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_0_bits_stale_pdst_0 = io_dis_uops_0_bits_stale_pdst; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_exception_0 = io_dis_uops_0_bits_exception; // @[issue-unit-age-ordered.scala:22:7] wire [63:0] io_dis_uops_0_bits_exc_cause_0 = io_dis_uops_0_bits_exc_cause; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_0_bits_mem_cmd_0 = io_dis_uops_0_bits_mem_cmd; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_mem_size_0 = io_dis_uops_0_bits_mem_size; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_mem_signed_0 = io_dis_uops_0_bits_mem_signed; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_uses_ldq_0 = io_dis_uops_0_bits_uses_ldq; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_uses_stq_0 = io_dis_uops_0_bits_uses_stq; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_unique_0 = io_dis_uops_0_bits_is_unique; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_flush_on_commit_0 = io_dis_uops_0_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_0_bits_csr_cmd_0 = io_dis_uops_0_bits_csr_cmd; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_ldst_is_rs1_0 = io_dis_uops_0_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_0_bits_ldst_0 = io_dis_uops_0_bits_ldst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_0_bits_lrs1_0 = io_dis_uops_0_bits_lrs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_0_bits_lrs2_0 = io_dis_uops_0_bits_lrs2; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_0_bits_lrs3_0 = io_dis_uops_0_bits_lrs3; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_dst_rtype_0 = io_dis_uops_0_bits_dst_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_lrs1_rtype_0 = io_dis_uops_0_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_lrs2_rtype_0 = io_dis_uops_0_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_frs3_en_0 = io_dis_uops_0_bits_frs3_en; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fcn_dw_0 = io_dis_uops_0_bits_fcn_dw; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_0_bits_fcn_op_0 = io_dis_uops_0_bits_fcn_op; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_val_0 = io_dis_uops_0_bits_fp_val; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_0_bits_fp_rm_0 = io_dis_uops_0_bits_fp_rm; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_fp_typ_0 = io_dis_uops_0_bits_fp_typ; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_xcpt_pf_if_0 = io_dis_uops_0_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_xcpt_ae_if_0 = io_dis_uops_0_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_xcpt_ma_if_0 = io_dis_uops_0_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_bp_debug_if_0 = io_dis_uops_0_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_bp_xcpt_if_0 = io_dis_uops_0_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_0_bits_debug_fsrc_0 = io_dis_uops_0_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_0_bits_debug_tsrc_0 = io_dis_uops_0_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_valid_0 = io_dis_uops_1_valid; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_dis_uops_1_bits_inst_0 = io_dis_uops_1_bits_inst; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_dis_uops_1_bits_debug_inst_0 = io_dis_uops_1_bits_debug_inst; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_rvc_0 = io_dis_uops_1_bits_is_rvc; // @[issue-unit-age-ordered.scala:22:7] wire [39:0] io_dis_uops_1_bits_debug_pc_0 = io_dis_uops_1_bits_debug_pc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iq_type_0_0 = io_dis_uops_1_bits_iq_type_0; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iq_type_1_0 = io_dis_uops_1_bits_iq_type_1; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iq_type_2_0 = io_dis_uops_1_bits_iq_type_2; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iq_type_3_0 = io_dis_uops_1_bits_iq_type_3; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_0_0 = io_dis_uops_1_bits_fu_code_0; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_1_0 = io_dis_uops_1_bits_fu_code_1; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_2_0 = io_dis_uops_1_bits_fu_code_2; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_3_0 = io_dis_uops_1_bits_fu_code_3; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_4_0 = io_dis_uops_1_bits_fu_code_4; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_5_0 = io_dis_uops_1_bits_fu_code_5; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_6_0 = io_dis_uops_1_bits_fu_code_6; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_7_0 = io_dis_uops_1_bits_fu_code_7; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_8_0 = io_dis_uops_1_bits_fu_code_8; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_9_0 = io_dis_uops_1_bits_fu_code_9; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iw_issued_0 = io_dis_uops_1_bits_iw_issued; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iw_issued_partial_agen_0 = io_dis_uops_1_bits_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iw_issued_partial_dgen_0 = io_dis_uops_1_bits_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_iw_p1_speculative_child_0 = io_dis_uops_1_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_iw_p2_speculative_child_0 = io_dis_uops_1_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iw_p1_bypass_hint_0 = io_dis_uops_1_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iw_p2_bypass_hint_0 = io_dis_uops_1_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iw_p3_bypass_hint_0 = io_dis_uops_1_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_dis_col_sel_0 = io_dis_uops_1_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7] wire [11:0] io_dis_uops_1_bits_br_mask_0 = io_dis_uops_1_bits_br_mask; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_dis_uops_1_bits_br_tag_0 = io_dis_uops_1_bits_br_tag; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_dis_uops_1_bits_br_type_0 = io_dis_uops_1_bits_br_type; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_sfb_0 = io_dis_uops_1_bits_is_sfb; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_fence_0 = io_dis_uops_1_bits_is_fence; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_fencei_0 = io_dis_uops_1_bits_is_fencei; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_sfence_0 = io_dis_uops_1_bits_is_sfence; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_amo_0 = io_dis_uops_1_bits_is_amo; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_eret_0 = io_dis_uops_1_bits_is_eret; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_sys_pc2epc_0 = io_dis_uops_1_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_rocc_0 = io_dis_uops_1_bits_is_rocc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_mov_0 = io_dis_uops_1_bits_is_mov; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_1_bits_ftq_idx_0 = io_dis_uops_1_bits_ftq_idx; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_edge_inst_0 = io_dis_uops_1_bits_edge_inst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_1_bits_pc_lob_0 = io_dis_uops_1_bits_pc_lob; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_taken_0 = io_dis_uops_1_bits_taken; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_imm_rename_0 = io_dis_uops_1_bits_imm_rename; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_1_bits_imm_sel_0 = io_dis_uops_1_bits_imm_sel; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_1_bits_pimm_0 = io_dis_uops_1_bits_pimm; // @[issue-unit-age-ordered.scala:22:7] wire [19:0] io_dis_uops_1_bits_imm_packed_0 = io_dis_uops_1_bits_imm_packed; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_op1_sel_0 = io_dis_uops_1_bits_op1_sel; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_1_bits_op2_sel_0 = io_dis_uops_1_bits_op2_sel; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_ldst_0 = io_dis_uops_1_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_wen_0 = io_dis_uops_1_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_ren1_0 = io_dis_uops_1_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_ren2_0 = io_dis_uops_1_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_ren3_0 = io_dis_uops_1_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_swap12_0 = io_dis_uops_1_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_swap23_0 = io_dis_uops_1_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_fp_ctrl_typeTagIn_0 = io_dis_uops_1_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_fp_ctrl_typeTagOut_0 = io_dis_uops_1_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_fromint_0 = io_dis_uops_1_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_toint_0 = io_dis_uops_1_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_fastpipe_0 = io_dis_uops_1_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_fma_0 = io_dis_uops_1_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_div_0 = io_dis_uops_1_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_sqrt_0 = io_dis_uops_1_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_wflags_0 = io_dis_uops_1_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_vec_0 = io_dis_uops_1_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_1_bits_rob_idx_0 = io_dis_uops_1_bits_rob_idx; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_dis_uops_1_bits_ldq_idx_0 = io_dis_uops_1_bits_ldq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_dis_uops_1_bits_stq_idx_0 = io_dis_uops_1_bits_stq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_rxq_idx_0 = io_dis_uops_1_bits_rxq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_1_bits_pdst_0 = io_dis_uops_1_bits_pdst; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_1_bits_prs1_0 = io_dis_uops_1_bits_prs1; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_1_bits_prs2_0 = io_dis_uops_1_bits_prs2; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_1_bits_prs3_0 = io_dis_uops_1_bits_prs3; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_1_bits_ppred_0 = io_dis_uops_1_bits_ppred; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_prs1_busy_0 = io_dis_uops_1_bits_prs1_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_prs2_busy_0 = io_dis_uops_1_bits_prs2_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_prs3_busy_0 = io_dis_uops_1_bits_prs3_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_ppred_busy_0 = io_dis_uops_1_bits_ppred_busy; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_1_bits_stale_pdst_0 = io_dis_uops_1_bits_stale_pdst; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_exception_0 = io_dis_uops_1_bits_exception; // @[issue-unit-age-ordered.scala:22:7] wire [63:0] io_dis_uops_1_bits_exc_cause_0 = io_dis_uops_1_bits_exc_cause; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_1_bits_mem_cmd_0 = io_dis_uops_1_bits_mem_cmd; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_mem_size_0 = io_dis_uops_1_bits_mem_size; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_mem_signed_0 = io_dis_uops_1_bits_mem_signed; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_uses_ldq_0 = io_dis_uops_1_bits_uses_ldq; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_uses_stq_0 = io_dis_uops_1_bits_uses_stq; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_unique_0 = io_dis_uops_1_bits_is_unique; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_flush_on_commit_0 = io_dis_uops_1_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_1_bits_csr_cmd_0 = io_dis_uops_1_bits_csr_cmd; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_ldst_is_rs1_0 = io_dis_uops_1_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_1_bits_ldst_0 = io_dis_uops_1_bits_ldst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_1_bits_lrs1_0 = io_dis_uops_1_bits_lrs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_1_bits_lrs2_0 = io_dis_uops_1_bits_lrs2; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_1_bits_lrs3_0 = io_dis_uops_1_bits_lrs3; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_dst_rtype_0 = io_dis_uops_1_bits_dst_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_lrs1_rtype_0 = io_dis_uops_1_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_lrs2_rtype_0 = io_dis_uops_1_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_frs3_en_0 = io_dis_uops_1_bits_frs3_en; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fcn_dw_0 = io_dis_uops_1_bits_fcn_dw; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_1_bits_fcn_op_0 = io_dis_uops_1_bits_fcn_op; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_val_0 = io_dis_uops_1_bits_fp_val; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_1_bits_fp_rm_0 = io_dis_uops_1_bits_fp_rm; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_fp_typ_0 = io_dis_uops_1_bits_fp_typ; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_xcpt_pf_if_0 = io_dis_uops_1_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_xcpt_ae_if_0 = io_dis_uops_1_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_xcpt_ma_if_0 = io_dis_uops_1_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_bp_debug_if_0 = io_dis_uops_1_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_bp_xcpt_if_0 = io_dis_uops_1_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_1_bits_debug_fsrc_0 = io_dis_uops_1_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_1_bits_debug_tsrc_0 = io_dis_uops_1_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-unit-age-ordered.scala:22:7] wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7] wire [11:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-unit-age-ordered.scala:22:7] wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-unit-age-ordered.scala:22:7] wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_bypassable_0 = io_wakeup_ports_0_bits_bypassable; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_speculative_mask_0 = io_wakeup_ports_0_bits_speculative_mask; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_rebusy_0 = io_wakeup_ports_0_bits_rebusy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-unit-age-ordered.scala:22:7] wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7] wire [11:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-unit-age-ordered.scala:22:7] wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-unit-age-ordered.scala:22:7] wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_wakeup_ports_2_bits_uop_inst_0 = io_wakeup_ports_2_bits_uop_inst; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_wakeup_ports_2_bits_uop_debug_inst_0 = io_wakeup_ports_2_bits_uop_debug_inst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_is_rvc_0 = io_wakeup_ports_2_bits_uop_is_rvc; // @[issue-unit-age-ordered.scala:22:7] wire [39:0] io_wakeup_ports_2_bits_uop_debug_pc_0 = io_wakeup_ports_2_bits_uop_debug_pc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_iq_type_0_0 = io_wakeup_ports_2_bits_uop_iq_type_0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_iq_type_1_0 = io_wakeup_ports_2_bits_uop_iq_type_1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_iq_type_2_0 = io_wakeup_ports_2_bits_uop_iq_type_2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_iq_type_3_0 = io_wakeup_ports_2_bits_uop_iq_type_3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fu_code_0_0 = io_wakeup_ports_2_bits_uop_fu_code_0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fu_code_1_0 = io_wakeup_ports_2_bits_uop_fu_code_1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fu_code_2_0 = io_wakeup_ports_2_bits_uop_fu_code_2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fu_code_3_0 = io_wakeup_ports_2_bits_uop_fu_code_3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fu_code_4_0 = io_wakeup_ports_2_bits_uop_fu_code_4; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fu_code_5_0 = io_wakeup_ports_2_bits_uop_fu_code_5; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fu_code_6_0 = io_wakeup_ports_2_bits_uop_fu_code_6; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fu_code_7_0 = io_wakeup_ports_2_bits_uop_fu_code_7; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fu_code_8_0 = io_wakeup_ports_2_bits_uop_fu_code_8; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fu_code_9_0 = io_wakeup_ports_2_bits_uop_fu_code_9; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_iw_issued_0 = io_wakeup_ports_2_bits_uop_iw_issued; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_2_bits_uop_dis_col_sel_0 = io_wakeup_ports_2_bits_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7] wire [11:0] io_wakeup_ports_2_bits_uop_br_mask_0 = io_wakeup_ports_2_bits_uop_br_mask; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_tag_0 = io_wakeup_ports_2_bits_uop_br_tag; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_type_0 = io_wakeup_ports_2_bits_uop_br_type; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_is_sfb_0 = io_wakeup_ports_2_bits_uop_is_sfb; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_is_fence_0 = io_wakeup_ports_2_bits_uop_is_fence; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_is_fencei_0 = io_wakeup_ports_2_bits_uop_is_fencei; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_is_sfence_0 = io_wakeup_ports_2_bits_uop_is_sfence; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_is_amo_0 = io_wakeup_ports_2_bits_uop_is_amo; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_is_eret_0 = io_wakeup_ports_2_bits_uop_is_eret; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_2_bits_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_is_rocc_0 = io_wakeup_ports_2_bits_uop_is_rocc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_is_mov_0 = io_wakeup_ports_2_bits_uop_is_mov; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_2_bits_uop_ftq_idx_0 = io_wakeup_ports_2_bits_uop_ftq_idx; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_edge_inst_0 = io_wakeup_ports_2_bits_uop_edge_inst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_2_bits_uop_pc_lob_0 = io_wakeup_ports_2_bits_uop_pc_lob; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_taken_0 = io_wakeup_ports_2_bits_uop_taken; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_imm_rename_0 = io_wakeup_ports_2_bits_uop_imm_rename; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_2_bits_uop_imm_sel_0 = io_wakeup_ports_2_bits_uop_imm_sel; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_2_bits_uop_pimm_0 = io_wakeup_ports_2_bits_uop_pimm; // @[issue-unit-age-ordered.scala:22:7] wire [19:0] io_wakeup_ports_2_bits_uop_imm_packed_0 = io_wakeup_ports_2_bits_uop_imm_packed; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_2_bits_uop_op1_sel_0 = io_wakeup_ports_2_bits_uop_op1_sel; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_2_bits_uop_op2_sel_0 = io_wakeup_ports_2_bits_uop_op2_sel; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_2_bits_uop_rob_idx_0 = io_wakeup_ports_2_bits_uop_rob_idx; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_wakeup_ports_2_bits_uop_ldq_idx_0 = io_wakeup_ports_2_bits_uop_ldq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_wakeup_ports_2_bits_uop_stq_idx_0 = io_wakeup_ports_2_bits_uop_stq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_2_bits_uop_rxq_idx_0 = io_wakeup_ports_2_bits_uop_rxq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_2_bits_uop_pdst_0 = io_wakeup_ports_2_bits_uop_pdst; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs1_0 = io_wakeup_ports_2_bits_uop_prs1; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs2_0 = io_wakeup_ports_2_bits_uop_prs2; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs3_0 = io_wakeup_ports_2_bits_uop_prs3; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_2_bits_uop_ppred_0 = io_wakeup_ports_2_bits_uop_ppred; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_prs1_busy_0 = io_wakeup_ports_2_bits_uop_prs1_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_prs2_busy_0 = io_wakeup_ports_2_bits_uop_prs2_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_prs3_busy_0 = io_wakeup_ports_2_bits_uop_prs3_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_ppred_busy_0 = io_wakeup_ports_2_bits_uop_ppred_busy; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_2_bits_uop_stale_pdst_0 = io_wakeup_ports_2_bits_uop_stale_pdst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_exception_0 = io_wakeup_ports_2_bits_uop_exception; // @[issue-unit-age-ordered.scala:22:7] wire [63:0] io_wakeup_ports_2_bits_uop_exc_cause_0 = io_wakeup_ports_2_bits_uop_exc_cause; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_2_bits_uop_mem_cmd_0 = io_wakeup_ports_2_bits_uop_mem_cmd; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_2_bits_uop_mem_size_0 = io_wakeup_ports_2_bits_uop_mem_size; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_mem_signed_0 = io_wakeup_ports_2_bits_uop_mem_signed; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_uses_ldq_0 = io_wakeup_ports_2_bits_uop_uses_ldq; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_uses_stq_0 = io_wakeup_ports_2_bits_uop_uses_stq; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_is_unique_0 = io_wakeup_ports_2_bits_uop_is_unique; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_flush_on_commit_0 = io_wakeup_ports_2_bits_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_2_bits_uop_csr_cmd_0 = io_wakeup_ports_2_bits_uop_csr_cmd; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_2_bits_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_2_bits_uop_ldst_0 = io_wakeup_ports_2_bits_uop_ldst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs1_0 = io_wakeup_ports_2_bits_uop_lrs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs2_0 = io_wakeup_ports_2_bits_uop_lrs2; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs3_0 = io_wakeup_ports_2_bits_uop_lrs3; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_2_bits_uop_dst_rtype_0 = io_wakeup_ports_2_bits_uop_dst_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype_0 = io_wakeup_ports_2_bits_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype_0 = io_wakeup_ports_2_bits_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_frs3_en_0 = io_wakeup_ports_2_bits_uop_frs3_en; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fcn_dw_0 = io_wakeup_ports_2_bits_uop_fcn_dw; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_2_bits_uop_fcn_op_0 = io_wakeup_ports_2_bits_uop_fcn_op; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fp_val_0 = io_wakeup_ports_2_bits_uop_fp_val; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_2_bits_uop_fp_rm_0 = io_wakeup_ports_2_bits_uop_fp_rm; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_typ_0 = io_wakeup_ports_2_bits_uop_fp_typ; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_2_bits_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_bp_debug_if_0 = io_wakeup_ports_2_bits_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_2_bits_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc_0 = io_wakeup_ports_2_bits_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc_0 = io_wakeup_ports_2_bits_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_wakeup_ports_3_bits_uop_inst_0 = io_wakeup_ports_3_bits_uop_inst; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_wakeup_ports_3_bits_uop_debug_inst_0 = io_wakeup_ports_3_bits_uop_debug_inst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_is_rvc_0 = io_wakeup_ports_3_bits_uop_is_rvc; // @[issue-unit-age-ordered.scala:22:7] wire [39:0] io_wakeup_ports_3_bits_uop_debug_pc_0 = io_wakeup_ports_3_bits_uop_debug_pc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_iq_type_0_0 = io_wakeup_ports_3_bits_uop_iq_type_0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_iq_type_1_0 = io_wakeup_ports_3_bits_uop_iq_type_1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_iq_type_2_0 = io_wakeup_ports_3_bits_uop_iq_type_2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_iq_type_3_0 = io_wakeup_ports_3_bits_uop_iq_type_3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fu_code_0_0 = io_wakeup_ports_3_bits_uop_fu_code_0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fu_code_1_0 = io_wakeup_ports_3_bits_uop_fu_code_1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fu_code_2_0 = io_wakeup_ports_3_bits_uop_fu_code_2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fu_code_3_0 = io_wakeup_ports_3_bits_uop_fu_code_3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fu_code_4_0 = io_wakeup_ports_3_bits_uop_fu_code_4; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fu_code_5_0 = io_wakeup_ports_3_bits_uop_fu_code_5; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fu_code_6_0 = io_wakeup_ports_3_bits_uop_fu_code_6; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fu_code_7_0 = io_wakeup_ports_3_bits_uop_fu_code_7; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fu_code_8_0 = io_wakeup_ports_3_bits_uop_fu_code_8; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fu_code_9_0 = io_wakeup_ports_3_bits_uop_fu_code_9; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_iw_issued_0 = io_wakeup_ports_3_bits_uop_iw_issued; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_3_bits_uop_dis_col_sel_0 = io_wakeup_ports_3_bits_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7] wire [11:0] io_wakeup_ports_3_bits_uop_br_mask_0 = io_wakeup_ports_3_bits_uop_br_mask; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_tag_0 = io_wakeup_ports_3_bits_uop_br_tag; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_type_0 = io_wakeup_ports_3_bits_uop_br_type; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_is_sfb_0 = io_wakeup_ports_3_bits_uop_is_sfb; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_is_fence_0 = io_wakeup_ports_3_bits_uop_is_fence; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_is_fencei_0 = io_wakeup_ports_3_bits_uop_is_fencei; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_is_sfence_0 = io_wakeup_ports_3_bits_uop_is_sfence; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_is_amo_0 = io_wakeup_ports_3_bits_uop_is_amo; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_is_eret_0 = io_wakeup_ports_3_bits_uop_is_eret; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_3_bits_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_is_rocc_0 = io_wakeup_ports_3_bits_uop_is_rocc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_is_mov_0 = io_wakeup_ports_3_bits_uop_is_mov; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_3_bits_uop_ftq_idx_0 = io_wakeup_ports_3_bits_uop_ftq_idx; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_edge_inst_0 = io_wakeup_ports_3_bits_uop_edge_inst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_3_bits_uop_pc_lob_0 = io_wakeup_ports_3_bits_uop_pc_lob; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_taken_0 = io_wakeup_ports_3_bits_uop_taken; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_imm_rename_0 = io_wakeup_ports_3_bits_uop_imm_rename; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_3_bits_uop_imm_sel_0 = io_wakeup_ports_3_bits_uop_imm_sel; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_3_bits_uop_pimm_0 = io_wakeup_ports_3_bits_uop_pimm; // @[issue-unit-age-ordered.scala:22:7] wire [19:0] io_wakeup_ports_3_bits_uop_imm_packed_0 = io_wakeup_ports_3_bits_uop_imm_packed; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_3_bits_uop_op1_sel_0 = io_wakeup_ports_3_bits_uop_op1_sel; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_3_bits_uop_op2_sel_0 = io_wakeup_ports_3_bits_uop_op2_sel; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_3_bits_uop_rob_idx_0 = io_wakeup_ports_3_bits_uop_rob_idx; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_wakeup_ports_3_bits_uop_ldq_idx_0 = io_wakeup_ports_3_bits_uop_ldq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_wakeup_ports_3_bits_uop_stq_idx_0 = io_wakeup_ports_3_bits_uop_stq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_3_bits_uop_rxq_idx_0 = io_wakeup_ports_3_bits_uop_rxq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_3_bits_uop_pdst_0 = io_wakeup_ports_3_bits_uop_pdst; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs1_0 = io_wakeup_ports_3_bits_uop_prs1; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs2_0 = io_wakeup_ports_3_bits_uop_prs2; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs3_0 = io_wakeup_ports_3_bits_uop_prs3; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_3_bits_uop_ppred_0 = io_wakeup_ports_3_bits_uop_ppred; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_prs1_busy_0 = io_wakeup_ports_3_bits_uop_prs1_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_prs2_busy_0 = io_wakeup_ports_3_bits_uop_prs2_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_prs3_busy_0 = io_wakeup_ports_3_bits_uop_prs3_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_ppred_busy_0 = io_wakeup_ports_3_bits_uop_ppred_busy; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_3_bits_uop_stale_pdst_0 = io_wakeup_ports_3_bits_uop_stale_pdst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_exception_0 = io_wakeup_ports_3_bits_uop_exception; // @[issue-unit-age-ordered.scala:22:7] wire [63:0] io_wakeup_ports_3_bits_uop_exc_cause_0 = io_wakeup_ports_3_bits_uop_exc_cause; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_3_bits_uop_mem_cmd_0 = io_wakeup_ports_3_bits_uop_mem_cmd; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_3_bits_uop_mem_size_0 = io_wakeup_ports_3_bits_uop_mem_size; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_mem_signed_0 = io_wakeup_ports_3_bits_uop_mem_signed; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_uses_ldq_0 = io_wakeup_ports_3_bits_uop_uses_ldq; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_uses_stq_0 = io_wakeup_ports_3_bits_uop_uses_stq; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_is_unique_0 = io_wakeup_ports_3_bits_uop_is_unique; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_flush_on_commit_0 = io_wakeup_ports_3_bits_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_3_bits_uop_csr_cmd_0 = io_wakeup_ports_3_bits_uop_csr_cmd; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_3_bits_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_3_bits_uop_ldst_0 = io_wakeup_ports_3_bits_uop_ldst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs1_0 = io_wakeup_ports_3_bits_uop_lrs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs2_0 = io_wakeup_ports_3_bits_uop_lrs2; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs3_0 = io_wakeup_ports_3_bits_uop_lrs3; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_3_bits_uop_dst_rtype_0 = io_wakeup_ports_3_bits_uop_dst_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype_0 = io_wakeup_ports_3_bits_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype_0 = io_wakeup_ports_3_bits_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_frs3_en_0 = io_wakeup_ports_3_bits_uop_frs3_en; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fcn_dw_0 = io_wakeup_ports_3_bits_uop_fcn_dw; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_3_bits_uop_fcn_op_0 = io_wakeup_ports_3_bits_uop_fcn_op; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fp_val_0 = io_wakeup_ports_3_bits_uop_fp_val; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_3_bits_uop_fp_rm_0 = io_wakeup_ports_3_bits_uop_fp_rm; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_typ_0 = io_wakeup_ports_3_bits_uop_fp_typ; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_3_bits_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_bp_debug_if_0 = io_wakeup_ports_3_bits_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_3_bits_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc_0 = io_wakeup_ports_3_bits_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc_0 = io_wakeup_ports_3_bits_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_child_rebusys_0 = io_child_rebusys; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_4_0 = io_fu_types_0_4; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_8_0 = io_fu_types_0_8; // @[issue-unit-age-ordered.scala:22:7] wire [11:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-unit-age-ordered.scala:22:7] wire [11:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-unit-age-ordered.scala:22:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7] wire [11:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-unit-age-ordered.scala:22:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-unit-age-ordered.scala:22:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-unit-age-ordered.scala:22:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-unit-age-ordered.scala:22:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-unit-age-ordered.scala:22:7] wire io_flush_pipeline_0 = io_flush_pipeline; // @[issue-unit-age-ordered.scala:22:7] wire io_squash_grant_0 = io_squash_grant; // @[issue-unit-age-ordered.scala:22:7] wire [63:0] io_tsc_reg_0 = io_tsc_reg; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_0 = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_1 = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_2 = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_6 = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_7 = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_9 = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire prs1_rebusys_1 = 1'h0; // @[issue-unit-age-ordered.scala:50:95] wire prs1_rebusys_2 = 1'h0; // @[issue-unit-age-ordered.scala:50:95] wire prs1_rebusys_3 = 1'h0; // @[issue-unit-age-ordered.scala:50:95] wire prs2_rebusys_1 = 1'h0; // @[issue-unit-age-ordered.scala:51:95] wire prs2_rebusys_2 = 1'h0; // @[issue-unit-age-ordered.scala:51:95] wire prs2_rebusys_3 = 1'h0; // @[issue-unit-age-ordered.scala:51:95] wire prs1_rebusys_1_1 = 1'h0; // @[issue-unit-age-ordered.scala:50:95] wire prs1_rebusys_2_1 = 1'h0; // @[issue-unit-age-ordered.scala:50:95] wire prs1_rebusys_3_1 = 1'h0; // @[issue-unit-age-ordered.scala:50:95] wire prs2_rebusys_1_1 = 1'h0; // @[issue-unit-age-ordered.scala:51:95] wire prs2_rebusys_2_1 = 1'h0; // @[issue-unit-age-ordered.scala:51:95] wire prs2_rebusys_3_1 = 1'h0; // @[issue-unit-age-ordered.scala:51:95] wire issue_slots_0_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_clear = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iw_issued = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_ppred_busy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire _shamts_oh_1_T_2 = 1'h0; // @[issue-unit-age-ordered.scala:165:28] wire _issue_slots_0_clear_T = 1'h0; // @[issue-unit-age-ordered.scala:199:49] wire iss_uops_0_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:241:22] wire _fu_code_match_T = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_1 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_2 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_6 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_7 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_9 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_10 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_11 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_18 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_19 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_20 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_24 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_25 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_27 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_28 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_29 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_36 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_37 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_38 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_42 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_43 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_45 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_46 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_47 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_54 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_55 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_56 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_60 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_61 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_63 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_64 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_65 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_72 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_73 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_74 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_78 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_79 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_81 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_82 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_83 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_90 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_91 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_92 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_96 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_97 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_99 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_100 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_101 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_108 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_109 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_110 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_114 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_115 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_117 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_118 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_119 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_126 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_127 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_128 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_132 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_133 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_135 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_136 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_137 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_144 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_145 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_146 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_150 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_151 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_153 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_154 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_155 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_162 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_163 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_164 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_168 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_169 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_171 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_172 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_173 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_180 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_181 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_182 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_186 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_187 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_189 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_190 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_191 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_198 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_199 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_200 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_204 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_205 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_207 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_208 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_209 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire [1:0] io_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] issue_slots_0_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] shamts_oh_0 = 2'h0; // @[issue-unit-age-ordered.scala:158:23] wire io_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_3 = 1'h1; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_5 = 1'h1; // @[issue-unit-age-ordered.scala:22:7] wire issue_slots_0_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire _shamts_oh_1_T = 1'h1; // @[issue-unit-age-ordered.scala:163:21] wire _shamts_oh_1_T_3 = 1'h1; // @[issue-unit-age-ordered.scala:165:19] wire [1:0] io_wakeup_ports_2_bits_speculative_mask = 2'h1; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] issue_slots_0_wakeup_ports_2_bits_speculative_mask = 2'h1; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_wakeup_ports_2_bits_speculative_mask = 2'h1; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_wakeup_ports_2_bits_speculative_mask = 2'h1; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_wakeup_ports_2_bits_speculative_mask = 2'h1; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_wakeup_ports_2_bits_speculative_mask = 2'h1; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_wakeup_ports_2_bits_speculative_mask = 2'h1; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_wakeup_ports_2_bits_speculative_mask = 2'h1; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_wakeup_ports_2_bits_speculative_mask = 2'h1; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_wakeup_ports_2_bits_speculative_mask = 2'h1; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_wakeup_ports_2_bits_speculative_mask = 2'h1; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_wakeup_ports_2_bits_speculative_mask = 2'h1; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_wakeup_ports_2_bits_speculative_mask = 2'h1; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] io_wakeup_ports_3_bits_speculative_mask = 2'h2; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] issue_slots_0_wakeup_ports_3_bits_speculative_mask = 2'h2; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_wakeup_ports_3_bits_speculative_mask = 2'h2; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_wakeup_ports_3_bits_speculative_mask = 2'h2; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_wakeup_ports_3_bits_speculative_mask = 2'h2; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_wakeup_ports_3_bits_speculative_mask = 2'h2; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_wakeup_ports_3_bits_speculative_mask = 2'h2; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_wakeup_ports_3_bits_speculative_mask = 2'h2; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_wakeup_ports_3_bits_speculative_mask = 2'h2; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_wakeup_ports_3_bits_speculative_mask = 2'h2; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_wakeup_ports_3_bits_speculative_mask = 2'h2; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_wakeup_ports_3_bits_speculative_mask = 2'h2; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_wakeup_ports_3_bits_speculative_mask = 2'h2; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] issue_slots_0_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] _shamts_oh_1_next_T = 3'h0; // @[issue-unit-age-ordered.scala:166:26] wire [31:0] iss_uops_0_bits_inst; // @[issue-unit-age-ordered.scala:241:22] wire [31:0] iss_uops_0_bits_debug_inst; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_rvc; // @[issue-unit-age-ordered.scala:241:22] wire [39:0] iss_uops_0_bits_debug_pc; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_iq_type_0; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_iq_type_1; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_iq_type_2; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_iq_type_3; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_0; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_1; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_2; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_3; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_4; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_5; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_6; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_7; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_8; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_9; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_iw_issued; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:241:22] wire [11:0] iss_uops_0_bits_br_mask; // @[issue-unit-age-ordered.scala:241:22] wire [3:0] iss_uops_0_bits_br_tag; // @[issue-unit-age-ordered.scala:241:22] wire [3:0] iss_uops_0_bits_br_type; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_sfb; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_fence; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_fencei; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_sfence; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_amo; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_eret; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_rocc; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_mov; // @[issue-unit-age-ordered.scala:241:22] wire [4:0] iss_uops_0_bits_ftq_idx; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_edge_inst; // @[issue-unit-age-ordered.scala:241:22] wire [5:0] iss_uops_0_bits_pc_lob; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_taken; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_imm_rename; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] iss_uops_0_bits_imm_sel; // @[issue-unit-age-ordered.scala:241:22] wire [4:0] iss_uops_0_bits_pimm; // @[issue-unit-age-ordered.scala:241:22] wire [19:0] iss_uops_0_bits_imm_packed; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_op1_sel; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] iss_uops_0_bits_op2_sel; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:241:22] wire [5:0] iss_uops_0_bits_rob_idx; // @[issue-unit-age-ordered.scala:241:22] wire [3:0] iss_uops_0_bits_ldq_idx; // @[issue-unit-age-ordered.scala:241:22] wire [3:0] iss_uops_0_bits_stq_idx; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_rxq_idx; // @[issue-unit-age-ordered.scala:241:22] wire [6:0] iss_uops_0_bits_pdst; // @[issue-unit-age-ordered.scala:241:22] wire [6:0] iss_uops_0_bits_prs1; // @[issue-unit-age-ordered.scala:241:22] wire [6:0] iss_uops_0_bits_prs2; // @[issue-unit-age-ordered.scala:241:22] wire [6:0] iss_uops_0_bits_prs3; // @[issue-unit-age-ordered.scala:241:22] wire [4:0] iss_uops_0_bits_ppred; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_prs1_busy; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_prs2_busy; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_prs3_busy; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_ppred_busy; // @[issue-unit-age-ordered.scala:241:22] wire [6:0] iss_uops_0_bits_stale_pdst; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_exception; // @[issue-unit-age-ordered.scala:241:22] wire [63:0] iss_uops_0_bits_exc_cause; // @[issue-unit-age-ordered.scala:241:22] wire [4:0] iss_uops_0_bits_mem_cmd; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_mem_size; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_mem_signed; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_uses_ldq; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_uses_stq; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_unique; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] iss_uops_0_bits_csr_cmd; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:241:22] wire [5:0] iss_uops_0_bits_ldst; // @[issue-unit-age-ordered.scala:241:22] wire [5:0] iss_uops_0_bits_lrs1; // @[issue-unit-age-ordered.scala:241:22] wire [5:0] iss_uops_0_bits_lrs2; // @[issue-unit-age-ordered.scala:241:22] wire [5:0] iss_uops_0_bits_lrs3; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_dst_rtype; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_frs3_en; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fcn_dw; // @[issue-unit-age-ordered.scala:241:22] wire [4:0] iss_uops_0_bits_fcn_op; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_val; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] iss_uops_0_bits_fp_rm; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_fp_typ; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] iss_uops_0_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] iss_uops_0_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:241:22] wire issue_slots_0_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_0_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_1_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_2_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_3_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_4_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_5_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_6_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_7_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_8_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_9_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_10_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_11_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_0_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_1_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_2_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_3_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_4_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_5_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_6_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_7_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_8_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_9_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_10_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_11_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_0_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_1_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_2_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_3_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_4_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_5_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_6_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_7_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_8_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_9_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_10_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_11_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_0_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_1_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_2_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_3_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_4_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_5_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_6_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_7_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_8_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_9_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_10_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_11_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_0_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_1_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_2_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_3_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_4_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_5_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_6_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_7_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_8_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_9_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_10_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_11_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_0_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_1_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_2_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_3_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_4_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_5_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_6_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_7_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_8_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_9_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_10_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_11_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_0_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_1_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_2_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_3_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_4_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_5_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_6_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_7_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_8_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_9_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_10_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_11_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_0_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_1_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_2_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_3_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_4_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_5_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_6_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_7_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_8_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_9_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_10_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_11_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_0_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_1_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_2_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_3_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_4_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_5_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_6_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_7_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_8_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_9_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_10_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_11_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_0_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_1_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_2_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_3_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_4_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_5_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_6_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_7_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_8_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_9_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_10_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_11_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_0_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_1_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_2_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_3_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_4_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_5_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_6_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_7_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_8_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_9_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_10_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_11_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_0_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_1_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_2_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_3_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_4_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_5_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_6_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_7_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_8_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_9_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_10_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_11_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_0_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_1_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_2_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_3_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_4_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_5_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_6_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_7_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_8_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_9_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_10_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_11_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_0_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_1_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_2_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_3_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_4_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_5_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_6_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_7_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_8_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_9_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_10_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_11_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_0_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_1_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_2_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_3_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_4_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_5_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_6_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_7_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_8_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_9_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_10_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_11_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_0_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_1_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_2_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_3_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_4_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_5_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_6_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_7_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_8_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_9_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_10_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_11_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_0_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_1_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_2_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_3_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_4_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_5_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_6_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_7_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_8_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_9_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_10_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_11_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_0_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_1_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_2_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_3_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_4_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_5_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_6_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_7_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_8_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_9_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_10_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_11_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_0_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_1_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_2_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_3_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_4_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_5_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_6_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_7_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_8_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_9_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_10_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_11_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_0_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_1_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_2_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_3_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_4_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_5_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_6_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_7_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_8_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_9_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_10_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_11_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_0_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_1_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_2_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_3_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_4_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_5_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_6_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_7_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_8_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_9_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_10_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_11_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_0_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_1_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_2_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_3_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_4_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_5_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_6_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_7_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_8_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_9_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_10_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_11_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_0_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_1_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_2_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_3_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_4_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_5_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_6_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_7_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_8_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_9_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_10_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_11_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_0_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_1_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_2_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_3_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_4_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_5_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_6_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_7_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_8_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_9_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_10_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_11_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_0_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_1_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_2_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_3_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_4_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_5_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_6_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_7_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_8_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_9_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_10_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_11_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_0_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_1_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_2_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_3_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_4_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_5_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_6_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_7_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_8_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_9_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_10_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_11_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_0_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_1_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_2_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_3_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_4_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_5_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_6_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_7_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_8_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_9_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_10_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_11_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_0_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_1_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_2_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_3_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_4_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_5_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_6_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_7_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_8_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_9_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_10_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_11_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_0_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_1_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_2_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_3_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_4_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_5_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_6_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_7_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_8_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_9_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_10_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_11_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_0_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_1_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_2_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_3_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_4_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_5_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_6_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_7_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_8_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_9_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_10_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_11_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_0_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_1_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_2_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_3_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_4_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_5_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_6_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_7_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_8_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_9_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_10_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_11_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_0_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_1_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_2_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_3_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_4_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_5_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_6_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_7_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_8_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_9_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_10_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_11_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_0_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_1_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_2_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_3_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_4_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_5_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_6_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_7_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_8_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_9_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_10_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_11_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_0_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_1_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_2_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_3_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_4_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_5_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_6_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_7_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_8_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_9_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_10_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_11_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire io_dis_uops_0_ready_0; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_ready_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_iss_uops_0_bits_inst_0; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_iss_uops_0_bits_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7] wire [39:0] io_iss_uops_0_bits_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7] wire [11:0] io_iss_uops_0_bits_br_mask_0; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_iss_uops_0_bits_br_tag_0; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_iss_uops_0_bits_br_type_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_fence_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_amo_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_eret_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_mov_0; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_iss_uops_0_bits_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_iss_uops_0_bits_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_taken_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_iss_uops_0_bits_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_iss_uops_0_bits_pimm_0; // @[issue-unit-age-ordered.scala:22:7] wire [19:0] io_iss_uops_0_bits_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_iss_uops_0_bits_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_iss_uops_0_bits_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_iss_uops_0_bits_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_iss_uops_0_bits_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_iss_uops_0_bits_pdst_0; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_iss_uops_0_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_iss_uops_0_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_iss_uops_0_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_iss_uops_0_bits_ppred_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_iss_uops_0_bits_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_exception_0; // @[issue-unit-age-ordered.scala:22:7] wire [63:0] io_iss_uops_0_bits_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_iss_uops_0_bits_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_mem_size_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_unique_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_iss_uops_0_bits_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_iss_uops_0_bits_ldst_0; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_iss_uops_0_bits_lrs1_0; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_iss_uops_0_bits_lrs2_0; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_iss_uops_0_bits_lrs3_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_iss_uops_0_bits_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_val_0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_iss_uops_0_bits_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_iss_uops_0_bits_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_iss_uops_0_bits_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_valid_0; // @[issue-unit-age-ordered.scala:22:7] wire prs1_matches_0 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_0_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs1_matches_1 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_0_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs1_matches_2 = io_wakeup_ports_2_bits_uop_pdst_0 == io_dis_uops_0_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs1_matches_3 = io_wakeup_ports_3_bits_uop_pdst_0 == io_dis_uops_0_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs2_matches_0 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_0_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs2_matches_1 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_0_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs2_matches_2 = io_wakeup_ports_2_bits_uop_pdst_0 == io_dis_uops_0_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs2_matches_3 = io_wakeup_ports_3_bits_uop_pdst_0 == io_dis_uops_0_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs3_matches_0 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_0_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs3_matches_1 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_0_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs3_matches_2 = io_wakeup_ports_2_bits_uop_pdst_0 == io_dis_uops_0_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs3_matches_3 = io_wakeup_ports_3_bits_uop_pdst_0 == io_dis_uops_0_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs1_wakeups_0 = io_wakeup_ports_0_valid_0 & prs1_matches_0; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs1_wakeups_1 = io_wakeup_ports_1_valid_0 & prs1_matches_1; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs1_wakeups_2 = io_wakeup_ports_2_valid_0 & prs1_matches_2; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs1_wakeups_3 = io_wakeup_ports_3_valid_0 & prs1_matches_3; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs2_wakeups_0 = io_wakeup_ports_0_valid_0 & prs2_matches_0; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs2_wakeups_1 = io_wakeup_ports_1_valid_0 & prs2_matches_1; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs2_wakeups_2 = io_wakeup_ports_2_valid_0 & prs2_matches_2; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs2_wakeups_3 = io_wakeup_ports_3_valid_0 & prs2_matches_3; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs3_wakeups_0 = io_wakeup_ports_0_valid_0 & prs3_matches_0; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire prs3_wakeups_1 = io_wakeup_ports_1_valid_0 & prs3_matches_1; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire prs3_wakeups_2 = io_wakeup_ports_2_valid_0 & prs3_matches_2; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire prs3_wakeups_3 = io_wakeup_ports_3_valid_0 & prs3_matches_3; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire prs1_rebusys_0 = io_wakeup_ports_0_bits_rebusy_0 & prs1_matches_0; // @[issue-unit-age-ordered.scala:22:7, :44:69, :50:95] wire prs2_rebusys_0 = io_wakeup_ports_0_bits_rebusy_0 & prs2_matches_0; // @[issue-unit-age-ordered.scala:22:7, :45:69, :51:95] wire _T_2 = prs1_wakeups_0 | prs1_wakeups_1 | prs1_wakeups_2 | prs1_wakeups_3; // @[issue-unit-age-ordered.scala:47:89, :57:32] wire [1:0] _WIRE_iw_p1_speculative_child = _T_2 ? (prs1_wakeups_0 ? io_wakeup_ports_0_bits_speculative_mask_0 : 2'h0) | {prs1_wakeups_3, prs1_wakeups_2} : io_dis_uops_0_bits_iw_p1_speculative_child_0; // @[Mux.scala:30:73] wire _WIRE_iw_p1_bypass_hint = _T_2 & (prs1_wakeups_0 & io_wakeup_ports_0_bits_bypassable_0 | prs1_wakeups_2 | prs1_wakeups_3); // @[Mux.scala:30:73] wire _WIRE_prs1_busy = (|{prs1_rebusys_0, io_child_rebusys_0 & io_dis_uops_0_bits_iw_p1_speculative_child_0}) ? io_dis_uops_0_bits_lrs1_rtype_0 == 2'h0 : ~_T_2 & io_dis_uops_0_bits_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :35:17, :50:95, :57:{32,38}, :58:29, :62:{37,59,106,116}, :63:{29,63}] wire _T_26 = prs2_wakeups_0 | prs2_wakeups_1 | prs2_wakeups_2 | prs2_wakeups_3; // @[issue-unit-age-ordered.scala:48:89, :65:32] wire [1:0] _WIRE_iw_p2_speculative_child = _T_26 ? (prs2_wakeups_0 ? io_wakeup_ports_0_bits_speculative_mask_0 : 2'h0) | {prs2_wakeups_3, prs2_wakeups_2} : io_dis_uops_0_bits_iw_p2_speculative_child_0; // @[Mux.scala:30:73] wire _WIRE_iw_p2_bypass_hint = _T_26 & (prs2_wakeups_0 & io_wakeup_ports_0_bits_bypassable_0 | prs2_wakeups_2 | prs2_wakeups_3); // @[Mux.scala:30:73] wire _WIRE_prs2_busy = (|{prs2_rebusys_0, io_child_rebusys_0 & io_dis_uops_0_bits_iw_p2_speculative_child_0}) ? io_dis_uops_0_bits_lrs2_rtype_0 == 2'h0 : ~_T_26 & io_dis_uops_0_bits_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :35:17, :51:95, :65:{32,38}, :66:29, :71:{37,59,106,116}, :72:{29,63}] wire _T_50 = prs3_wakeups_0 | prs3_wakeups_1 | prs3_wakeups_2 | prs3_wakeups_3; // @[issue-unit-age-ordered.scala:49:89, :76:32] wire _WIRE_prs3_busy = ~_T_50 & io_dis_uops_0_bits_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :35:17, :76:{32,38}, :77:29] wire _WIRE_iw_p3_bypass_hint = _T_50 & (prs3_wakeups_0 & io_wakeup_ports_0_bits_bypassable_0 | prs3_wakeups_2 | prs3_wakeups_3); // @[Mux.scala:30:73] wire [6:0] _WIRE_prs2 = io_dis_uops_0_bits_fu_code_8_0 ? {2'h0, io_dis_uops_0_bits_fp_rm_0, io_dis_uops_0_bits_fp_typ_0} : io_dis_uops_0_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :35:17, :86:50, :87:26] wire [4:0] _WIRE_pimm = io_dis_uops_0_bits_is_sfence_0 ? {3'h0, io_dis_uops_0_bits_mem_size_0} : io_dis_uops_0_bits_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :35:17, :89:44, :90:26] wire prs1_matches_0_1 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_1_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs1_matches_1_1 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_1_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs1_matches_2_1 = io_wakeup_ports_2_bits_uop_pdst_0 == io_dis_uops_1_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs1_matches_3_1 = io_wakeup_ports_3_bits_uop_pdst_0 == io_dis_uops_1_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs2_matches_0_1 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_1_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs2_matches_1_1 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_1_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs2_matches_2_1 = io_wakeup_ports_2_bits_uop_pdst_0 == io_dis_uops_1_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs2_matches_3_1 = io_wakeup_ports_3_bits_uop_pdst_0 == io_dis_uops_1_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs3_matches_0_1 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_1_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs3_matches_1_1 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_1_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs3_matches_2_1 = io_wakeup_ports_2_bits_uop_pdst_0 == io_dis_uops_1_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs3_matches_3_1 = io_wakeup_ports_3_bits_uop_pdst_0 == io_dis_uops_1_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs1_wakeups_0_1 = io_wakeup_ports_0_valid_0 & prs1_matches_0_1; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs1_wakeups_1_1 = io_wakeup_ports_1_valid_0 & prs1_matches_1_1; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs1_wakeups_2_1 = io_wakeup_ports_2_valid_0 & prs1_matches_2_1; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs1_wakeups_3_1 = io_wakeup_ports_3_valid_0 & prs1_matches_3_1; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs2_wakeups_0_1 = io_wakeup_ports_0_valid_0 & prs2_matches_0_1; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs2_wakeups_1_1 = io_wakeup_ports_1_valid_0 & prs2_matches_1_1; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs2_wakeups_2_1 = io_wakeup_ports_2_valid_0 & prs2_matches_2_1; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs2_wakeups_3_1 = io_wakeup_ports_3_valid_0 & prs2_matches_3_1; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs3_wakeups_0_1 = io_wakeup_ports_0_valid_0 & prs3_matches_0_1; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire prs3_wakeups_1_1 = io_wakeup_ports_1_valid_0 & prs3_matches_1_1; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire prs3_wakeups_2_1 = io_wakeup_ports_2_valid_0 & prs3_matches_2_1; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire prs3_wakeups_3_1 = io_wakeup_ports_3_valid_0 & prs3_matches_3_1; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire prs1_rebusys_0_1 = io_wakeup_ports_0_bits_rebusy_0 & prs1_matches_0_1; // @[issue-unit-age-ordered.scala:22:7, :44:69, :50:95] wire prs2_rebusys_0_1 = io_wakeup_ports_0_bits_rebusy_0 & prs2_matches_0_1; // @[issue-unit-age-ordered.scala:22:7, :45:69, :51:95] wire _T_68 = prs1_wakeups_0_1 | prs1_wakeups_1_1 | prs1_wakeups_2_1 | prs1_wakeups_3_1; // @[issue-unit-age-ordered.scala:47:89, :57:32] wire _T_92 = prs2_wakeups_0_1 | prs2_wakeups_1_1 | prs2_wakeups_2_1 | prs2_wakeups_3_1; // @[issue-unit-age-ordered.scala:48:89, :65:32] wire _T_116 = prs3_wakeups_0_1 | prs3_wakeups_1_1 | prs3_wakeups_2_1 | prs3_wakeups_3_1; // @[issue-unit-age-ordered.scala:49:89, :76:32] wire _fu_code_match_T_3 = issue_slots_0_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _fu_code_match_T_5 = issue_slots_0_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _fu_code_match_T_21 = issue_slots_1_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _fu_code_match_T_23 = issue_slots_1_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_1_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_39 = issue_slots_2_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _fu_code_match_T_41 = issue_slots_2_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_2_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_57 = issue_slots_3_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _fu_code_match_T_59 = issue_slots_3_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_3_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_75 = issue_slots_4_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _fu_code_match_T_77 = issue_slots_4_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_4_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_93 = issue_slots_5_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _fu_code_match_T_95 = issue_slots_5_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_5_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_111 = issue_slots_6_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _fu_code_match_T_113 = issue_slots_6_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_6_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_129 = issue_slots_7_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _fu_code_match_T_131 = issue_slots_7_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_7_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_147 = issue_slots_8_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _fu_code_match_T_149 = issue_slots_8_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_8_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_165 = issue_slots_9_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _fu_code_match_T_167 = issue_slots_9_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_9_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_183 = issue_slots_10_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _fu_code_match_T_185 = issue_slots_10_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_10_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_201 = issue_slots_11_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _fu_code_match_T_203 = issue_slots_11_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_11_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire issue_slots_0_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_0_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_0_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_0_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_0_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_0_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_0_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_0_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_0_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_0_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_0_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_0_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_0_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_0_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_0_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_0_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_0_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_0_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_0_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_0_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_0_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_0_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_0_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_0_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_0_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_0_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_0_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_0_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_0_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_0_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_0_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_1_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_1_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_1_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_1_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_1_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_1_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_1_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_1_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_1_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_1_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_1_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_1_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_1_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_1_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_1_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_1_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_1_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_1_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_1_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_1_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_1_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_1_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_1_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_1_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_1_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_1_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_1_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_1_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_1_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_1_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_2_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_2_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_2_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_2_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_2_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_2_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_2_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_2_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_2_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_2_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_2_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_2_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_2_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_2_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_2_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_2_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_2_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_2_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_2_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_2_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_2_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_2_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_2_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_2_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_2_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_2_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_2_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_2_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_2_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_2_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_3_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_3_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_3_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_3_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_3_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_3_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_3_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_3_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_3_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_3_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_3_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_3_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_3_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_3_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_3_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_3_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_3_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_3_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_3_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_3_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_3_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_3_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_3_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_3_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_3_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_3_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_3_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_3_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_3_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_3_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_4_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_4_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_4_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_4_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_4_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_4_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_4_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_4_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_4_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_4_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_4_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_4_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_4_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_4_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_4_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_4_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_4_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_4_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_4_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_4_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_4_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_4_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_4_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_4_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_4_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_4_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_4_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_4_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_4_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_4_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_5_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_5_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_5_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_5_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_5_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_5_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_5_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_5_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_5_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_5_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_5_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_5_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_5_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_5_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_5_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_5_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_5_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_5_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_5_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_5_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_5_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_5_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_5_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_5_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_5_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_5_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_5_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_5_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_5_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_5_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_6_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_6_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_6_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_6_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_6_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_6_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_6_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_6_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_6_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_6_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_6_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_6_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_6_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_6_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_6_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_6_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_6_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_6_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_6_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_6_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_6_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_6_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_6_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_6_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_6_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_6_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_6_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_6_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_6_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_6_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_7_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_7_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_7_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_7_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_7_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_7_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_7_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_7_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_7_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_7_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_7_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_7_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_7_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_7_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_7_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_7_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_7_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_7_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_7_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_7_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_7_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_7_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_7_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_7_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_7_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_7_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_7_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_7_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_7_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_7_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_8_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_8_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_8_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_8_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_8_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_8_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_8_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_8_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_8_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_8_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_8_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_8_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_8_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_8_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_8_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_8_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_8_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_8_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_8_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_8_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_8_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_8_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_8_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_8_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_8_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_8_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_8_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_8_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_8_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_8_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_9_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_9_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_9_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_9_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_9_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_9_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_9_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_9_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_9_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_9_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_9_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_9_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_9_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_9_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_9_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_9_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_9_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_9_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_9_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_9_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_9_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_9_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_9_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_9_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_9_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_9_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_9_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_9_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_9_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_9_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_10_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_10_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_10_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_10_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_10_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_10_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_10_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_10_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_10_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_10_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_10_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_10_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_10_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_10_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_10_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_10_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_10_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_10_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_10_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_10_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_10_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_10_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_10_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_10_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_10_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_10_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_10_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_10_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_10_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_10_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_11_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_11_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_11_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_11_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_11_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_11_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_11_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_11_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_11_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_11_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_11_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_11_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_11_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_11_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_11_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_11_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_11_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_11_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_11_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_11_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_11_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_11_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_11_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_11_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_11_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_11_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_11_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_11_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_11_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_11_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_clear; // @[issue-unit-age-ordered.scala:122:28] wire vacants_0 = ~issue_slots_0_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire _shamts_oh_1_T_1 = vacants_0; // @[issue-unit-age-ordered.scala:157:38, :163:29] wire _shamts_oh_1_T_4 = vacants_0; // @[issue-unit-age-ordered.scala:157:38, :165:36] wire vacants_1 = ~issue_slots_1_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_2 = ~issue_slots_2_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_3 = ~issue_slots_3_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_4 = ~issue_slots_4_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_5 = ~issue_slots_5_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_6 = ~issue_slots_6_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_7 = ~issue_slots_7_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_8 = ~issue_slots_8_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_9 = ~issue_slots_9_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_10 = ~issue_slots_10_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_11 = ~issue_slots_11_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_12 = ~io_dis_uops_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :157:82] wire vacants_13 = ~io_dis_uops_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :157:82] wire [1:0] shamts_oh_1_next; // @[issue-unit-age-ordered.scala:161:21] wire [1:0] shamts_oh_2_next; // @[issue-unit-age-ordered.scala:161:21] wire [1:0] shamts_oh_3_next; // @[issue-unit-age-ordered.scala:161:21] wire [1:0] shamts_oh_4_next; // @[issue-unit-age-ordered.scala:161:21] wire [1:0] shamts_oh_5_next; // @[issue-unit-age-ordered.scala:161:21] wire [1:0] shamts_oh_6_next; // @[issue-unit-age-ordered.scala:161:21] wire [1:0] shamts_oh_7_next; // @[issue-unit-age-ordered.scala:161:21] wire [1:0] shamts_oh_8_next; // @[issue-unit-age-ordered.scala:161:21] wire [1:0] shamts_oh_9_next; // @[issue-unit-age-ordered.scala:161:21] wire [1:0] shamts_oh_10_next; // @[issue-unit-age-ordered.scala:161:21] wire [1:0] shamts_oh_11_next; // @[issue-unit-age-ordered.scala:161:21] wire [1:0] shamts_oh_12_next; // @[issue-unit-age-ordered.scala:161:21] wire [1:0] shamts_oh_13_next; // @[issue-unit-age-ordered.scala:161:21] wire [1:0] shamts_oh_1; // @[issue-unit-age-ordered.scala:158:23] wire [1:0] shamts_oh_2; // @[issue-unit-age-ordered.scala:158:23] wire [1:0] shamts_oh_3; // @[issue-unit-age-ordered.scala:158:23] wire [1:0] shamts_oh_4; // @[issue-unit-age-ordered.scala:158:23] wire [1:0] shamts_oh_5; // @[issue-unit-age-ordered.scala:158:23] wire [1:0] shamts_oh_6; // @[issue-unit-age-ordered.scala:158:23] wire [1:0] shamts_oh_7; // @[issue-unit-age-ordered.scala:158:23] wire [1:0] shamts_oh_8; // @[issue-unit-age-ordered.scala:158:23] wire [1:0] shamts_oh_9; // @[issue-unit-age-ordered.scala:158:23] wire [1:0] shamts_oh_10; // @[issue-unit-age-ordered.scala:158:23] wire [1:0] shamts_oh_11; // @[issue-unit-age-ordered.scala:158:23] wire [1:0] shamts_oh_12; // @[issue-unit-age-ordered.scala:158:23] wire [1:0] shamts_oh_13; // @[issue-unit-age-ordered.scala:158:23] assign shamts_oh_1 = shamts_oh_1_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] assign shamts_oh_1_next = {1'h0, _shamts_oh_1_T_1}; // @[issue-unit-age-ordered.scala:161:21, :163:{29,37}, :164:13, :165:44] assign shamts_oh_2 = shamts_oh_2_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_2_T = ~(|shamts_oh_1); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_2_T_1 = _shamts_oh_2_T & vacants_1; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_2_T_2 = shamts_oh_1[1]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_2_T_3 = ~_shamts_oh_2_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_2_T_4 = _shamts_oh_2_T_3 & vacants_1; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [2:0] _shamts_oh_2_next_T = {shamts_oh_1, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_2_next = _shamts_oh_2_T_1 ? 2'h1 : _shamts_oh_2_T_4 ? _shamts_oh_2_next_T[1:0] : shamts_oh_1; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_3 = shamts_oh_3_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_3_T = ~(|shamts_oh_2); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_3_T_1 = _shamts_oh_3_T & vacants_2; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_3_T_2 = shamts_oh_2[1]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_3_T_3 = ~_shamts_oh_3_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_3_T_4 = _shamts_oh_3_T_3 & vacants_2; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [2:0] _shamts_oh_3_next_T = {shamts_oh_2, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_3_next = _shamts_oh_3_T_1 ? 2'h1 : _shamts_oh_3_T_4 ? _shamts_oh_3_next_T[1:0] : shamts_oh_2; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_4 = shamts_oh_4_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_4_T = ~(|shamts_oh_3); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_4_T_1 = _shamts_oh_4_T & vacants_3; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_4_T_2 = shamts_oh_3[1]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_4_T_3 = ~_shamts_oh_4_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_4_T_4 = _shamts_oh_4_T_3 & vacants_3; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [2:0] _shamts_oh_4_next_T = {shamts_oh_3, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_4_next = _shamts_oh_4_T_1 ? 2'h1 : _shamts_oh_4_T_4 ? _shamts_oh_4_next_T[1:0] : shamts_oh_3; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_5 = shamts_oh_5_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_5_T = ~(|shamts_oh_4); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_5_T_1 = _shamts_oh_5_T & vacants_4; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_5_T_2 = shamts_oh_4[1]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_5_T_3 = ~_shamts_oh_5_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_5_T_4 = _shamts_oh_5_T_3 & vacants_4; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [2:0] _shamts_oh_5_next_T = {shamts_oh_4, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_5_next = _shamts_oh_5_T_1 ? 2'h1 : _shamts_oh_5_T_4 ? _shamts_oh_5_next_T[1:0] : shamts_oh_4; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_6 = shamts_oh_6_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_6_T = ~(|shamts_oh_5); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_6_T_1 = _shamts_oh_6_T & vacants_5; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_6_T_2 = shamts_oh_5[1]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_6_T_3 = ~_shamts_oh_6_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_6_T_4 = _shamts_oh_6_T_3 & vacants_5; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [2:0] _shamts_oh_6_next_T = {shamts_oh_5, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_6_next = _shamts_oh_6_T_1 ? 2'h1 : _shamts_oh_6_T_4 ? _shamts_oh_6_next_T[1:0] : shamts_oh_5; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_7 = shamts_oh_7_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_7_T = ~(|shamts_oh_6); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_7_T_1 = _shamts_oh_7_T & vacants_6; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_7_T_2 = shamts_oh_6[1]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_7_T_3 = ~_shamts_oh_7_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_7_T_4 = _shamts_oh_7_T_3 & vacants_6; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [2:0] _shamts_oh_7_next_T = {shamts_oh_6, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_7_next = _shamts_oh_7_T_1 ? 2'h1 : _shamts_oh_7_T_4 ? _shamts_oh_7_next_T[1:0] : shamts_oh_6; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_8 = shamts_oh_8_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_8_T = ~(|shamts_oh_7); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_8_T_1 = _shamts_oh_8_T & vacants_7; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_8_T_2 = shamts_oh_7[1]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_8_T_3 = ~_shamts_oh_8_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_8_T_4 = _shamts_oh_8_T_3 & vacants_7; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [2:0] _shamts_oh_8_next_T = {shamts_oh_7, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_8_next = _shamts_oh_8_T_1 ? 2'h1 : _shamts_oh_8_T_4 ? _shamts_oh_8_next_T[1:0] : shamts_oh_7; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_9 = shamts_oh_9_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_9_T = ~(|shamts_oh_8); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_9_T_1 = _shamts_oh_9_T & vacants_8; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_9_T_2 = shamts_oh_8[1]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_9_T_3 = ~_shamts_oh_9_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_9_T_4 = _shamts_oh_9_T_3 & vacants_8; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [2:0] _shamts_oh_9_next_T = {shamts_oh_8, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_9_next = _shamts_oh_9_T_1 ? 2'h1 : _shamts_oh_9_T_4 ? _shamts_oh_9_next_T[1:0] : shamts_oh_8; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_10 = shamts_oh_10_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_10_T = ~(|shamts_oh_9); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_10_T_1 = _shamts_oh_10_T & vacants_9; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_10_T_2 = shamts_oh_9[1]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_10_T_3 = ~_shamts_oh_10_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_10_T_4 = _shamts_oh_10_T_3 & vacants_9; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [2:0] _shamts_oh_10_next_T = {shamts_oh_9, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_10_next = _shamts_oh_10_T_1 ? 2'h1 : _shamts_oh_10_T_4 ? _shamts_oh_10_next_T[1:0] : shamts_oh_9; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_11 = shamts_oh_11_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_11_T = ~(|shamts_oh_10); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_11_T_1 = _shamts_oh_11_T & vacants_10; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_11_T_2 = shamts_oh_10[1]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_11_T_3 = ~_shamts_oh_11_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_11_T_4 = _shamts_oh_11_T_3 & vacants_10; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [2:0] _shamts_oh_11_next_T = {shamts_oh_10, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_11_next = _shamts_oh_11_T_1 ? 2'h1 : _shamts_oh_11_T_4 ? _shamts_oh_11_next_T[1:0] : shamts_oh_10; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_12 = shamts_oh_12_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_12_T = ~(|shamts_oh_11); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_12_T_1 = _shamts_oh_12_T & vacants_11; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_12_T_2 = shamts_oh_11[1]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_12_T_3 = ~_shamts_oh_12_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_12_T_4 = _shamts_oh_12_T_3 & vacants_11; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [2:0] _shamts_oh_12_next_T = {shamts_oh_11, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_12_next = _shamts_oh_12_T_1 ? 2'h1 : _shamts_oh_12_T_4 ? _shamts_oh_12_next_T[1:0] : shamts_oh_11; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_13 = shamts_oh_13_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_13_T = shamts_oh_12 == 2'h0; // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_13_T_1 = _shamts_oh_13_T & vacants_12; // @[issue-unit-age-ordered.scala:157:82, :163:{21,29}] wire _shamts_oh_13_T_2 = shamts_oh_12[1]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_13_T_3 = ~_shamts_oh_13_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_13_T_4 = _shamts_oh_13_T_3 & vacants_12; // @[issue-unit-age-ordered.scala:157:82, :165:{19,36}] wire [2:0] _shamts_oh_13_next_T = {shamts_oh_12, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_13_next = _shamts_oh_13_T_1 ? 2'h1 : _shamts_oh_13_T_4 ? _shamts_oh_13_next_T[1:0] : shamts_oh_12; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] wire _will_be_valid_T = ~io_dis_uops_0_bits_exception_0; // @[issue-unit-age-ordered.scala:22:7, :185:57] wire _will_be_valid_T_1 = io_dis_uops_0_valid_0 & _will_be_valid_T; // @[issue-unit-age-ordered.scala:22:7, :184:77, :185:57] wire _will_be_valid_T_2 = ~io_dis_uops_0_bits_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :186:57] wire _will_be_valid_T_3 = _will_be_valid_T_1 & _will_be_valid_T_2; // @[issue-unit-age-ordered.scala:184:77, :185:80, :186:57] wire _will_be_valid_T_4 = ~io_dis_uops_0_bits_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :187:57] wire will_be_valid_12 = _will_be_valid_T_3 & _will_be_valid_T_4; // @[issue-unit-age-ordered.scala:185:80, :186:79, :187:57] wire _will_be_valid_T_5 = ~io_dis_uops_1_bits_exception_0; // @[issue-unit-age-ordered.scala:22:7, :185:57] wire _will_be_valid_T_6 = io_dis_uops_1_valid_0 & _will_be_valid_T_5; // @[issue-unit-age-ordered.scala:22:7, :184:77, :185:57] wire _will_be_valid_T_7 = ~io_dis_uops_1_bits_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :186:57] wire _will_be_valid_T_8 = _will_be_valid_T_6 & _will_be_valid_T_7; // @[issue-unit-age-ordered.scala:184:77, :185:80, :186:57] wire _will_be_valid_T_9 = ~io_dis_uops_1_bits_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :187:57] wire will_be_valid_13 = _will_be_valid_T_8 & _will_be_valid_T_9; // @[issue-unit-age-ordered.scala:185:80, :186:79, :187:57] wire _T_159 = shamts_oh_2 == 2'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_0_in_uop_valid = _T_159 ? issue_slots_2_will_be_valid : shamts_oh_1 == 2'h1 & issue_slots_1_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_0_in_uop_bits_debug_tsrc = _T_159 ? issue_slots_2_out_uop_debug_tsrc : issue_slots_1_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_debug_fsrc = _T_159 ? issue_slots_2_out_uop_debug_fsrc : issue_slots_1_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_bp_xcpt_if = _T_159 ? issue_slots_2_out_uop_bp_xcpt_if : issue_slots_1_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_bp_debug_if = _T_159 ? issue_slots_2_out_uop_bp_debug_if : issue_slots_1_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_xcpt_ma_if = _T_159 ? issue_slots_2_out_uop_xcpt_ma_if : issue_slots_1_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_xcpt_ae_if = _T_159 ? issue_slots_2_out_uop_xcpt_ae_if : issue_slots_1_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_xcpt_pf_if = _T_159 ? issue_slots_2_out_uop_xcpt_pf_if : issue_slots_1_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_typ = _T_159 ? issue_slots_2_out_uop_fp_typ : issue_slots_1_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_rm = _T_159 ? issue_slots_2_out_uop_fp_rm : issue_slots_1_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_val = _T_159 ? issue_slots_2_out_uop_fp_val : issue_slots_1_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fcn_op = _T_159 ? issue_slots_2_out_uop_fcn_op : issue_slots_1_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fcn_dw = _T_159 ? issue_slots_2_out_uop_fcn_dw : issue_slots_1_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_frs3_en = _T_159 ? issue_slots_2_out_uop_frs3_en : issue_slots_1_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_lrs2_rtype = _T_159 ? issue_slots_2_out_uop_lrs2_rtype : issue_slots_1_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_lrs1_rtype = _T_159 ? issue_slots_2_out_uop_lrs1_rtype : issue_slots_1_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_dst_rtype = _T_159 ? issue_slots_2_out_uop_dst_rtype : issue_slots_1_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_lrs3 = _T_159 ? issue_slots_2_out_uop_lrs3 : issue_slots_1_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_lrs2 = _T_159 ? issue_slots_2_out_uop_lrs2 : issue_slots_1_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_lrs1 = _T_159 ? issue_slots_2_out_uop_lrs1 : issue_slots_1_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_ldst = _T_159 ? issue_slots_2_out_uop_ldst : issue_slots_1_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_ldst_is_rs1 = _T_159 ? issue_slots_2_out_uop_ldst_is_rs1 : issue_slots_1_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_csr_cmd = _T_159 ? issue_slots_2_out_uop_csr_cmd : issue_slots_1_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_flush_on_commit = _T_159 ? issue_slots_2_out_uop_flush_on_commit : issue_slots_1_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_unique = _T_159 ? issue_slots_2_out_uop_is_unique : issue_slots_1_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_uses_stq = _T_159 ? issue_slots_2_out_uop_uses_stq : issue_slots_1_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_uses_ldq = _T_159 ? issue_slots_2_out_uop_uses_ldq : issue_slots_1_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_mem_signed = _T_159 ? issue_slots_2_out_uop_mem_signed : issue_slots_1_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_mem_size = _T_159 ? issue_slots_2_out_uop_mem_size : issue_slots_1_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_mem_cmd = _T_159 ? issue_slots_2_out_uop_mem_cmd : issue_slots_1_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_exc_cause = _T_159 ? issue_slots_2_out_uop_exc_cause : issue_slots_1_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_exception = _T_159 ? issue_slots_2_out_uop_exception : issue_slots_1_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_stale_pdst = _T_159 ? issue_slots_2_out_uop_stale_pdst : issue_slots_1_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_ppred_busy = _T_159 ? issue_slots_2_out_uop_ppred_busy : issue_slots_1_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_prs3_busy = _T_159 ? issue_slots_2_out_uop_prs3_busy : issue_slots_1_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_prs2_busy = _T_159 ? issue_slots_2_out_uop_prs2_busy : issue_slots_1_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_prs1_busy = _T_159 ? issue_slots_2_out_uop_prs1_busy : issue_slots_1_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_ppred = _T_159 ? issue_slots_2_out_uop_ppred : issue_slots_1_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_prs3 = _T_159 ? issue_slots_2_out_uop_prs3 : issue_slots_1_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_prs2 = _T_159 ? issue_slots_2_out_uop_prs2 : issue_slots_1_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_prs1 = _T_159 ? issue_slots_2_out_uop_prs1 : issue_slots_1_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_pdst = _T_159 ? issue_slots_2_out_uop_pdst : issue_slots_1_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_rxq_idx = _T_159 ? issue_slots_2_out_uop_rxq_idx : issue_slots_1_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_stq_idx = _T_159 ? issue_slots_2_out_uop_stq_idx : issue_slots_1_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_ldq_idx = _T_159 ? issue_slots_2_out_uop_ldq_idx : issue_slots_1_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_rob_idx = _T_159 ? issue_slots_2_out_uop_rob_idx : issue_slots_1_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_vec = _T_159 ? issue_slots_2_out_uop_fp_ctrl_vec : issue_slots_1_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_wflags = _T_159 ? issue_slots_2_out_uop_fp_ctrl_wflags : issue_slots_1_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_sqrt = _T_159 ? issue_slots_2_out_uop_fp_ctrl_sqrt : issue_slots_1_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_div = _T_159 ? issue_slots_2_out_uop_fp_ctrl_div : issue_slots_1_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_fma = _T_159 ? issue_slots_2_out_uop_fp_ctrl_fma : issue_slots_1_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_fastpipe = _T_159 ? issue_slots_2_out_uop_fp_ctrl_fastpipe : issue_slots_1_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_toint = _T_159 ? issue_slots_2_out_uop_fp_ctrl_toint : issue_slots_1_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_fromint = _T_159 ? issue_slots_2_out_uop_fp_ctrl_fromint : issue_slots_1_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_typeTagOut = _T_159 ? issue_slots_2_out_uop_fp_ctrl_typeTagOut : issue_slots_1_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_typeTagIn = _T_159 ? issue_slots_2_out_uop_fp_ctrl_typeTagIn : issue_slots_1_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_swap23 = _T_159 ? issue_slots_2_out_uop_fp_ctrl_swap23 : issue_slots_1_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_swap12 = _T_159 ? issue_slots_2_out_uop_fp_ctrl_swap12 : issue_slots_1_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_ren3 = _T_159 ? issue_slots_2_out_uop_fp_ctrl_ren3 : issue_slots_1_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_ren2 = _T_159 ? issue_slots_2_out_uop_fp_ctrl_ren2 : issue_slots_1_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_ren1 = _T_159 ? issue_slots_2_out_uop_fp_ctrl_ren1 : issue_slots_1_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_wen = _T_159 ? issue_slots_2_out_uop_fp_ctrl_wen : issue_slots_1_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_ldst = _T_159 ? issue_slots_2_out_uop_fp_ctrl_ldst : issue_slots_1_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_op2_sel = _T_159 ? issue_slots_2_out_uop_op2_sel : issue_slots_1_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_op1_sel = _T_159 ? issue_slots_2_out_uop_op1_sel : issue_slots_1_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_imm_packed = _T_159 ? issue_slots_2_out_uop_imm_packed : issue_slots_1_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_pimm = _T_159 ? issue_slots_2_out_uop_pimm : issue_slots_1_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_imm_sel = _T_159 ? issue_slots_2_out_uop_imm_sel : issue_slots_1_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_imm_rename = _T_159 ? issue_slots_2_out_uop_imm_rename : issue_slots_1_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_taken = _T_159 ? issue_slots_2_out_uop_taken : issue_slots_1_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_pc_lob = _T_159 ? issue_slots_2_out_uop_pc_lob : issue_slots_1_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_edge_inst = _T_159 ? issue_slots_2_out_uop_edge_inst : issue_slots_1_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_ftq_idx = _T_159 ? issue_slots_2_out_uop_ftq_idx : issue_slots_1_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_mov = _T_159 ? issue_slots_2_out_uop_is_mov : issue_slots_1_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_rocc = _T_159 ? issue_slots_2_out_uop_is_rocc : issue_slots_1_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_sys_pc2epc = _T_159 ? issue_slots_2_out_uop_is_sys_pc2epc : issue_slots_1_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_eret = _T_159 ? issue_slots_2_out_uop_is_eret : issue_slots_1_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_amo = _T_159 ? issue_slots_2_out_uop_is_amo : issue_slots_1_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_sfence = _T_159 ? issue_slots_2_out_uop_is_sfence : issue_slots_1_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_fencei = _T_159 ? issue_slots_2_out_uop_is_fencei : issue_slots_1_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_fence = _T_159 ? issue_slots_2_out_uop_is_fence : issue_slots_1_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_sfb = _T_159 ? issue_slots_2_out_uop_is_sfb : issue_slots_1_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_br_type = _T_159 ? issue_slots_2_out_uop_br_type : issue_slots_1_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_br_tag = _T_159 ? issue_slots_2_out_uop_br_tag : issue_slots_1_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_br_mask = _T_159 ? issue_slots_2_out_uop_br_mask : issue_slots_1_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_dis_col_sel = _T_159 ? issue_slots_2_out_uop_dis_col_sel : issue_slots_1_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_iw_p3_bypass_hint = _T_159 ? issue_slots_2_out_uop_iw_p3_bypass_hint : issue_slots_1_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_iw_p2_bypass_hint = _T_159 ? issue_slots_2_out_uop_iw_p2_bypass_hint : issue_slots_1_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_iw_p1_bypass_hint = _T_159 ? issue_slots_2_out_uop_iw_p1_bypass_hint : issue_slots_1_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_iw_p2_speculative_child = _T_159 ? issue_slots_2_out_uop_iw_p2_speculative_child : issue_slots_1_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_iw_p1_speculative_child = _T_159 ? issue_slots_2_out_uop_iw_p1_speculative_child : issue_slots_1_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_iw_issued = _T_159 ? issue_slots_2_out_uop_iw_issued : issue_slots_1_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_0 = _T_159 ? issue_slots_2_out_uop_fu_code_0 : issue_slots_1_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_1 = _T_159 ? issue_slots_2_out_uop_fu_code_1 : issue_slots_1_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_2 = _T_159 ? issue_slots_2_out_uop_fu_code_2 : issue_slots_1_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_3 = _T_159 ? issue_slots_2_out_uop_fu_code_3 : issue_slots_1_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_4 = _T_159 ? issue_slots_2_out_uop_fu_code_4 : issue_slots_1_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_5 = _T_159 ? issue_slots_2_out_uop_fu_code_5 : issue_slots_1_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_6 = _T_159 ? issue_slots_2_out_uop_fu_code_6 : issue_slots_1_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_7 = _T_159 ? issue_slots_2_out_uop_fu_code_7 : issue_slots_1_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_8 = _T_159 ? issue_slots_2_out_uop_fu_code_8 : issue_slots_1_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_9 = _T_159 ? issue_slots_2_out_uop_fu_code_9 : issue_slots_1_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_iq_type_0 = _T_159 ? issue_slots_2_out_uop_iq_type_0 : issue_slots_1_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_iq_type_1 = _T_159 ? issue_slots_2_out_uop_iq_type_1 : issue_slots_1_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_iq_type_2 = _T_159 ? issue_slots_2_out_uop_iq_type_2 : issue_slots_1_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_iq_type_3 = _T_159 ? issue_slots_2_out_uop_iq_type_3 : issue_slots_1_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_debug_pc = _T_159 ? issue_slots_2_out_uop_debug_pc : issue_slots_1_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_rvc = _T_159 ? issue_slots_2_out_uop_is_rvc : issue_slots_1_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_debug_inst = _T_159 ? issue_slots_2_out_uop_debug_inst : issue_slots_1_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_inst = _T_159 ? issue_slots_2_out_uop_inst : issue_slots_1_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] wire _T_161 = shamts_oh_3 == 2'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_1_in_uop_valid = _T_161 ? issue_slots_3_will_be_valid : shamts_oh_2 == 2'h1 & issue_slots_2_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_1_in_uop_bits_debug_tsrc = _T_161 ? issue_slots_3_out_uop_debug_tsrc : issue_slots_2_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_debug_fsrc = _T_161 ? issue_slots_3_out_uop_debug_fsrc : issue_slots_2_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_bp_xcpt_if = _T_161 ? issue_slots_3_out_uop_bp_xcpt_if : issue_slots_2_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_bp_debug_if = _T_161 ? issue_slots_3_out_uop_bp_debug_if : issue_slots_2_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_xcpt_ma_if = _T_161 ? issue_slots_3_out_uop_xcpt_ma_if : issue_slots_2_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_xcpt_ae_if = _T_161 ? issue_slots_3_out_uop_xcpt_ae_if : issue_slots_2_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_xcpt_pf_if = _T_161 ? issue_slots_3_out_uop_xcpt_pf_if : issue_slots_2_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_typ = _T_161 ? issue_slots_3_out_uop_fp_typ : issue_slots_2_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_rm = _T_161 ? issue_slots_3_out_uop_fp_rm : issue_slots_2_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_val = _T_161 ? issue_slots_3_out_uop_fp_val : issue_slots_2_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fcn_op = _T_161 ? issue_slots_3_out_uop_fcn_op : issue_slots_2_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fcn_dw = _T_161 ? issue_slots_3_out_uop_fcn_dw : issue_slots_2_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_frs3_en = _T_161 ? issue_slots_3_out_uop_frs3_en : issue_slots_2_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_lrs2_rtype = _T_161 ? issue_slots_3_out_uop_lrs2_rtype : issue_slots_2_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_lrs1_rtype = _T_161 ? issue_slots_3_out_uop_lrs1_rtype : issue_slots_2_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_dst_rtype = _T_161 ? issue_slots_3_out_uop_dst_rtype : issue_slots_2_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_lrs3 = _T_161 ? issue_slots_3_out_uop_lrs3 : issue_slots_2_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_lrs2 = _T_161 ? issue_slots_3_out_uop_lrs2 : issue_slots_2_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_lrs1 = _T_161 ? issue_slots_3_out_uop_lrs1 : issue_slots_2_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_ldst = _T_161 ? issue_slots_3_out_uop_ldst : issue_slots_2_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_ldst_is_rs1 = _T_161 ? issue_slots_3_out_uop_ldst_is_rs1 : issue_slots_2_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_csr_cmd = _T_161 ? issue_slots_3_out_uop_csr_cmd : issue_slots_2_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_flush_on_commit = _T_161 ? issue_slots_3_out_uop_flush_on_commit : issue_slots_2_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_unique = _T_161 ? issue_slots_3_out_uop_is_unique : issue_slots_2_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_uses_stq = _T_161 ? issue_slots_3_out_uop_uses_stq : issue_slots_2_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_uses_ldq = _T_161 ? issue_slots_3_out_uop_uses_ldq : issue_slots_2_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_mem_signed = _T_161 ? issue_slots_3_out_uop_mem_signed : issue_slots_2_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_mem_size = _T_161 ? issue_slots_3_out_uop_mem_size : issue_slots_2_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_mem_cmd = _T_161 ? issue_slots_3_out_uop_mem_cmd : issue_slots_2_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_exc_cause = _T_161 ? issue_slots_3_out_uop_exc_cause : issue_slots_2_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_exception = _T_161 ? issue_slots_3_out_uop_exception : issue_slots_2_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_stale_pdst = _T_161 ? issue_slots_3_out_uop_stale_pdst : issue_slots_2_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_ppred_busy = _T_161 ? issue_slots_3_out_uop_ppred_busy : issue_slots_2_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_prs3_busy = _T_161 ? issue_slots_3_out_uop_prs3_busy : issue_slots_2_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_prs2_busy = _T_161 ? issue_slots_3_out_uop_prs2_busy : issue_slots_2_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_prs1_busy = _T_161 ? issue_slots_3_out_uop_prs1_busy : issue_slots_2_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_ppred = _T_161 ? issue_slots_3_out_uop_ppred : issue_slots_2_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_prs3 = _T_161 ? issue_slots_3_out_uop_prs3 : issue_slots_2_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_prs2 = _T_161 ? issue_slots_3_out_uop_prs2 : issue_slots_2_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_prs1 = _T_161 ? issue_slots_3_out_uop_prs1 : issue_slots_2_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_pdst = _T_161 ? issue_slots_3_out_uop_pdst : issue_slots_2_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_rxq_idx = _T_161 ? issue_slots_3_out_uop_rxq_idx : issue_slots_2_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_stq_idx = _T_161 ? issue_slots_3_out_uop_stq_idx : issue_slots_2_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_ldq_idx = _T_161 ? issue_slots_3_out_uop_ldq_idx : issue_slots_2_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_rob_idx = _T_161 ? issue_slots_3_out_uop_rob_idx : issue_slots_2_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_vec = _T_161 ? issue_slots_3_out_uop_fp_ctrl_vec : issue_slots_2_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_wflags = _T_161 ? issue_slots_3_out_uop_fp_ctrl_wflags : issue_slots_2_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_sqrt = _T_161 ? issue_slots_3_out_uop_fp_ctrl_sqrt : issue_slots_2_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_div = _T_161 ? issue_slots_3_out_uop_fp_ctrl_div : issue_slots_2_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_fma = _T_161 ? issue_slots_3_out_uop_fp_ctrl_fma : issue_slots_2_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_fastpipe = _T_161 ? issue_slots_3_out_uop_fp_ctrl_fastpipe : issue_slots_2_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_toint = _T_161 ? issue_slots_3_out_uop_fp_ctrl_toint : issue_slots_2_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_fromint = _T_161 ? issue_slots_3_out_uop_fp_ctrl_fromint : issue_slots_2_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_typeTagOut = _T_161 ? issue_slots_3_out_uop_fp_ctrl_typeTagOut : issue_slots_2_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_typeTagIn = _T_161 ? issue_slots_3_out_uop_fp_ctrl_typeTagIn : issue_slots_2_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_swap23 = _T_161 ? issue_slots_3_out_uop_fp_ctrl_swap23 : issue_slots_2_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_swap12 = _T_161 ? issue_slots_3_out_uop_fp_ctrl_swap12 : issue_slots_2_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_ren3 = _T_161 ? issue_slots_3_out_uop_fp_ctrl_ren3 : issue_slots_2_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_ren2 = _T_161 ? issue_slots_3_out_uop_fp_ctrl_ren2 : issue_slots_2_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_ren1 = _T_161 ? issue_slots_3_out_uop_fp_ctrl_ren1 : issue_slots_2_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_wen = _T_161 ? issue_slots_3_out_uop_fp_ctrl_wen : issue_slots_2_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_ldst = _T_161 ? issue_slots_3_out_uop_fp_ctrl_ldst : issue_slots_2_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_op2_sel = _T_161 ? issue_slots_3_out_uop_op2_sel : issue_slots_2_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_op1_sel = _T_161 ? issue_slots_3_out_uop_op1_sel : issue_slots_2_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_imm_packed = _T_161 ? issue_slots_3_out_uop_imm_packed : issue_slots_2_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_pimm = _T_161 ? issue_slots_3_out_uop_pimm : issue_slots_2_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_imm_sel = _T_161 ? issue_slots_3_out_uop_imm_sel : issue_slots_2_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_imm_rename = _T_161 ? issue_slots_3_out_uop_imm_rename : issue_slots_2_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_taken = _T_161 ? issue_slots_3_out_uop_taken : issue_slots_2_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_pc_lob = _T_161 ? issue_slots_3_out_uop_pc_lob : issue_slots_2_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_edge_inst = _T_161 ? issue_slots_3_out_uop_edge_inst : issue_slots_2_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_ftq_idx = _T_161 ? issue_slots_3_out_uop_ftq_idx : issue_slots_2_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_mov = _T_161 ? issue_slots_3_out_uop_is_mov : issue_slots_2_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_rocc = _T_161 ? issue_slots_3_out_uop_is_rocc : issue_slots_2_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_sys_pc2epc = _T_161 ? issue_slots_3_out_uop_is_sys_pc2epc : issue_slots_2_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_eret = _T_161 ? issue_slots_3_out_uop_is_eret : issue_slots_2_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_amo = _T_161 ? issue_slots_3_out_uop_is_amo : issue_slots_2_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_sfence = _T_161 ? issue_slots_3_out_uop_is_sfence : issue_slots_2_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_fencei = _T_161 ? issue_slots_3_out_uop_is_fencei : issue_slots_2_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_fence = _T_161 ? issue_slots_3_out_uop_is_fence : issue_slots_2_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_sfb = _T_161 ? issue_slots_3_out_uop_is_sfb : issue_slots_2_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_br_type = _T_161 ? issue_slots_3_out_uop_br_type : issue_slots_2_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_br_tag = _T_161 ? issue_slots_3_out_uop_br_tag : issue_slots_2_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_br_mask = _T_161 ? issue_slots_3_out_uop_br_mask : issue_slots_2_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_dis_col_sel = _T_161 ? issue_slots_3_out_uop_dis_col_sel : issue_slots_2_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_iw_p3_bypass_hint = _T_161 ? issue_slots_3_out_uop_iw_p3_bypass_hint : issue_slots_2_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_iw_p2_bypass_hint = _T_161 ? issue_slots_3_out_uop_iw_p2_bypass_hint : issue_slots_2_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_iw_p1_bypass_hint = _T_161 ? issue_slots_3_out_uop_iw_p1_bypass_hint : issue_slots_2_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_iw_p2_speculative_child = _T_161 ? issue_slots_3_out_uop_iw_p2_speculative_child : issue_slots_2_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_iw_p1_speculative_child = _T_161 ? issue_slots_3_out_uop_iw_p1_speculative_child : issue_slots_2_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_iw_issued = _T_161 ? issue_slots_3_out_uop_iw_issued : issue_slots_2_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_0 = _T_161 ? issue_slots_3_out_uop_fu_code_0 : issue_slots_2_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_1 = _T_161 ? issue_slots_3_out_uop_fu_code_1 : issue_slots_2_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_2 = _T_161 ? issue_slots_3_out_uop_fu_code_2 : issue_slots_2_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_3 = _T_161 ? issue_slots_3_out_uop_fu_code_3 : issue_slots_2_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_4 = _T_161 ? issue_slots_3_out_uop_fu_code_4 : issue_slots_2_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_5 = _T_161 ? issue_slots_3_out_uop_fu_code_5 : issue_slots_2_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_6 = _T_161 ? issue_slots_3_out_uop_fu_code_6 : issue_slots_2_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_7 = _T_161 ? issue_slots_3_out_uop_fu_code_7 : issue_slots_2_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_8 = _T_161 ? issue_slots_3_out_uop_fu_code_8 : issue_slots_2_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_9 = _T_161 ? issue_slots_3_out_uop_fu_code_9 : issue_slots_2_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_iq_type_0 = _T_161 ? issue_slots_3_out_uop_iq_type_0 : issue_slots_2_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_iq_type_1 = _T_161 ? issue_slots_3_out_uop_iq_type_1 : issue_slots_2_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_iq_type_2 = _T_161 ? issue_slots_3_out_uop_iq_type_2 : issue_slots_2_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_iq_type_3 = _T_161 ? issue_slots_3_out_uop_iq_type_3 : issue_slots_2_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_debug_pc = _T_161 ? issue_slots_3_out_uop_debug_pc : issue_slots_2_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_rvc = _T_161 ? issue_slots_3_out_uop_is_rvc : issue_slots_2_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_debug_inst = _T_161 ? issue_slots_3_out_uop_debug_inst : issue_slots_2_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_inst = _T_161 ? issue_slots_3_out_uop_inst : issue_slots_2_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_1_clear_T = |shamts_oh_1; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_1_clear = _issue_slots_1_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_163 = shamts_oh_4 == 2'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_2_in_uop_valid = _T_163 ? issue_slots_4_will_be_valid : shamts_oh_3 == 2'h1 & issue_slots_3_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_2_in_uop_bits_debug_tsrc = _T_163 ? issue_slots_4_out_uop_debug_tsrc : issue_slots_3_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_debug_fsrc = _T_163 ? issue_slots_4_out_uop_debug_fsrc : issue_slots_3_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_bp_xcpt_if = _T_163 ? issue_slots_4_out_uop_bp_xcpt_if : issue_slots_3_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_bp_debug_if = _T_163 ? issue_slots_4_out_uop_bp_debug_if : issue_slots_3_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_xcpt_ma_if = _T_163 ? issue_slots_4_out_uop_xcpt_ma_if : issue_slots_3_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_xcpt_ae_if = _T_163 ? issue_slots_4_out_uop_xcpt_ae_if : issue_slots_3_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_xcpt_pf_if = _T_163 ? issue_slots_4_out_uop_xcpt_pf_if : issue_slots_3_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_typ = _T_163 ? issue_slots_4_out_uop_fp_typ : issue_slots_3_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_rm = _T_163 ? issue_slots_4_out_uop_fp_rm : issue_slots_3_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_val = _T_163 ? issue_slots_4_out_uop_fp_val : issue_slots_3_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fcn_op = _T_163 ? issue_slots_4_out_uop_fcn_op : issue_slots_3_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fcn_dw = _T_163 ? issue_slots_4_out_uop_fcn_dw : issue_slots_3_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_frs3_en = _T_163 ? issue_slots_4_out_uop_frs3_en : issue_slots_3_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_lrs2_rtype = _T_163 ? issue_slots_4_out_uop_lrs2_rtype : issue_slots_3_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_lrs1_rtype = _T_163 ? issue_slots_4_out_uop_lrs1_rtype : issue_slots_3_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_dst_rtype = _T_163 ? issue_slots_4_out_uop_dst_rtype : issue_slots_3_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_lrs3 = _T_163 ? issue_slots_4_out_uop_lrs3 : issue_slots_3_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_lrs2 = _T_163 ? issue_slots_4_out_uop_lrs2 : issue_slots_3_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_lrs1 = _T_163 ? issue_slots_4_out_uop_lrs1 : issue_slots_3_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_ldst = _T_163 ? issue_slots_4_out_uop_ldst : issue_slots_3_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_ldst_is_rs1 = _T_163 ? issue_slots_4_out_uop_ldst_is_rs1 : issue_slots_3_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_csr_cmd = _T_163 ? issue_slots_4_out_uop_csr_cmd : issue_slots_3_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_flush_on_commit = _T_163 ? issue_slots_4_out_uop_flush_on_commit : issue_slots_3_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_unique = _T_163 ? issue_slots_4_out_uop_is_unique : issue_slots_3_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_uses_stq = _T_163 ? issue_slots_4_out_uop_uses_stq : issue_slots_3_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_uses_ldq = _T_163 ? issue_slots_4_out_uop_uses_ldq : issue_slots_3_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_mem_signed = _T_163 ? issue_slots_4_out_uop_mem_signed : issue_slots_3_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_mem_size = _T_163 ? issue_slots_4_out_uop_mem_size : issue_slots_3_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_mem_cmd = _T_163 ? issue_slots_4_out_uop_mem_cmd : issue_slots_3_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_exc_cause = _T_163 ? issue_slots_4_out_uop_exc_cause : issue_slots_3_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_exception = _T_163 ? issue_slots_4_out_uop_exception : issue_slots_3_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_stale_pdst = _T_163 ? issue_slots_4_out_uop_stale_pdst : issue_slots_3_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_ppred_busy = _T_163 ? issue_slots_4_out_uop_ppred_busy : issue_slots_3_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_prs3_busy = _T_163 ? issue_slots_4_out_uop_prs3_busy : issue_slots_3_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_prs2_busy = _T_163 ? issue_slots_4_out_uop_prs2_busy : issue_slots_3_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_prs1_busy = _T_163 ? issue_slots_4_out_uop_prs1_busy : issue_slots_3_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_ppred = _T_163 ? issue_slots_4_out_uop_ppred : issue_slots_3_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_prs3 = _T_163 ? issue_slots_4_out_uop_prs3 : issue_slots_3_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_prs2 = _T_163 ? issue_slots_4_out_uop_prs2 : issue_slots_3_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_prs1 = _T_163 ? issue_slots_4_out_uop_prs1 : issue_slots_3_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_pdst = _T_163 ? issue_slots_4_out_uop_pdst : issue_slots_3_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_rxq_idx = _T_163 ? issue_slots_4_out_uop_rxq_idx : issue_slots_3_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_stq_idx = _T_163 ? issue_slots_4_out_uop_stq_idx : issue_slots_3_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_ldq_idx = _T_163 ? issue_slots_4_out_uop_ldq_idx : issue_slots_3_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_rob_idx = _T_163 ? issue_slots_4_out_uop_rob_idx : issue_slots_3_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_vec = _T_163 ? issue_slots_4_out_uop_fp_ctrl_vec : issue_slots_3_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_wflags = _T_163 ? issue_slots_4_out_uop_fp_ctrl_wflags : issue_slots_3_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_sqrt = _T_163 ? issue_slots_4_out_uop_fp_ctrl_sqrt : issue_slots_3_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_div = _T_163 ? issue_slots_4_out_uop_fp_ctrl_div : issue_slots_3_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_fma = _T_163 ? issue_slots_4_out_uop_fp_ctrl_fma : issue_slots_3_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_fastpipe = _T_163 ? issue_slots_4_out_uop_fp_ctrl_fastpipe : issue_slots_3_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_toint = _T_163 ? issue_slots_4_out_uop_fp_ctrl_toint : issue_slots_3_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_fromint = _T_163 ? issue_slots_4_out_uop_fp_ctrl_fromint : issue_slots_3_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_typeTagOut = _T_163 ? issue_slots_4_out_uop_fp_ctrl_typeTagOut : issue_slots_3_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_typeTagIn = _T_163 ? issue_slots_4_out_uop_fp_ctrl_typeTagIn : issue_slots_3_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_swap23 = _T_163 ? issue_slots_4_out_uop_fp_ctrl_swap23 : issue_slots_3_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_swap12 = _T_163 ? issue_slots_4_out_uop_fp_ctrl_swap12 : issue_slots_3_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_ren3 = _T_163 ? issue_slots_4_out_uop_fp_ctrl_ren3 : issue_slots_3_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_ren2 = _T_163 ? issue_slots_4_out_uop_fp_ctrl_ren2 : issue_slots_3_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_ren1 = _T_163 ? issue_slots_4_out_uop_fp_ctrl_ren1 : issue_slots_3_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_wen = _T_163 ? issue_slots_4_out_uop_fp_ctrl_wen : issue_slots_3_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_ldst = _T_163 ? issue_slots_4_out_uop_fp_ctrl_ldst : issue_slots_3_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_op2_sel = _T_163 ? issue_slots_4_out_uop_op2_sel : issue_slots_3_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_op1_sel = _T_163 ? issue_slots_4_out_uop_op1_sel : issue_slots_3_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_imm_packed = _T_163 ? issue_slots_4_out_uop_imm_packed : issue_slots_3_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_pimm = _T_163 ? issue_slots_4_out_uop_pimm : issue_slots_3_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_imm_sel = _T_163 ? issue_slots_4_out_uop_imm_sel : issue_slots_3_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_imm_rename = _T_163 ? issue_slots_4_out_uop_imm_rename : issue_slots_3_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_taken = _T_163 ? issue_slots_4_out_uop_taken : issue_slots_3_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_pc_lob = _T_163 ? issue_slots_4_out_uop_pc_lob : issue_slots_3_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_edge_inst = _T_163 ? issue_slots_4_out_uop_edge_inst : issue_slots_3_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_ftq_idx = _T_163 ? issue_slots_4_out_uop_ftq_idx : issue_slots_3_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_mov = _T_163 ? issue_slots_4_out_uop_is_mov : issue_slots_3_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_rocc = _T_163 ? issue_slots_4_out_uop_is_rocc : issue_slots_3_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_sys_pc2epc = _T_163 ? issue_slots_4_out_uop_is_sys_pc2epc : issue_slots_3_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_eret = _T_163 ? issue_slots_4_out_uop_is_eret : issue_slots_3_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_amo = _T_163 ? issue_slots_4_out_uop_is_amo : issue_slots_3_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_sfence = _T_163 ? issue_slots_4_out_uop_is_sfence : issue_slots_3_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_fencei = _T_163 ? issue_slots_4_out_uop_is_fencei : issue_slots_3_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_fence = _T_163 ? issue_slots_4_out_uop_is_fence : issue_slots_3_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_sfb = _T_163 ? issue_slots_4_out_uop_is_sfb : issue_slots_3_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_br_type = _T_163 ? issue_slots_4_out_uop_br_type : issue_slots_3_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_br_tag = _T_163 ? issue_slots_4_out_uop_br_tag : issue_slots_3_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_br_mask = _T_163 ? issue_slots_4_out_uop_br_mask : issue_slots_3_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_dis_col_sel = _T_163 ? issue_slots_4_out_uop_dis_col_sel : issue_slots_3_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_iw_p3_bypass_hint = _T_163 ? issue_slots_4_out_uop_iw_p3_bypass_hint : issue_slots_3_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_iw_p2_bypass_hint = _T_163 ? issue_slots_4_out_uop_iw_p2_bypass_hint : issue_slots_3_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_iw_p1_bypass_hint = _T_163 ? issue_slots_4_out_uop_iw_p1_bypass_hint : issue_slots_3_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_iw_p2_speculative_child = _T_163 ? issue_slots_4_out_uop_iw_p2_speculative_child : issue_slots_3_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_iw_p1_speculative_child = _T_163 ? issue_slots_4_out_uop_iw_p1_speculative_child : issue_slots_3_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_iw_issued = _T_163 ? issue_slots_4_out_uop_iw_issued : issue_slots_3_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_0 = _T_163 ? issue_slots_4_out_uop_fu_code_0 : issue_slots_3_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_1 = _T_163 ? issue_slots_4_out_uop_fu_code_1 : issue_slots_3_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_2 = _T_163 ? issue_slots_4_out_uop_fu_code_2 : issue_slots_3_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_3 = _T_163 ? issue_slots_4_out_uop_fu_code_3 : issue_slots_3_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_4 = _T_163 ? issue_slots_4_out_uop_fu_code_4 : issue_slots_3_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_5 = _T_163 ? issue_slots_4_out_uop_fu_code_5 : issue_slots_3_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_6 = _T_163 ? issue_slots_4_out_uop_fu_code_6 : issue_slots_3_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_7 = _T_163 ? issue_slots_4_out_uop_fu_code_7 : issue_slots_3_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_8 = _T_163 ? issue_slots_4_out_uop_fu_code_8 : issue_slots_3_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_9 = _T_163 ? issue_slots_4_out_uop_fu_code_9 : issue_slots_3_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_iq_type_0 = _T_163 ? issue_slots_4_out_uop_iq_type_0 : issue_slots_3_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_iq_type_1 = _T_163 ? issue_slots_4_out_uop_iq_type_1 : issue_slots_3_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_iq_type_2 = _T_163 ? issue_slots_4_out_uop_iq_type_2 : issue_slots_3_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_iq_type_3 = _T_163 ? issue_slots_4_out_uop_iq_type_3 : issue_slots_3_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_debug_pc = _T_163 ? issue_slots_4_out_uop_debug_pc : issue_slots_3_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_rvc = _T_163 ? issue_slots_4_out_uop_is_rvc : issue_slots_3_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_debug_inst = _T_163 ? issue_slots_4_out_uop_debug_inst : issue_slots_3_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_inst = _T_163 ? issue_slots_4_out_uop_inst : issue_slots_3_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_2_clear_T = |shamts_oh_2; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_2_clear = _issue_slots_2_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_165 = shamts_oh_5 == 2'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_3_in_uop_valid = _T_165 ? issue_slots_5_will_be_valid : shamts_oh_4 == 2'h1 & issue_slots_4_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_3_in_uop_bits_debug_tsrc = _T_165 ? issue_slots_5_out_uop_debug_tsrc : issue_slots_4_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_debug_fsrc = _T_165 ? issue_slots_5_out_uop_debug_fsrc : issue_slots_4_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_bp_xcpt_if = _T_165 ? issue_slots_5_out_uop_bp_xcpt_if : issue_slots_4_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_bp_debug_if = _T_165 ? issue_slots_5_out_uop_bp_debug_if : issue_slots_4_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_xcpt_ma_if = _T_165 ? issue_slots_5_out_uop_xcpt_ma_if : issue_slots_4_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_xcpt_ae_if = _T_165 ? issue_slots_5_out_uop_xcpt_ae_if : issue_slots_4_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_xcpt_pf_if = _T_165 ? issue_slots_5_out_uop_xcpt_pf_if : issue_slots_4_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_typ = _T_165 ? issue_slots_5_out_uop_fp_typ : issue_slots_4_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_rm = _T_165 ? issue_slots_5_out_uop_fp_rm : issue_slots_4_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_val = _T_165 ? issue_slots_5_out_uop_fp_val : issue_slots_4_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fcn_op = _T_165 ? issue_slots_5_out_uop_fcn_op : issue_slots_4_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fcn_dw = _T_165 ? issue_slots_5_out_uop_fcn_dw : issue_slots_4_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_frs3_en = _T_165 ? issue_slots_5_out_uop_frs3_en : issue_slots_4_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_lrs2_rtype = _T_165 ? issue_slots_5_out_uop_lrs2_rtype : issue_slots_4_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_lrs1_rtype = _T_165 ? issue_slots_5_out_uop_lrs1_rtype : issue_slots_4_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_dst_rtype = _T_165 ? issue_slots_5_out_uop_dst_rtype : issue_slots_4_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_lrs3 = _T_165 ? issue_slots_5_out_uop_lrs3 : issue_slots_4_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_lrs2 = _T_165 ? issue_slots_5_out_uop_lrs2 : issue_slots_4_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_lrs1 = _T_165 ? issue_slots_5_out_uop_lrs1 : issue_slots_4_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_ldst = _T_165 ? issue_slots_5_out_uop_ldst : issue_slots_4_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_ldst_is_rs1 = _T_165 ? issue_slots_5_out_uop_ldst_is_rs1 : issue_slots_4_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_csr_cmd = _T_165 ? issue_slots_5_out_uop_csr_cmd : issue_slots_4_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_flush_on_commit = _T_165 ? issue_slots_5_out_uop_flush_on_commit : issue_slots_4_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_unique = _T_165 ? issue_slots_5_out_uop_is_unique : issue_slots_4_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_uses_stq = _T_165 ? issue_slots_5_out_uop_uses_stq : issue_slots_4_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_uses_ldq = _T_165 ? issue_slots_5_out_uop_uses_ldq : issue_slots_4_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_mem_signed = _T_165 ? issue_slots_5_out_uop_mem_signed : issue_slots_4_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_mem_size = _T_165 ? issue_slots_5_out_uop_mem_size : issue_slots_4_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_mem_cmd = _T_165 ? issue_slots_5_out_uop_mem_cmd : issue_slots_4_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_exc_cause = _T_165 ? issue_slots_5_out_uop_exc_cause : issue_slots_4_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_exception = _T_165 ? issue_slots_5_out_uop_exception : issue_slots_4_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_stale_pdst = _T_165 ? issue_slots_5_out_uop_stale_pdst : issue_slots_4_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_ppred_busy = _T_165 ? issue_slots_5_out_uop_ppred_busy : issue_slots_4_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_prs3_busy = _T_165 ? issue_slots_5_out_uop_prs3_busy : issue_slots_4_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_prs2_busy = _T_165 ? issue_slots_5_out_uop_prs2_busy : issue_slots_4_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_prs1_busy = _T_165 ? issue_slots_5_out_uop_prs1_busy : issue_slots_4_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_ppred = _T_165 ? issue_slots_5_out_uop_ppred : issue_slots_4_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_prs3 = _T_165 ? issue_slots_5_out_uop_prs3 : issue_slots_4_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_prs2 = _T_165 ? issue_slots_5_out_uop_prs2 : issue_slots_4_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_prs1 = _T_165 ? issue_slots_5_out_uop_prs1 : issue_slots_4_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_pdst = _T_165 ? issue_slots_5_out_uop_pdst : issue_slots_4_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_rxq_idx = _T_165 ? issue_slots_5_out_uop_rxq_idx : issue_slots_4_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_stq_idx = _T_165 ? issue_slots_5_out_uop_stq_idx : issue_slots_4_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_ldq_idx = _T_165 ? issue_slots_5_out_uop_ldq_idx : issue_slots_4_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_rob_idx = _T_165 ? issue_slots_5_out_uop_rob_idx : issue_slots_4_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_vec = _T_165 ? issue_slots_5_out_uop_fp_ctrl_vec : issue_slots_4_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_wflags = _T_165 ? issue_slots_5_out_uop_fp_ctrl_wflags : issue_slots_4_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_sqrt = _T_165 ? issue_slots_5_out_uop_fp_ctrl_sqrt : issue_slots_4_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_div = _T_165 ? issue_slots_5_out_uop_fp_ctrl_div : issue_slots_4_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_fma = _T_165 ? issue_slots_5_out_uop_fp_ctrl_fma : issue_slots_4_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_fastpipe = _T_165 ? issue_slots_5_out_uop_fp_ctrl_fastpipe : issue_slots_4_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_toint = _T_165 ? issue_slots_5_out_uop_fp_ctrl_toint : issue_slots_4_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_fromint = _T_165 ? issue_slots_5_out_uop_fp_ctrl_fromint : issue_slots_4_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_typeTagOut = _T_165 ? issue_slots_5_out_uop_fp_ctrl_typeTagOut : issue_slots_4_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_typeTagIn = _T_165 ? issue_slots_5_out_uop_fp_ctrl_typeTagIn : issue_slots_4_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_swap23 = _T_165 ? issue_slots_5_out_uop_fp_ctrl_swap23 : issue_slots_4_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_swap12 = _T_165 ? issue_slots_5_out_uop_fp_ctrl_swap12 : issue_slots_4_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_ren3 = _T_165 ? issue_slots_5_out_uop_fp_ctrl_ren3 : issue_slots_4_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_ren2 = _T_165 ? issue_slots_5_out_uop_fp_ctrl_ren2 : issue_slots_4_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_ren1 = _T_165 ? issue_slots_5_out_uop_fp_ctrl_ren1 : issue_slots_4_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_wen = _T_165 ? issue_slots_5_out_uop_fp_ctrl_wen : issue_slots_4_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_ldst = _T_165 ? issue_slots_5_out_uop_fp_ctrl_ldst : issue_slots_4_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_op2_sel = _T_165 ? issue_slots_5_out_uop_op2_sel : issue_slots_4_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_op1_sel = _T_165 ? issue_slots_5_out_uop_op1_sel : issue_slots_4_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_imm_packed = _T_165 ? issue_slots_5_out_uop_imm_packed : issue_slots_4_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_pimm = _T_165 ? issue_slots_5_out_uop_pimm : issue_slots_4_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_imm_sel = _T_165 ? issue_slots_5_out_uop_imm_sel : issue_slots_4_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_imm_rename = _T_165 ? issue_slots_5_out_uop_imm_rename : issue_slots_4_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_taken = _T_165 ? issue_slots_5_out_uop_taken : issue_slots_4_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_pc_lob = _T_165 ? issue_slots_5_out_uop_pc_lob : issue_slots_4_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_edge_inst = _T_165 ? issue_slots_5_out_uop_edge_inst : issue_slots_4_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_ftq_idx = _T_165 ? issue_slots_5_out_uop_ftq_idx : issue_slots_4_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_mov = _T_165 ? issue_slots_5_out_uop_is_mov : issue_slots_4_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_rocc = _T_165 ? issue_slots_5_out_uop_is_rocc : issue_slots_4_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_sys_pc2epc = _T_165 ? issue_slots_5_out_uop_is_sys_pc2epc : issue_slots_4_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_eret = _T_165 ? issue_slots_5_out_uop_is_eret : issue_slots_4_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_amo = _T_165 ? issue_slots_5_out_uop_is_amo : issue_slots_4_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_sfence = _T_165 ? issue_slots_5_out_uop_is_sfence : issue_slots_4_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_fencei = _T_165 ? issue_slots_5_out_uop_is_fencei : issue_slots_4_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_fence = _T_165 ? issue_slots_5_out_uop_is_fence : issue_slots_4_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_sfb = _T_165 ? issue_slots_5_out_uop_is_sfb : issue_slots_4_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_br_type = _T_165 ? issue_slots_5_out_uop_br_type : issue_slots_4_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_br_tag = _T_165 ? issue_slots_5_out_uop_br_tag : issue_slots_4_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_br_mask = _T_165 ? issue_slots_5_out_uop_br_mask : issue_slots_4_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_dis_col_sel = _T_165 ? issue_slots_5_out_uop_dis_col_sel : issue_slots_4_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_iw_p3_bypass_hint = _T_165 ? issue_slots_5_out_uop_iw_p3_bypass_hint : issue_slots_4_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_iw_p2_bypass_hint = _T_165 ? issue_slots_5_out_uop_iw_p2_bypass_hint : issue_slots_4_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_iw_p1_bypass_hint = _T_165 ? issue_slots_5_out_uop_iw_p1_bypass_hint : issue_slots_4_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_iw_p2_speculative_child = _T_165 ? issue_slots_5_out_uop_iw_p2_speculative_child : issue_slots_4_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_iw_p1_speculative_child = _T_165 ? issue_slots_5_out_uop_iw_p1_speculative_child : issue_slots_4_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_iw_issued = _T_165 ? issue_slots_5_out_uop_iw_issued : issue_slots_4_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_0 = _T_165 ? issue_slots_5_out_uop_fu_code_0 : issue_slots_4_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_1 = _T_165 ? issue_slots_5_out_uop_fu_code_1 : issue_slots_4_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_2 = _T_165 ? issue_slots_5_out_uop_fu_code_2 : issue_slots_4_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_3 = _T_165 ? issue_slots_5_out_uop_fu_code_3 : issue_slots_4_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_4 = _T_165 ? issue_slots_5_out_uop_fu_code_4 : issue_slots_4_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_5 = _T_165 ? issue_slots_5_out_uop_fu_code_5 : issue_slots_4_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_6 = _T_165 ? issue_slots_5_out_uop_fu_code_6 : issue_slots_4_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_7 = _T_165 ? issue_slots_5_out_uop_fu_code_7 : issue_slots_4_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_8 = _T_165 ? issue_slots_5_out_uop_fu_code_8 : issue_slots_4_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_9 = _T_165 ? issue_slots_5_out_uop_fu_code_9 : issue_slots_4_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_iq_type_0 = _T_165 ? issue_slots_5_out_uop_iq_type_0 : issue_slots_4_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_iq_type_1 = _T_165 ? issue_slots_5_out_uop_iq_type_1 : issue_slots_4_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_iq_type_2 = _T_165 ? issue_slots_5_out_uop_iq_type_2 : issue_slots_4_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_iq_type_3 = _T_165 ? issue_slots_5_out_uop_iq_type_3 : issue_slots_4_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_debug_pc = _T_165 ? issue_slots_5_out_uop_debug_pc : issue_slots_4_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_rvc = _T_165 ? issue_slots_5_out_uop_is_rvc : issue_slots_4_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_debug_inst = _T_165 ? issue_slots_5_out_uop_debug_inst : issue_slots_4_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_inst = _T_165 ? issue_slots_5_out_uop_inst : issue_slots_4_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_3_clear_T = |shamts_oh_3; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_3_clear = _issue_slots_3_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_167 = shamts_oh_6 == 2'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_4_in_uop_valid = _T_167 ? issue_slots_6_will_be_valid : shamts_oh_5 == 2'h1 & issue_slots_5_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_4_in_uop_bits_debug_tsrc = _T_167 ? issue_slots_6_out_uop_debug_tsrc : issue_slots_5_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_debug_fsrc = _T_167 ? issue_slots_6_out_uop_debug_fsrc : issue_slots_5_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_bp_xcpt_if = _T_167 ? issue_slots_6_out_uop_bp_xcpt_if : issue_slots_5_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_bp_debug_if = _T_167 ? issue_slots_6_out_uop_bp_debug_if : issue_slots_5_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_xcpt_ma_if = _T_167 ? issue_slots_6_out_uop_xcpt_ma_if : issue_slots_5_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_xcpt_ae_if = _T_167 ? issue_slots_6_out_uop_xcpt_ae_if : issue_slots_5_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_xcpt_pf_if = _T_167 ? issue_slots_6_out_uop_xcpt_pf_if : issue_slots_5_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_typ = _T_167 ? issue_slots_6_out_uop_fp_typ : issue_slots_5_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_rm = _T_167 ? issue_slots_6_out_uop_fp_rm : issue_slots_5_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_val = _T_167 ? issue_slots_6_out_uop_fp_val : issue_slots_5_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fcn_op = _T_167 ? issue_slots_6_out_uop_fcn_op : issue_slots_5_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fcn_dw = _T_167 ? issue_slots_6_out_uop_fcn_dw : issue_slots_5_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_frs3_en = _T_167 ? issue_slots_6_out_uop_frs3_en : issue_slots_5_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_lrs2_rtype = _T_167 ? issue_slots_6_out_uop_lrs2_rtype : issue_slots_5_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_lrs1_rtype = _T_167 ? issue_slots_6_out_uop_lrs1_rtype : issue_slots_5_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_dst_rtype = _T_167 ? issue_slots_6_out_uop_dst_rtype : issue_slots_5_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_lrs3 = _T_167 ? issue_slots_6_out_uop_lrs3 : issue_slots_5_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_lrs2 = _T_167 ? issue_slots_6_out_uop_lrs2 : issue_slots_5_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_lrs1 = _T_167 ? issue_slots_6_out_uop_lrs1 : issue_slots_5_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_ldst = _T_167 ? issue_slots_6_out_uop_ldst : issue_slots_5_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_ldst_is_rs1 = _T_167 ? issue_slots_6_out_uop_ldst_is_rs1 : issue_slots_5_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_csr_cmd = _T_167 ? issue_slots_6_out_uop_csr_cmd : issue_slots_5_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_flush_on_commit = _T_167 ? issue_slots_6_out_uop_flush_on_commit : issue_slots_5_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_unique = _T_167 ? issue_slots_6_out_uop_is_unique : issue_slots_5_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_uses_stq = _T_167 ? issue_slots_6_out_uop_uses_stq : issue_slots_5_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_uses_ldq = _T_167 ? issue_slots_6_out_uop_uses_ldq : issue_slots_5_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_mem_signed = _T_167 ? issue_slots_6_out_uop_mem_signed : issue_slots_5_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_mem_size = _T_167 ? issue_slots_6_out_uop_mem_size : issue_slots_5_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_mem_cmd = _T_167 ? issue_slots_6_out_uop_mem_cmd : issue_slots_5_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_exc_cause = _T_167 ? issue_slots_6_out_uop_exc_cause : issue_slots_5_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_exception = _T_167 ? issue_slots_6_out_uop_exception : issue_slots_5_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_stale_pdst = _T_167 ? issue_slots_6_out_uop_stale_pdst : issue_slots_5_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_ppred_busy = _T_167 ? issue_slots_6_out_uop_ppred_busy : issue_slots_5_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_prs3_busy = _T_167 ? issue_slots_6_out_uop_prs3_busy : issue_slots_5_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_prs2_busy = _T_167 ? issue_slots_6_out_uop_prs2_busy : issue_slots_5_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_prs1_busy = _T_167 ? issue_slots_6_out_uop_prs1_busy : issue_slots_5_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_ppred = _T_167 ? issue_slots_6_out_uop_ppred : issue_slots_5_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_prs3 = _T_167 ? issue_slots_6_out_uop_prs3 : issue_slots_5_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_prs2 = _T_167 ? issue_slots_6_out_uop_prs2 : issue_slots_5_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_prs1 = _T_167 ? issue_slots_6_out_uop_prs1 : issue_slots_5_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_pdst = _T_167 ? issue_slots_6_out_uop_pdst : issue_slots_5_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_rxq_idx = _T_167 ? issue_slots_6_out_uop_rxq_idx : issue_slots_5_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_stq_idx = _T_167 ? issue_slots_6_out_uop_stq_idx : issue_slots_5_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_ldq_idx = _T_167 ? issue_slots_6_out_uop_ldq_idx : issue_slots_5_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_rob_idx = _T_167 ? issue_slots_6_out_uop_rob_idx : issue_slots_5_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_vec = _T_167 ? issue_slots_6_out_uop_fp_ctrl_vec : issue_slots_5_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_wflags = _T_167 ? issue_slots_6_out_uop_fp_ctrl_wflags : issue_slots_5_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_sqrt = _T_167 ? issue_slots_6_out_uop_fp_ctrl_sqrt : issue_slots_5_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_div = _T_167 ? issue_slots_6_out_uop_fp_ctrl_div : issue_slots_5_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_fma = _T_167 ? issue_slots_6_out_uop_fp_ctrl_fma : issue_slots_5_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_fastpipe = _T_167 ? issue_slots_6_out_uop_fp_ctrl_fastpipe : issue_slots_5_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_toint = _T_167 ? issue_slots_6_out_uop_fp_ctrl_toint : issue_slots_5_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_fromint = _T_167 ? issue_slots_6_out_uop_fp_ctrl_fromint : issue_slots_5_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_typeTagOut = _T_167 ? issue_slots_6_out_uop_fp_ctrl_typeTagOut : issue_slots_5_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_typeTagIn = _T_167 ? issue_slots_6_out_uop_fp_ctrl_typeTagIn : issue_slots_5_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_swap23 = _T_167 ? issue_slots_6_out_uop_fp_ctrl_swap23 : issue_slots_5_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_swap12 = _T_167 ? issue_slots_6_out_uop_fp_ctrl_swap12 : issue_slots_5_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_ren3 = _T_167 ? issue_slots_6_out_uop_fp_ctrl_ren3 : issue_slots_5_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_ren2 = _T_167 ? issue_slots_6_out_uop_fp_ctrl_ren2 : issue_slots_5_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_ren1 = _T_167 ? issue_slots_6_out_uop_fp_ctrl_ren1 : issue_slots_5_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_wen = _T_167 ? issue_slots_6_out_uop_fp_ctrl_wen : issue_slots_5_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_ldst = _T_167 ? issue_slots_6_out_uop_fp_ctrl_ldst : issue_slots_5_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_op2_sel = _T_167 ? issue_slots_6_out_uop_op2_sel : issue_slots_5_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_op1_sel = _T_167 ? issue_slots_6_out_uop_op1_sel : issue_slots_5_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_imm_packed = _T_167 ? issue_slots_6_out_uop_imm_packed : issue_slots_5_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_pimm = _T_167 ? issue_slots_6_out_uop_pimm : issue_slots_5_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_imm_sel = _T_167 ? issue_slots_6_out_uop_imm_sel : issue_slots_5_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_imm_rename = _T_167 ? issue_slots_6_out_uop_imm_rename : issue_slots_5_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_taken = _T_167 ? issue_slots_6_out_uop_taken : issue_slots_5_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_pc_lob = _T_167 ? issue_slots_6_out_uop_pc_lob : issue_slots_5_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_edge_inst = _T_167 ? issue_slots_6_out_uop_edge_inst : issue_slots_5_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_ftq_idx = _T_167 ? issue_slots_6_out_uop_ftq_idx : issue_slots_5_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_mov = _T_167 ? issue_slots_6_out_uop_is_mov : issue_slots_5_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_rocc = _T_167 ? issue_slots_6_out_uop_is_rocc : issue_slots_5_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_sys_pc2epc = _T_167 ? issue_slots_6_out_uop_is_sys_pc2epc : issue_slots_5_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_eret = _T_167 ? issue_slots_6_out_uop_is_eret : issue_slots_5_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_amo = _T_167 ? issue_slots_6_out_uop_is_amo : issue_slots_5_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_sfence = _T_167 ? issue_slots_6_out_uop_is_sfence : issue_slots_5_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_fencei = _T_167 ? issue_slots_6_out_uop_is_fencei : issue_slots_5_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_fence = _T_167 ? issue_slots_6_out_uop_is_fence : issue_slots_5_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_sfb = _T_167 ? issue_slots_6_out_uop_is_sfb : issue_slots_5_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_br_type = _T_167 ? issue_slots_6_out_uop_br_type : issue_slots_5_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_br_tag = _T_167 ? issue_slots_6_out_uop_br_tag : issue_slots_5_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_br_mask = _T_167 ? issue_slots_6_out_uop_br_mask : issue_slots_5_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_dis_col_sel = _T_167 ? issue_slots_6_out_uop_dis_col_sel : issue_slots_5_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_iw_p3_bypass_hint = _T_167 ? issue_slots_6_out_uop_iw_p3_bypass_hint : issue_slots_5_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_iw_p2_bypass_hint = _T_167 ? issue_slots_6_out_uop_iw_p2_bypass_hint : issue_slots_5_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_iw_p1_bypass_hint = _T_167 ? issue_slots_6_out_uop_iw_p1_bypass_hint : issue_slots_5_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_iw_p2_speculative_child = _T_167 ? issue_slots_6_out_uop_iw_p2_speculative_child : issue_slots_5_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_iw_p1_speculative_child = _T_167 ? issue_slots_6_out_uop_iw_p1_speculative_child : issue_slots_5_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_iw_issued = _T_167 ? issue_slots_6_out_uop_iw_issued : issue_slots_5_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_0 = _T_167 ? issue_slots_6_out_uop_fu_code_0 : issue_slots_5_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_1 = _T_167 ? issue_slots_6_out_uop_fu_code_1 : issue_slots_5_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_2 = _T_167 ? issue_slots_6_out_uop_fu_code_2 : issue_slots_5_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_3 = _T_167 ? issue_slots_6_out_uop_fu_code_3 : issue_slots_5_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_4 = _T_167 ? issue_slots_6_out_uop_fu_code_4 : issue_slots_5_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_5 = _T_167 ? issue_slots_6_out_uop_fu_code_5 : issue_slots_5_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_6 = _T_167 ? issue_slots_6_out_uop_fu_code_6 : issue_slots_5_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_7 = _T_167 ? issue_slots_6_out_uop_fu_code_7 : issue_slots_5_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_8 = _T_167 ? issue_slots_6_out_uop_fu_code_8 : issue_slots_5_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_9 = _T_167 ? issue_slots_6_out_uop_fu_code_9 : issue_slots_5_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_iq_type_0 = _T_167 ? issue_slots_6_out_uop_iq_type_0 : issue_slots_5_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_iq_type_1 = _T_167 ? issue_slots_6_out_uop_iq_type_1 : issue_slots_5_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_iq_type_2 = _T_167 ? issue_slots_6_out_uop_iq_type_2 : issue_slots_5_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_iq_type_3 = _T_167 ? issue_slots_6_out_uop_iq_type_3 : issue_slots_5_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_debug_pc = _T_167 ? issue_slots_6_out_uop_debug_pc : issue_slots_5_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_rvc = _T_167 ? issue_slots_6_out_uop_is_rvc : issue_slots_5_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_debug_inst = _T_167 ? issue_slots_6_out_uop_debug_inst : issue_slots_5_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_inst = _T_167 ? issue_slots_6_out_uop_inst : issue_slots_5_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_4_clear_T = |shamts_oh_4; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_4_clear = _issue_slots_4_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_169 = shamts_oh_7 == 2'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_5_in_uop_valid = _T_169 ? issue_slots_7_will_be_valid : shamts_oh_6 == 2'h1 & issue_slots_6_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_5_in_uop_bits_debug_tsrc = _T_169 ? issue_slots_7_out_uop_debug_tsrc : issue_slots_6_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_debug_fsrc = _T_169 ? issue_slots_7_out_uop_debug_fsrc : issue_slots_6_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_bp_xcpt_if = _T_169 ? issue_slots_7_out_uop_bp_xcpt_if : issue_slots_6_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_bp_debug_if = _T_169 ? issue_slots_7_out_uop_bp_debug_if : issue_slots_6_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_xcpt_ma_if = _T_169 ? issue_slots_7_out_uop_xcpt_ma_if : issue_slots_6_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_xcpt_ae_if = _T_169 ? issue_slots_7_out_uop_xcpt_ae_if : issue_slots_6_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_xcpt_pf_if = _T_169 ? issue_slots_7_out_uop_xcpt_pf_if : issue_slots_6_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_typ = _T_169 ? issue_slots_7_out_uop_fp_typ : issue_slots_6_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_rm = _T_169 ? issue_slots_7_out_uop_fp_rm : issue_slots_6_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_val = _T_169 ? issue_slots_7_out_uop_fp_val : issue_slots_6_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fcn_op = _T_169 ? issue_slots_7_out_uop_fcn_op : issue_slots_6_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fcn_dw = _T_169 ? issue_slots_7_out_uop_fcn_dw : issue_slots_6_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_frs3_en = _T_169 ? issue_slots_7_out_uop_frs3_en : issue_slots_6_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_lrs2_rtype = _T_169 ? issue_slots_7_out_uop_lrs2_rtype : issue_slots_6_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_lrs1_rtype = _T_169 ? issue_slots_7_out_uop_lrs1_rtype : issue_slots_6_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_dst_rtype = _T_169 ? issue_slots_7_out_uop_dst_rtype : issue_slots_6_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_lrs3 = _T_169 ? issue_slots_7_out_uop_lrs3 : issue_slots_6_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_lrs2 = _T_169 ? issue_slots_7_out_uop_lrs2 : issue_slots_6_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_lrs1 = _T_169 ? issue_slots_7_out_uop_lrs1 : issue_slots_6_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_ldst = _T_169 ? issue_slots_7_out_uop_ldst : issue_slots_6_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_ldst_is_rs1 = _T_169 ? issue_slots_7_out_uop_ldst_is_rs1 : issue_slots_6_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_csr_cmd = _T_169 ? issue_slots_7_out_uop_csr_cmd : issue_slots_6_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_flush_on_commit = _T_169 ? issue_slots_7_out_uop_flush_on_commit : issue_slots_6_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_unique = _T_169 ? issue_slots_7_out_uop_is_unique : issue_slots_6_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_uses_stq = _T_169 ? issue_slots_7_out_uop_uses_stq : issue_slots_6_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_uses_ldq = _T_169 ? issue_slots_7_out_uop_uses_ldq : issue_slots_6_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_mem_signed = _T_169 ? issue_slots_7_out_uop_mem_signed : issue_slots_6_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_mem_size = _T_169 ? issue_slots_7_out_uop_mem_size : issue_slots_6_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_mem_cmd = _T_169 ? issue_slots_7_out_uop_mem_cmd : issue_slots_6_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_exc_cause = _T_169 ? issue_slots_7_out_uop_exc_cause : issue_slots_6_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_exception = _T_169 ? issue_slots_7_out_uop_exception : issue_slots_6_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_stale_pdst = _T_169 ? issue_slots_7_out_uop_stale_pdst : issue_slots_6_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_ppred_busy = _T_169 ? issue_slots_7_out_uop_ppred_busy : issue_slots_6_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_prs3_busy = _T_169 ? issue_slots_7_out_uop_prs3_busy : issue_slots_6_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_prs2_busy = _T_169 ? issue_slots_7_out_uop_prs2_busy : issue_slots_6_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_prs1_busy = _T_169 ? issue_slots_7_out_uop_prs1_busy : issue_slots_6_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_ppred = _T_169 ? issue_slots_7_out_uop_ppred : issue_slots_6_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_prs3 = _T_169 ? issue_slots_7_out_uop_prs3 : issue_slots_6_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_prs2 = _T_169 ? issue_slots_7_out_uop_prs2 : issue_slots_6_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_prs1 = _T_169 ? issue_slots_7_out_uop_prs1 : issue_slots_6_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_pdst = _T_169 ? issue_slots_7_out_uop_pdst : issue_slots_6_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_rxq_idx = _T_169 ? issue_slots_7_out_uop_rxq_idx : issue_slots_6_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_stq_idx = _T_169 ? issue_slots_7_out_uop_stq_idx : issue_slots_6_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_ldq_idx = _T_169 ? issue_slots_7_out_uop_ldq_idx : issue_slots_6_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_rob_idx = _T_169 ? issue_slots_7_out_uop_rob_idx : issue_slots_6_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_vec = _T_169 ? issue_slots_7_out_uop_fp_ctrl_vec : issue_slots_6_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_wflags = _T_169 ? issue_slots_7_out_uop_fp_ctrl_wflags : issue_slots_6_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_sqrt = _T_169 ? issue_slots_7_out_uop_fp_ctrl_sqrt : issue_slots_6_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_div = _T_169 ? issue_slots_7_out_uop_fp_ctrl_div : issue_slots_6_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_fma = _T_169 ? issue_slots_7_out_uop_fp_ctrl_fma : issue_slots_6_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_fastpipe = _T_169 ? issue_slots_7_out_uop_fp_ctrl_fastpipe : issue_slots_6_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_toint = _T_169 ? issue_slots_7_out_uop_fp_ctrl_toint : issue_slots_6_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_fromint = _T_169 ? issue_slots_7_out_uop_fp_ctrl_fromint : issue_slots_6_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_typeTagOut = _T_169 ? issue_slots_7_out_uop_fp_ctrl_typeTagOut : issue_slots_6_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_typeTagIn = _T_169 ? issue_slots_7_out_uop_fp_ctrl_typeTagIn : issue_slots_6_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_swap23 = _T_169 ? issue_slots_7_out_uop_fp_ctrl_swap23 : issue_slots_6_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_swap12 = _T_169 ? issue_slots_7_out_uop_fp_ctrl_swap12 : issue_slots_6_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_ren3 = _T_169 ? issue_slots_7_out_uop_fp_ctrl_ren3 : issue_slots_6_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_ren2 = _T_169 ? issue_slots_7_out_uop_fp_ctrl_ren2 : issue_slots_6_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_ren1 = _T_169 ? issue_slots_7_out_uop_fp_ctrl_ren1 : issue_slots_6_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_wen = _T_169 ? issue_slots_7_out_uop_fp_ctrl_wen : issue_slots_6_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_ldst = _T_169 ? issue_slots_7_out_uop_fp_ctrl_ldst : issue_slots_6_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_op2_sel = _T_169 ? issue_slots_7_out_uop_op2_sel : issue_slots_6_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_op1_sel = _T_169 ? issue_slots_7_out_uop_op1_sel : issue_slots_6_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_imm_packed = _T_169 ? issue_slots_7_out_uop_imm_packed : issue_slots_6_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_pimm = _T_169 ? issue_slots_7_out_uop_pimm : issue_slots_6_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_imm_sel = _T_169 ? issue_slots_7_out_uop_imm_sel : issue_slots_6_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_imm_rename = _T_169 ? issue_slots_7_out_uop_imm_rename : issue_slots_6_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_taken = _T_169 ? issue_slots_7_out_uop_taken : issue_slots_6_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_pc_lob = _T_169 ? issue_slots_7_out_uop_pc_lob : issue_slots_6_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_edge_inst = _T_169 ? issue_slots_7_out_uop_edge_inst : issue_slots_6_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_ftq_idx = _T_169 ? issue_slots_7_out_uop_ftq_idx : issue_slots_6_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_mov = _T_169 ? issue_slots_7_out_uop_is_mov : issue_slots_6_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_rocc = _T_169 ? issue_slots_7_out_uop_is_rocc : issue_slots_6_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_sys_pc2epc = _T_169 ? issue_slots_7_out_uop_is_sys_pc2epc : issue_slots_6_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_eret = _T_169 ? issue_slots_7_out_uop_is_eret : issue_slots_6_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_amo = _T_169 ? issue_slots_7_out_uop_is_amo : issue_slots_6_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_sfence = _T_169 ? issue_slots_7_out_uop_is_sfence : issue_slots_6_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_fencei = _T_169 ? issue_slots_7_out_uop_is_fencei : issue_slots_6_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_fence = _T_169 ? issue_slots_7_out_uop_is_fence : issue_slots_6_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_sfb = _T_169 ? issue_slots_7_out_uop_is_sfb : issue_slots_6_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_br_type = _T_169 ? issue_slots_7_out_uop_br_type : issue_slots_6_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_br_tag = _T_169 ? issue_slots_7_out_uop_br_tag : issue_slots_6_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_br_mask = _T_169 ? issue_slots_7_out_uop_br_mask : issue_slots_6_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_dis_col_sel = _T_169 ? issue_slots_7_out_uop_dis_col_sel : issue_slots_6_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_iw_p3_bypass_hint = _T_169 ? issue_slots_7_out_uop_iw_p3_bypass_hint : issue_slots_6_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_iw_p2_bypass_hint = _T_169 ? issue_slots_7_out_uop_iw_p2_bypass_hint : issue_slots_6_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_iw_p1_bypass_hint = _T_169 ? issue_slots_7_out_uop_iw_p1_bypass_hint : issue_slots_6_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_iw_p2_speculative_child = _T_169 ? issue_slots_7_out_uop_iw_p2_speculative_child : issue_slots_6_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_iw_p1_speculative_child = _T_169 ? issue_slots_7_out_uop_iw_p1_speculative_child : issue_slots_6_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_iw_issued = _T_169 ? issue_slots_7_out_uop_iw_issued : issue_slots_6_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_0 = _T_169 ? issue_slots_7_out_uop_fu_code_0 : issue_slots_6_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_1 = _T_169 ? issue_slots_7_out_uop_fu_code_1 : issue_slots_6_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_2 = _T_169 ? issue_slots_7_out_uop_fu_code_2 : issue_slots_6_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_3 = _T_169 ? issue_slots_7_out_uop_fu_code_3 : issue_slots_6_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_4 = _T_169 ? issue_slots_7_out_uop_fu_code_4 : issue_slots_6_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_5 = _T_169 ? issue_slots_7_out_uop_fu_code_5 : issue_slots_6_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_6 = _T_169 ? issue_slots_7_out_uop_fu_code_6 : issue_slots_6_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_7 = _T_169 ? issue_slots_7_out_uop_fu_code_7 : issue_slots_6_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_8 = _T_169 ? issue_slots_7_out_uop_fu_code_8 : issue_slots_6_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_9 = _T_169 ? issue_slots_7_out_uop_fu_code_9 : issue_slots_6_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_iq_type_0 = _T_169 ? issue_slots_7_out_uop_iq_type_0 : issue_slots_6_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_iq_type_1 = _T_169 ? issue_slots_7_out_uop_iq_type_1 : issue_slots_6_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_iq_type_2 = _T_169 ? issue_slots_7_out_uop_iq_type_2 : issue_slots_6_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_iq_type_3 = _T_169 ? issue_slots_7_out_uop_iq_type_3 : issue_slots_6_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_debug_pc = _T_169 ? issue_slots_7_out_uop_debug_pc : issue_slots_6_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_rvc = _T_169 ? issue_slots_7_out_uop_is_rvc : issue_slots_6_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_debug_inst = _T_169 ? issue_slots_7_out_uop_debug_inst : issue_slots_6_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_inst = _T_169 ? issue_slots_7_out_uop_inst : issue_slots_6_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_5_clear_T = |shamts_oh_5; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_5_clear = _issue_slots_5_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_171 = shamts_oh_8 == 2'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_6_in_uop_valid = _T_171 ? issue_slots_8_will_be_valid : shamts_oh_7 == 2'h1 & issue_slots_7_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_6_in_uop_bits_debug_tsrc = _T_171 ? issue_slots_8_out_uop_debug_tsrc : issue_slots_7_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_debug_fsrc = _T_171 ? issue_slots_8_out_uop_debug_fsrc : issue_slots_7_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_bp_xcpt_if = _T_171 ? issue_slots_8_out_uop_bp_xcpt_if : issue_slots_7_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_bp_debug_if = _T_171 ? issue_slots_8_out_uop_bp_debug_if : issue_slots_7_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_xcpt_ma_if = _T_171 ? issue_slots_8_out_uop_xcpt_ma_if : issue_slots_7_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_xcpt_ae_if = _T_171 ? issue_slots_8_out_uop_xcpt_ae_if : issue_slots_7_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_xcpt_pf_if = _T_171 ? issue_slots_8_out_uop_xcpt_pf_if : issue_slots_7_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_typ = _T_171 ? issue_slots_8_out_uop_fp_typ : issue_slots_7_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_rm = _T_171 ? issue_slots_8_out_uop_fp_rm : issue_slots_7_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_val = _T_171 ? issue_slots_8_out_uop_fp_val : issue_slots_7_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fcn_op = _T_171 ? issue_slots_8_out_uop_fcn_op : issue_slots_7_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fcn_dw = _T_171 ? issue_slots_8_out_uop_fcn_dw : issue_slots_7_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_frs3_en = _T_171 ? issue_slots_8_out_uop_frs3_en : issue_slots_7_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_lrs2_rtype = _T_171 ? issue_slots_8_out_uop_lrs2_rtype : issue_slots_7_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_lrs1_rtype = _T_171 ? issue_slots_8_out_uop_lrs1_rtype : issue_slots_7_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_dst_rtype = _T_171 ? issue_slots_8_out_uop_dst_rtype : issue_slots_7_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_lrs3 = _T_171 ? issue_slots_8_out_uop_lrs3 : issue_slots_7_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_lrs2 = _T_171 ? issue_slots_8_out_uop_lrs2 : issue_slots_7_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_lrs1 = _T_171 ? issue_slots_8_out_uop_lrs1 : issue_slots_7_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_ldst = _T_171 ? issue_slots_8_out_uop_ldst : issue_slots_7_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_ldst_is_rs1 = _T_171 ? issue_slots_8_out_uop_ldst_is_rs1 : issue_slots_7_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_csr_cmd = _T_171 ? issue_slots_8_out_uop_csr_cmd : issue_slots_7_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_flush_on_commit = _T_171 ? issue_slots_8_out_uop_flush_on_commit : issue_slots_7_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_unique = _T_171 ? issue_slots_8_out_uop_is_unique : issue_slots_7_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_uses_stq = _T_171 ? issue_slots_8_out_uop_uses_stq : issue_slots_7_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_uses_ldq = _T_171 ? issue_slots_8_out_uop_uses_ldq : issue_slots_7_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_mem_signed = _T_171 ? issue_slots_8_out_uop_mem_signed : issue_slots_7_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_mem_size = _T_171 ? issue_slots_8_out_uop_mem_size : issue_slots_7_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_mem_cmd = _T_171 ? issue_slots_8_out_uop_mem_cmd : issue_slots_7_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_exc_cause = _T_171 ? issue_slots_8_out_uop_exc_cause : issue_slots_7_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_exception = _T_171 ? issue_slots_8_out_uop_exception : issue_slots_7_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_stale_pdst = _T_171 ? issue_slots_8_out_uop_stale_pdst : issue_slots_7_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_ppred_busy = _T_171 ? issue_slots_8_out_uop_ppred_busy : issue_slots_7_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_prs3_busy = _T_171 ? issue_slots_8_out_uop_prs3_busy : issue_slots_7_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_prs2_busy = _T_171 ? issue_slots_8_out_uop_prs2_busy : issue_slots_7_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_prs1_busy = _T_171 ? issue_slots_8_out_uop_prs1_busy : issue_slots_7_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_ppred = _T_171 ? issue_slots_8_out_uop_ppred : issue_slots_7_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_prs3 = _T_171 ? issue_slots_8_out_uop_prs3 : issue_slots_7_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_prs2 = _T_171 ? issue_slots_8_out_uop_prs2 : issue_slots_7_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_prs1 = _T_171 ? issue_slots_8_out_uop_prs1 : issue_slots_7_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_pdst = _T_171 ? issue_slots_8_out_uop_pdst : issue_slots_7_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_rxq_idx = _T_171 ? issue_slots_8_out_uop_rxq_idx : issue_slots_7_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_stq_idx = _T_171 ? issue_slots_8_out_uop_stq_idx : issue_slots_7_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_ldq_idx = _T_171 ? issue_slots_8_out_uop_ldq_idx : issue_slots_7_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_rob_idx = _T_171 ? issue_slots_8_out_uop_rob_idx : issue_slots_7_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_vec = _T_171 ? issue_slots_8_out_uop_fp_ctrl_vec : issue_slots_7_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_wflags = _T_171 ? issue_slots_8_out_uop_fp_ctrl_wflags : issue_slots_7_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_sqrt = _T_171 ? issue_slots_8_out_uop_fp_ctrl_sqrt : issue_slots_7_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_div = _T_171 ? issue_slots_8_out_uop_fp_ctrl_div : issue_slots_7_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_fma = _T_171 ? issue_slots_8_out_uop_fp_ctrl_fma : issue_slots_7_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_fastpipe = _T_171 ? issue_slots_8_out_uop_fp_ctrl_fastpipe : issue_slots_7_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_toint = _T_171 ? issue_slots_8_out_uop_fp_ctrl_toint : issue_slots_7_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_fromint = _T_171 ? issue_slots_8_out_uop_fp_ctrl_fromint : issue_slots_7_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_typeTagOut = _T_171 ? issue_slots_8_out_uop_fp_ctrl_typeTagOut : issue_slots_7_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_typeTagIn = _T_171 ? issue_slots_8_out_uop_fp_ctrl_typeTagIn : issue_slots_7_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_swap23 = _T_171 ? issue_slots_8_out_uop_fp_ctrl_swap23 : issue_slots_7_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_swap12 = _T_171 ? issue_slots_8_out_uop_fp_ctrl_swap12 : issue_slots_7_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_ren3 = _T_171 ? issue_slots_8_out_uop_fp_ctrl_ren3 : issue_slots_7_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_ren2 = _T_171 ? issue_slots_8_out_uop_fp_ctrl_ren2 : issue_slots_7_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_ren1 = _T_171 ? issue_slots_8_out_uop_fp_ctrl_ren1 : issue_slots_7_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_wen = _T_171 ? issue_slots_8_out_uop_fp_ctrl_wen : issue_slots_7_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_ldst = _T_171 ? issue_slots_8_out_uop_fp_ctrl_ldst : issue_slots_7_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_op2_sel = _T_171 ? issue_slots_8_out_uop_op2_sel : issue_slots_7_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_op1_sel = _T_171 ? issue_slots_8_out_uop_op1_sel : issue_slots_7_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_imm_packed = _T_171 ? issue_slots_8_out_uop_imm_packed : issue_slots_7_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_pimm = _T_171 ? issue_slots_8_out_uop_pimm : issue_slots_7_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_imm_sel = _T_171 ? issue_slots_8_out_uop_imm_sel : issue_slots_7_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_imm_rename = _T_171 ? issue_slots_8_out_uop_imm_rename : issue_slots_7_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_taken = _T_171 ? issue_slots_8_out_uop_taken : issue_slots_7_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_pc_lob = _T_171 ? issue_slots_8_out_uop_pc_lob : issue_slots_7_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_edge_inst = _T_171 ? issue_slots_8_out_uop_edge_inst : issue_slots_7_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_ftq_idx = _T_171 ? issue_slots_8_out_uop_ftq_idx : issue_slots_7_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_mov = _T_171 ? issue_slots_8_out_uop_is_mov : issue_slots_7_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_rocc = _T_171 ? issue_slots_8_out_uop_is_rocc : issue_slots_7_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_sys_pc2epc = _T_171 ? issue_slots_8_out_uop_is_sys_pc2epc : issue_slots_7_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_eret = _T_171 ? issue_slots_8_out_uop_is_eret : issue_slots_7_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_amo = _T_171 ? issue_slots_8_out_uop_is_amo : issue_slots_7_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_sfence = _T_171 ? issue_slots_8_out_uop_is_sfence : issue_slots_7_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_fencei = _T_171 ? issue_slots_8_out_uop_is_fencei : issue_slots_7_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_fence = _T_171 ? issue_slots_8_out_uop_is_fence : issue_slots_7_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_sfb = _T_171 ? issue_slots_8_out_uop_is_sfb : issue_slots_7_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_br_type = _T_171 ? issue_slots_8_out_uop_br_type : issue_slots_7_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_br_tag = _T_171 ? issue_slots_8_out_uop_br_tag : issue_slots_7_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_br_mask = _T_171 ? issue_slots_8_out_uop_br_mask : issue_slots_7_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_dis_col_sel = _T_171 ? issue_slots_8_out_uop_dis_col_sel : issue_slots_7_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_iw_p3_bypass_hint = _T_171 ? issue_slots_8_out_uop_iw_p3_bypass_hint : issue_slots_7_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_iw_p2_bypass_hint = _T_171 ? issue_slots_8_out_uop_iw_p2_bypass_hint : issue_slots_7_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_iw_p1_bypass_hint = _T_171 ? issue_slots_8_out_uop_iw_p1_bypass_hint : issue_slots_7_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_iw_p2_speculative_child = _T_171 ? issue_slots_8_out_uop_iw_p2_speculative_child : issue_slots_7_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_iw_p1_speculative_child = _T_171 ? issue_slots_8_out_uop_iw_p1_speculative_child : issue_slots_7_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_iw_issued = _T_171 ? issue_slots_8_out_uop_iw_issued : issue_slots_7_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_0 = _T_171 ? issue_slots_8_out_uop_fu_code_0 : issue_slots_7_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_1 = _T_171 ? issue_slots_8_out_uop_fu_code_1 : issue_slots_7_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_2 = _T_171 ? issue_slots_8_out_uop_fu_code_2 : issue_slots_7_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_3 = _T_171 ? issue_slots_8_out_uop_fu_code_3 : issue_slots_7_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_4 = _T_171 ? issue_slots_8_out_uop_fu_code_4 : issue_slots_7_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_5 = _T_171 ? issue_slots_8_out_uop_fu_code_5 : issue_slots_7_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_6 = _T_171 ? issue_slots_8_out_uop_fu_code_6 : issue_slots_7_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_7 = _T_171 ? issue_slots_8_out_uop_fu_code_7 : issue_slots_7_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_8 = _T_171 ? issue_slots_8_out_uop_fu_code_8 : issue_slots_7_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_9 = _T_171 ? issue_slots_8_out_uop_fu_code_9 : issue_slots_7_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_iq_type_0 = _T_171 ? issue_slots_8_out_uop_iq_type_0 : issue_slots_7_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_iq_type_1 = _T_171 ? issue_slots_8_out_uop_iq_type_1 : issue_slots_7_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_iq_type_2 = _T_171 ? issue_slots_8_out_uop_iq_type_2 : issue_slots_7_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_iq_type_3 = _T_171 ? issue_slots_8_out_uop_iq_type_3 : issue_slots_7_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_debug_pc = _T_171 ? issue_slots_8_out_uop_debug_pc : issue_slots_7_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_rvc = _T_171 ? issue_slots_8_out_uop_is_rvc : issue_slots_7_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_debug_inst = _T_171 ? issue_slots_8_out_uop_debug_inst : issue_slots_7_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_inst = _T_171 ? issue_slots_8_out_uop_inst : issue_slots_7_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_6_clear_T = |shamts_oh_6; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_6_clear = _issue_slots_6_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_173 = shamts_oh_9 == 2'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_7_in_uop_valid = _T_173 ? issue_slots_9_will_be_valid : shamts_oh_8 == 2'h1 & issue_slots_8_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_7_in_uop_bits_debug_tsrc = _T_173 ? issue_slots_9_out_uop_debug_tsrc : issue_slots_8_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_debug_fsrc = _T_173 ? issue_slots_9_out_uop_debug_fsrc : issue_slots_8_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_bp_xcpt_if = _T_173 ? issue_slots_9_out_uop_bp_xcpt_if : issue_slots_8_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_bp_debug_if = _T_173 ? issue_slots_9_out_uop_bp_debug_if : issue_slots_8_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_xcpt_ma_if = _T_173 ? issue_slots_9_out_uop_xcpt_ma_if : issue_slots_8_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_xcpt_ae_if = _T_173 ? issue_slots_9_out_uop_xcpt_ae_if : issue_slots_8_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_xcpt_pf_if = _T_173 ? issue_slots_9_out_uop_xcpt_pf_if : issue_slots_8_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_typ = _T_173 ? issue_slots_9_out_uop_fp_typ : issue_slots_8_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_rm = _T_173 ? issue_slots_9_out_uop_fp_rm : issue_slots_8_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_val = _T_173 ? issue_slots_9_out_uop_fp_val : issue_slots_8_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fcn_op = _T_173 ? issue_slots_9_out_uop_fcn_op : issue_slots_8_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fcn_dw = _T_173 ? issue_slots_9_out_uop_fcn_dw : issue_slots_8_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_frs3_en = _T_173 ? issue_slots_9_out_uop_frs3_en : issue_slots_8_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_lrs2_rtype = _T_173 ? issue_slots_9_out_uop_lrs2_rtype : issue_slots_8_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_lrs1_rtype = _T_173 ? issue_slots_9_out_uop_lrs1_rtype : issue_slots_8_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_dst_rtype = _T_173 ? issue_slots_9_out_uop_dst_rtype : issue_slots_8_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_lrs3 = _T_173 ? issue_slots_9_out_uop_lrs3 : issue_slots_8_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_lrs2 = _T_173 ? issue_slots_9_out_uop_lrs2 : issue_slots_8_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_lrs1 = _T_173 ? issue_slots_9_out_uop_lrs1 : issue_slots_8_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_ldst = _T_173 ? issue_slots_9_out_uop_ldst : issue_slots_8_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_ldst_is_rs1 = _T_173 ? issue_slots_9_out_uop_ldst_is_rs1 : issue_slots_8_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_csr_cmd = _T_173 ? issue_slots_9_out_uop_csr_cmd : issue_slots_8_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_flush_on_commit = _T_173 ? issue_slots_9_out_uop_flush_on_commit : issue_slots_8_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_unique = _T_173 ? issue_slots_9_out_uop_is_unique : issue_slots_8_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_uses_stq = _T_173 ? issue_slots_9_out_uop_uses_stq : issue_slots_8_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_uses_ldq = _T_173 ? issue_slots_9_out_uop_uses_ldq : issue_slots_8_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_mem_signed = _T_173 ? issue_slots_9_out_uop_mem_signed : issue_slots_8_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_mem_size = _T_173 ? issue_slots_9_out_uop_mem_size : issue_slots_8_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_mem_cmd = _T_173 ? issue_slots_9_out_uop_mem_cmd : issue_slots_8_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_exc_cause = _T_173 ? issue_slots_9_out_uop_exc_cause : issue_slots_8_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_exception = _T_173 ? issue_slots_9_out_uop_exception : issue_slots_8_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_stale_pdst = _T_173 ? issue_slots_9_out_uop_stale_pdst : issue_slots_8_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_ppred_busy = _T_173 ? issue_slots_9_out_uop_ppred_busy : issue_slots_8_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_prs3_busy = _T_173 ? issue_slots_9_out_uop_prs3_busy : issue_slots_8_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_prs2_busy = _T_173 ? issue_slots_9_out_uop_prs2_busy : issue_slots_8_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_prs1_busy = _T_173 ? issue_slots_9_out_uop_prs1_busy : issue_slots_8_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_ppred = _T_173 ? issue_slots_9_out_uop_ppred : issue_slots_8_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_prs3 = _T_173 ? issue_slots_9_out_uop_prs3 : issue_slots_8_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_prs2 = _T_173 ? issue_slots_9_out_uop_prs2 : issue_slots_8_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_prs1 = _T_173 ? issue_slots_9_out_uop_prs1 : issue_slots_8_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_pdst = _T_173 ? issue_slots_9_out_uop_pdst : issue_slots_8_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_rxq_idx = _T_173 ? issue_slots_9_out_uop_rxq_idx : issue_slots_8_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_stq_idx = _T_173 ? issue_slots_9_out_uop_stq_idx : issue_slots_8_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_ldq_idx = _T_173 ? issue_slots_9_out_uop_ldq_idx : issue_slots_8_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_rob_idx = _T_173 ? issue_slots_9_out_uop_rob_idx : issue_slots_8_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_vec = _T_173 ? issue_slots_9_out_uop_fp_ctrl_vec : issue_slots_8_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_wflags = _T_173 ? issue_slots_9_out_uop_fp_ctrl_wflags : issue_slots_8_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_sqrt = _T_173 ? issue_slots_9_out_uop_fp_ctrl_sqrt : issue_slots_8_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_div = _T_173 ? issue_slots_9_out_uop_fp_ctrl_div : issue_slots_8_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_fma = _T_173 ? issue_slots_9_out_uop_fp_ctrl_fma : issue_slots_8_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_fastpipe = _T_173 ? issue_slots_9_out_uop_fp_ctrl_fastpipe : issue_slots_8_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_toint = _T_173 ? issue_slots_9_out_uop_fp_ctrl_toint : issue_slots_8_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_fromint = _T_173 ? issue_slots_9_out_uop_fp_ctrl_fromint : issue_slots_8_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_typeTagOut = _T_173 ? issue_slots_9_out_uop_fp_ctrl_typeTagOut : issue_slots_8_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_typeTagIn = _T_173 ? issue_slots_9_out_uop_fp_ctrl_typeTagIn : issue_slots_8_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_swap23 = _T_173 ? issue_slots_9_out_uop_fp_ctrl_swap23 : issue_slots_8_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_swap12 = _T_173 ? issue_slots_9_out_uop_fp_ctrl_swap12 : issue_slots_8_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_ren3 = _T_173 ? issue_slots_9_out_uop_fp_ctrl_ren3 : issue_slots_8_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_ren2 = _T_173 ? issue_slots_9_out_uop_fp_ctrl_ren2 : issue_slots_8_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_ren1 = _T_173 ? issue_slots_9_out_uop_fp_ctrl_ren1 : issue_slots_8_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_wen = _T_173 ? issue_slots_9_out_uop_fp_ctrl_wen : issue_slots_8_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_ldst = _T_173 ? issue_slots_9_out_uop_fp_ctrl_ldst : issue_slots_8_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_op2_sel = _T_173 ? issue_slots_9_out_uop_op2_sel : issue_slots_8_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_op1_sel = _T_173 ? issue_slots_9_out_uop_op1_sel : issue_slots_8_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_imm_packed = _T_173 ? issue_slots_9_out_uop_imm_packed : issue_slots_8_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_pimm = _T_173 ? issue_slots_9_out_uop_pimm : issue_slots_8_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_imm_sel = _T_173 ? issue_slots_9_out_uop_imm_sel : issue_slots_8_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_imm_rename = _T_173 ? issue_slots_9_out_uop_imm_rename : issue_slots_8_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_taken = _T_173 ? issue_slots_9_out_uop_taken : issue_slots_8_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_pc_lob = _T_173 ? issue_slots_9_out_uop_pc_lob : issue_slots_8_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_edge_inst = _T_173 ? issue_slots_9_out_uop_edge_inst : issue_slots_8_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_ftq_idx = _T_173 ? issue_slots_9_out_uop_ftq_idx : issue_slots_8_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_mov = _T_173 ? issue_slots_9_out_uop_is_mov : issue_slots_8_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_rocc = _T_173 ? issue_slots_9_out_uop_is_rocc : issue_slots_8_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_sys_pc2epc = _T_173 ? issue_slots_9_out_uop_is_sys_pc2epc : issue_slots_8_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_eret = _T_173 ? issue_slots_9_out_uop_is_eret : issue_slots_8_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_amo = _T_173 ? issue_slots_9_out_uop_is_amo : issue_slots_8_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_sfence = _T_173 ? issue_slots_9_out_uop_is_sfence : issue_slots_8_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_fencei = _T_173 ? issue_slots_9_out_uop_is_fencei : issue_slots_8_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_fence = _T_173 ? issue_slots_9_out_uop_is_fence : issue_slots_8_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_sfb = _T_173 ? issue_slots_9_out_uop_is_sfb : issue_slots_8_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_br_type = _T_173 ? issue_slots_9_out_uop_br_type : issue_slots_8_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_br_tag = _T_173 ? issue_slots_9_out_uop_br_tag : issue_slots_8_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_br_mask = _T_173 ? issue_slots_9_out_uop_br_mask : issue_slots_8_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_dis_col_sel = _T_173 ? issue_slots_9_out_uop_dis_col_sel : issue_slots_8_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_iw_p3_bypass_hint = _T_173 ? issue_slots_9_out_uop_iw_p3_bypass_hint : issue_slots_8_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_iw_p2_bypass_hint = _T_173 ? issue_slots_9_out_uop_iw_p2_bypass_hint : issue_slots_8_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_iw_p1_bypass_hint = _T_173 ? issue_slots_9_out_uop_iw_p1_bypass_hint : issue_slots_8_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_iw_p2_speculative_child = _T_173 ? issue_slots_9_out_uop_iw_p2_speculative_child : issue_slots_8_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_iw_p1_speculative_child = _T_173 ? issue_slots_9_out_uop_iw_p1_speculative_child : issue_slots_8_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_iw_issued = _T_173 ? issue_slots_9_out_uop_iw_issued : issue_slots_8_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_0 = _T_173 ? issue_slots_9_out_uop_fu_code_0 : issue_slots_8_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_1 = _T_173 ? issue_slots_9_out_uop_fu_code_1 : issue_slots_8_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_2 = _T_173 ? issue_slots_9_out_uop_fu_code_2 : issue_slots_8_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_3 = _T_173 ? issue_slots_9_out_uop_fu_code_3 : issue_slots_8_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_4 = _T_173 ? issue_slots_9_out_uop_fu_code_4 : issue_slots_8_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_5 = _T_173 ? issue_slots_9_out_uop_fu_code_5 : issue_slots_8_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_6 = _T_173 ? issue_slots_9_out_uop_fu_code_6 : issue_slots_8_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_7 = _T_173 ? issue_slots_9_out_uop_fu_code_7 : issue_slots_8_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_8 = _T_173 ? issue_slots_9_out_uop_fu_code_8 : issue_slots_8_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_9 = _T_173 ? issue_slots_9_out_uop_fu_code_9 : issue_slots_8_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_iq_type_0 = _T_173 ? issue_slots_9_out_uop_iq_type_0 : issue_slots_8_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_iq_type_1 = _T_173 ? issue_slots_9_out_uop_iq_type_1 : issue_slots_8_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_iq_type_2 = _T_173 ? issue_slots_9_out_uop_iq_type_2 : issue_slots_8_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_iq_type_3 = _T_173 ? issue_slots_9_out_uop_iq_type_3 : issue_slots_8_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_debug_pc = _T_173 ? issue_slots_9_out_uop_debug_pc : issue_slots_8_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_rvc = _T_173 ? issue_slots_9_out_uop_is_rvc : issue_slots_8_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_debug_inst = _T_173 ? issue_slots_9_out_uop_debug_inst : issue_slots_8_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_inst = _T_173 ? issue_slots_9_out_uop_inst : issue_slots_8_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_7_clear_T = |shamts_oh_7; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_7_clear = _issue_slots_7_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_175 = shamts_oh_10 == 2'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_8_in_uop_valid = _T_175 ? issue_slots_10_will_be_valid : shamts_oh_9 == 2'h1 & issue_slots_9_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_8_in_uop_bits_debug_tsrc = _T_175 ? issue_slots_10_out_uop_debug_tsrc : issue_slots_9_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_debug_fsrc = _T_175 ? issue_slots_10_out_uop_debug_fsrc : issue_slots_9_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_bp_xcpt_if = _T_175 ? issue_slots_10_out_uop_bp_xcpt_if : issue_slots_9_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_bp_debug_if = _T_175 ? issue_slots_10_out_uop_bp_debug_if : issue_slots_9_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_xcpt_ma_if = _T_175 ? issue_slots_10_out_uop_xcpt_ma_if : issue_slots_9_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_xcpt_ae_if = _T_175 ? issue_slots_10_out_uop_xcpt_ae_if : issue_slots_9_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_xcpt_pf_if = _T_175 ? issue_slots_10_out_uop_xcpt_pf_if : issue_slots_9_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_typ = _T_175 ? issue_slots_10_out_uop_fp_typ : issue_slots_9_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_rm = _T_175 ? issue_slots_10_out_uop_fp_rm : issue_slots_9_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_val = _T_175 ? issue_slots_10_out_uop_fp_val : issue_slots_9_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fcn_op = _T_175 ? issue_slots_10_out_uop_fcn_op : issue_slots_9_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fcn_dw = _T_175 ? issue_slots_10_out_uop_fcn_dw : issue_slots_9_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_frs3_en = _T_175 ? issue_slots_10_out_uop_frs3_en : issue_slots_9_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_lrs2_rtype = _T_175 ? issue_slots_10_out_uop_lrs2_rtype : issue_slots_9_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_lrs1_rtype = _T_175 ? issue_slots_10_out_uop_lrs1_rtype : issue_slots_9_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_dst_rtype = _T_175 ? issue_slots_10_out_uop_dst_rtype : issue_slots_9_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_lrs3 = _T_175 ? issue_slots_10_out_uop_lrs3 : issue_slots_9_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_lrs2 = _T_175 ? issue_slots_10_out_uop_lrs2 : issue_slots_9_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_lrs1 = _T_175 ? issue_slots_10_out_uop_lrs1 : issue_slots_9_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_ldst = _T_175 ? issue_slots_10_out_uop_ldst : issue_slots_9_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_ldst_is_rs1 = _T_175 ? issue_slots_10_out_uop_ldst_is_rs1 : issue_slots_9_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_csr_cmd = _T_175 ? issue_slots_10_out_uop_csr_cmd : issue_slots_9_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_flush_on_commit = _T_175 ? issue_slots_10_out_uop_flush_on_commit : issue_slots_9_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_unique = _T_175 ? issue_slots_10_out_uop_is_unique : issue_slots_9_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_uses_stq = _T_175 ? issue_slots_10_out_uop_uses_stq : issue_slots_9_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_uses_ldq = _T_175 ? issue_slots_10_out_uop_uses_ldq : issue_slots_9_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_mem_signed = _T_175 ? issue_slots_10_out_uop_mem_signed : issue_slots_9_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_mem_size = _T_175 ? issue_slots_10_out_uop_mem_size : issue_slots_9_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_mem_cmd = _T_175 ? issue_slots_10_out_uop_mem_cmd : issue_slots_9_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_exc_cause = _T_175 ? issue_slots_10_out_uop_exc_cause : issue_slots_9_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_exception = _T_175 ? issue_slots_10_out_uop_exception : issue_slots_9_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_stale_pdst = _T_175 ? issue_slots_10_out_uop_stale_pdst : issue_slots_9_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_ppred_busy = _T_175 ? issue_slots_10_out_uop_ppred_busy : issue_slots_9_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_prs3_busy = _T_175 ? issue_slots_10_out_uop_prs3_busy : issue_slots_9_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_prs2_busy = _T_175 ? issue_slots_10_out_uop_prs2_busy : issue_slots_9_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_prs1_busy = _T_175 ? issue_slots_10_out_uop_prs1_busy : issue_slots_9_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_ppred = _T_175 ? issue_slots_10_out_uop_ppred : issue_slots_9_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_prs3 = _T_175 ? issue_slots_10_out_uop_prs3 : issue_slots_9_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_prs2 = _T_175 ? issue_slots_10_out_uop_prs2 : issue_slots_9_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_prs1 = _T_175 ? issue_slots_10_out_uop_prs1 : issue_slots_9_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_pdst = _T_175 ? issue_slots_10_out_uop_pdst : issue_slots_9_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_rxq_idx = _T_175 ? issue_slots_10_out_uop_rxq_idx : issue_slots_9_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_stq_idx = _T_175 ? issue_slots_10_out_uop_stq_idx : issue_slots_9_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_ldq_idx = _T_175 ? issue_slots_10_out_uop_ldq_idx : issue_slots_9_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_rob_idx = _T_175 ? issue_slots_10_out_uop_rob_idx : issue_slots_9_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_vec = _T_175 ? issue_slots_10_out_uop_fp_ctrl_vec : issue_slots_9_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_wflags = _T_175 ? issue_slots_10_out_uop_fp_ctrl_wflags : issue_slots_9_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_sqrt = _T_175 ? issue_slots_10_out_uop_fp_ctrl_sqrt : issue_slots_9_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_div = _T_175 ? issue_slots_10_out_uop_fp_ctrl_div : issue_slots_9_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_fma = _T_175 ? issue_slots_10_out_uop_fp_ctrl_fma : issue_slots_9_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_fastpipe = _T_175 ? issue_slots_10_out_uop_fp_ctrl_fastpipe : issue_slots_9_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_toint = _T_175 ? issue_slots_10_out_uop_fp_ctrl_toint : issue_slots_9_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_fromint = _T_175 ? issue_slots_10_out_uop_fp_ctrl_fromint : issue_slots_9_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_typeTagOut = _T_175 ? issue_slots_10_out_uop_fp_ctrl_typeTagOut : issue_slots_9_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_typeTagIn = _T_175 ? issue_slots_10_out_uop_fp_ctrl_typeTagIn : issue_slots_9_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_swap23 = _T_175 ? issue_slots_10_out_uop_fp_ctrl_swap23 : issue_slots_9_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_swap12 = _T_175 ? issue_slots_10_out_uop_fp_ctrl_swap12 : issue_slots_9_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_ren3 = _T_175 ? issue_slots_10_out_uop_fp_ctrl_ren3 : issue_slots_9_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_ren2 = _T_175 ? issue_slots_10_out_uop_fp_ctrl_ren2 : issue_slots_9_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_ren1 = _T_175 ? issue_slots_10_out_uop_fp_ctrl_ren1 : issue_slots_9_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_wen = _T_175 ? issue_slots_10_out_uop_fp_ctrl_wen : issue_slots_9_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_ldst = _T_175 ? issue_slots_10_out_uop_fp_ctrl_ldst : issue_slots_9_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_op2_sel = _T_175 ? issue_slots_10_out_uop_op2_sel : issue_slots_9_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_op1_sel = _T_175 ? issue_slots_10_out_uop_op1_sel : issue_slots_9_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_imm_packed = _T_175 ? issue_slots_10_out_uop_imm_packed : issue_slots_9_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_pimm = _T_175 ? issue_slots_10_out_uop_pimm : issue_slots_9_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_imm_sel = _T_175 ? issue_slots_10_out_uop_imm_sel : issue_slots_9_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_imm_rename = _T_175 ? issue_slots_10_out_uop_imm_rename : issue_slots_9_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_taken = _T_175 ? issue_slots_10_out_uop_taken : issue_slots_9_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_pc_lob = _T_175 ? issue_slots_10_out_uop_pc_lob : issue_slots_9_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_edge_inst = _T_175 ? issue_slots_10_out_uop_edge_inst : issue_slots_9_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_ftq_idx = _T_175 ? issue_slots_10_out_uop_ftq_idx : issue_slots_9_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_mov = _T_175 ? issue_slots_10_out_uop_is_mov : issue_slots_9_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_rocc = _T_175 ? issue_slots_10_out_uop_is_rocc : issue_slots_9_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_sys_pc2epc = _T_175 ? issue_slots_10_out_uop_is_sys_pc2epc : issue_slots_9_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_eret = _T_175 ? issue_slots_10_out_uop_is_eret : issue_slots_9_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_amo = _T_175 ? issue_slots_10_out_uop_is_amo : issue_slots_9_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_sfence = _T_175 ? issue_slots_10_out_uop_is_sfence : issue_slots_9_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_fencei = _T_175 ? issue_slots_10_out_uop_is_fencei : issue_slots_9_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_fence = _T_175 ? issue_slots_10_out_uop_is_fence : issue_slots_9_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_sfb = _T_175 ? issue_slots_10_out_uop_is_sfb : issue_slots_9_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_br_type = _T_175 ? issue_slots_10_out_uop_br_type : issue_slots_9_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_br_tag = _T_175 ? issue_slots_10_out_uop_br_tag : issue_slots_9_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_br_mask = _T_175 ? issue_slots_10_out_uop_br_mask : issue_slots_9_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_dis_col_sel = _T_175 ? issue_slots_10_out_uop_dis_col_sel : issue_slots_9_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_iw_p3_bypass_hint = _T_175 ? issue_slots_10_out_uop_iw_p3_bypass_hint : issue_slots_9_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_iw_p2_bypass_hint = _T_175 ? issue_slots_10_out_uop_iw_p2_bypass_hint : issue_slots_9_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_iw_p1_bypass_hint = _T_175 ? issue_slots_10_out_uop_iw_p1_bypass_hint : issue_slots_9_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_iw_p2_speculative_child = _T_175 ? issue_slots_10_out_uop_iw_p2_speculative_child : issue_slots_9_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_iw_p1_speculative_child = _T_175 ? issue_slots_10_out_uop_iw_p1_speculative_child : issue_slots_9_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_iw_issued = _T_175 ? issue_slots_10_out_uop_iw_issued : issue_slots_9_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_0 = _T_175 ? issue_slots_10_out_uop_fu_code_0 : issue_slots_9_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_1 = _T_175 ? issue_slots_10_out_uop_fu_code_1 : issue_slots_9_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_2 = _T_175 ? issue_slots_10_out_uop_fu_code_2 : issue_slots_9_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_3 = _T_175 ? issue_slots_10_out_uop_fu_code_3 : issue_slots_9_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_4 = _T_175 ? issue_slots_10_out_uop_fu_code_4 : issue_slots_9_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_5 = _T_175 ? issue_slots_10_out_uop_fu_code_5 : issue_slots_9_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_6 = _T_175 ? issue_slots_10_out_uop_fu_code_6 : issue_slots_9_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_7 = _T_175 ? issue_slots_10_out_uop_fu_code_7 : issue_slots_9_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_8 = _T_175 ? issue_slots_10_out_uop_fu_code_8 : issue_slots_9_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_9 = _T_175 ? issue_slots_10_out_uop_fu_code_9 : issue_slots_9_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_iq_type_0 = _T_175 ? issue_slots_10_out_uop_iq_type_0 : issue_slots_9_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_iq_type_1 = _T_175 ? issue_slots_10_out_uop_iq_type_1 : issue_slots_9_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_iq_type_2 = _T_175 ? issue_slots_10_out_uop_iq_type_2 : issue_slots_9_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_iq_type_3 = _T_175 ? issue_slots_10_out_uop_iq_type_3 : issue_slots_9_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_debug_pc = _T_175 ? issue_slots_10_out_uop_debug_pc : issue_slots_9_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_rvc = _T_175 ? issue_slots_10_out_uop_is_rvc : issue_slots_9_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_debug_inst = _T_175 ? issue_slots_10_out_uop_debug_inst : issue_slots_9_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_inst = _T_175 ? issue_slots_10_out_uop_inst : issue_slots_9_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_8_clear_T = |shamts_oh_8; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_8_clear = _issue_slots_8_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_177 = shamts_oh_11 == 2'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_9_in_uop_valid = _T_177 ? issue_slots_11_will_be_valid : shamts_oh_10 == 2'h1 & issue_slots_10_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_9_in_uop_bits_debug_tsrc = _T_177 ? issue_slots_11_out_uop_debug_tsrc : issue_slots_10_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_debug_fsrc = _T_177 ? issue_slots_11_out_uop_debug_fsrc : issue_slots_10_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_bp_xcpt_if = _T_177 ? issue_slots_11_out_uop_bp_xcpt_if : issue_slots_10_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_bp_debug_if = _T_177 ? issue_slots_11_out_uop_bp_debug_if : issue_slots_10_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_xcpt_ma_if = _T_177 ? issue_slots_11_out_uop_xcpt_ma_if : issue_slots_10_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_xcpt_ae_if = _T_177 ? issue_slots_11_out_uop_xcpt_ae_if : issue_slots_10_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_xcpt_pf_if = _T_177 ? issue_slots_11_out_uop_xcpt_pf_if : issue_slots_10_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_typ = _T_177 ? issue_slots_11_out_uop_fp_typ : issue_slots_10_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_rm = _T_177 ? issue_slots_11_out_uop_fp_rm : issue_slots_10_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_val = _T_177 ? issue_slots_11_out_uop_fp_val : issue_slots_10_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fcn_op = _T_177 ? issue_slots_11_out_uop_fcn_op : issue_slots_10_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fcn_dw = _T_177 ? issue_slots_11_out_uop_fcn_dw : issue_slots_10_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_frs3_en = _T_177 ? issue_slots_11_out_uop_frs3_en : issue_slots_10_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_lrs2_rtype = _T_177 ? issue_slots_11_out_uop_lrs2_rtype : issue_slots_10_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_lrs1_rtype = _T_177 ? issue_slots_11_out_uop_lrs1_rtype : issue_slots_10_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_dst_rtype = _T_177 ? issue_slots_11_out_uop_dst_rtype : issue_slots_10_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_lrs3 = _T_177 ? issue_slots_11_out_uop_lrs3 : issue_slots_10_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_lrs2 = _T_177 ? issue_slots_11_out_uop_lrs2 : issue_slots_10_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_lrs1 = _T_177 ? issue_slots_11_out_uop_lrs1 : issue_slots_10_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_ldst = _T_177 ? issue_slots_11_out_uop_ldst : issue_slots_10_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_ldst_is_rs1 = _T_177 ? issue_slots_11_out_uop_ldst_is_rs1 : issue_slots_10_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_csr_cmd = _T_177 ? issue_slots_11_out_uop_csr_cmd : issue_slots_10_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_flush_on_commit = _T_177 ? issue_slots_11_out_uop_flush_on_commit : issue_slots_10_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_unique = _T_177 ? issue_slots_11_out_uop_is_unique : issue_slots_10_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_uses_stq = _T_177 ? issue_slots_11_out_uop_uses_stq : issue_slots_10_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_uses_ldq = _T_177 ? issue_slots_11_out_uop_uses_ldq : issue_slots_10_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_mem_signed = _T_177 ? issue_slots_11_out_uop_mem_signed : issue_slots_10_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_mem_size = _T_177 ? issue_slots_11_out_uop_mem_size : issue_slots_10_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_mem_cmd = _T_177 ? issue_slots_11_out_uop_mem_cmd : issue_slots_10_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_exc_cause = _T_177 ? issue_slots_11_out_uop_exc_cause : issue_slots_10_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_exception = _T_177 ? issue_slots_11_out_uop_exception : issue_slots_10_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_stale_pdst = _T_177 ? issue_slots_11_out_uop_stale_pdst : issue_slots_10_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_ppred_busy = _T_177 ? issue_slots_11_out_uop_ppred_busy : issue_slots_10_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_prs3_busy = _T_177 ? issue_slots_11_out_uop_prs3_busy : issue_slots_10_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_prs2_busy = _T_177 ? issue_slots_11_out_uop_prs2_busy : issue_slots_10_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_prs1_busy = _T_177 ? issue_slots_11_out_uop_prs1_busy : issue_slots_10_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_ppred = _T_177 ? issue_slots_11_out_uop_ppred : issue_slots_10_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_prs3 = _T_177 ? issue_slots_11_out_uop_prs3 : issue_slots_10_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_prs2 = _T_177 ? issue_slots_11_out_uop_prs2 : issue_slots_10_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_prs1 = _T_177 ? issue_slots_11_out_uop_prs1 : issue_slots_10_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_pdst = _T_177 ? issue_slots_11_out_uop_pdst : issue_slots_10_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_rxq_idx = _T_177 ? issue_slots_11_out_uop_rxq_idx : issue_slots_10_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_stq_idx = _T_177 ? issue_slots_11_out_uop_stq_idx : issue_slots_10_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_ldq_idx = _T_177 ? issue_slots_11_out_uop_ldq_idx : issue_slots_10_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_rob_idx = _T_177 ? issue_slots_11_out_uop_rob_idx : issue_slots_10_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_vec = _T_177 ? issue_slots_11_out_uop_fp_ctrl_vec : issue_slots_10_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_wflags = _T_177 ? issue_slots_11_out_uop_fp_ctrl_wflags : issue_slots_10_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_sqrt = _T_177 ? issue_slots_11_out_uop_fp_ctrl_sqrt : issue_slots_10_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_div = _T_177 ? issue_slots_11_out_uop_fp_ctrl_div : issue_slots_10_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_fma = _T_177 ? issue_slots_11_out_uop_fp_ctrl_fma : issue_slots_10_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_fastpipe = _T_177 ? issue_slots_11_out_uop_fp_ctrl_fastpipe : issue_slots_10_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_toint = _T_177 ? issue_slots_11_out_uop_fp_ctrl_toint : issue_slots_10_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_fromint = _T_177 ? issue_slots_11_out_uop_fp_ctrl_fromint : issue_slots_10_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_typeTagOut = _T_177 ? issue_slots_11_out_uop_fp_ctrl_typeTagOut : issue_slots_10_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_typeTagIn = _T_177 ? issue_slots_11_out_uop_fp_ctrl_typeTagIn : issue_slots_10_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_swap23 = _T_177 ? issue_slots_11_out_uop_fp_ctrl_swap23 : issue_slots_10_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_swap12 = _T_177 ? issue_slots_11_out_uop_fp_ctrl_swap12 : issue_slots_10_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_ren3 = _T_177 ? issue_slots_11_out_uop_fp_ctrl_ren3 : issue_slots_10_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_ren2 = _T_177 ? issue_slots_11_out_uop_fp_ctrl_ren2 : issue_slots_10_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_ren1 = _T_177 ? issue_slots_11_out_uop_fp_ctrl_ren1 : issue_slots_10_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_wen = _T_177 ? issue_slots_11_out_uop_fp_ctrl_wen : issue_slots_10_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_ldst = _T_177 ? issue_slots_11_out_uop_fp_ctrl_ldst : issue_slots_10_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_op2_sel = _T_177 ? issue_slots_11_out_uop_op2_sel : issue_slots_10_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_op1_sel = _T_177 ? issue_slots_11_out_uop_op1_sel : issue_slots_10_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_imm_packed = _T_177 ? issue_slots_11_out_uop_imm_packed : issue_slots_10_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_pimm = _T_177 ? issue_slots_11_out_uop_pimm : issue_slots_10_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_imm_sel = _T_177 ? issue_slots_11_out_uop_imm_sel : issue_slots_10_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_imm_rename = _T_177 ? issue_slots_11_out_uop_imm_rename : issue_slots_10_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_taken = _T_177 ? issue_slots_11_out_uop_taken : issue_slots_10_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_pc_lob = _T_177 ? issue_slots_11_out_uop_pc_lob : issue_slots_10_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_edge_inst = _T_177 ? issue_slots_11_out_uop_edge_inst : issue_slots_10_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_ftq_idx = _T_177 ? issue_slots_11_out_uop_ftq_idx : issue_slots_10_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_mov = _T_177 ? issue_slots_11_out_uop_is_mov : issue_slots_10_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_rocc = _T_177 ? issue_slots_11_out_uop_is_rocc : issue_slots_10_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_sys_pc2epc = _T_177 ? issue_slots_11_out_uop_is_sys_pc2epc : issue_slots_10_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_eret = _T_177 ? issue_slots_11_out_uop_is_eret : issue_slots_10_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_amo = _T_177 ? issue_slots_11_out_uop_is_amo : issue_slots_10_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_sfence = _T_177 ? issue_slots_11_out_uop_is_sfence : issue_slots_10_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_fencei = _T_177 ? issue_slots_11_out_uop_is_fencei : issue_slots_10_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_fence = _T_177 ? issue_slots_11_out_uop_is_fence : issue_slots_10_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_sfb = _T_177 ? issue_slots_11_out_uop_is_sfb : issue_slots_10_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_br_type = _T_177 ? issue_slots_11_out_uop_br_type : issue_slots_10_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_br_tag = _T_177 ? issue_slots_11_out_uop_br_tag : issue_slots_10_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_br_mask = _T_177 ? issue_slots_11_out_uop_br_mask : issue_slots_10_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_dis_col_sel = _T_177 ? issue_slots_11_out_uop_dis_col_sel : issue_slots_10_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_iw_p3_bypass_hint = _T_177 ? issue_slots_11_out_uop_iw_p3_bypass_hint : issue_slots_10_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_iw_p2_bypass_hint = _T_177 ? issue_slots_11_out_uop_iw_p2_bypass_hint : issue_slots_10_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_iw_p1_bypass_hint = _T_177 ? issue_slots_11_out_uop_iw_p1_bypass_hint : issue_slots_10_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_iw_p2_speculative_child = _T_177 ? issue_slots_11_out_uop_iw_p2_speculative_child : issue_slots_10_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_iw_p1_speculative_child = _T_177 ? issue_slots_11_out_uop_iw_p1_speculative_child : issue_slots_10_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_iw_issued = _T_177 ? issue_slots_11_out_uop_iw_issued : issue_slots_10_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_0 = _T_177 ? issue_slots_11_out_uop_fu_code_0 : issue_slots_10_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_1 = _T_177 ? issue_slots_11_out_uop_fu_code_1 : issue_slots_10_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_2 = _T_177 ? issue_slots_11_out_uop_fu_code_2 : issue_slots_10_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_3 = _T_177 ? issue_slots_11_out_uop_fu_code_3 : issue_slots_10_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_4 = _T_177 ? issue_slots_11_out_uop_fu_code_4 : issue_slots_10_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_5 = _T_177 ? issue_slots_11_out_uop_fu_code_5 : issue_slots_10_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_6 = _T_177 ? issue_slots_11_out_uop_fu_code_6 : issue_slots_10_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_7 = _T_177 ? issue_slots_11_out_uop_fu_code_7 : issue_slots_10_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_8 = _T_177 ? issue_slots_11_out_uop_fu_code_8 : issue_slots_10_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_9 = _T_177 ? issue_slots_11_out_uop_fu_code_9 : issue_slots_10_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_iq_type_0 = _T_177 ? issue_slots_11_out_uop_iq_type_0 : issue_slots_10_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_iq_type_1 = _T_177 ? issue_slots_11_out_uop_iq_type_1 : issue_slots_10_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_iq_type_2 = _T_177 ? issue_slots_11_out_uop_iq_type_2 : issue_slots_10_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_iq_type_3 = _T_177 ? issue_slots_11_out_uop_iq_type_3 : issue_slots_10_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_debug_pc = _T_177 ? issue_slots_11_out_uop_debug_pc : issue_slots_10_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_rvc = _T_177 ? issue_slots_11_out_uop_is_rvc : issue_slots_10_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_debug_inst = _T_177 ? issue_slots_11_out_uop_debug_inst : issue_slots_10_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_inst = _T_177 ? issue_slots_11_out_uop_inst : issue_slots_10_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_9_clear_T = |shamts_oh_9; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_9_clear = _issue_slots_9_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_179 = shamts_oh_12 == 2'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_10_in_uop_valid = _T_179 ? will_be_valid_12 : shamts_oh_11 == 2'h1 & issue_slots_11_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :186:79, :191:33, :194:{28,48}, :195:37] assign issue_slots_10_in_uop_bits_debug_tsrc = _T_179 ? io_dis_uops_0_bits_debug_tsrc_0 : issue_slots_11_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_debug_fsrc = _T_179 ? io_dis_uops_0_bits_debug_fsrc_0 : issue_slots_11_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_bp_xcpt_if = _T_179 ? io_dis_uops_0_bits_bp_xcpt_if_0 : issue_slots_11_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_bp_debug_if = _T_179 ? io_dis_uops_0_bits_bp_debug_if_0 : issue_slots_11_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_xcpt_ma_if = _T_179 ? io_dis_uops_0_bits_xcpt_ma_if_0 : issue_slots_11_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_xcpt_ae_if = _T_179 ? io_dis_uops_0_bits_xcpt_ae_if_0 : issue_slots_11_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_xcpt_pf_if = _T_179 ? io_dis_uops_0_bits_xcpt_pf_if_0 : issue_slots_11_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_typ = _T_179 ? io_dis_uops_0_bits_fp_typ_0 : issue_slots_11_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_rm = _T_179 ? io_dis_uops_0_bits_fp_rm_0 : issue_slots_11_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_val = _T_179 ? io_dis_uops_0_bits_fp_val_0 : issue_slots_11_out_uop_fp_val; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fcn_op = _T_179 ? io_dis_uops_0_bits_fcn_op_0 : issue_slots_11_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fcn_dw = _T_179 ? io_dis_uops_0_bits_fcn_dw_0 : issue_slots_11_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_frs3_en = _T_179 ? io_dis_uops_0_bits_frs3_en_0 : issue_slots_11_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_lrs2_rtype = _T_179 ? io_dis_uops_0_bits_lrs2_rtype_0 : issue_slots_11_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_lrs1_rtype = _T_179 ? io_dis_uops_0_bits_lrs1_rtype_0 : issue_slots_11_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_dst_rtype = _T_179 ? io_dis_uops_0_bits_dst_rtype_0 : issue_slots_11_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_lrs3 = _T_179 ? io_dis_uops_0_bits_lrs3_0 : issue_slots_11_out_uop_lrs3; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_lrs2 = _T_179 ? io_dis_uops_0_bits_lrs2_0 : issue_slots_11_out_uop_lrs2; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_lrs1 = _T_179 ? io_dis_uops_0_bits_lrs1_0 : issue_slots_11_out_uop_lrs1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_ldst = _T_179 ? io_dis_uops_0_bits_ldst_0 : issue_slots_11_out_uop_ldst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_ldst_is_rs1 = _T_179 ? io_dis_uops_0_bits_ldst_is_rs1_0 : issue_slots_11_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_csr_cmd = _T_179 ? io_dis_uops_0_bits_csr_cmd_0 : issue_slots_11_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_flush_on_commit = _T_179 ? io_dis_uops_0_bits_flush_on_commit_0 : issue_slots_11_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_unique = _T_179 ? io_dis_uops_0_bits_is_unique_0 : issue_slots_11_out_uop_is_unique; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_uses_stq = _T_179 ? io_dis_uops_0_bits_uses_stq_0 : issue_slots_11_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_uses_ldq = _T_179 ? io_dis_uops_0_bits_uses_ldq_0 : issue_slots_11_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_mem_signed = _T_179 ? io_dis_uops_0_bits_mem_signed_0 : issue_slots_11_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_mem_size = _T_179 ? io_dis_uops_0_bits_mem_size_0 : issue_slots_11_out_uop_mem_size; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_mem_cmd = _T_179 ? io_dis_uops_0_bits_mem_cmd_0 : issue_slots_11_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_exc_cause = _T_179 ? io_dis_uops_0_bits_exc_cause_0 : issue_slots_11_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_exception = _T_179 ? io_dis_uops_0_bits_exception_0 : issue_slots_11_out_uop_exception; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_stale_pdst = _T_179 ? io_dis_uops_0_bits_stale_pdst_0 : issue_slots_11_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_ppred_busy = ~_T_179 & issue_slots_11_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_prs3_busy = _T_179 ? _WIRE_prs3_busy : issue_slots_11_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:35:17, :76:38, :77:29, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_prs2_busy = _T_179 ? _WIRE_prs2_busy : issue_slots_11_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:65:38, :71:116, :72:29, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_prs1_busy = _T_179 ? _WIRE_prs1_busy : issue_slots_11_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:57:38, :62:116, :63:29, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_ppred = _T_179 ? io_dis_uops_0_bits_ppred_0 : issue_slots_11_out_uop_ppred; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_prs3 = _T_179 ? io_dis_uops_0_bits_prs3_0 : issue_slots_11_out_uop_prs3; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_prs2 = _T_179 ? _WIRE_prs2 : issue_slots_11_out_uop_prs2; // @[issue-unit-age-ordered.scala:35:17, :86:50, :87:26, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_prs1 = _T_179 ? io_dis_uops_0_bits_prs1_0 : issue_slots_11_out_uop_prs1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_pdst = _T_179 ? io_dis_uops_0_bits_pdst_0 : issue_slots_11_out_uop_pdst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_rxq_idx = _T_179 ? io_dis_uops_0_bits_rxq_idx_0 : issue_slots_11_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_stq_idx = _T_179 ? io_dis_uops_0_bits_stq_idx_0 : issue_slots_11_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_ldq_idx = _T_179 ? io_dis_uops_0_bits_ldq_idx_0 : issue_slots_11_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_rob_idx = _T_179 ? io_dis_uops_0_bits_rob_idx_0 : issue_slots_11_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_vec = _T_179 ? io_dis_uops_0_bits_fp_ctrl_vec_0 : issue_slots_11_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_wflags = _T_179 ? io_dis_uops_0_bits_fp_ctrl_wflags_0 : issue_slots_11_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_sqrt = _T_179 ? io_dis_uops_0_bits_fp_ctrl_sqrt_0 : issue_slots_11_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_div = _T_179 ? io_dis_uops_0_bits_fp_ctrl_div_0 : issue_slots_11_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_fma = _T_179 ? io_dis_uops_0_bits_fp_ctrl_fma_0 : issue_slots_11_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_fastpipe = _T_179 ? io_dis_uops_0_bits_fp_ctrl_fastpipe_0 : issue_slots_11_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_toint = _T_179 ? io_dis_uops_0_bits_fp_ctrl_toint_0 : issue_slots_11_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_fromint = _T_179 ? io_dis_uops_0_bits_fp_ctrl_fromint_0 : issue_slots_11_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_typeTagOut = _T_179 ? io_dis_uops_0_bits_fp_ctrl_typeTagOut_0 : issue_slots_11_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_typeTagIn = _T_179 ? io_dis_uops_0_bits_fp_ctrl_typeTagIn_0 : issue_slots_11_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_swap23 = _T_179 ? io_dis_uops_0_bits_fp_ctrl_swap23_0 : issue_slots_11_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_swap12 = _T_179 ? io_dis_uops_0_bits_fp_ctrl_swap12_0 : issue_slots_11_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_ren3 = _T_179 ? io_dis_uops_0_bits_fp_ctrl_ren3_0 : issue_slots_11_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_ren2 = _T_179 ? io_dis_uops_0_bits_fp_ctrl_ren2_0 : issue_slots_11_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_ren1 = _T_179 ? io_dis_uops_0_bits_fp_ctrl_ren1_0 : issue_slots_11_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_wen = _T_179 ? io_dis_uops_0_bits_fp_ctrl_wen_0 : issue_slots_11_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_ldst = _T_179 ? io_dis_uops_0_bits_fp_ctrl_ldst_0 : issue_slots_11_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_op2_sel = _T_179 ? io_dis_uops_0_bits_op2_sel_0 : issue_slots_11_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_op1_sel = _T_179 ? io_dis_uops_0_bits_op1_sel_0 : issue_slots_11_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_imm_packed = _T_179 ? io_dis_uops_0_bits_imm_packed_0 : issue_slots_11_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_pimm = _T_179 ? _WIRE_pimm : issue_slots_11_out_uop_pimm; // @[issue-unit-age-ordered.scala:35:17, :89:44, :90:26, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_imm_sel = _T_179 ? io_dis_uops_0_bits_imm_sel_0 : issue_slots_11_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_imm_rename = _T_179 ? io_dis_uops_0_bits_imm_rename_0 : issue_slots_11_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_taken = _T_179 ? io_dis_uops_0_bits_taken_0 : issue_slots_11_out_uop_taken; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_pc_lob = _T_179 ? io_dis_uops_0_bits_pc_lob_0 : issue_slots_11_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_edge_inst = _T_179 ? io_dis_uops_0_bits_edge_inst_0 : issue_slots_11_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_ftq_idx = _T_179 ? io_dis_uops_0_bits_ftq_idx_0 : issue_slots_11_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_mov = _T_179 ? io_dis_uops_0_bits_is_mov_0 : issue_slots_11_out_uop_is_mov; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_rocc = _T_179 ? io_dis_uops_0_bits_is_rocc_0 : issue_slots_11_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_sys_pc2epc = _T_179 ? io_dis_uops_0_bits_is_sys_pc2epc_0 : issue_slots_11_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_eret = _T_179 ? io_dis_uops_0_bits_is_eret_0 : issue_slots_11_out_uop_is_eret; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_amo = _T_179 ? io_dis_uops_0_bits_is_amo_0 : issue_slots_11_out_uop_is_amo; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_sfence = _T_179 ? io_dis_uops_0_bits_is_sfence_0 : issue_slots_11_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_fencei = _T_179 ? io_dis_uops_0_bits_is_fencei_0 : issue_slots_11_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_fence = _T_179 ? io_dis_uops_0_bits_is_fence_0 : issue_slots_11_out_uop_is_fence; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_sfb = _T_179 ? io_dis_uops_0_bits_is_sfb_0 : issue_slots_11_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_br_type = _T_179 ? io_dis_uops_0_bits_br_type_0 : issue_slots_11_out_uop_br_type; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_br_tag = _T_179 ? io_dis_uops_0_bits_br_tag_0 : issue_slots_11_out_uop_br_tag; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_br_mask = _T_179 ? io_dis_uops_0_bits_br_mask_0 : issue_slots_11_out_uop_br_mask; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_dis_col_sel = _T_179 ? io_dis_uops_0_bits_dis_col_sel_0 : issue_slots_11_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iw_p3_bypass_hint = _T_179 ? _WIRE_iw_p3_bypass_hint : issue_slots_11_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:41:35, :76:38, :78:37, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iw_p2_bypass_hint = _T_179 ? _WIRE_iw_p2_bypass_hint : issue_slots_11_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:40:35, :65:38, :68:37, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iw_p1_bypass_hint = _T_179 ? _WIRE_iw_p1_bypass_hint : issue_slots_11_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:39:35, :57:38, :60:37, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iw_p2_speculative_child = _T_179 ? _WIRE_iw_p2_speculative_child : issue_slots_11_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:35:17, :65:38, :67:43, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iw_p1_speculative_child = _T_179 ? _WIRE_iw_p1_speculative_child : issue_slots_11_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:35:17, :57:38, :59:43, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iw_issued = ~_T_179 & issue_slots_11_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_0 = _T_179 ? io_dis_uops_0_bits_fu_code_0_0 : issue_slots_11_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_1 = _T_179 ? io_dis_uops_0_bits_fu_code_1_0 : issue_slots_11_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_2 = _T_179 ? io_dis_uops_0_bits_fu_code_2_0 : issue_slots_11_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_3 = _T_179 ? io_dis_uops_0_bits_fu_code_3_0 : issue_slots_11_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_4 = _T_179 ? io_dis_uops_0_bits_fu_code_4_0 : issue_slots_11_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_5 = _T_179 ? io_dis_uops_0_bits_fu_code_5_0 : issue_slots_11_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_6 = _T_179 ? io_dis_uops_0_bits_fu_code_6_0 : issue_slots_11_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_7 = _T_179 ? io_dis_uops_0_bits_fu_code_7_0 : issue_slots_11_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_8 = _T_179 ? io_dis_uops_0_bits_fu_code_8_0 : issue_slots_11_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_9 = _T_179 ? io_dis_uops_0_bits_fu_code_9_0 : issue_slots_11_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iq_type_0 = _T_179 ? io_dis_uops_0_bits_iq_type_0_0 : issue_slots_11_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iq_type_1 = _T_179 ? io_dis_uops_0_bits_iq_type_1_0 : issue_slots_11_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iq_type_2 = _T_179 ? io_dis_uops_0_bits_iq_type_2_0 : issue_slots_11_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iq_type_3 = _T_179 ? io_dis_uops_0_bits_iq_type_3_0 : issue_slots_11_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_debug_pc = _T_179 ? io_dis_uops_0_bits_debug_pc_0 : issue_slots_11_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_rvc = _T_179 ? io_dis_uops_0_bits_is_rvc_0 : issue_slots_11_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_debug_inst = _T_179 ? io_dis_uops_0_bits_debug_inst_0 : issue_slots_11_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_inst = _T_179 ? io_dis_uops_0_bits_inst_0 : issue_slots_11_out_uop_inst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign _issue_slots_10_clear_T = |shamts_oh_10; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_10_clear = _issue_slots_10_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_181 = shamts_oh_13 == 2'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_11_in_uop_valid = _T_181 ? will_be_valid_13 : shamts_oh_12 == 2'h1 & will_be_valid_12; // @[issue-unit-age-ordered.scala:122:28, :158:23, :186:79, :191:33, :194:{28,48}, :195:37] assign issue_slots_11_in_uop_bits_debug_tsrc = _T_181 ? io_dis_uops_1_bits_debug_tsrc_0 : io_dis_uops_0_bits_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_debug_fsrc = _T_181 ? io_dis_uops_1_bits_debug_fsrc_0 : io_dis_uops_0_bits_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_bp_xcpt_if = _T_181 ? io_dis_uops_1_bits_bp_xcpt_if_0 : io_dis_uops_0_bits_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_bp_debug_if = _T_181 ? io_dis_uops_1_bits_bp_debug_if_0 : io_dis_uops_0_bits_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_xcpt_ma_if = _T_181 ? io_dis_uops_1_bits_xcpt_ma_if_0 : io_dis_uops_0_bits_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_xcpt_ae_if = _T_181 ? io_dis_uops_1_bits_xcpt_ae_if_0 : io_dis_uops_0_bits_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_xcpt_pf_if = _T_181 ? io_dis_uops_1_bits_xcpt_pf_if_0 : io_dis_uops_0_bits_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_typ = _T_181 ? io_dis_uops_1_bits_fp_typ_0 : io_dis_uops_0_bits_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_rm = _T_181 ? io_dis_uops_1_bits_fp_rm_0 : io_dis_uops_0_bits_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_val = _T_181 ? io_dis_uops_1_bits_fp_val_0 : io_dis_uops_0_bits_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fcn_op = _T_181 ? io_dis_uops_1_bits_fcn_op_0 : io_dis_uops_0_bits_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fcn_dw = _T_181 ? io_dis_uops_1_bits_fcn_dw_0 : io_dis_uops_0_bits_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_frs3_en = _T_181 ? io_dis_uops_1_bits_frs3_en_0 : io_dis_uops_0_bits_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_lrs2_rtype = _T_181 ? io_dis_uops_1_bits_lrs2_rtype_0 : io_dis_uops_0_bits_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_lrs1_rtype = _T_181 ? io_dis_uops_1_bits_lrs1_rtype_0 : io_dis_uops_0_bits_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_dst_rtype = _T_181 ? io_dis_uops_1_bits_dst_rtype_0 : io_dis_uops_0_bits_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_lrs3 = _T_181 ? io_dis_uops_1_bits_lrs3_0 : io_dis_uops_0_bits_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_lrs2 = _T_181 ? io_dis_uops_1_bits_lrs2_0 : io_dis_uops_0_bits_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_lrs1 = _T_181 ? io_dis_uops_1_bits_lrs1_0 : io_dis_uops_0_bits_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_ldst = _T_181 ? io_dis_uops_1_bits_ldst_0 : io_dis_uops_0_bits_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_ldst_is_rs1 = _T_181 ? io_dis_uops_1_bits_ldst_is_rs1_0 : io_dis_uops_0_bits_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_csr_cmd = _T_181 ? io_dis_uops_1_bits_csr_cmd_0 : io_dis_uops_0_bits_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_flush_on_commit = _T_181 ? io_dis_uops_1_bits_flush_on_commit_0 : io_dis_uops_0_bits_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_unique = _T_181 ? io_dis_uops_1_bits_is_unique_0 : io_dis_uops_0_bits_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_uses_stq = _T_181 ? io_dis_uops_1_bits_uses_stq_0 : io_dis_uops_0_bits_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_uses_ldq = _T_181 ? io_dis_uops_1_bits_uses_ldq_0 : io_dis_uops_0_bits_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_mem_signed = _T_181 ? io_dis_uops_1_bits_mem_signed_0 : io_dis_uops_0_bits_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_mem_size = _T_181 ? io_dis_uops_1_bits_mem_size_0 : io_dis_uops_0_bits_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_mem_cmd = _T_181 ? io_dis_uops_1_bits_mem_cmd_0 : io_dis_uops_0_bits_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_exc_cause = _T_181 ? io_dis_uops_1_bits_exc_cause_0 : io_dis_uops_0_bits_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_exception = _T_181 ? io_dis_uops_1_bits_exception_0 : io_dis_uops_0_bits_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_stale_pdst = _T_181 ? io_dis_uops_1_bits_stale_pdst_0 : io_dis_uops_0_bits_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_prs3_busy = _T_181 ? ~_T_116 & io_dis_uops_1_bits_prs3_busy_0 : _WIRE_prs3_busy; // @[issue-unit-age-ordered.scala:22:7, :35:17, :76:{32,38}, :77:29, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_prs2_busy = _T_181 ? ((|{prs2_rebusys_0_1, io_child_rebusys_0 & io_dis_uops_1_bits_iw_p2_speculative_child_0}) ? io_dis_uops_1_bits_lrs2_rtype_0 == 2'h0 : ~_T_92 & io_dis_uops_1_bits_prs2_busy_0) : _WIRE_prs2_busy; // @[issue-unit-age-ordered.scala:22:7, :35:17, :51:95, :65:{32,38}, :66:29, :71:{37,59,106,116}, :72:{29,63}, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_prs1_busy = _T_181 ? ((|{prs1_rebusys_0_1, io_child_rebusys_0 & io_dis_uops_1_bits_iw_p1_speculative_child_0}) ? io_dis_uops_1_bits_lrs1_rtype_0 == 2'h0 : ~_T_68 & io_dis_uops_1_bits_prs1_busy_0) : _WIRE_prs1_busy; // @[issue-unit-age-ordered.scala:22:7, :35:17, :50:95, :57:{32,38}, :58:29, :62:{37,59,106,116}, :63:{29,63}, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_ppred = _T_181 ? io_dis_uops_1_bits_ppred_0 : io_dis_uops_0_bits_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_prs3 = _T_181 ? io_dis_uops_1_bits_prs3_0 : io_dis_uops_0_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_prs2 = _T_181 ? (io_dis_uops_1_bits_fu_code_8_0 ? {2'h0, io_dis_uops_1_bits_fp_rm_0, io_dis_uops_1_bits_fp_typ_0} : io_dis_uops_1_bits_prs2_0) : _WIRE_prs2; // @[issue-unit-age-ordered.scala:22:7, :35:17, :86:50, :87:26, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_prs1 = _T_181 ? io_dis_uops_1_bits_prs1_0 : io_dis_uops_0_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_pdst = _T_181 ? io_dis_uops_1_bits_pdst_0 : io_dis_uops_0_bits_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_rxq_idx = _T_181 ? io_dis_uops_1_bits_rxq_idx_0 : io_dis_uops_0_bits_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_stq_idx = _T_181 ? io_dis_uops_1_bits_stq_idx_0 : io_dis_uops_0_bits_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_ldq_idx = _T_181 ? io_dis_uops_1_bits_ldq_idx_0 : io_dis_uops_0_bits_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_rob_idx = _T_181 ? io_dis_uops_1_bits_rob_idx_0 : io_dis_uops_0_bits_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_vec = _T_181 ? io_dis_uops_1_bits_fp_ctrl_vec_0 : io_dis_uops_0_bits_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_wflags = _T_181 ? io_dis_uops_1_bits_fp_ctrl_wflags_0 : io_dis_uops_0_bits_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_sqrt = _T_181 ? io_dis_uops_1_bits_fp_ctrl_sqrt_0 : io_dis_uops_0_bits_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_div = _T_181 ? io_dis_uops_1_bits_fp_ctrl_div_0 : io_dis_uops_0_bits_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_fma = _T_181 ? io_dis_uops_1_bits_fp_ctrl_fma_0 : io_dis_uops_0_bits_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_fastpipe = _T_181 ? io_dis_uops_1_bits_fp_ctrl_fastpipe_0 : io_dis_uops_0_bits_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_toint = _T_181 ? io_dis_uops_1_bits_fp_ctrl_toint_0 : io_dis_uops_0_bits_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_fromint = _T_181 ? io_dis_uops_1_bits_fp_ctrl_fromint_0 : io_dis_uops_0_bits_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_typeTagOut = _T_181 ? io_dis_uops_1_bits_fp_ctrl_typeTagOut_0 : io_dis_uops_0_bits_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_typeTagIn = _T_181 ? io_dis_uops_1_bits_fp_ctrl_typeTagIn_0 : io_dis_uops_0_bits_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_swap23 = _T_181 ? io_dis_uops_1_bits_fp_ctrl_swap23_0 : io_dis_uops_0_bits_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_swap12 = _T_181 ? io_dis_uops_1_bits_fp_ctrl_swap12_0 : io_dis_uops_0_bits_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_ren3 = _T_181 ? io_dis_uops_1_bits_fp_ctrl_ren3_0 : io_dis_uops_0_bits_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_ren2 = _T_181 ? io_dis_uops_1_bits_fp_ctrl_ren2_0 : io_dis_uops_0_bits_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_ren1 = _T_181 ? io_dis_uops_1_bits_fp_ctrl_ren1_0 : io_dis_uops_0_bits_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_wen = _T_181 ? io_dis_uops_1_bits_fp_ctrl_wen_0 : io_dis_uops_0_bits_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_ldst = _T_181 ? io_dis_uops_1_bits_fp_ctrl_ldst_0 : io_dis_uops_0_bits_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_op2_sel = _T_181 ? io_dis_uops_1_bits_op2_sel_0 : io_dis_uops_0_bits_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_op1_sel = _T_181 ? io_dis_uops_1_bits_op1_sel_0 : io_dis_uops_0_bits_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_imm_packed = _T_181 ? io_dis_uops_1_bits_imm_packed_0 : io_dis_uops_0_bits_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_pimm = _T_181 ? (io_dis_uops_1_bits_is_sfence_0 ? {3'h0, io_dis_uops_1_bits_mem_size_0} : io_dis_uops_1_bits_pimm_0) : _WIRE_pimm; // @[issue-unit-age-ordered.scala:22:7, :35:17, :89:44, :90:26, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_imm_sel = _T_181 ? io_dis_uops_1_bits_imm_sel_0 : io_dis_uops_0_bits_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_imm_rename = _T_181 ? io_dis_uops_1_bits_imm_rename_0 : io_dis_uops_0_bits_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_taken = _T_181 ? io_dis_uops_1_bits_taken_0 : io_dis_uops_0_bits_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_pc_lob = _T_181 ? io_dis_uops_1_bits_pc_lob_0 : io_dis_uops_0_bits_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_edge_inst = _T_181 ? io_dis_uops_1_bits_edge_inst_0 : io_dis_uops_0_bits_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_ftq_idx = _T_181 ? io_dis_uops_1_bits_ftq_idx_0 : io_dis_uops_0_bits_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_mov = _T_181 ? io_dis_uops_1_bits_is_mov_0 : io_dis_uops_0_bits_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_rocc = _T_181 ? io_dis_uops_1_bits_is_rocc_0 : io_dis_uops_0_bits_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_sys_pc2epc = _T_181 ? io_dis_uops_1_bits_is_sys_pc2epc_0 : io_dis_uops_0_bits_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_eret = _T_181 ? io_dis_uops_1_bits_is_eret_0 : io_dis_uops_0_bits_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_amo = _T_181 ? io_dis_uops_1_bits_is_amo_0 : io_dis_uops_0_bits_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_sfence = _T_181 ? io_dis_uops_1_bits_is_sfence_0 : io_dis_uops_0_bits_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_fencei = _T_181 ? io_dis_uops_1_bits_is_fencei_0 : io_dis_uops_0_bits_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_fence = _T_181 ? io_dis_uops_1_bits_is_fence_0 : io_dis_uops_0_bits_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_sfb = _T_181 ? io_dis_uops_1_bits_is_sfb_0 : io_dis_uops_0_bits_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_br_type = _T_181 ? io_dis_uops_1_bits_br_type_0 : io_dis_uops_0_bits_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_br_tag = _T_181 ? io_dis_uops_1_bits_br_tag_0 : io_dis_uops_0_bits_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_br_mask = _T_181 ? io_dis_uops_1_bits_br_mask_0 : io_dis_uops_0_bits_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_dis_col_sel = _T_181 ? io_dis_uops_1_bits_dis_col_sel_0 : io_dis_uops_0_bits_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_iw_p3_bypass_hint = _T_181 ? _T_116 & (prs3_wakeups_0_1 & io_wakeup_ports_0_bits_bypassable_0 | prs3_wakeups_2_1 | prs3_wakeups_3_1) : _WIRE_iw_p3_bypass_hint; // @[Mux.scala:30:73] assign issue_slots_11_in_uop_bits_iw_p2_bypass_hint = _T_181 ? _T_92 & (prs2_wakeups_0_1 & io_wakeup_ports_0_bits_bypassable_0 | prs2_wakeups_2_1 | prs2_wakeups_3_1) : _WIRE_iw_p2_bypass_hint; // @[Mux.scala:30:73] assign issue_slots_11_in_uop_bits_iw_p1_bypass_hint = _T_181 ? _T_68 & (prs1_wakeups_0_1 & io_wakeup_ports_0_bits_bypassable_0 | prs1_wakeups_2_1 | prs1_wakeups_3_1) : _WIRE_iw_p1_bypass_hint; // @[Mux.scala:30:73] assign issue_slots_11_in_uop_bits_iw_p2_speculative_child = _T_181 ? (_T_92 ? (prs2_wakeups_0_1 ? io_wakeup_ports_0_bits_speculative_mask_0 : 2'h0) | {prs2_wakeups_3_1, prs2_wakeups_2_1} : io_dis_uops_1_bits_iw_p2_speculative_child_0) : _WIRE_iw_p2_speculative_child; // @[Mux.scala:30:73] assign issue_slots_11_in_uop_bits_iw_p1_speculative_child = _T_181 ? (_T_68 ? (prs1_wakeups_0_1 ? io_wakeup_ports_0_bits_speculative_mask_0 : 2'h0) | {prs1_wakeups_3_1, prs1_wakeups_2_1} : io_dis_uops_1_bits_iw_p1_speculative_child_0) : _WIRE_iw_p1_speculative_child; // @[Mux.scala:30:73] assign issue_slots_11_in_uop_bits_fu_code_0 = _T_181 ? io_dis_uops_1_bits_fu_code_0_0 : io_dis_uops_0_bits_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_1 = _T_181 ? io_dis_uops_1_bits_fu_code_1_0 : io_dis_uops_0_bits_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_2 = _T_181 ? io_dis_uops_1_bits_fu_code_2_0 : io_dis_uops_0_bits_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_3 = _T_181 ? io_dis_uops_1_bits_fu_code_3_0 : io_dis_uops_0_bits_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_4 = _T_181 ? io_dis_uops_1_bits_fu_code_4_0 : io_dis_uops_0_bits_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_5 = _T_181 ? io_dis_uops_1_bits_fu_code_5_0 : io_dis_uops_0_bits_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_6 = _T_181 ? io_dis_uops_1_bits_fu_code_6_0 : io_dis_uops_0_bits_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_7 = _T_181 ? io_dis_uops_1_bits_fu_code_7_0 : io_dis_uops_0_bits_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_8 = _T_181 ? io_dis_uops_1_bits_fu_code_8_0 : io_dis_uops_0_bits_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_9 = _T_181 ? io_dis_uops_1_bits_fu_code_9_0 : io_dis_uops_0_bits_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_iq_type_0 = _T_181 ? io_dis_uops_1_bits_iq_type_0_0 : io_dis_uops_0_bits_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_iq_type_1 = _T_181 ? io_dis_uops_1_bits_iq_type_1_0 : io_dis_uops_0_bits_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_iq_type_2 = _T_181 ? io_dis_uops_1_bits_iq_type_2_0 : io_dis_uops_0_bits_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_iq_type_3 = _T_181 ? io_dis_uops_1_bits_iq_type_3_0 : io_dis_uops_0_bits_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_debug_pc = _T_181 ? io_dis_uops_1_bits_debug_pc_0 : io_dis_uops_0_bits_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_rvc = _T_181 ? io_dis_uops_1_bits_is_rvc_0 : io_dis_uops_0_bits_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_debug_inst = _T_181 ? io_dis_uops_1_bits_debug_inst_0 : io_dis_uops_0_bits_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_inst = _T_181 ? io_dis_uops_1_bits_inst_0 : io_dis_uops_0_bits_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign _issue_slots_11_clear_T = |shamts_oh_11; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_11_clear = _issue_slots_11_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] reg is_available_0; // @[issue-unit-age-ordered.scala:208:25] reg is_available_1; // @[issue-unit-age-ordered.scala:208:25] reg is_available_2; // @[issue-unit-age-ordered.scala:208:25] reg is_available_3; // @[issue-unit-age-ordered.scala:208:25] reg is_available_4; // @[issue-unit-age-ordered.scala:208:25] reg is_available_5; // @[issue-unit-age-ordered.scala:208:25] reg is_available_6; // @[issue-unit-age-ordered.scala:208:25] reg is_available_7; // @[issue-unit-age-ordered.scala:208:25] reg is_available_8; // @[issue-unit-age-ordered.scala:208:25] reg is_available_9; // @[issue-unit-age-ordered.scala:208:25] reg is_available_10; // @[issue-unit-age-ordered.scala:208:25] reg is_available_11; // @[issue-unit-age-ordered.scala:208:25] wire [1:0] _GEN = {1'h0, is_available_1} + {1'h0, is_available_2}; // @[issue-unit-age-ordered.scala:208:25, :212:45] wire [1:0] _io_dis_uops_0_ready_T; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_0_ready_T = _GEN; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_1_ready_T = _GEN; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_0_ready_T_1 = _io_dis_uops_0_ready_T; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _GEN_0 = {2'h0, is_available_0}; // @[issue-unit-age-ordered.scala:208:25, :212:45] wire [2:0] _io_dis_uops_0_ready_T_2 = _GEN_0 + {1'h0, _io_dis_uops_0_ready_T_1}; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_0_ready_T_3 = _io_dis_uops_0_ready_T_2[1:0]; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _GEN_1 = {1'h0, is_available_4} + {1'h0, is_available_5}; // @[issue-unit-age-ordered.scala:208:25, :212:45] wire [1:0] _io_dis_uops_0_ready_T_4; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_0_ready_T_4 = _GEN_1; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_4; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_1_ready_T_4 = _GEN_1; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_0_ready_T_5 = _io_dis_uops_0_ready_T_4; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _GEN_2 = {2'h0, is_available_3}; // @[issue-unit-age-ordered.scala:208:25, :212:45] wire [2:0] _io_dis_uops_0_ready_T_6 = _GEN_2 + {1'h0, _io_dis_uops_0_ready_T_5}; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_0_ready_T_7 = _io_dis_uops_0_ready_T_6[1:0]; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_0_ready_T_8 = {1'h0, _io_dis_uops_0_ready_T_3} + {1'h0, _io_dis_uops_0_ready_T_7}; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_0_ready_T_9 = _io_dis_uops_0_ready_T_8; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _GEN_3 = {1'h0, is_available_7} + {1'h0, is_available_8}; // @[issue-unit-age-ordered.scala:208:25, :212:45] wire [1:0] _io_dis_uops_0_ready_T_10; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_0_ready_T_10 = _GEN_3; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_10; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_1_ready_T_10 = _GEN_3; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_0_ready_T_11 = _io_dis_uops_0_ready_T_10; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _GEN_4 = {2'h0, is_available_6}; // @[issue-unit-age-ordered.scala:208:25, :212:45] wire [2:0] _io_dis_uops_0_ready_T_12 = _GEN_4 + {1'h0, _io_dis_uops_0_ready_T_11}; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_0_ready_T_13 = _io_dis_uops_0_ready_T_12[1:0]; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _GEN_5 = {1'h0, is_available_10} + {1'h0, is_available_11}; // @[issue-unit-age-ordered.scala:208:25, :212:45] wire [1:0] _io_dis_uops_0_ready_T_14; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_0_ready_T_14 = _GEN_5; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_14; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_1_ready_T_14 = _GEN_5; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_0_ready_T_15 = _io_dis_uops_0_ready_T_14; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _GEN_6 = {2'h0, is_available_9}; // @[issue-unit-age-ordered.scala:208:25, :212:45] wire [2:0] _io_dis_uops_0_ready_T_16 = _GEN_6 + {1'h0, _io_dis_uops_0_ready_T_15}; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_0_ready_T_17 = _io_dis_uops_0_ready_T_16[1:0]; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_0_ready_T_18 = {1'h0, _io_dis_uops_0_ready_T_13} + {1'h0, _io_dis_uops_0_ready_T_17}; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_0_ready_T_19 = _io_dis_uops_0_ready_T_18; // @[issue-unit-age-ordered.scala:212:45] wire [3:0] _io_dis_uops_0_ready_T_20 = {1'h0, _io_dis_uops_0_ready_T_9} + {1'h0, _io_dis_uops_0_ready_T_19}; // @[issue-unit-age-ordered.scala:212:45] wire [3:0] _io_dis_uops_0_ready_T_21 = _io_dis_uops_0_ready_T_20; // @[issue-unit-age-ordered.scala:212:45] wire _GEN_7 = io_dis_uops_0_ready_0 & io_dis_uops_0_valid_0; // @[Decoupled.scala:51:35] wire _io_dis_uops_0_ready_T_22; // @[Decoupled.scala:51:35] assign _io_dis_uops_0_ready_T_22 = _GEN_7; // @[Decoupled.scala:51:35] wire _io_dis_uops_1_ready_T_22; // @[Decoupled.scala:51:35] assign _io_dis_uops_1_ready_T_22 = _GEN_7; // @[Decoupled.scala:51:35] wire _GEN_8 = io_dis_uops_1_ready_0 & io_dis_uops_1_valid_0; // @[Decoupled.scala:51:35] wire _io_dis_uops_0_ready_T_23; // @[Decoupled.scala:51:35] assign _io_dis_uops_0_ready_T_23 = _GEN_8; // @[Decoupled.scala:51:35] wire _io_dis_uops_1_ready_T_23; // @[Decoupled.scala:51:35] assign _io_dis_uops_1_ready_T_23 = _GEN_8; // @[Decoupled.scala:51:35] wire [1:0] _io_dis_uops_0_ready_T_24 = {1'h0, _io_dis_uops_0_ready_T_22} + {1'h0, _io_dis_uops_0_ready_T_23}; // @[Decoupled.scala:51:35] wire [1:0] _io_dis_uops_0_ready_T_25 = _io_dis_uops_0_ready_T_24; // @[issue-unit-age-ordered.scala:212:100] wire [4:0] _io_dis_uops_0_ready_T_26 = {3'h0, _io_dis_uops_0_ready_T_25}; // @[issue-unit-age-ordered.scala:212:{90,100}] wire [3:0] _io_dis_uops_0_ready_T_27 = _io_dis_uops_0_ready_T_26[3:0]; // @[issue-unit-age-ordered.scala:212:90] wire _io_dis_uops_0_ready_T_28 = _io_dis_uops_0_ready_T_21 > _io_dis_uops_0_ready_T_27; // @[issue-unit-age-ordered.scala:212:{45,60,90}] reg io_dis_uops_0_ready_REG; // @[issue-unit-age-ordered.scala:212:36] assign io_dis_uops_0_ready_0 = io_dis_uops_0_ready_REG; // @[issue-unit-age-ordered.scala:22:7, :212:36] wire [1:0] _io_dis_uops_1_ready_T_1 = _io_dis_uops_1_ready_T; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_1_ready_T_2 = _GEN_0 + {1'h0, _io_dis_uops_1_ready_T_1}; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_3 = _io_dis_uops_1_ready_T_2[1:0]; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_5 = _io_dis_uops_1_ready_T_4; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_1_ready_T_6 = _GEN_2 + {1'h0, _io_dis_uops_1_ready_T_5}; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_7 = _io_dis_uops_1_ready_T_6[1:0]; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_1_ready_T_8 = {1'h0, _io_dis_uops_1_ready_T_3} + {1'h0, _io_dis_uops_1_ready_T_7}; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_1_ready_T_9 = _io_dis_uops_1_ready_T_8; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_11 = _io_dis_uops_1_ready_T_10; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_1_ready_T_12 = _GEN_4 + {1'h0, _io_dis_uops_1_ready_T_11}; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_13 = _io_dis_uops_1_ready_T_12[1:0]; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_15 = _io_dis_uops_1_ready_T_14; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_1_ready_T_16 = _GEN_6 + {1'h0, _io_dis_uops_1_ready_T_15}; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_17 = _io_dis_uops_1_ready_T_16[1:0]; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_1_ready_T_18 = {1'h0, _io_dis_uops_1_ready_T_13} + {1'h0, _io_dis_uops_1_ready_T_17}; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_1_ready_T_19 = _io_dis_uops_1_ready_T_18; // @[issue-unit-age-ordered.scala:212:45] wire [3:0] _io_dis_uops_1_ready_T_20 = {1'h0, _io_dis_uops_1_ready_T_9} + {1'h0, _io_dis_uops_1_ready_T_19}; // @[issue-unit-age-ordered.scala:212:45] wire [3:0] _io_dis_uops_1_ready_T_21 = _io_dis_uops_1_ready_T_20; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_24 = {1'h0, _io_dis_uops_1_ready_T_22} + {1'h0, _io_dis_uops_1_ready_T_23}; // @[Decoupled.scala:51:35] wire [1:0] _io_dis_uops_1_ready_T_25 = _io_dis_uops_1_ready_T_24; // @[issue-unit-age-ordered.scala:212:100] wire [4:0] _io_dis_uops_1_ready_T_26 = {3'h0, _io_dis_uops_1_ready_T_25} + 5'h1; // @[issue-unit-age-ordered.scala:212:{90,100}] wire [3:0] _io_dis_uops_1_ready_T_27 = _io_dis_uops_1_ready_T_26[3:0]; // @[issue-unit-age-ordered.scala:212:90] wire _io_dis_uops_1_ready_T_28 = _io_dis_uops_1_ready_T_21 > _io_dis_uops_1_ready_T_27; // @[issue-unit-age-ordered.scala:212:{45,60,90}] reg io_dis_uops_1_ready_REG; // @[issue-unit-age-ordered.scala:212:36] assign io_dis_uops_1_ready_0 = io_dis_uops_1_ready_REG; // @[issue-unit-age-ordered.scala:22:7, :212:36]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_32( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54] wire [258:0] _c_sizes_set_T_1 = 259'h0; // @[Monitor.scala:768:52] wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79] wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35] wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35] wire [79:0] c_opcodes_set = 80'h0; // @[Monitor.scala:740:34] wire [79:0] c_sizes_set = 80'h0; // @[Monitor.scala:741:34] wire [19:0] c_set = 20'h0; // @[Monitor.scala:738:34] wire [19:0] c_set_wo_ready = 20'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 5'h14; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [4:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [4:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 5'h14; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_732 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_732; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_732; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [4:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_805 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_805; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_805; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_805; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [4:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [19:0] inflight; // @[Monitor.scala:614:27] reg [79:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [79:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [19:0] a_set; // @[Monitor.scala:626:34] wire [19:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [79:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [79:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [79:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [79:0] _a_opcode_lookup_T_6 = {76'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [79:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[79:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [79:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [79:0] _a_size_lookup_T_6 = {76'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [79:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[79:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [31:0] _GEN_2 = 32'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [31:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[19:0] : 20'h0; // @[OneHot.scala:58:35] wire _T_658 = _T_732 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_658 ? _a_set_T[19:0] : 20'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_658 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_658 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [7:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [7:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [7:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_658 ? _a_opcodes_set_T_1[79:0] : 80'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [258:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_658 ? _a_sizes_set_T_1[79:0] : 80'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [19:0] d_clr; // @[Monitor.scala:664:34] wire [19:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [79:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [79:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_704 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [31:0] _GEN_5 = 32'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_704 & ~d_release_ack ? _d_clr_wo_ready_T[19:0] : 20'h0; // @[OneHot.scala:58:35] wire _T_673 = _T_805 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_673 ? _d_clr_T[19:0] : 20'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_673 ? _d_opcodes_clr_T_5[79:0] : 80'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [270:0] _d_sizes_clr_T_5 = 271'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_673 ? _d_sizes_clr_T_5[79:0] : 80'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [19:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [19:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [19:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [79:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [79:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [79:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [79:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [79:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [79:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [19:0] inflight_1; // @[Monitor.scala:726:35] wire [19:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [79:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [79:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [79:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [79:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [79:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [79:0] _c_opcode_lookup_T_6 = {76'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [79:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[79:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [79:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [79:0] _c_size_lookup_T_6 = {76'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [79:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[79:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [19:0] d_clr_1; // @[Monitor.scala:774:34] wire [19:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [79:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [79:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_776 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_776 & d_release_ack_1 ? _d_clr_wo_ready_T_1[19:0] : 20'h0; // @[OneHot.scala:58:35] wire _T_758 = _T_805 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_758 ? _d_clr_T_1[19:0] : 20'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_758 ? _d_opcodes_clr_T_11[79:0] : 80'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [270:0] _d_sizes_clr_T_11 = 271'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_758 ? _d_sizes_clr_T_11[79:0] : 80'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113] wire [19:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [19:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [79:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [79:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [79:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [79:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File RecFNToRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import consts._ class RecFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val in = Input(Bits((inExpWidth + inSigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawIn = rawFloatFromRecFN(inExpWidth, inSigWidth, io.in); if ((inExpWidth == outExpWidth) && (inSigWidth <= outSigWidth)) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- io.out := io.in<<(outSigWidth - inSigWidth) io.exceptionFlags := isSigNaNRawFloat(rawIn) ## 0.U(4.W) } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( inExpWidth, inSigWidth, outExpWidth, outSigWidth, flRoundOpt_sigMSBitAlwaysZero )) roundAnyRawFNToRecFN.io.invalidExc := isSigNaNRawFloat(rawIn) roundAnyRawFNToRecFN.io.infiniteExc := false.B roundAnyRawFNToRecFN.io.in := rawIn roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags } } File rawFloatFromRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ /*---------------------------------------------------------------------------- | In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be | set. *----------------------------------------------------------------------------*/ object rawFloatFromRecFN { def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat = { val exp = in(expWidth + sigWidth - 1, sigWidth - 1) val isZero = exp(expWidth, expWidth - 2) === 0.U val isSpecial = exp(expWidth, expWidth - 1) === 3.U val out = Wire(new RawFloat(expWidth, sigWidth)) out.isNaN := isSpecial && exp(expWidth - 2) out.isInf := isSpecial && ! exp(expWidth - 2) out.isZero := isZero out.sign := in(expWidth + sigWidth) out.sExp := exp.zext out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0) out } }
module RecFNToRecFN_40( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Tile.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ import Util._ /** * A Tile is a purely combinational 2D array of passThrough PEs. * a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs * @param width The data width of each PE in bits * @param rows Number of PEs on each row * @param columns Number of PEs on each column */ class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module { val io = IO(new Bundle { val in_a = Input(Vec(rows, inputType)) val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it val in_d = Input(Vec(columns, outputType)) val in_control = Input(Vec(columns, new PEControl(accType))) val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val in_last = Input(Vec(columns, Bool())) val out_a = Output(Vec(rows, inputType)) val out_c = Output(Vec(columns, outputType)) val out_b = Output(Vec(columns, outputType)) val out_control = Output(Vec(columns, new PEControl(accType))) val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val out_last = Output(Vec(columns, Bool())) val in_valid = Input(Vec(columns, Bool())) val out_valid = Output(Vec(columns, Bool())) val bad_dataflow = Output(Bool()) }) import ev._ val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls))) val tileT = tile.transpose // TODO: abstract hori/vert broadcast, all these connections look the same // Broadcast 'a' horizontally across the Tile for (r <- 0 until rows) { tile(r).foldLeft(io.in_a(r)) { case (in_a, pe) => pe.io.in_a := in_a pe.io.out_a } } // Broadcast 'b' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_b(c)) { case (in_b, pe) => pe.io.in_b := (if (tree_reduction) in_b.zero else in_b) pe.io.out_b } } // Broadcast 'd' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_d(c)) { case (in_d, pe) => pe.io.in_d := in_d pe.io.out_c } } // Broadcast 'control' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_control(c)) { case (in_ctrl, pe) => pe.io.in_control := in_ctrl pe.io.out_control } } // Broadcast 'garbage' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_valid(c)) { case (v, pe) => pe.io.in_valid := v pe.io.out_valid } } // Broadcast 'id' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_id(c)) { case (id, pe) => pe.io.in_id := id pe.io.out_id } } // Broadcast 'last' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_last(c)) { case (last, pe) => pe.io.in_last := last pe.io.out_last } } // Drive the Tile's bottom IO for (c <- 0 until columns) { io.out_c(c) := tile(rows-1)(c).io.out_c io.out_control(c) := tile(rows-1)(c).io.out_control io.out_id(c) := tile(rows-1)(c).io.out_id io.out_last(c) := tile(rows-1)(c).io.out_last io.out_valid(c) := tile(rows-1)(c).io.out_valid io.out_b(c) := { if (tree_reduction) { val prods = tileT(c).map(_.io.out_b) accumulateTree(prods :+ io.in_b(c)) } else { tile(rows - 1)(c).io.out_b } } } io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_||_)).reduce(_||_) // Drive the Tile's right IO for (r <- 0 until rows) { io.out_a(r) := tile(r)(columns-1).io.out_a } }
module Tile_82( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_338 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File RegisterRouter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes} import freechips.rocketchip.resources.{Device, Resource, ResourceBindings} import freechips.rocketchip.prci.{NoCrossing} import freechips.rocketchip.regmapper.{RegField, RegMapper, RegMapperParams, RegMapperInput, RegisterRouter} import freechips.rocketchip.util.{BundleField, ControlKey, ElaborationArtefacts, GenRegDescsAnno} import scala.math.min class TLRegisterRouterExtraBundle(val sourceBits: Int, val sizeBits: Int) extends Bundle { val source = UInt((sourceBits max 1).W) val size = UInt((sizeBits max 1).W) } case object TLRegisterRouterExtra extends ControlKey[TLRegisterRouterExtraBundle]("tlrr_extra") case class TLRegisterRouterExtraField(sourceBits: Int, sizeBits: Int) extends BundleField[TLRegisterRouterExtraBundle](TLRegisterRouterExtra, Output(new TLRegisterRouterExtraBundle(sourceBits, sizeBits)), x => { x.size := 0.U x.source := 0.U }) /** TLRegisterNode is a specialized TL SinkNode that encapsulates MMIO registers. * It provides functionality for describing and outputting metdata about the registers in several formats. * It also provides a concrete implementation of a regmap function that will be used * to wire a map of internal registers associated with this node to the node's interconnect port. */ case class TLRegisterNode( address: Seq[AddressSet], device: Device, deviceKey: String = "reg/control", concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)( implicit valName: ValName) extends SinkNode(TLImp)(Seq(TLSlavePortParameters.v1( Seq(TLSlaveParameters.v1( address = address, resources = Seq(Resource(device, deviceKey)), executable = executable, supportsGet = TransferSizes(1, beatBytes), supportsPutPartial = TransferSizes(1, beatBytes), supportsPutFull = TransferSizes(1, beatBytes), fifoId = Some(0))), // requests are handled in order beatBytes = beatBytes, minLatency = min(concurrency, 1)))) with TLFormatNode // the Queue adds at most one cycle { val size = 1 << log2Ceil(1 + address.map(_.max).max - address.map(_.base).min) require (size >= beatBytes) address.foreach { case a => require (a.widen(size-1).base == address.head.widen(size-1).base, s"TLRegisterNode addresses (${address}) must be aligned to its size ${size}") } // Calling this method causes the matching TL2 bundle to be // configured to route all requests to the listed RegFields. def regmap(mapping: RegField.Map*) = { val (bundleIn, edge) = this.in(0) val a = bundleIn.a val d = bundleIn.d val fields = TLRegisterRouterExtraField(edge.bundle.sourceBits, edge.bundle.sizeBits) +: a.bits.params.echoFields val params = RegMapperParams(log2Up(size/beatBytes), beatBytes, fields) val in = Wire(Decoupled(new RegMapperInput(params))) in.bits.read := a.bits.opcode === TLMessages.Get in.bits.index := edge.addr_hi(a.bits) in.bits.data := a.bits.data in.bits.mask := a.bits.mask Connectable.waiveUnmatched(in.bits.extra, a.bits.echo) match { case (lhs, rhs) => lhs :<= rhs } val a_extra = in.bits.extra(TLRegisterRouterExtra) a_extra.source := a.bits.source a_extra.size := a.bits.size // Invoke the register map builder val out = RegMapper(beatBytes, concurrency, undefZero, in, mapping:_*) // No flow control needed in.valid := a.valid a.ready := in.ready d.valid := out.valid out.ready := d.ready // We must restore the size to enable width adapters to work val d_extra = out.bits.extra(TLRegisterRouterExtra) d.bits := edge.AccessAck(toSource = d_extra.source, lgSize = d_extra.size) // avoid a Mux on the data bus by manually overriding two fields d.bits.data := out.bits.data Connectable.waiveUnmatched(d.bits.echo, out.bits.extra) match { case (lhs, rhs) => lhs :<= rhs } d.bits.opcode := Mux(out.bits.read, TLMessages.AccessAckData, TLMessages.AccessAck) // Tie off unused channels bundleIn.b.valid := false.B bundleIn.c.ready := true.B bundleIn.e.ready := true.B genRegDescsJson(mapping:_*) } def genRegDescsJson(mapping: RegField.Map*): Unit = { // Dump out the register map for documentation purposes. val base = address.head.base val baseHex = s"0x${base.toInt.toHexString}" val name = s"${device.describe(ResourceBindings()).name}.At${baseHex}" val json = GenRegDescsAnno.serialize(base, name, mapping:_*) var suffix = 0 while( ElaborationArtefacts.contains(s"${baseHex}.${suffix}.regmap.json")) { suffix = suffix + 1 } ElaborationArtefacts.add(s"${baseHex}.${suffix}.regmap.json", json) val module = Module.currentModule.get.asInstanceOf[RawModule] GenRegDescsAnno.anno( module, base, mapping:_*) } } /** Mix HasTLControlRegMap into any subclass of RegisterRouter to gain helper functions for attaching a device control register map to TileLink. * - The intended use case is that controlNode will diplomatically publish a SW-visible device's memory-mapped control registers. * - Use the clock crossing helper controlXing to externally connect controlNode to a TileLink interconnect. * - Use the mapping helper function regmap to internally fill out the space of device control registers. */ trait HasTLControlRegMap { this: RegisterRouter => protected val controlNode = TLRegisterNode( address = address, device = device, deviceKey = "reg/control", concurrency = concurrency, beatBytes = beatBytes, undefZero = undefZero, executable = executable) // Externally, this helper should be used to connect the register control port to a bus val controlXing: TLInwardClockCrossingHelper = this.crossIn(controlNode) // Backwards-compatibility default node accessor with no clock crossing lazy val node: TLInwardNode = controlXing(NoCrossing) // Internally, this function should be used to populate the control port with registers protected def regmap(mapping: RegField.Map*): Unit = { controlNode.regmap(mapping:_*) } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File DspBlocks.scala: package chipyard.example import chisel3._ import chisel3.util._ import dspblocks._ import dsptools.numbers._ import freechips.rocketchip.amba.axi4stream._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.regmapper._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.subsystem._ /** * The memory interface writes entries into the queue. * They stream out the streaming interface * @param depth number of entries in the queue * @param streamParameters parameters for the stream node * @param p */ abstract class WriteQueue[D, U, E, O, B <: Data] ( val depth: Int, val streamParameters: AXI4StreamMasterParameters = AXI4StreamMasterParameters() )(implicit p: Parameters) extends DspBlock[D, U, E, O, B] with HasCSR { // stream node, output only val streamNode = AXI4StreamMasterNode(streamParameters) lazy val module = new LazyModuleImp(this) { require(streamNode.out.length == 1) // get the output bundle associated with the AXI4Stream node val out = streamNode.out.head._1 // width (in bits) of the output interface val width = out.params.n * 8 // instantiate a queue val queue = Module(new Queue(UInt(out.params.dataBits.W), depth)) // connect queue output to streaming output out.valid := queue.io.deq.valid out.bits.data := queue.io.deq.bits // don't use last out.bits.last := false.B queue.io.deq.ready := out.ready regmap( // each write adds an entry to the queue 0x0 -> Seq(RegField.w(width, queue.io.enq)), // read the number of entries in the queue (width+7)/8 -> Seq(RegField.r(width, queue.io.count)), ) } } /** * TLDspBlock specialization of WriteQueue * @param depth number of entries in the queue * @param csrAddress address range for peripheral * @param beatBytes beatBytes of TL interface * @param p */ class TLWriteQueue (depth: Int, csrAddress: AddressSet, beatBytes: Int) (implicit p: Parameters) extends WriteQueue[ TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle ](depth) with TLHasCSR { val devname = "tlQueueIn" val devcompat = Seq("ucb-art", "dsptools") val device = new SimpleDevice(devname, devcompat) { override def describe(resources: ResourceBindings): Description = { val Description(name, mapping) = super.describe(resources) Description(name, mapping) } } // make diplomatic TL node for regmap override val mem = Some(TLRegisterNode(address = Seq(csrAddress), device = device, beatBytes = beatBytes)) } object TLWriteQueue { def apply( depth: Int = 8, csrAddress: AddressSet = AddressSet(0x2000, 0xff), beatBytes: Int = 8, )(implicit p: Parameters) = { val writeQueue = LazyModule(new TLWriteQueue(depth = depth, csrAddress = csrAddress, beatBytes = beatBytes)) writeQueue } } /** * The streaming interface adds elements into the queue. * The memory interface can read elements out of the queue. * @param depth number of entries in the queue * @param streamParameters parameters for the stream node * @param p */ abstract class ReadQueue[D, U, E, O, B <: Data] ( val depth: Int, val streamParameters: AXI4StreamSlaveParameters = AXI4StreamSlaveParameters() )(implicit p: Parameters) extends DspBlock[D, U, E, O, B] with HasCSR { val streamNode = AXI4StreamSlaveNode(streamParameters) lazy val module = new LazyModuleImp(this) { require(streamNode.in.length == 1) // get the input associated with the stream node val in = streamNode.in.head._1 // make a Decoupled[UInt] that RegReadFn can do something with val out = Wire(Decoupled(UInt())) // get width of streaming input interface val width = in.params.n * 8 // instantiate a queue val queue = Module(new Queue(UInt(in.params.dataBits.W), depth)) // connect input to the streaming interface queue.io.enq.valid := in.valid queue.io.enq.bits := in.bits.data in.ready := queue.io.enq.ready // connect output to wire out.valid := queue.io.deq.valid out.bits := queue.io.deq.bits queue.io.deq.ready := out.ready regmap( // map the output of the queue 0x0 -> Seq(RegField.r(width, RegReadFn(out))), // read the number of elements in the queue (width+7)/8 -> Seq(RegField.r(width, queue.io.count)), ) } } /** * TLDspBlock specialization of ReadQueue * @param depth number of entries in the queue * @param csrAddress address range * @param beatBytes beatBytes of TL interface * @param p */ class TLReadQueue( depth: Int, csrAddress: AddressSet, beatBytes: Int) (implicit p: Parameters) extends ReadQueue[ TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle ](depth) with TLHasCSR { val devname = "tlQueueOut" val devcompat = Seq("ucb-art", "dsptools") val device = new SimpleDevice(devname, devcompat) { override def describe(resources: ResourceBindings): Description = { val Description(name, mapping) = super.describe(resources) Description(name, mapping) } } // make diplomatic TL node for regmap override val mem = Some(TLRegisterNode(address = Seq(csrAddress), device = device, beatBytes = beatBytes)) } object TLReadQueue { def apply( depth: Int = 8, csrAddress: AddressSet = AddressSet(0x2100, 0xff), beatBytes: Int = 8)(implicit p: Parameters) = { val readQueue = LazyModule(new TLReadQueue(depth = depth, csrAddress = csrAddress, beatBytes = beatBytes)) readQueue } }
module TLReadQueue_1( // @[DspBlocks.scala:102:25] input clock, // @[DspBlocks.scala:102:25] input reset, // @[DspBlocks.scala:102:25] output auto_mem_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_mem_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_mem_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_mem_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_mem_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_mem_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [13:0] auto_mem_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_mem_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input auto_mem_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_mem_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_mem_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_mem_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_mem_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_mem_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_mem_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_stream_in_ready, // @[LazyModuleImp.scala:107:25] input auto_stream_in_valid, // @[LazyModuleImp.scala:107:25] input [63:0] auto_stream_in_bits_data // @[LazyModuleImp.scala:107:25] ); wire out_backSel_0; // @[RegisterRouter.scala:87:24] wire _queue_io_deq_valid; // @[DspBlocks.scala:112:23] wire [63:0] _queue_io_deq_bits; // @[DspBlocks.scala:112:23] wire [3:0] _queue_io_count; // @[DspBlocks.scala:112:23] wire in_bits_read = auto_mem_in_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] wire _out_T_3 = auto_mem_in_a_bits_address[7:4] == 4'h0; // @[RegisterRouter.scala:75:19, :87:24] wire [63:0] out_backMask = {{8{auto_mem_in_a_bits_mask[7]}}, {8{auto_mem_in_a_bits_mask[6]}}, {8{auto_mem_in_a_bits_mask[5]}}, {8{auto_mem_in_a_bits_mask[4]}}, {8{auto_mem_in_a_bits_mask[3]}}, {8{auto_mem_in_a_bits_mask[2]}}, {8{auto_mem_in_a_bits_mask[1]}}, {8{auto_mem_in_a_bits_mask[0]}}}; // @[RegisterRouter.scala:87:24] assign out_backSel_0 = ~(auto_mem_in_a_bits_address[3]); // @[RegisterRouter.scala:87:24] wire out_oready = ~in_bits_read | auto_mem_in_a_bits_address[3] | (|{_queue_io_deq_valid | ~(|out_backMask), auto_mem_in_a_bits_address[7:4]}); // @[MuxLiteral.scala:49:10] wire out_front_ready = auto_mem_in_d_ready & out_oready; // @[MuxLiteral.scala:49:10] wire out_1_valid = auto_mem_in_a_valid & out_oready; // @[MuxLiteral.scala:49:10] wire [2:0] memIn_d_bits_opcode = {2'h0, in_bits_read}; // @[RegisterRouter.scala:74:36, :105:19] TLMonitor_62 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (out_front_ready), // @[RegisterRouter.scala:87:24] .io_in_a_valid (auto_mem_in_a_valid), .io_in_a_bits_opcode (auto_mem_in_a_bits_opcode), .io_in_a_bits_param (auto_mem_in_a_bits_param), .io_in_a_bits_size (auto_mem_in_a_bits_size), .io_in_a_bits_source (auto_mem_in_a_bits_source), .io_in_a_bits_address (auto_mem_in_a_bits_address), .io_in_a_bits_mask (auto_mem_in_a_bits_mask), .io_in_a_bits_corrupt (auto_mem_in_a_bits_corrupt), .io_in_d_ready (auto_mem_in_d_ready), .io_in_d_valid (out_1_valid), // @[RegisterRouter.scala:87:24] .io_in_d_bits_opcode (memIn_d_bits_opcode), // @[RegisterRouter.scala:105:19] .io_in_d_bits_size (auto_mem_in_a_bits_size), .io_in_d_bits_source (auto_mem_in_a_bits_source) ); // @[Nodes.scala:27:25] Queue8_UInt64 queue ( // @[DspBlocks.scala:112:23] .clock (clock), .reset (reset), .io_enq_ready (auto_stream_in_ready), .io_enq_valid (auto_stream_in_valid), .io_enq_bits (auto_stream_in_bits_data), .io_deq_ready (auto_mem_in_a_valid & auto_mem_in_d_ready & in_bits_read & out_backSel_0 & _out_T_3 & (|out_backMask)), // @[RegisterRouter.scala:74:36, :87:24] .io_deq_valid (_queue_io_deq_valid), .io_deq_bits (_queue_io_deq_bits), .io_count (_queue_io_count) ); // @[DspBlocks.scala:112:23] assign auto_mem_in_a_ready = out_front_ready; // @[RegisterRouter.scala:87:24] assign auto_mem_in_d_valid = out_1_valid; // @[RegisterRouter.scala:87:24] assign auto_mem_in_d_bits_opcode = memIn_d_bits_opcode; // @[RegisterRouter.scala:105:19] assign auto_mem_in_d_bits_size = auto_mem_in_a_bits_size; // @[DspBlocks.scala:102:25] assign auto_mem_in_d_bits_source = auto_mem_in_a_bits_source; // @[DspBlocks.scala:102:25] assign auto_mem_in_d_bits_data = _out_T_3 ? (auto_mem_in_a_bits_address[3] ? {60'h0, _queue_io_count} : _queue_io_deq_bits) : 64'h0; // @[MuxLiteral.scala:49:10] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Error.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.devices.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.resources.SimpleDevice import freechips.rocketchip.tilelink.{TLArbiter, TLMessages, TLPermissions} /** Adds a /dev/null slave that generates TL error response messages */ class TLError(params: DevNullParams, buffer: Boolean = true, beatBytes: Int = 4)(implicit p: Parameters) extends DevNullDevice(params, minLatency = if (buffer) 1 else 0, beatBytes, new SimpleDevice("error-device", Seq("sifive,error0"))) { lazy val module = new Impl class Impl extends LazyModuleImp(this) { import TLMessages._ import TLPermissions._ val (in, edge) = node.in(0) val a = if (buffer) {Queue(in.a, 1)} else in.a val da = Wire(chiselTypeOf(in.d)) val idle = RegInit(true.B) val a_last = edge.last(a) val (da_first, da_last, _) = edge.firstlast(da) assert (idle || da_first) // we only send Grant, never GrantData => simplified flow control below a.ready := (da.ready && da_last && idle) || !a_last da.valid := a.valid && a_last && idle da.bits.opcode := TLMessages.adResponse(a.bits.opcode) da.bits.param := 0.U // toT, but error grants must be handled transiently (ie: you don't keep permissions) da.bits.size := a.bits.size da.bits.source := a.bits.source da.bits.sink := 0.U da.bits.denied := true.B da.bits.data := 0.U da.bits.corrupt := edge.hasData(da.bits) if (params.acquire) { val c = if (buffer) {Queue(in.c, 1)} else in.c val dc = Wire(chiselTypeOf(in.d)) val c_last = edge.last(c) val dc_last = edge.last(dc) // Only allow one Grant in-flight at a time when (da.fire && da.bits.opcode === Grant) { idle := false.B } when (in.e.fire) { idle := true.B } c.ready := (dc.ready && dc_last) || !c_last dc.valid := c.valid && c_last // ReleaseAck is not allowed to report failure dc.bits.opcode := ReleaseAck dc.bits.param := VecInit(toB, toN, toN)(c.bits.param(1,0)) dc.bits.size := c.bits.size dc.bits.source := c.bits.source dc.bits.sink := 0.U dc.bits.denied := false.B dc.bits.data := 0.U dc.bits.corrupt := false.B // Combine response channels TLArbiter.lowest(edge, in.d, dc, da) } else { in.d <> da } // We never probe or issue B requests in.b.valid := false.B // Sink GrantAcks in.e.ready := true.B } } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLError( // @[Error.scala:21:9] input clock, // @[Error.scala:21:9] input reset, // @[Error.scala:21:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [8:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [13:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [8:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire _a_q_io_deq_valid; // @[Decoupled.scala:362:21] wire [2:0] _a_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] wire [3:0] _a_q_io_deq_bits_size; // @[Decoupled.scala:362:21] wire auto_in_a_valid_0 = auto_in_a_valid; // @[Error.scala:21:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Error.scala:21:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Error.scala:21:9] wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Error.scala:21:9] wire [8:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Error.scala:21:9] wire [13:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Error.scala:21:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Error.scala:21:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Error.scala:21:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Error.scala:21:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Error.scala:21:9] wire [7:0][2:0] _GEN = '{3'h4, 3'h4, 3'h2, 3'h1, 3'h1, 3'h1, 3'h0, 3'h0}; wire auto_in_d_bits_denied = 1'h1; // @[Error.scala:21:9] wire nodeIn_d_bits_denied = 1'h1; // @[MixedNode.scala:551:17] wire da_bits_denied = 1'h1; // @[Error.scala:28:18] wire [1:0] auto_in_d_bits_param = 2'h0; // @[Error.scala:21:9] wire [1:0] nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] da_bits_param = 2'h0; // @[Error.scala:28:18] wire auto_in_d_bits_sink = 1'h0; // @[Error.scala:21:9] wire nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire da_bits_sink = 1'h0; // @[Error.scala:28:18] wire [63:0] auto_in_d_bits_data = 64'h0; // @[Error.scala:21:9] wire [63:0] nodeIn_d_bits_data = 64'h0; // @[MixedNode.scala:551:17] wire [63:0] da_bits_data = 64'h0; // @[Error.scala:28:18] wire [2:0] _da_bits_opcode_WIRE_6 = 3'h4; // @[Bundles.scala:47:27] wire [2:0] _da_bits_opcode_WIRE_7 = 3'h4; // @[Bundles.scala:47:27] wire [2:0] _da_bits_opcode_WIRE_5 = 3'h2; // @[Bundles.scala:47:27] wire [2:0] _da_bits_opcode_WIRE_2 = 3'h1; // @[Bundles.scala:47:27] wire [2:0] _da_bits_opcode_WIRE_3 = 3'h1; // @[Bundles.scala:47:27] wire [2:0] _da_bits_opcode_WIRE_4 = 3'h1; // @[Bundles.scala:47:27] wire [2:0] _da_bits_opcode_WIRE_0 = 3'h0; // @[Bundles.scala:47:27] wire [2:0] _da_bits_opcode_WIRE_1 = 3'h0; // @[Bundles.scala:47:27] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Error.scala:21:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Error.scala:21:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Error.scala:21:9] wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Error.scala:21:9] wire [8:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Error.scala:21:9] wire [13:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Error.scala:21:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Error.scala:21:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Error.scala:21:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Error.scala:21:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Error.scala:21:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [8:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire auto_in_a_ready_0; // @[Error.scala:21:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Error.scala:21:9] wire [3:0] auto_in_d_bits_size_0; // @[Error.scala:21:9] wire [8:0] auto_in_d_bits_source_0; // @[Error.scala:21:9] wire auto_in_d_bits_corrupt_0; // @[Error.scala:21:9] wire auto_in_d_valid_0; // @[Error.scala:21:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Error.scala:21:9] wire da_ready = nodeIn_d_ready; // @[Error.scala:28:18] wire da_valid; // @[Error.scala:28:18] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Error.scala:21:9] wire [2:0] da_bits_opcode; // @[Error.scala:28:18] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Error.scala:21:9] wire [3:0] da_bits_size; // @[Error.scala:28:18] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Error.scala:21:9] wire [8:0] da_bits_source; // @[Error.scala:28:18] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Error.scala:21:9] wire da_bits_corrupt; // @[Error.scala:28:18] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Error.scala:21:9] wire _da_valid_T_1; // @[Error.scala:36:35] assign nodeIn_d_valid = da_valid; // @[Error.scala:28:18] assign nodeIn_d_bits_opcode = da_bits_opcode; // @[Error.scala:28:18] assign nodeIn_d_bits_size = da_bits_size; // @[Error.scala:28:18] assign nodeIn_d_bits_source = da_bits_source; // @[Error.scala:28:18] wire da_bits_corrupt_opdata; // @[Edges.scala:106:36] assign nodeIn_d_bits_corrupt = da_bits_corrupt; // @[Error.scala:28:18] wire _q_io_deq_ready_T_3; // @[Error.scala:35:46] wire _a_last_T = _q_io_deq_ready_T_3 & _a_q_io_deq_valid; // @[Decoupled.scala:51:35, :362:21] wire [26:0] _a_last_beats1_decode_T = 27'hFFF << _a_q_io_deq_bits_size; // @[Decoupled.scala:362:21] wire [11:0] _a_last_beats1_decode_T_1 = _a_last_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_last_beats1_decode_T_2 = ~_a_last_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_last_beats1_decode = _a_last_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_last_beats1_opdata_T = _a_q_io_deq_bits_opcode[2]; // @[Decoupled.scala:362:21] wire a_last_beats1_opdata = ~_a_last_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_last_beats1 = a_last_beats1_opdata ? a_last_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_last_counter; // @[Edges.scala:229:27] wire [9:0] _a_last_counter1_T = {1'h0, a_last_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_last_counter1 = _a_last_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_last_first = a_last_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_last_last_T = a_last_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_last_last_T_1 = a_last_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_last = _a_last_last_T | _a_last_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_last_done = a_last & _a_last_T; // @[Decoupled.scala:51:35] wire [8:0] _a_last_count_T = ~a_last_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_last_count = a_last_beats1 & _a_last_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_last_counter_T = a_last_first ? a_last_beats1 : a_last_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire _T = da_ready & da_valid; // @[Decoupled.scala:51:35] wire [26:0] _r_beats1_decode_T = 27'hFFF << da_bits_size; // @[package.scala:243:71] wire [11:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] r_beats1_decode = _r_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire r_beats1_opdata = da_bits_opcode[0]; // @[Edges.scala:106:36] assign da_bits_corrupt_opdata = da_bits_opcode[0]; // @[Edges.scala:106:36] wire [8:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] r_counter; // @[Edges.scala:229:27] wire [9:0] _r_counter1_T = {1'h0, r_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] r_counter1 = _r_counter1_T[8:0]; // @[Edges.scala:230:28] wire da_first = r_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _r_last_T = r_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _r_last_T_1 = r_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire da_last = _r_last_T | _r_last_T_1; // @[Edges.scala:232:{25,33,43}] wire r_3 = da_last & _T; // @[Decoupled.scala:51:35] wire [8:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] r_4 = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _r_counter_T = da_first ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire _q_io_deq_ready_T = da_ready & da_last; // @[Edges.scala:232:33] wire _q_io_deq_ready_T_1 = _q_io_deq_ready_T; // @[Error.scala:35:{26,37}] wire _q_io_deq_ready_T_2 = ~a_last; // @[Edges.scala:232:33] assign _q_io_deq_ready_T_3 = _q_io_deq_ready_T_1 | _q_io_deq_ready_T_2; // @[Error.scala:35:{37,46,49}] wire _da_valid_T = _a_q_io_deq_valid & a_last; // @[Decoupled.scala:362:21] assign _da_valid_T_1 = _da_valid_T; // @[Error.scala:36:{25,35}] assign da_valid = _da_valid_T_1; // @[Error.scala:28:18, :36:35] assign da_bits_opcode = _GEN[_a_q_io_deq_bits_opcode]; // @[Decoupled.scala:362:21] assign da_bits_corrupt = da_bits_corrupt_opdata; // @[Edges.scala:106:36] always @(posedge clock) begin // @[Error.scala:21:9] if (reset) begin // @[Error.scala:21:9] a_last_counter <= 9'h0; // @[Edges.scala:229:27] r_counter <= 9'h0; // @[Edges.scala:229:27] end else begin // @[Error.scala:21:9] if (_a_last_T) // @[Decoupled.scala:51:35] a_last_counter <= _a_last_counter_T; // @[Edges.scala:229:27, :236:21] if (_T) // @[Decoupled.scala:51:35] r_counter <= _r_counter_T; // @[Edges.scala:229:27, :236:21] end always @(posedge) TLMonitor_21 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue1_TLBundleA_a14d64s9k1z4u a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (_q_io_deq_ready_T_3), // @[Error.scala:35:46] .io_deq_valid (_a_q_io_deq_valid), .io_deq_bits_opcode (_a_q_io_deq_bits_opcode), .io_deq_bits_size (_a_q_io_deq_bits_size), .io_deq_bits_source (da_bits_source) ); // @[Decoupled.scala:362:21] assign da_bits_size = _a_q_io_deq_bits_size; // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Error.scala:21:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Error.scala:21:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Error.scala:21:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Error.scala:21:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Error.scala:21:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Error.scala:21:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File RecFNToIN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util.log2Up import scala.math._ import consts._ class RecFNToIN(expWidth: Int, sigWidth: Int, intWidth: Int) extends chisel3.Module { override def desiredName = s"RecFNToIN_e${expWidth}_s${sigWidth}_i${intWidth}" val io = IO(new Bundle { val in = Input(Bits((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val signedOut = Input(Bool()) val out = Output(Bits(intWidth.W)) val intExceptionFlags = Output(Bits(3.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawIn = rawFloatFromRecFN(expWidth, sigWidth, io.in) val magGeOne = rawIn.sExp(expWidth) val posExp = rawIn.sExp(expWidth - 1, 0) val magJustBelowOne = !magGeOne && posExp.andR //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_near_even = (io.roundingMode === round_near_even) val roundingMode_minMag = (io.roundingMode === round_minMag) val roundingMode_min = (io.roundingMode === round_min) val roundingMode_max = (io.roundingMode === round_max) val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag) val roundingMode_odd = (io.roundingMode === round_odd) /*------------------------------------------------------------------------ | Assuming the input floating-point value is not a NaN, its magnitude is | at least 1, and it is not obviously so large as to lead to overflow, | convert its significand to fixed-point (i.e., with the binary point in a | fixed location). For a non-NaN input with a magnitude less than 1, this | expression contrives to ensure that the integer bits of 'alignedSig' | will all be zeros. *------------------------------------------------------------------------*/ val shiftedSig = (magGeOne ## rawIn.sig(sigWidth - 2, 0))<< Mux(magGeOne, rawIn.sExp(min(expWidth - 2, log2Up(intWidth) - 1), 0), 0.U ) val alignedSig = (shiftedSig>>(sigWidth - 2)) ## shiftedSig(sigWidth - 3, 0).orR val unroundedInt = 0.U(intWidth.W) | alignedSig>>2 val common_inexact = Mux(magGeOne, alignedSig(1, 0).orR, !rawIn.isZero) val roundIncr_near_even = (magGeOne && (alignedSig(2, 1).andR || alignedSig(1, 0).andR)) || (magJustBelowOne && alignedSig(1, 0).orR) val roundIncr_near_maxMag = (magGeOne && alignedSig(1)) || magJustBelowOne val roundIncr = (roundingMode_near_even && roundIncr_near_even ) || (roundingMode_near_maxMag && roundIncr_near_maxMag) || ((roundingMode_min || roundingMode_odd) && (rawIn.sign && common_inexact)) || (roundingMode_max && (!rawIn.sign && common_inexact)) val complUnroundedInt = Mux(rawIn.sign, ~unroundedInt, unroundedInt) val roundedInt = Mux(roundIncr ^ rawIn.sign, complUnroundedInt + 1.U, complUnroundedInt ) | (roundingMode_odd && common_inexact) val magGeOne_atOverflowEdge = (posExp === (intWidth - 1).U) //*** CHANGE TO TAKE BITS FROM THE ORIGINAL 'rawIn.sig' INSTEAD OF FROM //*** 'unroundedInt'?: val roundCarryBut2 = unroundedInt(intWidth - 3, 0).andR && roundIncr val common_overflow = Mux(magGeOne, (posExp >= intWidth.U) || Mux(io.signedOut, Mux(rawIn.sign, magGeOne_atOverflowEdge && (unroundedInt(intWidth - 2, 0).orR || roundIncr), magGeOne_atOverflowEdge || ((posExp === (intWidth - 2).U) && roundCarryBut2) ), rawIn.sign || (magGeOne_atOverflowEdge && unroundedInt(intWidth - 2) && roundCarryBut2) ), !io.signedOut && rawIn.sign && roundIncr ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val invalidExc = rawIn.isNaN || rawIn.isInf val overflow = !invalidExc && common_overflow val inexact = !invalidExc && !common_overflow && common_inexact val excSign = !rawIn.isNaN && rawIn.sign val excOut = Mux((io.signedOut === excSign), (BigInt(1)<<(intWidth - 1)).U, 0.U ) | Mux(!excSign, ((BigInt(1)<<(intWidth - 1)) - 1).U, 0.U) io.out := Mux(invalidExc || common_overflow, excOut, roundedInt) io.intExceptionFlags := invalidExc ## overflow ## inexact } File rawFloatFromRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ /*---------------------------------------------------------------------------- | In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be | set. *----------------------------------------------------------------------------*/ object rawFloatFromRecFN { def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat = { val exp = in(expWidth + sigWidth - 1, sigWidth - 1) val isZero = exp(expWidth, expWidth - 2) === 0.U val isSpecial = exp(expWidth, expWidth - 1) === 3.U val out = Wire(new RawFloat(expWidth, sigWidth)) out.isNaN := isSpecial && exp(expWidth - 2) out.isInf := isSpecial && ! exp(expWidth - 2) out.isZero := isZero out.sign := in(expWidth + sigWidth) out.sExp := exp.zext out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0) out } }
module RecFNToIN_e8_s24_i32_1( // @[RecFNToIN.scala:46:7] input clock, // @[RecFNToIN.scala:46:7] input reset, // @[RecFNToIN.scala:46:7] input [32:0] io_in, // @[RecFNToIN.scala:49:16] output [31:0] io_out, // @[RecFNToIN.scala:49:16] output [2:0] io_intExceptionFlags // @[RecFNToIN.scala:49:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToIN.scala:46:7] wire roundingMode_minMag = 1'h0; // @[RecFNToIN.scala:68:53] wire roundingMode_min = 1'h0; // @[RecFNToIN.scala:69:53] wire roundingMode_max = 1'h0; // @[RecFNToIN.scala:70:53] wire roundingMode_near_maxMag = 1'h0; // @[RecFNToIN.scala:71:53] wire roundingMode_odd = 1'h0; // @[RecFNToIN.scala:72:53] wire _roundIncr_T_1 = 1'h0; // @[RecFNToIN.scala:99:35] wire _roundIncr_T_3 = 1'h0; // @[RecFNToIN.scala:100:28] wire _roundIncr_T_5 = 1'h0; // @[RecFNToIN.scala:100:49] wire _roundIncr_T_9 = 1'h0; // @[RecFNToIN.scala:102:27] wire _roundedInt_T_4 = 1'h0; // @[RecFNToIN.scala:108:31] wire _common_overflow_T_15 = 1'h0; // @[RecFNToIN.scala:128:13] wire _common_overflow_T_16 = 1'h0; // @[RecFNToIN.scala:128:27] wire _common_overflow_T_17 = 1'h0; // @[RecFNToIN.scala:128:41] wire io_signedOut = 1'h1; // @[RecFNToIN.scala:46:7] wire roundingMode_near_even = 1'h1; // @[RecFNToIN.scala:67:53] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToIN.scala:46:7] wire [31:0] _io_out_T_1; // @[RecFNToIN.scala:145:18] wire [2:0] _io_intExceptionFlags_T_1; // @[RecFNToIN.scala:146:52] wire [31:0] io_out_0; // @[RecFNToIN.scala:46:7] wire [2:0] io_intExceptionFlags_0; // @[RecFNToIN.scala:46:7] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire magGeOne = rawIn_sExp[8]; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] posExp = rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire _magJustBelowOne_T = ~magGeOne; // @[RecFNToIN.scala:61:30, :63:27] wire _magJustBelowOne_T_1 = &posExp; // @[RecFNToIN.scala:62:28, :63:47] wire magJustBelowOne = _magJustBelowOne_T & _magJustBelowOne_T_1; // @[RecFNToIN.scala:63:{27,37,47}] wire [22:0] _shiftedSig_T = rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _shiftedSig_T_1 = {magGeOne, _shiftedSig_T}; // @[RecFNToIN.scala:61:30, :83:{19,31}] wire [4:0] _shiftedSig_T_2 = rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _shiftedSig_T_3 = magGeOne ? _shiftedSig_T_2 : 5'h0; // @[RecFNToIN.scala:61:30, :84:16, :85:27] wire [54:0] shiftedSig = {31'h0, _shiftedSig_T_1} << _shiftedSig_T_3; // @[RecFNToIN.scala:83:{19,49}, :84:16] wire [32:0] _alignedSig_T = shiftedSig[54:22]; // @[RecFNToIN.scala:83:49, :89:20] wire [21:0] _alignedSig_T_1 = shiftedSig[21:0]; // @[RecFNToIN.scala:83:49, :89:51] wire _alignedSig_T_2 = |_alignedSig_T_1; // @[RecFNToIN.scala:89:{51,69}] wire [33:0] alignedSig = {_alignedSig_T, _alignedSig_T_2}; // @[RecFNToIN.scala:89:{20,38,69}] wire [31:0] _unroundedInt_T = alignedSig[33:2]; // @[RecFNToIN.scala:89:38, :90:52] wire [31:0] unroundedInt = _unroundedInt_T; // @[RecFNToIN.scala:90:{40,52}] wire [1:0] _common_inexact_T = alignedSig[1:0]; // @[RecFNToIN.scala:89:38, :92:50] wire [1:0] _roundIncr_near_even_T_2 = alignedSig[1:0]; // @[RecFNToIN.scala:89:38, :92:50, :94:64] wire [1:0] _roundIncr_near_even_T_6 = alignedSig[1:0]; // @[RecFNToIN.scala:89:38, :92:50, :95:39] wire _common_inexact_T_1 = |_common_inexact_T; // @[RecFNToIN.scala:92:{50,57}] wire _common_inexact_T_2 = ~rawIn_isZero_0; // @[rawFloatFromRecFN.scala:55:23] wire common_inexact = magGeOne ? _common_inexact_T_1 : _common_inexact_T_2; // @[RecFNToIN.scala:61:30, :92:{29,57,62}] wire [1:0] _roundIncr_near_even_T = alignedSig[2:1]; // @[RecFNToIN.scala:89:38, :94:39] wire _roundIncr_near_even_T_1 = &_roundIncr_near_even_T; // @[RecFNToIN.scala:94:{39,46}] wire _roundIncr_near_even_T_3 = &_roundIncr_near_even_T_2; // @[RecFNToIN.scala:94:{64,71}] wire _roundIncr_near_even_T_4 = _roundIncr_near_even_T_1 | _roundIncr_near_even_T_3; // @[RecFNToIN.scala:94:{46,51,71}] wire _roundIncr_near_even_T_5 = magGeOne & _roundIncr_near_even_T_4; // @[RecFNToIN.scala:61:30, :94:{25,51}] wire _roundIncr_near_even_T_7 = |_roundIncr_near_even_T_6; // @[RecFNToIN.scala:95:{39,46}] wire _roundIncr_near_even_T_8 = magJustBelowOne & _roundIncr_near_even_T_7; // @[RecFNToIN.scala:63:37, :95:{26,46}] wire roundIncr_near_even = _roundIncr_near_even_T_5 | _roundIncr_near_even_T_8; // @[RecFNToIN.scala:94:{25,78}, :95:26] wire _roundIncr_T = roundIncr_near_even; // @[RecFNToIN.scala:94:78, :98:35] wire _roundIncr_near_maxMag_T = alignedSig[1]; // @[RecFNToIN.scala:89:38, :96:56] wire _roundIncr_near_maxMag_T_1 = magGeOne & _roundIncr_near_maxMag_T; // @[RecFNToIN.scala:61:30, :96:{43,56}] wire roundIncr_near_maxMag = _roundIncr_near_maxMag_T_1 | magJustBelowOne; // @[RecFNToIN.scala:63:37, :96:{43,61}] wire _roundIncr_T_2 = _roundIncr_T; // @[RecFNToIN.scala:98:{35,61}] wire _roundIncr_T_6 = _roundIncr_T_2; // @[RecFNToIN.scala:98:61, :99:61] wire _roundIncr_T_4 = rawIn_sign & common_inexact; // @[rawFloatFromRecFN.scala:55:23] wire roundIncr = _roundIncr_T_6; // @[RecFNToIN.scala:99:61, :101:46] wire _roundIncr_T_7 = ~rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire _roundIncr_T_8 = _roundIncr_T_7 & common_inexact; // @[RecFNToIN.scala:92:29, :102:{31,43}] wire [31:0] _complUnroundedInt_T = ~unroundedInt; // @[RecFNToIN.scala:90:40, :103:45] wire [31:0] complUnroundedInt = rawIn_sign ? _complUnroundedInt_T : unroundedInt; // @[rawFloatFromRecFN.scala:55:23] wire _roundedInt_T = roundIncr ^ rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [32:0] _roundedInt_T_1 = {1'h0, complUnroundedInt} + 33'h1; // @[RecFNToIN.scala:103:32, :106:31] wire [31:0] _roundedInt_T_2 = _roundedInt_T_1[31:0]; // @[RecFNToIN.scala:106:31] wire [31:0] _roundedInt_T_3 = _roundedInt_T ? _roundedInt_T_2 : complUnroundedInt; // @[RecFNToIN.scala:103:32, :105:{12,23}, :106:31] wire [31:0] roundedInt = _roundedInt_T_3; // @[RecFNToIN.scala:105:12, :108:11] wire magGeOne_atOverflowEdge = posExp == 8'h1F; // @[RecFNToIN.scala:62:28, :110:43] wire [29:0] _roundCarryBut2_T = unroundedInt[29:0]; // @[RecFNToIN.scala:90:40, :113:38] wire _roundCarryBut2_T_1 = &_roundCarryBut2_T; // @[RecFNToIN.scala:113:{38,56}] wire roundCarryBut2 = _roundCarryBut2_T_1 & roundIncr; // @[RecFNToIN.scala:101:46, :113:{56,61}] wire _common_overflow_T = |(posExp[7:5]); // @[RecFNToIN.scala:62:28, :116:21] wire [30:0] _common_overflow_T_1 = unroundedInt[30:0]; // @[RecFNToIN.scala:90:40, :120:42] wire _common_overflow_T_2 = |_common_overflow_T_1; // @[RecFNToIN.scala:120:{42,60}] wire _common_overflow_T_3 = _common_overflow_T_2 | roundIncr; // @[RecFNToIN.scala:101:46, :120:{60,64}] wire _common_overflow_T_4 = magGeOne_atOverflowEdge & _common_overflow_T_3; // @[RecFNToIN.scala:110:43, :119:49, :120:64] wire _common_overflow_T_5 = posExp == 8'h1E; // @[RecFNToIN.scala:62:28, :122:38] wire _common_overflow_T_6 = _common_overflow_T_5 & roundCarryBut2; // @[RecFNToIN.scala:113:61, :122:{38,60}] wire _common_overflow_T_7 = magGeOne_atOverflowEdge | _common_overflow_T_6; // @[RecFNToIN.scala:110:43, :121:49, :122:60] wire _common_overflow_T_8 = rawIn_sign ? _common_overflow_T_4 : _common_overflow_T_7; // @[rawFloatFromRecFN.scala:55:23] wire _common_overflow_T_13 = _common_overflow_T_8; // @[RecFNToIN.scala:117:20, :118:24] wire _common_overflow_T_9 = unroundedInt[30]; // @[RecFNToIN.scala:90:40, :126:42] wire _common_overflow_T_10 = magGeOne_atOverflowEdge & _common_overflow_T_9; // @[RecFNToIN.scala:110:43, :125:50, :126:42] wire _common_overflow_T_11 = _common_overflow_T_10 & roundCarryBut2; // @[RecFNToIN.scala:113:61, :125:50, :126:57] wire _common_overflow_T_12 = rawIn_sign | _common_overflow_T_11; // @[rawFloatFromRecFN.scala:55:23] wire _common_overflow_T_14 = _common_overflow_T | _common_overflow_T_13; // @[RecFNToIN.scala:116:{21,36}, :117:20] wire common_overflow = magGeOne & _common_overflow_T_14; // @[RecFNToIN.scala:61:30, :115:12, :116:36] wire invalidExc = rawIn_isNaN | rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire _overflow_T = ~invalidExc; // @[RecFNToIN.scala:133:34, :134:20] wire overflow = _overflow_T & common_overflow; // @[RecFNToIN.scala:115:12, :134:{20,32}] wire _inexact_T = ~invalidExc; // @[RecFNToIN.scala:133:34, :134:20, :135:20] wire _inexact_T_1 = ~common_overflow; // @[RecFNToIN.scala:115:12, :135:35] wire _inexact_T_2 = _inexact_T & _inexact_T_1; // @[RecFNToIN.scala:135:{20,32,35}] wire inexact = _inexact_T_2 & common_inexact; // @[RecFNToIN.scala:92:29, :135:{32,52}] wire _excSign_T = ~rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire excSign = _excSign_T & rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire _excOut_T = excSign; // @[RecFNToIN.scala:137:32, :139:27] wire [31:0] _excOut_T_1 = {_excOut_T, 31'h0}; // @[RecFNToIN.scala:139:{12,27}] wire _excOut_T_2 = ~excSign; // @[RecFNToIN.scala:137:32, :143:13] wire [30:0] _excOut_T_3 = {31{_excOut_T_2}}; // @[RecFNToIN.scala:143:{12,13}] wire [31:0] excOut = {_excOut_T_1[31], _excOut_T_1[30:0] | _excOut_T_3}; // @[RecFNToIN.scala:139:12, :142:11, :143:12] wire _io_out_T = invalidExc | common_overflow; // @[RecFNToIN.scala:115:12, :133:34, :145:30] assign _io_out_T_1 = _io_out_T ? excOut : roundedInt; // @[RecFNToIN.scala:108:11, :142:11, :145:{18,30}] assign io_out_0 = _io_out_T_1; // @[RecFNToIN.scala:46:7, :145:18] wire [1:0] _io_intExceptionFlags_T = {invalidExc, overflow}; // @[RecFNToIN.scala:133:34, :134:32, :146:40] assign _io_intExceptionFlags_T_1 = {_io_intExceptionFlags_T, inexact}; // @[RecFNToIN.scala:135:52, :146:{40,52}] assign io_intExceptionFlags_0 = _io_intExceptionFlags_T_1; // @[RecFNToIN.scala:46:7, :146:52] assign io_out = io_out_0; // @[RecFNToIN.scala:46:7] assign io_intExceptionFlags = io_intExceptionFlags_0; // @[RecFNToIN.scala:46:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }
module AsyncValidSync_151( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_172 io_out_source_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} |acquireB = ${acquireB} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT || supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED || supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED || supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB || supportsGet, w = supportsAcquireT || supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} |Slave Address = ${address} |supports = ${supports.infoString} | |""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ || _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_||_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ || _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B || s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_||_) }.foldLeft(false.B)(_||_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} |visibility = ${visibility} |emits = ${emits.infoString} |sourceId = ${sourceId} | |""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ || _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ || _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ || _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ || _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ || _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ || _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ || _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ || _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_||_) }.foldLeft(false.B)(_||_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE || x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps */ class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_47( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready = 1'h1; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26] wire mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size = 1'h1; // @[Misc.scala:209:26] wire mask_acc = 1'h1; // @[Misc.scala:215:29] wire mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_4 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_5 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_6 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_7 = 1'h1; // @[Misc.scala:215:29] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire _a_first_beats1_opdata_T = 1'h1; // @[Edges.scala:92:37] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_beats1_opdata_T_1 = 1'h1; // @[Edges.scala:92:37] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7] wire mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire a_first_beats1_opdata = 1'h0; // @[Edges.scala:92:28] wire a_first_beats1_opdata_1 = 1'h0; // @[Edges.scala:92:28] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] a_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] a_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] a_first_beats1_1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] a_first_count_1 = 9'h0; // @[Edges.scala:234:25] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [3:0] io_in_a_bits_size = 4'h6; // @[Monitor.scala:36:7] wire [3:0] _mask_sizeOH_T = 4'h6; // @[Misc.scala:202:34] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] io_in_a_bits_opcode = 3'h4; // @[Monitor.scala:36:7] wire [2:0] _mask_sizeOH_T_2 = 3'h4; // @[OneHot.scala:65:27] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [7:0] io_in_a_bits_mask = 8'hFF; // @[Monitor.scala:36:7] wire [7:0] mask = 8'hFF; // @[Misc.scala:222:10] wire [63:0] io_in_a_bits_data = 64'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101] wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69] wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101] wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [30:0] _d_sizes_clr_T_5 = 31'hFF; // @[Monitor.scala:681:74] wire [30:0] _d_sizes_clr_T_11 = 31'hFF; // @[Monitor.scala:791:74] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _a_opcodes_set_interm_T = 4'h8; // @[Monitor.scala:657:53] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] mask_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi = 4'hF; // @[Misc.scala:222:10] wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76] wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [3:0] _mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [4:0] _a_sizes_set_interm_T_1 = 5'hD; // @[Monitor.scala:658:59] wire [4:0] _a_sizes_set_interm_T = 5'hC; // @[Monitor.scala:658:51] wire [3:0] _a_opcodes_set_interm_T_1 = 4'h9; // @[Monitor.scala:657:61] wire [2:0] mask_sizeOH = 3'h5; // @[Misc.scala:202:81] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [8:0] a_first_beats1_decode = 9'h7; // @[Edges.scala:220:59] wire [8:0] a_first_beats1_decode_1 = 9'h7; // @[Edges.scala:220:59] wire [11:0] is_aligned_mask = 12'h3F; // @[package.scala:243:46] wire [11:0] _a_first_beats1_decode_T_2 = 12'h3F; // @[package.scala:243:46] wire [11:0] _a_first_beats1_decode_T_5 = 12'h3F; // @[package.scala:243:46] wire [11:0] _is_aligned_mask_T_1 = 12'hFC0; // @[package.scala:243:76] wire [11:0] _a_first_beats1_decode_T_1 = 12'hFC0; // @[package.scala:243:76] wire [11:0] _a_first_beats1_decode_T_4 = 12'hFC0; // @[package.scala:243:76] wire [26:0] _is_aligned_mask_T = 27'h3FFC0; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T = 27'h3FFC0; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3 = 27'h3FFC0; // @[package.scala:243:71] wire [1:0] mask_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49] wire _d_first_T = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T_1 = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T_2 = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0]}; // @[Monitor.scala:36:7] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_0_2; // @[Misc.scala:214:27, :215:38] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_1_2; // @[Misc.scala:214:27, :215:38] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_eq_4; // @[Misc.scala:214:27, :215:38] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_eq_5; // @[Misc.scala:214:27, :215:38] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_eq_6; // @[Misc.scala:214:27, :215:38] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_eq_7; // @[Misc.scala:214:27, :215:38] wire _T_1212 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1212; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1212; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] _a_first_counter_T = a_first ? 9'h0 : a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [31:0] address; // @[Monitor.scala:391:22] wire [26:0] _GEN = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] wire [7:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] _a_first_counter_T_1 = a_first_1 ? 9'h0 : a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [7:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_1135 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_1135; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_1135; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_1212 & a_first_1; // @[Decoupled.scala:51:35] assign a_opcodes_set_interm = a_set ? 4'h9 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:28] assign a_sizes_set_interm = a_set ? 5'hD : 5'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[package.scala:243:71] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[package.scala:243:71] assign a_sizes_set = a_set ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_0 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_0; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_0; // @[Monitor.scala:673:46, :783:46] wire _T_1184 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] assign d_clr_wo_ready = _T_1184 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}] assign d_clr = io_in_d_valid_0 & d_first_1 & ~d_release_ack; // @[Monitor.scala:36:7, :664:34, :673:46, :674:74, :678:{25,70}] assign d_opcodes_clr = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21] assign d_sizes_clr = {8{d_clr}}; // @[Monitor.scala:664:34, :670:31, :678:89, :681:21] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}] wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [7:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42] wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1256 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1256 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}] assign d_clr_1 = io_in_d_valid_0 & d_first_2 & d_release_ack_1; // @[Monitor.scala:36:7, :774:34, :783:46, :788:{25,70}] assign d_opcodes_clr_1 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21] assign d_sizes_clr_1 = {8{d_clr_1}}; // @[Monitor.scala:774:34, :777:34, :788:88, :791:21] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag }
module OptimizationBarrier_TLBEntryData_36( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }
module AsyncValidSync_21( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_30 io_out_sink_valid_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File Nodes.scala: package constellation.channel import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Parameters, Field} import freechips.rocketchip.diplomacy._ case class EmptyParams() case class ChannelEdgeParams(cp: ChannelParams, p: Parameters) object ChannelImp extends SimpleNodeImp[EmptyParams, ChannelParams, ChannelEdgeParams, Channel] { def edge(pd: EmptyParams, pu: ChannelParams, p: Parameters, sourceInfo: SourceInfo) = { ChannelEdgeParams(pu, p) } def bundle(e: ChannelEdgeParams) = new Channel(e.cp)(e.p) def render(e: ChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) { RenderedEdge(colour = "ffffff", label = "X") } else { RenderedEdge(colour = "#0000ff", label = e.cp.payloadBits.toString) } override def monitor(bundle: Channel, edge: ChannelEdgeParams): Unit = { val monitor = Module(new NoCMonitor(edge.cp)(edge.p)) monitor.io.in := bundle } // TODO: Add nodepath stuff? override def mixO, override def mixI } case class ChannelSourceNode(val destId: Int)(implicit valName: ValName) extends SourceNode(ChannelImp)(Seq(EmptyParams())) case class ChannelDestNode(val destParams: ChannelParams)(implicit valName: ValName) extends SinkNode(ChannelImp)(Seq(destParams)) case class ChannelAdapterNode( slaveFn: ChannelParams => ChannelParams = { d => d })( implicit valName: ValName) extends AdapterNode(ChannelImp)((e: EmptyParams) => e, slaveFn) case class ChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(ChannelImp)() case class ChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(ChannelImp)() case class IngressChannelEdgeParams(cp: IngressChannelParams, p: Parameters) case class EgressChannelEdgeParams(cp: EgressChannelParams, p: Parameters) object IngressChannelImp extends SimpleNodeImp[EmptyParams, IngressChannelParams, IngressChannelEdgeParams, IngressChannel] { def edge(pd: EmptyParams, pu: IngressChannelParams, p: Parameters, sourceInfo: SourceInfo) = { IngressChannelEdgeParams(pu, p) } def bundle(e: IngressChannelEdgeParams) = new IngressChannel(e.cp)(e.p) def render(e: IngressChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) { RenderedEdge(colour = "ffffff", label = "X") } else { RenderedEdge(colour = "#00ff00", label = e.cp.payloadBits.toString) } } object EgressChannelImp extends SimpleNodeImp[EmptyParams, EgressChannelParams, EgressChannelEdgeParams, EgressChannel] { def edge(pd: EmptyParams, pu: EgressChannelParams, p: Parameters, sourceInfo: SourceInfo) = { EgressChannelEdgeParams(pu, p) } def bundle(e: EgressChannelEdgeParams) = new EgressChannel(e.cp)(e.p) def render(e: EgressChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) { RenderedEdge(colour = "ffffff", label = "X") } else { RenderedEdge(colour = "#ff0000", label = e.cp.payloadBits.toString) } } case class IngressChannelSourceNode(val destId: Int)(implicit valName: ValName) extends SourceNode(IngressChannelImp)(Seq(EmptyParams())) case class IngressChannelDestNode(val destParams: IngressChannelParams)(implicit valName: ValName) extends SinkNode(IngressChannelImp)(Seq(destParams)) case class EgressChannelSourceNode(val egressId: Int)(implicit valName: ValName) extends SourceNode(EgressChannelImp)(Seq(EmptyParams())) case class EgressChannelDestNode(val destParams: EgressChannelParams)(implicit valName: ValName) extends SinkNode(EgressChannelImp)(Seq(destParams)) case class IngressChannelAdapterNode( slaveFn: IngressChannelParams => IngressChannelParams = { d => d })( implicit valName: ValName) extends AdapterNode(IngressChannelImp)(m => m, slaveFn) case class EgressChannelAdapterNode( slaveFn: EgressChannelParams => EgressChannelParams = { d => d })( implicit valName: ValName) extends AdapterNode(EgressChannelImp)(m => m, slaveFn) case class IngressChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(IngressChannelImp)() case class EgressChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(EgressChannelImp)() case class IngressChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(IngressChannelImp)() case class EgressChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(EgressChannelImp)() File Router.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{RoutingRelation} import constellation.noc.{HasNoCParams} case class UserRouterParams( // Payload width. Must match payload width on all channels attached to this routing node payloadBits: Int = 64, // Combines SA and ST stages (removes pipeline register) combineSAST: Boolean = false, // Combines RC and VA stages (removes pipeline register) combineRCVA: Boolean = false, // Adds combinational path from SA to VA coupleSAVA: Boolean = false, vcAllocator: VCAllocatorParams => Parameters => VCAllocator = (vP) => (p) => new RotatingSingleVCAllocator(vP)(p) ) case class RouterParams( nodeId: Int, nIngress: Int, nEgress: Int, user: UserRouterParams ) trait HasRouterOutputParams { def outParams: Seq[ChannelParams] def egressParams: Seq[EgressChannelParams] def allOutParams = outParams ++ egressParams def nOutputs = outParams.size def nEgress = egressParams.size def nAllOutputs = allOutParams.size } trait HasRouterInputParams { def inParams: Seq[ChannelParams] def ingressParams: Seq[IngressChannelParams] def allInParams = inParams ++ ingressParams def nInputs = inParams.size def nIngress = ingressParams.size def nAllInputs = allInParams.size } trait HasRouterParams { def routerParams: RouterParams def nodeId = routerParams.nodeId def payloadBits = routerParams.user.payloadBits } class DebugBundle(val nIn: Int) extends Bundle { val va_stall = Vec(nIn, UInt()) val sa_stall = Vec(nIn, UInt()) } class Router( val routerParams: RouterParams, preDiplomaticInParams: Seq[ChannelParams], preDiplomaticIngressParams: Seq[IngressChannelParams], outDests: Seq[Int], egressIds: Seq[Int] )(implicit p: Parameters) extends LazyModule with HasNoCParams with HasRouterParams { val allPreDiplomaticInParams = preDiplomaticInParams ++ preDiplomaticIngressParams val destNodes = preDiplomaticInParams.map(u => ChannelDestNode(u)) val sourceNodes = outDests.map(u => ChannelSourceNode(u)) val ingressNodes = preDiplomaticIngressParams.map(u => IngressChannelDestNode(u)) val egressNodes = egressIds.map(u => EgressChannelSourceNode(u)) val debugNode = BundleBridgeSource(() => new DebugBundle(allPreDiplomaticInParams.size)) val ctrlNode = if (hasCtrl) Some(BundleBridgeSource(() => new RouterCtrlBundle)) else None def inParams = module.inParams def outParams = module.outParams def ingressParams = module.ingressParams def egressParams = module.egressParams lazy val module = new LazyModuleImp(this) with HasRouterInputParams with HasRouterOutputParams { val (io_in, edgesIn) = destNodes.map(_.in(0)).unzip val (io_out, edgesOut) = sourceNodes.map(_.out(0)).unzip val (io_ingress, edgesIngress) = ingressNodes.map(_.in(0)).unzip val (io_egress, edgesEgress) = egressNodes.map(_.out(0)).unzip val io_debug = debugNode.out(0)._1 val inParams = edgesIn.map(_.cp) val outParams = edgesOut.map(_.cp) val ingressParams = edgesIngress.map(_.cp) val egressParams = edgesEgress.map(_.cp) allOutParams.foreach(u => require(u.srcId == nodeId && u.payloadBits == routerParams.user.payloadBits)) allInParams.foreach(u => require(u.destId == nodeId && u.payloadBits == routerParams.user.payloadBits)) require(nIngress == routerParams.nIngress) require(nEgress == routerParams.nEgress) require(nAllInputs >= 1) require(nAllOutputs >= 1) require(nodeId < (1 << nodeIdBits)) val input_units = inParams.zipWithIndex.map { case (u,i) => Module(new InputUnit(u, outParams, egressParams, routerParams.user.combineRCVA, routerParams.user.combineSAST)) .suggestName(s"input_unit_${i}_from_${u.srcId}") } val ingress_units = ingressParams.zipWithIndex.map { case (u,i) => Module(new IngressUnit(i, u, outParams, egressParams, routerParams.user.combineRCVA, routerParams.user.combineSAST)) .suggestName(s"ingress_unit_${i+nInputs}_from_${u.ingressId}") } val all_input_units = input_units ++ ingress_units val output_units = outParams.zipWithIndex.map { case (u,i) => Module(new OutputUnit(inParams, ingressParams, u)) .suggestName(s"output_unit_${i}_to_${u.destId}")} val egress_units = egressParams.zipWithIndex.map { case (u,i) => Module(new EgressUnit(routerParams.user.coupleSAVA && all_input_units.size == 1, routerParams.user.combineSAST, inParams, ingressParams, u)) .suggestName(s"egress_unit_${i+nOutputs}_to_${u.egressId}")} val all_output_units = output_units ++ egress_units val switch = Module(new Switch(routerParams, inParams, outParams, ingressParams, egressParams)) val switch_allocator = Module(new SwitchAllocator(routerParams, inParams, outParams, ingressParams, egressParams)) val vc_allocator = Module(routerParams.user.vcAllocator( VCAllocatorParams(routerParams, inParams, outParams, ingressParams, egressParams) )(p)) val route_computer = Module(new RouteComputer(routerParams, inParams, outParams, ingressParams, egressParams)) val fires_count = WireInit(PopCount(vc_allocator.io.req.map(_.fire))) dontTouch(fires_count) (io_in zip input_units ).foreach { case (i,u) => u.io.in <> i } (io_ingress zip ingress_units).foreach { case (i,u) => u.io.in <> i.flit } (output_units zip io_out ).foreach { case (u,o) => o <> u.io.out } (egress_units zip io_egress).foreach { case (u,o) => o.flit <> u.io.out } (route_computer.io.req zip all_input_units).foreach { case (i,u) => i <> u.io.router_req } (all_input_units zip route_computer.io.resp).foreach { case (u,o) => u.io.router_resp <> o } (vc_allocator.io.req zip all_input_units).foreach { case (i,u) => i <> u.io.vcalloc_req } (all_input_units zip vc_allocator.io.resp).foreach { case (u,o) => u.io.vcalloc_resp <> o } (all_output_units zip vc_allocator.io.out_allocs).foreach { case (u,a) => u.io.allocs <> a } (vc_allocator.io.channel_status zip all_output_units).foreach { case (a,u) => a := u.io.channel_status } all_input_units.foreach(in => all_output_units.zipWithIndex.foreach { case (out,outIdx) => in.io.out_credit_available(outIdx) := out.io.credit_available }) (all_input_units zip switch_allocator.io.req).foreach { case (u,r) => r <> u.io.salloc_req } (all_output_units zip switch_allocator.io.credit_alloc).foreach { case (u,a) => u.io.credit_alloc := a } (switch.io.in zip all_input_units).foreach { case (i,u) => i <> u.io.out } (all_output_units zip switch.io.out).foreach { case (u,o) => u.io.in <> o } switch.io.sel := (if (routerParams.user.combineSAST) { switch_allocator.io.switch_sel } else { RegNext(switch_allocator.io.switch_sel) }) if (hasCtrl) { val io_ctrl = ctrlNode.get.out(0)._1 val ctrl = Module(new RouterControlUnit(routerParams, inParams, outParams, ingressParams, egressParams)) io_ctrl <> ctrl.io.ctrl (all_input_units zip ctrl.io.in_block ).foreach { case (l,r) => l.io.block := r } (all_input_units zip ctrl.io.in_fire ).foreach { case (l,r) => r := l.io.out.map(_.valid) } } else { input_units.foreach(_.io.block := false.B) ingress_units.foreach(_.io.block := false.B) } (io_debug.va_stall zip all_input_units.map(_.io.debug.va_stall)).map { case (l,r) => l := r } (io_debug.sa_stall zip all_input_units.map(_.io.debug.sa_stall)).map { case (l,r) => l := r } val debug_tsc = RegInit(0.U(64.W)) debug_tsc := debug_tsc + 1.U val debug_sample = RegInit(0.U(64.W)) debug_sample := debug_sample + 1.U val sample_rate = PlusArg("noc_util_sample_rate", width=20) when (debug_sample === sample_rate - 1.U) { debug_sample := 0.U } def sample(fire: Bool, s: String) = { val util_ctr = RegInit(0.U(64.W)) val fired = RegInit(false.B) util_ctr := util_ctr + fire fired := fired || fire when (sample_rate =/= 0.U && debug_sample === sample_rate - 1.U && fired) { val fmtStr = s"nocsample %d $s %d\n" printf(fmtStr, debug_tsc, util_ctr); fired := fire } } destNodes.map(_.in(0)).foreach { case (in, edge) => in.flit.map { f => sample(f.fire, s"${edge.cp.srcId} $nodeId") } } ingressNodes.map(_.in(0)).foreach { case (in, edge) => sample(in.flit.fire, s"i${edge.cp.asInstanceOf[IngressChannelParams].ingressId} $nodeId") } egressNodes.map(_.out(0)).foreach { case (out, edge) => sample(out.flit.fire, s"$nodeId e${edge.cp.asInstanceOf[EgressChannelParams].egressId}") } } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } }
module Router_1( // @[Router.scala:89:25] input clock, // @[Router.scala:89:25] input reset, // @[Router.scala:89:25] output [2:0] auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_va_stall_3, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_sa_stall_3, // @[LazyModuleImp.scala:107:25] input auto_egress_nodes_out_1_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_1_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_1_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_egress_nodes_out_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input auto_egress_nodes_out_0_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_0_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_0_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_egress_nodes_out_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_ingress_nodes_in_2_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_2_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_2_flit_bits_head, // @[LazyModuleImp.scala:107:25] input [72:0] auto_ingress_nodes_in_2_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [5:0] auto_ingress_nodes_in_2_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_ingress_nodes_in_1_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_1_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_1_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_ingress_nodes_in_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [4:0] auto_ingress_nodes_in_1_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_ingress_nodes_in_0_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_0_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_0_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_ingress_nodes_in_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [4:0] auto_ingress_nodes_in_0_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_source_nodes_out_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [7:0] auto_source_nodes_out_credit_return, // @[LazyModuleImp.scala:107:25] input [7:0] auto_source_nodes_out_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_dest_nodes_in_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dest_nodes_in_credit_return, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dest_nodes_in_vc_free // @[LazyModuleImp.scala:107:25] ); wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire _vc_allocator_io_req_3_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_2_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_1_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_2_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_2_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_1_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_2_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_3_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_4_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_5_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_6_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_7_alloc; // @[Router.scala:133:30] wire _switch_allocator_io_req_3_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_2_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_1_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_0_tail; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_0_tail; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_1_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_2_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_3_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_4_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_5_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_6_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_7_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_1_0; // @[Router.scala:132:34] wire _switch_io_out_2_0_valid; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_2_0_bits_payload; // @[Router.scala:131:24] wire [4:0] _switch_io_out_2_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_2_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire _switch_io_out_1_0_valid; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24] wire [4:0] _switch_io_out_1_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_1_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire _switch_io_out_0_0_valid; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24] wire [2:0] _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [2:0] _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _egress_unit_2_to_3_io_credit_available_0; // @[Router.scala:125:13] wire _egress_unit_2_to_3_io_channel_status_0_occupied; // @[Router.scala:125:13] wire _egress_unit_2_to_3_io_out_valid; // @[Router.scala:125:13] wire _egress_unit_1_to_2_io_credit_available_0; // @[Router.scala:125:13] wire _egress_unit_1_to_2_io_channel_status_0_occupied; // @[Router.scala:125:13] wire _egress_unit_1_to_2_io_out_valid; // @[Router.scala:125:13] wire _output_unit_0_to_17_io_credit_available_0; // @[Router.scala:122:13] wire _output_unit_0_to_17_io_credit_available_1; // @[Router.scala:122:13] wire _output_unit_0_to_17_io_credit_available_2; // @[Router.scala:122:13] wire _output_unit_0_to_17_io_credit_available_3; // @[Router.scala:122:13] wire _output_unit_0_to_17_io_credit_available_4; // @[Router.scala:122:13] wire _output_unit_0_to_17_io_credit_available_5; // @[Router.scala:122:13] wire _output_unit_0_to_17_io_credit_available_6; // @[Router.scala:122:13] wire _output_unit_0_to_17_io_credit_available_7; // @[Router.scala:122:13] wire _output_unit_0_to_17_io_channel_status_0_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_17_io_channel_status_1_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_17_io_channel_status_2_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_17_io_channel_status_3_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_17_io_channel_status_4_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_17_io_channel_status_5_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_17_io_channel_status_6_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_17_io_channel_status_7_occupied; // @[Router.scala:122:13] wire _ingress_unit_3_from_5_io_vcalloc_req_valid; // @[Router.scala:116:13] wire _ingress_unit_3_from_5_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_3_from_5_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_3_from_5_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_3_from_5_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_3_from_5_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_3_from_5_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:116:13] wire _ingress_unit_3_from_5_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:116:13] wire _ingress_unit_3_from_5_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:116:13] wire _ingress_unit_3_from_5_io_vcalloc_req_bits_vc_sel_0_6; // @[Router.scala:116:13] wire _ingress_unit_3_from_5_io_vcalloc_req_bits_vc_sel_0_7; // @[Router.scala:116:13] wire _ingress_unit_3_from_5_io_salloc_req_0_valid; // @[Router.scala:116:13] wire _ingress_unit_3_from_5_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_3_from_5_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_3_from_5_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_3_from_5_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_3_from_5_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_3_from_5_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:116:13] wire _ingress_unit_3_from_5_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:116:13] wire _ingress_unit_3_from_5_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:116:13] wire _ingress_unit_3_from_5_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:116:13] wire _ingress_unit_3_from_5_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:116:13] wire _ingress_unit_3_from_5_io_salloc_req_0_bits_tail; // @[Router.scala:116:13] wire _ingress_unit_3_from_5_io_out_0_valid; // @[Router.scala:116:13] wire _ingress_unit_3_from_5_io_out_0_bits_flit_head; // @[Router.scala:116:13] wire _ingress_unit_3_from_5_io_out_0_bits_flit_tail; // @[Router.scala:116:13] wire [72:0] _ingress_unit_3_from_5_io_out_0_bits_flit_payload; // @[Router.scala:116:13] wire [2:0] _ingress_unit_3_from_5_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13] wire [4:0] _ingress_unit_3_from_5_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_3_from_5_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13] wire [4:0] _ingress_unit_3_from_5_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_3_from_5_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13] wire [2:0] _ingress_unit_3_from_5_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13] wire _ingress_unit_3_from_5_io_in_ready; // @[Router.scala:116:13] wire _ingress_unit_2_from_4_io_vcalloc_req_valid; // @[Router.scala:116:13] wire _ingress_unit_2_from_4_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_4_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_4_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_4_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_2_from_4_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_2_from_4_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:116:13] wire _ingress_unit_2_from_4_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:116:13] wire _ingress_unit_2_from_4_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:116:13] wire _ingress_unit_2_from_4_io_vcalloc_req_bits_vc_sel_0_6; // @[Router.scala:116:13] wire _ingress_unit_2_from_4_io_vcalloc_req_bits_vc_sel_0_7; // @[Router.scala:116:13] wire _ingress_unit_2_from_4_io_salloc_req_0_valid; // @[Router.scala:116:13] wire _ingress_unit_2_from_4_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_4_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_4_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_4_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_2_from_4_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_2_from_4_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:116:13] wire _ingress_unit_2_from_4_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:116:13] wire _ingress_unit_2_from_4_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:116:13] wire _ingress_unit_2_from_4_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:116:13] wire _ingress_unit_2_from_4_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:116:13] wire _ingress_unit_2_from_4_io_salloc_req_0_bits_tail; // @[Router.scala:116:13] wire _ingress_unit_2_from_4_io_out_0_valid; // @[Router.scala:116:13] wire _ingress_unit_2_from_4_io_out_0_bits_flit_head; // @[Router.scala:116:13] wire _ingress_unit_2_from_4_io_out_0_bits_flit_tail; // @[Router.scala:116:13] wire [72:0] _ingress_unit_2_from_4_io_out_0_bits_flit_payload; // @[Router.scala:116:13] wire [2:0] _ingress_unit_2_from_4_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13] wire [4:0] _ingress_unit_2_from_4_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_2_from_4_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13] wire [4:0] _ingress_unit_2_from_4_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_2_from_4_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13] wire [2:0] _ingress_unit_2_from_4_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13] wire _ingress_unit_2_from_4_io_in_ready; // @[Router.scala:116:13] wire _ingress_unit_1_from_3_io_vcalloc_req_valid; // @[Router.scala:116:13] wire _ingress_unit_1_from_3_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_3_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_3_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_3_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_1_from_3_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_1_from_3_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:116:13] wire _ingress_unit_1_from_3_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:116:13] wire _ingress_unit_1_from_3_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:116:13] wire _ingress_unit_1_from_3_io_vcalloc_req_bits_vc_sel_0_6; // @[Router.scala:116:13] wire _ingress_unit_1_from_3_io_vcalloc_req_bits_vc_sel_0_7; // @[Router.scala:116:13] wire _ingress_unit_1_from_3_io_salloc_req_0_valid; // @[Router.scala:116:13] wire _ingress_unit_1_from_3_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_3_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_3_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_3_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_1_from_3_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_1_from_3_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:116:13] wire _ingress_unit_1_from_3_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:116:13] wire _ingress_unit_1_from_3_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:116:13] wire _ingress_unit_1_from_3_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:116:13] wire _ingress_unit_1_from_3_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:116:13] wire _ingress_unit_1_from_3_io_salloc_req_0_bits_tail; // @[Router.scala:116:13] wire _ingress_unit_1_from_3_io_out_0_valid; // @[Router.scala:116:13] wire _ingress_unit_1_from_3_io_out_0_bits_flit_head; // @[Router.scala:116:13] wire _ingress_unit_1_from_3_io_out_0_bits_flit_tail; // @[Router.scala:116:13] wire [72:0] _ingress_unit_1_from_3_io_out_0_bits_flit_payload; // @[Router.scala:116:13] wire [2:0] _ingress_unit_1_from_3_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13] wire [4:0] _ingress_unit_1_from_3_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_1_from_3_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13] wire [4:0] _ingress_unit_1_from_3_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_1_from_3_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13] wire [2:0] _ingress_unit_1_from_3_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13] wire _ingress_unit_1_from_3_io_in_ready; // @[Router.scala:116:13] wire _input_unit_0_from_17_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_0_from_17_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_0_from_17_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_0_from_17_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_17_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_0_from_17_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_0_from_17_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_0_from_17_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_17_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_0_from_17_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [72:0] _input_unit_0_from_17_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_17_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_0_from_17_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_17_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_0_from_17_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_17_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [2:0] fires_count = {1'h0, {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_17_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _ingress_unit_1_from_3_io_vcalloc_req_valid}} + {1'h0, {1'h0, _vc_allocator_io_req_2_ready & _ingress_unit_2_from_4_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_3_ready & _ingress_unit_3_from_5_io_vcalloc_req_valid}}; // @[Decoupled.scala:51:35] reg REG_2_0_3_0; // @[Router.scala:178:14] reg REG_2_0_2_0; // @[Router.scala:178:14] reg REG_2_0_1_0; // @[Router.scala:178:14] reg REG_2_0_0_0; // @[Router.scala:178:14] reg REG_1_0_3_0; // @[Router.scala:178:14] reg REG_1_0_2_0; // @[Router.scala:178:14] reg REG_1_0_1_0; // @[Router.scala:178:14] reg REG_1_0_0_0; // @[Router.scala:178:14] reg REG_0_0_3_0; // @[Router.scala:178:14] reg REG_0_0_2_0; // @[Router.scala:178:14] reg REG_0_0_1_0; // @[Router.scala:178:14] reg [63:0] debug_tsc; // @[Router.scala:195:28] reg [63:0] debug_sample; // @[Router.scala:197:31] wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11] reg [63:0] util_ctr; // @[Router.scala:203:29] reg fired; // @[Router.scala:204:26] wire _GEN_0 = (|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11] wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_1; // @[Router.scala:203:29] reg fired_1; // @[Router.scala:204:26] wire _GEN_2 = _GEN_0 & fired_1; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_2; // @[Router.scala:203:29] reg fired_2; // @[Router.scala:204:26] wire _GEN_3 = _GEN_0 & fired_2; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_3; // @[Router.scala:203:29] reg fired_3; // @[Router.scala:204:26] wire _GEN_4 = _GEN_0 & fired_3; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_4; // @[Router.scala:203:29] reg fired_4; // @[Router.scala:204:26] wire _GEN_5 = _GEN_0 & fired_4; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_5; // @[Router.scala:203:29] reg fired_5; // @[Router.scala:204:26] wire _GEN_6 = _GEN_0 & fired_5; // @[Router.scala:204:26, :207:{33,71}]
Generate the Verilog code corresponding to the following Chisel files. File decode.scala: //****************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ package boom.v4.exu import chisel3._ import chisel3.util._ import freechips.rocketchip.tile.FPConstants import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket.Instructions32 import freechips.rocketchip.rocket.CustomInstructions._ import freechips.rocketchip.rocket.RVCExpander import freechips.rocketchip.rocket.ALU._ import freechips.rocketchip.rocket.{CSR, Causes, DecodeLogic} import freechips.rocketchip.util._ import boom.v4.common._ import boom.v4.util._ // scalastyle:off /** * Abstract trait giving defaults and other relevant values to different Decode constants/ */ object DecodeTables extends freechips.rocketchip.rocket.constants.ScalarOpConstants with freechips.rocketchip.rocket.constants.MemoryOpConstants with freechips.rocketchip.tile.HasFPUParameters { lazy val fLen = 64 lazy val minFLen = 32 def xLen = 64 def xpr64 = Y // TODO inform this from xLen def DC(i: Int) = BitPat.dontCare(i) def fc2oh(fc: Int): UInt = (1 << fc).U(FC_SZ.W) // FP stores generate data through FP F2I, and generate address through MemAddrCalc def FCOH_F2IMEM = ((1 << FC_AGEN) | (1 << FC_F2I )).U(FC_SZ.W) def FCOH_STORE = ((1 << FC_AGEN) | (1 << FC_DGEN)).U(FC_SZ.W) def FN_00 = BitPat("b???00") def FN_01 = BitPat("b???01") def FN_10 = BitPat("b???10") def FN_11 = BitPat("b???11") def decode_default: List[BitPat] = // frs3_en // is val inst? | imm sel // | is fp inst? | | uses_ldq // | | rs1 regtype | | | uses_stq is unique? (clear pipeline for it) // | | | rs2 type| | | | is_amo | flush on commit // | | func unit | | | | | | | | | csr cmd // | | | | | | | | | | | | | fcn_dw swap12 fma // | | | dst | | | | | | | mem | | | | fcn_op | swap32 | div // | | | regtype | | | | | | | cmd | | | | | | | typeTagIn | | sqrt // | | | | | | | | | | | | | | | | | ldst | | | typeTagOut | | wflags // | | | | | | | | | | | | | | | | | | wen | | | | from_int | | | // | | | | | | | | | | | | | | | | | | | ren1 | | | | | to_int | | | // | | | | | | | | | | | | | | | | | | | | ren2 | | | | | | fast | | | // | | | | | | | | | | | | | | | | | | | | | ren3 | | | | | | | | | | // | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | List(N, N, DC(FC_SZ) , RT_X , DC(2) , DC(2) , X, IS_N, X, X, X, M_X, N, X, CSR.X, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X) def X32_table: Seq[(BitPat, List[BitPat])] = { import Instructions32._; Seq( SLLI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SL , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SRLI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SRAI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SRA , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X) ) } def X64_table: Seq[(BitPat, List[BitPat])] = Seq( LD -> List(Y, N, fc2oh(FC_AGEN), RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, M_XRD , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), LWU -> List(Y, N, fc2oh(FC_AGEN), RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, M_XRD , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SD -> List(Y, N, FCOH_STORE , RT_X , RT_FIX, RT_FIX, N, IS_S, N, Y, N, M_XWR , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SLLI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SL , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SRLI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SRAI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SRA , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), ADDIW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_32 , FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SLLIW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_32 , FN_SL , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SRAIW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_32 , FN_SRA , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SRLIW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_32 , FN_SR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), ADDW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_32 , FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SUBW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_32 , FN_SUB , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SLLW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_32 , FN_SL , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SRAW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_32 , FN_SRA , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SRLW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_32 , FN_SR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X) ) def X_table: Seq[(BitPat, List[BitPat])] = Seq( LW -> List(Y, N, fc2oh(FC_AGEN), RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, M_XRD , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), LH -> List(Y, N, fc2oh(FC_AGEN), RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, M_XRD , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), LHU -> List(Y, N, fc2oh(FC_AGEN), RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, M_XRD , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), LB -> List(Y, N, fc2oh(FC_AGEN), RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, M_XRD , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), LBU -> List(Y, N, fc2oh(FC_AGEN), RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, M_XRD , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SW -> List(Y, N, FCOH_STORE , RT_X , RT_FIX, RT_FIX, N, IS_S, N, Y, N, M_XWR , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SH -> List(Y, N, FCOH_STORE , RT_X , RT_FIX, RT_FIX, N, IS_S, N, Y, N, M_XWR , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SB -> List(Y, N, FCOH_STORE , RT_X , RT_FIX, RT_FIX, N, IS_S, N, Y, N, M_XWR , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), LUI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_X , RT_X , N, IS_U, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), ADDI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), ANDI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_AND , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), ORI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_OR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), XORI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_XOR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SLTI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SLT , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SLTIU -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SLTU, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SLL -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SL , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), ADD -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SUB -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SUB , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SLT -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SLT , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SLTU -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SLTU, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AND -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_AND , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), OR -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_OR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), XOR -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_XOR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SRA -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SRA , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SRL -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), MUL -> List(Y, N, fc2oh(FC_MUL) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_MUL , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), MULH -> List(Y, N, fc2oh(FC_MUL) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_MULH, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), MULHU -> List(Y, N, fc2oh(FC_MUL) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_MULHU, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), MULHSU -> List(Y, N, fc2oh(FC_MUL) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_MULHSU, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), MULW -> List(Y, N, fc2oh(FC_MUL) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_32 , FN_MUL , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), DIV -> List(Y, N, fc2oh(FC_DIV) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_DIV , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), DIVU -> List(Y, N, fc2oh(FC_DIV) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_DIVU, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), REM -> List(Y, N, fc2oh(FC_DIV) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_REM , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), REMU -> List(Y, N, fc2oh(FC_DIV) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_REMU, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), DIVW -> List(Y, N, fc2oh(FC_DIV) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_32 , FN_DIV , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), DIVUW -> List(Y, N, fc2oh(FC_DIV) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_32 , FN_DIVU, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), REMW -> List(Y, N, fc2oh(FC_DIV) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_32 , FN_REM , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), REMUW -> List(Y, N, fc2oh(FC_DIV) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_32 , FN_REMU, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AUIPC -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_X , RT_X , N, IS_U, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), // use BRU for the PC read JAL -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_X , RT_X , N, IS_J, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), JALR -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), BEQ -> List(Y, N, fc2oh(FC_ALU) , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SUB , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), BNE -> List(Y, N, fc2oh(FC_ALU) , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SUB , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), BGE -> List(Y, N, fc2oh(FC_ALU) , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SLT , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), BGEU -> List(Y, N, fc2oh(FC_ALU) , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SLTU, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), BLT -> List(Y, N, fc2oh(FC_ALU) , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SLT , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), BLTU -> List(Y, N, fc2oh(FC_ALU) , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SLTU, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), // I-type, the immedia2 holds the CSR regi ster. CSRRW -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , Y, Y, CSR.W, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CSRRS -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , Y, Y, CSR.S, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CSRRC -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , Y, Y, CSR.C, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CSRRWI -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_X , RT_X , N, IS_I, N, N, N, M_X , Y, Y, CSR.W, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CSRRSI -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_X , RT_X , N, IS_I, N, N, N, M_X , Y, Y, CSR.S, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CSRRCI -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_X , RT_X , N, IS_I, N, N, N, M_X , Y, Y, CSR.C, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SFENCE_VMA ->List(Y, N, fc2oh(FC_CSR) , RT_X , RT_FIX, RT_FIX, N, IS_N, N, N, N,M_SFENCE , Y, Y, CSR.R, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), ECALL -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_X , RT_X , N, IS_I, N, N, N, M_X , Y, Y, CSR.I, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), EBREAK -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_X , RT_X , N, IS_I, N, N, N, M_X , Y, Y, CSR.I, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SRET -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_X , RT_X , N, IS_I, N, N, N, M_X , Y, Y, CSR.I, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), MRET -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_X , RT_X , N, IS_I, N, N, N, M_X , Y, Y, CSR.I, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), DRET -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_X , RT_X , N, IS_I, N, N, N, M_X , Y, Y, CSR.I, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), WFI -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_X , RT_X , N, IS_I, N, N, N, M_X , Y, Y, CSR.I, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), FENCE_I -> List(Y, N, 0.U(FC_SZ.W) , RT_X , RT_X , RT_X , N, IS_N, N, N, N, M_X , Y, Y, CSR.N, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), FENCE -> List(Y, N, 0.U(FC_SZ.W) , RT_X , RT_X , RT_X , N, IS_N, N, Y, N, M_X , Y, Y, CSR.N, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), // TODO PERF make fence higher performance // currently serializes pipeline // A-type AMOADD_W -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_ADD, Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), // TODO make AMOs higherperformance AMOXOR_W -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_XOR, Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AMOSWAP_W -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_SWAP,Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AMOAND_W -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_AND, Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AMOOR_W -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_OR, Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AMOMIN_W -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_MIN, Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AMOMINU_W -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_MINU,Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AMOMAX_W -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_MAX, Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AMOMAXU_W -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_MAXU,Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AMOADD_D -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_ADD, Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AMOXOR_D -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_XOR, Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AMOSWAP_D -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_SWAP,Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AMOAND_D -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_AND, Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AMOOR_D -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_OR, Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AMOMIN_D -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_MIN, Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AMOMINU_D -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_MINU,Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AMOMAX_D -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_MAX, Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AMOMAXU_D -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_MAXU,Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), LR_W -> List(Y, N, fc2oh(FC_AGEN), RT_FIX, RT_FIX, RT_X , N, IS_N, Y, N, N, M_XLR , Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), LR_D -> List(Y, N, fc2oh(FC_AGEN), RT_FIX, RT_FIX, RT_X , N, IS_N, Y, N, N, M_XLR , Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SC_W -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XSC , Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SC_D -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XSC , Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X) ) def F_table: Seq[(BitPat, List[BitPat])] = Seq( FLW -> List(Y, Y, fc2oh(FC_AGEN), RT_FLT, RT_FIX, RT_X , N, IS_I, Y, N, N, M_XRD , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), FLD -> List(Y, Y, fc2oh(FC_AGEN), RT_FLT, RT_FIX, RT_X , N, IS_I, Y, N, N, M_XRD , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), FSW -> List(Y, Y, FCOH_F2IMEM , RT_X , RT_FIX, RT_FLT, N, IS_S, N, Y, N, M_XWR , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), // sort of a lie; broken into two micro-ops FSD -> List(Y, Y, FCOH_F2IMEM , RT_X , RT_FIX, RT_FLT, N, IS_S, N, Y, N, M_XWR , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), FCLASS_S -> List(Y, Y, fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,N,N, N,X,S,S,N,Y,N, N,N,N,N), FCLASS_D -> List(Y, Y, fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,N,N, N,X,D,D,N,Y,N, N,N,N,N), FMV_W_X -> List(Y, Y, fc2oh(FC_I2F) , RT_FLT, RT_FIX, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,N,N,N, X,X,S,D,Y,N,N, N,N,N,N), FMV_D_X -> List(Y, Y, fc2oh(FC_I2F) , RT_FLT, RT_FIX, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,N,N,N, X,X,D,D,Y,N,N, N,N,N,N), FMV_X_W -> List(Y, Y, fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,N,N, N,X,D,S,N,Y,N, N,N,N,N), FMV_X_D -> List(Y, Y, fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,N,N, N,X,D,D,N,Y,N, N,N,N,N), FSGNJ_S -> List(Y, Y, fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,N, N,N,S,S,N,N,Y, N,N,N,N), FSGNJ_D -> List(Y, Y, fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,N, N,N,D,D,N,N,Y, N,N,N,N), FSGNJX_S -> List(Y, Y, fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,N, N,N,S,S,N,N,Y, N,N,N,N), FSGNJX_D -> List(Y, Y, fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,N, N,N,D,D,N,N,Y, N,N,N,N), FSGNJN_S -> List(Y, Y, fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,N, N,N,S,S,N,N,Y, N,N,N,N), FSGNJN_D -> List(Y, Y, fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,N, N,N,D,D,N,N,Y, N,N,N,N), // FP to FP FCVT_S_D -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,N,N, N,X,D,S,N,N,Y, N,N,N,Y), FCVT_D_S -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,N,N, N,X,S,D,N,N,Y, N,N,N,Y), // Int to FP FCVT_S_W -> List(Y, Y,fc2oh(FC_I2F) , RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,N,N,N, X,X,S,S,Y,N,N, N,N,N,Y), FCVT_S_WU -> List(Y, Y,fc2oh(FC_I2F) , RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,N,N,N, X,X,S,S,Y,N,N, N,N,N,Y), FCVT_S_L -> List(Y, Y,fc2oh(FC_I2F) , RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,N,N,N, X,X,S,S,Y,N,N, N,N,N,Y), FCVT_S_LU -> List(Y, Y,fc2oh(FC_I2F) , RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,N,N,N, X,X,S,S,Y,N,N, N,N,N,Y), FCVT_D_W -> List(Y, Y,fc2oh(FC_I2F) , RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,N,N,N, X,X,D,D,Y,N,N, N,N,N,Y), FCVT_D_WU -> List(Y, Y,fc2oh(FC_I2F) , RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,N,N,N, X,X,D,D,Y,N,N, N,N,N,Y), FCVT_D_L -> List(Y, Y,fc2oh(FC_I2F) , RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,N,N,N, X,X,D,D,Y,N,N, N,N,N,Y), FCVT_D_LU -> List(Y, Y,fc2oh(FC_I2F) , RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,N,N,N, X,X,D,D,Y,N,N, N,N,N,Y), // FP to Int FCVT_W_S -> List(Y, Y,fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,N,N, N,X,S,S,N,Y,N, N,N,N,Y), FCVT_WU_S -> List(Y, Y,fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,N,N, N,X,S,S,N,Y,N, N,N,N,Y), FCVT_L_S -> List(Y, Y,fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,N,N, N,X,S,S,N,Y,N, N,N,N,Y), FCVT_LU_S -> List(Y, Y,fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,N,N, N,X,S,S,N,Y,N, N,N,N,Y), FCVT_W_D -> List(Y, Y,fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,N,N, N,X,D,D,N,Y,N, N,N,N,Y), FCVT_WU_D -> List(Y, Y,fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,N,N, N,X,D,D,N,Y,N, N,N,N,Y), FCVT_L_D -> List(Y, Y,fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,N,N, N,X,D,D,N,Y,N, N,N,N,Y), FCVT_LU_D -> List(Y, Y,fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,N,N, N,X,D,D,N,Y,N, N,N,N,Y), FEQ_S -> List(Y, Y, fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,N, N,N,S,S,N,Y,N, N,N,N,Y), FLT_S -> List(Y, Y, fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,N, N,N,S,S,N,Y,N, N,N,N,Y), FLE_S -> List(Y, Y, fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,N, N,N,S,S,N,Y,N, N,N,N,Y), FEQ_D -> List(Y, Y, fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,N, N,N,D,D,N,Y,N, N,N,N,Y), FLT_D -> List(Y, Y, fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,N, N,N,D,D,N,Y,N, N,N,N,Y), FLE_D -> List(Y, Y, fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,N, N,N,D,D,N,Y,N, N,N,N,Y), FMIN_S -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,N, N,N,S,S,N,N,Y, N,N,N,Y), FMAX_S -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,N, N,N,S,S,N,N,Y, N,N,N,Y), FMIN_D -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,N, N,N,D,D,N,N,Y, N,N,N,Y), FMAX_D -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,N, N,N,D,D,N,N,Y, N,N,N,Y), FADD_S -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_00 ,X,X,Y,Y,N, N,Y,S,S,N,N,N, Y,N,N,Y), FSUB_S -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_01 ,X,X,Y,Y,N, N,Y,S,S,N,N,N, Y,N,N,Y), FMUL_S -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_00 ,X,X,Y,Y,N, N,N,S,S,N,N,N, Y,N,N,Y), FADD_D -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_00 ,X,X,Y,Y,N, N,Y,D,D,N,N,N, Y,N,N,Y), FSUB_D -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_01 ,X,X,Y,Y,N, N,Y,D,D,N,N,N, Y,N,N,Y), FMUL_D -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_00 ,X,X,Y,Y,N, N,N,D,D,N,N,N, Y,N,N,Y), FMADD_S -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, Y, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_00 ,X,X,Y,Y,Y, N,N,S,S,N,N,N, Y,N,N,Y), FMSUB_S -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, Y, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_01 ,X,X,Y,Y,Y, N,N,S,S,N,N,N, Y,N,N,Y), FNMADD_S -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, Y, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_11 ,X,X,Y,Y,Y, N,N,S,S,N,N,N, Y,N,N,Y), FNMSUB_S -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, Y, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_10 ,X,X,Y,Y,Y, N,N,S,S,N,N,N, Y,N,N,Y), FMADD_D -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, Y, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_00 ,X,X,Y,Y,Y, N,N,D,D,N,N,N, Y,N,N,Y), FMSUB_D -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, Y, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_01 ,X,X,Y,Y,Y, N,N,D,D,N,N,N, Y,N,N,Y), FNMADD_D -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, Y, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_11 ,X,X,Y,Y,Y, N,N,D,D,N,N,N, Y,N,N,Y), FNMSUB_D -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, Y, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_10 ,X,X,Y,Y,Y, N,N,D,D,N,N,N, Y,N,N,Y) ) def FDivSqrt_table: Seq[(BitPat, List[BitPat])] = Seq( FDIV_S -> List(Y, Y, fc2oh(FC_FDV) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,X, X,X,S,S,X,X,X, X,Y,N,Y), FDIV_D -> List(Y, Y, fc2oh(FC_FDV) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,X, X,X,D,D,X,X,X, X,Y,N,Y), FSQRT_S -> List(Y, Y, fc2oh(FC_FDV) , RT_FLT, RT_FLT, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,N,X, X,X,S,S,X,X,X, X,N,Y,Y), FSQRT_D -> List(Y, Y, fc2oh(FC_FDV) , RT_FLT, RT_FLT, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,N,X, X,X,D,D,X,X,X, X,N,Y,Y), ) def B_table: Seq[(BitPat, List[BitPat])] = Seq( SH1ADD -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_F3,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SH2ADD -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_F3,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SH3ADD -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_F3,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SH1ADD_UW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_F3,N, N, N, M_X , N, N, CSR.N, DW_32 , FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SH2ADD_UW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_F3,N, N, N, M_X , N, N, CSR.N, DW_32 , FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SH3ADD_UW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_F3,N, N, N, M_X , N, N, CSR.N, DW_32 , FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), ADD_UW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_F3,N, N, N, M_X , N, N, CSR.N, DW_32 , FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SLLI_UW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_32 , FN_SL , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), ANDN -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_ANDN, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), ORN -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_ORN , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), XNOR -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_XNOR, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), MAX -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_MAX , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), MAXU -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_MAXU, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), MIN -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_MIN , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), MINU -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_MINU, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), ROL -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_ROL , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), ROR -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_ROR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), RORI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_ROR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CLZ -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_XPR,FN_UNARY, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CTZ -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_XPR,FN_UNARY, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CPOP -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_XPR,FN_UNARY, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), ORC_B -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_XPR,FN_UNARY, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SEXT_B -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_XPR,FN_UNARY, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SEXT_H -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_XPR,FN_UNARY, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), ZEXT_H -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_XPR,FN_UNARY, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), REV8 -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_XPR,FN_UNARY, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), ROLW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N ,N, N, N, M_X , N, N, CSR.N, DW_32 , FN_ROL , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), RORW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N ,N, N, N, M_X , N, N, CSR.N, DW_32 , FN_ROR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), RORIW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_32 , FN_ROR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CLZW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_32 ,FN_UNARY, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CTZW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_32 ,FN_UNARY, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CPOPW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_32 ,FN_UNARY, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), BCLR -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_ANDN, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), BCLRI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_ANDN, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), BINV -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_XOR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), BINVI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_XOR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), BSET -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_OR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), BSETI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_OR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), BEXT -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_BEXT, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), BEXTI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_BEXT, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), ) def RoCC_table: Seq[(BitPat, List[BitPat])] = Seq( // Note: We use fc2oh(FC_CSR) since CSR instructions cannot co-execute with RoCC instructions CUSTOM0 -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_X , RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM0_RS1 -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_FIX, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM0_RS1_RS2 -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM0_RD -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_X , RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM0_RD_RS1 -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_FIX, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM0_RD_RS1_RS2 -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM1 -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_X , RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM1_RS1 -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_FIX, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM1_RS1_RS2 -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM1_RD -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_X , RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM1_RD_RS1 -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_FIX, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM1_RD_RS1_RS2 -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM2 -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_X , RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM2_RS1 -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_FIX, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM2_RS1_RS2 -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM2_RD -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_X , RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM2_RD_RS1 -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_FIX, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM2_RD_RS1_RS2 -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM3 -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_X , RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM3_RS1 -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_FIX, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM3_RS1_RS2 -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM3_RD -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_X , RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM3_RD_RS1 -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_FIX, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM3_RD_RS1_RS2 -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X) ) } // scalastyle:on /** * Decoded control signals */ class CtrlSigs(implicit p: Parameters) extends Bundle { val legal = Bool() val fp_val = Bool() val fu_code = UInt(FC_SZ.W) val dst_type = UInt(2.W) val rs1_type = UInt(2.W) val rs2_type = UInt(2.W) val frs3_en = Bool() val imm_sel = UInt(IS_N.getWidth.W) val uses_ldq = Bool() val uses_stq = Bool() val is_amo = Bool() val mem_cmd = UInt(freechips.rocketchip.rocket.M_SZ.W) val inst_unique = Bool() val flush_on_commit = Bool() val csr_cmd = UInt(freechips.rocketchip.rocket.CSR.SZ.W) val fcn_dw = Bool() val fcn_op = UInt(SZ_ALU_FN.W) val fp = new freechips.rocketchip.tile.FPUCtrlSigs() def decode(inst: UInt, table: Iterable[(BitPat, List[BitPat])]) = { val decoder = freechips.rocketchip.rocket.DecodeLogic(inst, DecodeTables.decode_default, table) val sigs = Seq( legal, fp_val, fu_code, dst_type, rs1_type, rs2_type, frs3_en, imm_sel, uses_ldq, uses_stq, is_amo, mem_cmd, inst_unique, flush_on_commit, csr_cmd, fcn_dw, fcn_op, fp.ldst, fp.wen, fp.ren1, fp.ren2, fp.ren3, fp.swap12, fp.swap23, fp.typeTagIn, fp.typeTagOut, fp.fromint, fp.toint, fp.fastpipe, fp.fma, fp.div, fp.sqrt, fp.wflags ) sigs zip decoder map {case(s,d) => s := d} fp.vec := false.B this } } /** * IO bundle for the Decode unit */ class DecodeUnitIo(implicit p: Parameters) extends BoomBundle { val enq = new Bundle { val uop = Input(new MicroOp()) } val deq = new Bundle { val uop = Output(new MicroOp()) } // from CSRFile val status = Input(new freechips.rocketchip.rocket.MStatus()) val csr_decode = Flipped(new freechips.rocketchip.rocket.CSRDecodeIO) val fcsr_rm = Input(UInt(FPConstants.RM_SZ.W)) val interrupt = Input(Bool()) val interrupt_cause = Input(UInt(xLen.W)) } /** * Decode unit that takes in a single instruction and generates a MicroOp. */ class DecodeUnit(implicit p: Parameters) extends BoomModule with freechips.rocketchip.rocket.constants.MemoryOpConstants with freechips.rocketchip.rocket.constants.ScalarOpConstants { val io = IO(new DecodeUnitIo) val uop = Wire(new MicroOp()) uop := io.enq.uop val decode_table = ( DecodeTables.X_table ++ DecodeTables.F_table ++ DecodeTables.FDivSqrt_table ++ DecodeTables.X64_table ++ DecodeTables.B_table ++ (if (usingRoCC) DecodeTables.RoCC_table else Nil) ) val inst = uop.inst val LDST = inst(RD_MSB,RD_LSB) val LRS1 = inst(RS1_MSB,RS1_LSB) val LRS2 = inst(RS2_MSB,RS2_LSB) val LRS3 = inst(RS3_MSB,RS3_LSB) val cs = Wire(new CtrlSigs()).decode(inst, decode_table) // Exception Handling io.csr_decode.inst := inst val csr_en = cs.csr_cmd.isOneOf(CSR.S, CSR.C, CSR.W) val csr_ren = cs.csr_cmd.isOneOf(CSR.S, CSR.C) && uop.lrs1 === 0.U val system_insn = cs.csr_cmd === CSR.I val sfence = inst === SFENCE_VMA val cs_legal = cs.legal // dontTouch(cs_legal) require (fLen >= 64) val illegal_rm = inst(14,12).isOneOf(5.U,6.U) || (inst(14,12) === 7.U && io.fcsr_rm >= 5.U) val id_illegal_insn = (!cs_legal || (cs.fp_val && (io.csr_decode.fp_illegal || illegal_rm)) || (uop.is_rocc && io.csr_decode.rocc_illegal) || (cs.is_amo && !io.status.isa('a'-'a')) || (csr_en && (io.csr_decode.read_illegal || !csr_ren && io.csr_decode.write_illegal)) || ((sfence || system_insn) && io.csr_decode.system_illegal)) // cs.div && !csr.io.status.isa('m'-'a') || TODO check for illegal div instructions def checkExceptions(x: Seq[(Bool, UInt)]) = (x.map(_._1).reduce(_||_), PriorityMux(x)) val (xcpt_valid, xcpt_cause) = checkExceptions(List( (io.interrupt && !io.enq.uop.is_sfb, io.interrupt_cause), // Disallow interrupts while we are handling a SFB (uop.bp_debug_if, (CSR.debugTriggerCause).U), (uop.bp_xcpt_if, (Causes.breakpoint).U), (uop.xcpt_pf_if, (Causes.fetch_page_fault).U), (uop.xcpt_ae_if, (Causes.fetch_access).U), (id_illegal_insn, (Causes.illegal_instruction).U))) uop.exception := xcpt_valid uop.exc_cause := xcpt_cause //------------------------------------------------------------- uop.is_mov := inst === ADD && LRS1 === 0.U uop.iq_type(IQ_UNQ) := Seq(FC_MUL , FC_DIV, FC_CSR, FC_I2F).map { c => cs.fu_code(c) }.reduce(_||_) uop.iq_type(IQ_ALU) := Seq(FC_ALU ).map { c => cs.fu_code(c) }.reduce(_||_) uop.iq_type(IQ_MEM) := Seq(FC_AGEN, FC_DGEN ).map { c => cs.fu_code(c) }.reduce(_||_) uop.iq_type(IQ_FP ) := Seq(FC_FPU , FC_FDV, FC_F2I ).map { c => cs.fu_code(c) }.reduce(_||_) uop.fu_code := cs.fu_code.asBools uop.ldst := LDST uop.lrs1 := LRS1 uop.lrs2 := LRS2 uop.lrs3 := LRS3 uop.dst_rtype := cs.dst_type uop.lrs1_rtype := Mux(cs.rs1_type === RT_FIX && LRS1 === 0.U, RT_ZERO, cs.rs1_type) uop.lrs2_rtype := Mux(cs.rs2_type === RT_FIX && LRS2 === 0.U, RT_ZERO, cs.rs2_type) uop.frs3_en := cs.frs3_en uop.ldst_is_rs1 := uop.is_sfb_shadow // SFB optimization when (uop.is_sfb_shadow && cs.rs2_type === RT_X) { uop.lrs2_rtype := Mux(LDST === 0.U, RT_ZERO, RT_FIX) uop.lrs2 := LDST uop.ldst_is_rs1 := false.B } .elsewhen (uop.is_sfb_shadow && uop.is_mov) { uop.lrs1 := LDST uop.lrs1_rtype := Mux(LDST === 0.U, RT_ZERO, RT_FIX) uop.ldst_is_rs1 := true.B } uop.fp_val := cs.fp_val uop.fp_ctrl := cs.fp uop.mem_cmd := cs.mem_cmd uop.mem_size := Mux(cs.mem_cmd.isOneOf(M_SFENCE, M_FLUSH_ALL), Cat(LRS2 =/= 0.U, LRS1 =/= 0.U), inst(13,12)) uop.mem_signed := !inst(14) uop.uses_ldq := cs.uses_ldq uop.uses_stq := cs.uses_stq uop.is_amo := cs.is_amo uop.is_fence := inst === FENCE uop.is_fencei := inst === FENCE_I uop.is_sfence := inst === SFENCE_VMA uop.is_sys_pc2epc := inst === EBREAK || inst === ECALL uop.is_eret := inst === ECALL || inst === EBREAK || inst === SRET || inst === MRET || inst === DRET uop.is_unique := cs.inst_unique uop.is_rocc := inst(6,0).isOneOf("b0001011".U, "b0101011".U, "b1111011".U) && inst(14,12).isOneOf(0.U, 2.U, 3.U, 4.U, 6.U, 7.U) uop.flush_on_commit := cs.flush_on_commit || (csr_en && !csr_ren && io.csr_decode.write_flush) //------------------------------------------------------------- // immediates // repackage the immediate, and then pass the fewest number of bits around val di24_20 = Mux(cs.imm_sel === IS_B || cs.imm_sel === IS_S, inst(11,7), inst(24,20)) val imm_packed = Cat(inst(31,25), di24_20, inst(19,12)) val imm = ImmGen(imm_packed, cs.imm_sel) val imm_hi = imm >> (immPregSz-1) val imm_lo = imm(immPregSz-1, 0) val short_imm = imm_hi === 0.U || ~imm_hi === 0.U || cs.imm_sel === IS_F3 uop.imm_rename := cs.imm_sel =/= IS_N && cs.imm_sel =/= IS_F3 uop.imm_packed := imm_packed uop.imm_sel := cs.imm_sel when (short_imm) { uop.imm_rename := false.B uop.imm_sel := IS_SH uop.pimm := Mux(cs.imm_sel === IS_F3, inst(14,12), imm_lo) } uop.fp_rm := Mux(inst(14,12) === 7.U, io.fcsr_rm, inst(14,12)) uop.fp_typ := inst(21,20) //------------------------------------------------------------- uop.csr_cmd := cs.csr_cmd when ((cs.csr_cmd === CSR.S || cs.csr_cmd === CSR.C) && LRS1 === 0.U) { uop.csr_cmd := CSR.R } uop.fcn_dw := cs.fcn_dw uop.fcn_op := cs.fcn_op uop.op1_sel := OP1_RS1 when (inst === LUI || inst === CSRRWI || inst === CSRRSI || inst === CSRRCI || inst === WFI || inst === SRET || inst === MRET || inst === DRET) { uop.op1_sel := OP1_ZERO } .elsewhen (inst === JAL || inst === JALR || inst === AUIPC) { uop.op1_sel := OP1_PC } .elsewhen (Seq(SH1ADD, SH2ADD, SH3ADD, SH1ADD_UW, SH2ADD_UW, SH3ADD_UW, ADD_UW, SLLI_UW).map(_ === inst).orR) { uop.op1_sel := OP1_RS1SHL } uop.op2_sel := OP2_RS2 when (cs.is_amo || inst === CSRRW || inst === CSRRS || inst === CSRRC) { uop.op2_sel := OP2_ZERO } .elsewhen (inst === CSRRWI || inst === CSRRSI || inst === CSRRCI || inst === WFI || inst === SRET || inst === DRET || inst === MRET) { uop.op2_sel := OP2_IMMC } .elsewhen (inst === JAL || inst === JALR) { uop.op2_sel := OP2_NEXT } .elsewhen (Seq(BCLR, BCLRI, BINV, BINVI, BSET, BSETI).map(_ === inst).orR) { uop.op2_sel := Mux(uop.lrs2_rtype === RT_FIX, OP2_RS2OH, OP2_IMMOH) } .elsewhen (cs.imm_sel === IS_U || cs.imm_sel === IS_I || cs.imm_sel === IS_S) { uop.op2_sel := OP2_IMM } uop.br_type := Seq( (BEQ , B_EQ ), (BNE , B_NE ), (BGE , B_GE ), (BGEU , B_GEU), (BLT , B_LT ), (BLTU , B_LTU), (JAL , B_J ), (JALR , B_JR ) ) .map { case (c, b) => Mux(inst === c, b, 0.U) } .reduce(_|_) io.deq.uop := uop } /** * Smaller Decode unit for the Frontend to decode different * branches. * Accepts EXPANDED RVC instructions */ class BranchDecodeSignals(implicit p: Parameters) extends BoomBundle { val is_ret = Bool() val is_call = Bool() val target = UInt(vaddrBitsExtended.W) val cfi_type = UInt(CFI_SZ.W) // Is this branch a short forwards jump? val sfb_offset = Valid(UInt(log2Ceil(icBlockBytes).W)) // Is this instruction allowed to be inside a sfb? val shadowable = Bool() } class BranchDecode(implicit p: Parameters) extends BoomModule { val io = IO(new Bundle { val inst = Input(UInt(32.W)) val pc = Input(UInt(vaddrBitsExtended.W)) val out = Output(new BranchDecodeSignals) }) val bpd_csignals = freechips.rocketchip.rocket.DecodeLogic(io.inst, List[BitPat](N, N, N, N, X), //// is br? //// | is jal? //// | | is jalr? //// | | | //// | | | shadowable //// | | | | has_rs2 //// | | | | | Seq[(BitPat, List[BitPat])]( JAL -> List(N, Y, N, N, X), JALR -> List(N, N, Y, N, X), BEQ -> List(Y, N, N, N, X), BNE -> List(Y, N, N, N, X), BGE -> List(Y, N, N, N, X), BGEU -> List(Y, N, N, N, X), BLT -> List(Y, N, N, N, X), BLTU -> List(Y, N, N, N, X), SLLI -> List(N, N, N, Y, N), SRLI -> List(N, N, N, Y, N), SRAI -> List(N, N, N, Y, N), ADDIW -> List(N, N, N, Y, N), SLLIW -> List(N, N, N, Y, N), SRAIW -> List(N, N, N, Y, N), SRLIW -> List(N, N, N, Y, N), ADDW -> List(N, N, N, Y, Y), SUBW -> List(N, N, N, Y, Y), SLLW -> List(N, N, N, Y, Y), SRAW -> List(N, N, N, Y, Y), SRLW -> List(N, N, N, Y, Y), LUI -> List(N, N, N, Y, N), ADDI -> List(N, N, N, Y, N), ANDI -> List(N, N, N, Y, N), ORI -> List(N, N, N, Y, N), XORI -> List(N, N, N, Y, N), SLTI -> List(N, N, N, Y, N), SLTIU -> List(N, N, N, Y, N), SLL -> List(N, N, N, Y, Y), ADD -> List(N, N, N, Y, Y), SUB -> List(N, N, N, Y, Y), SLT -> List(N, N, N, Y, Y), SLTU -> List(N, N, N, Y, Y), AND -> List(N, N, N, Y, Y), OR -> List(N, N, N, Y, Y), XOR -> List(N, N, N, Y, Y), SRA -> List(N, N, N, Y, Y), SRL -> List(N, N, N, Y, Y) )) val cs_is_br = bpd_csignals(0)(0) val cs_is_jal = bpd_csignals(1)(0) val cs_is_jalr = bpd_csignals(2)(0) val cs_is_shadowable = bpd_csignals(3)(0) val cs_has_rs2 = bpd_csignals(4)(0) io.out.is_call := (cs_is_jal || cs_is_jalr) && GetRd(io.inst) === RA io.out.is_ret := cs_is_jalr && GetRs1(io.inst) === BitPat("b00?01") && GetRd(io.inst) === X0 io.out.target := Mux(cs_is_br, ComputeBranchTarget(io.pc, io.inst, xLen), ComputeJALTarget(io.pc, io.inst, xLen)) io.out.cfi_type := Mux(cs_is_jalr, CFI_JALR, Mux(cs_is_jal, CFI_JAL, Mux(cs_is_br, CFI_BR, CFI_X))) val br_offset = Cat(io.inst(7), io.inst(30,25), io.inst(11,8), 0.U(1.W)) // Is a sfb if it points forwards (offset is positive) io.out.sfb_offset.valid := cs_is_br && !io.inst(31) && br_offset =/= 0.U && (br_offset >> log2Ceil(icBlockBytes)) === 0.U io.out.sfb_offset.bits := br_offset io.out.shadowable := cs_is_shadowable && ( !cs_has_rs2 || (GetRs1(io.inst) === GetRd(io.inst)) || (io.inst === ADD && GetRs1(io.inst) === X0) ) } /** * Track the current "branch mask", and give out the branch mask to each micro-op in Decode * (each micro-op in the machine has a branch mask which says which branches it * is being speculated under). * * @param pl_width pipeline width for the processor */ class BranchMaskGenerationLogic(val pl_width: Int)(implicit p: Parameters) extends BoomModule { val io = IO(new Bundle { // guess if the uop is a branch (we'll catch this later) val is_branch = Input(Vec(pl_width, Bool())) // lock in that it's actually a branch and will fire, so we update // the branch_masks. val will_fire = Input(Vec(pl_width, Bool())) // give out tag immediately (needed in rename) // mask can come later in the cycle val br_tag = Output(Vec(pl_width, UInt(brTagSz.W))) val br_mask = Output(Vec(pl_width, UInt(maxBrCount.W))) // tell decoders the branch mask has filled up, but on the granularity // of an individual micro-op (so some micro-ops can go through) val is_full = Output(Vec(pl_width, Bool())) val brupdate = Input(new BrUpdateInfo()) val flush_pipeline = Input(Bool()) val debug_branch_mask = Output(UInt(maxBrCount.W)) }) val branch_mask = RegInit(0.U(maxBrCount.W)) //------------------------------------------------------------- // Give out the branch tag to each branch micro-op var allocate_mask = branch_mask val tag_masks = Wire(Vec(pl_width, UInt(maxBrCount.W))) for (w <- 0 until pl_width) { // TODO this is a loss of performance as we're blocking branches based on potentially fake branches io.is_full(w) := (allocate_mask === ~(0.U(maxBrCount.W))) && io.is_branch(w) // find br_tag and compute next br_mask val new_br_tag = Wire(UInt(brTagSz.W)) new_br_tag := 0.U tag_masks(w) := 0.U for (i <- maxBrCount-1 to 0 by -1) { when (~allocate_mask(i)) { new_br_tag := i.U tag_masks(w) := (1.U << i.U) } } io.br_tag(w) := new_br_tag allocate_mask = Mux(io.is_branch(w), tag_masks(w) | allocate_mask, allocate_mask) } //------------------------------------------------------------- // Give out the branch mask to each micro-op // (kill off the bits that corresponded to branches that aren't going to fire) var curr_mask = branch_mask for (w <- 0 until pl_width) { io.br_mask(w) := GetNewBrMask(io.brupdate, curr_mask) curr_mask = Mux(io.will_fire(w), tag_masks(w) | curr_mask, curr_mask) } //------------------------------------------------------------- // Update the current branch_mask when (io.flush_pipeline) { branch_mask := 0.U } .otherwise { val mask = Mux(io.brupdate.b2.mispredict, io.brupdate.b2.uop.br_mask, ~(0.U(maxBrCount.W))) branch_mask := GetNewBrMask(io.brupdate, curr_mask) & mask } io.debug_branch_mask := branch_mask } File consts.scala: //****************************************************************************** // Copyright (c) 2011 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Constants //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v4.common.constants import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util.Str import freechips.rocketchip.rocket.RVCExpander /** * Mixin for scalar operation constants */ trait ScalarOpConstants { val X = BitPat("b?") val Y = BitPat("b1") val N = BitPat("b0") //************************************ // Extra Constants // Which branch predictor predicted us val BSRC_SZ = 3 val BSRC_1 = 0.U(BSRC_SZ.W) // 1-cycle branch pred val BSRC_2 = 1.U(BSRC_SZ.W) // 2-cycle branch pred val BSRC_3 = 2.U(BSRC_SZ.W) // 3-cycle branch pred val BSRC_4 = 3.U(BSRC_SZ.W) // 4-cycle branch pred val BSRC_C = 4.U(BSRC_SZ.W) // core branch resolution //************************************ // Control Signals // CFI types val CFI_SZ = 3 val CFI_X = 0.U(CFI_SZ.W) // Not a CFI instruction val CFI_BR = 1.U(CFI_SZ.W) // Branch val CFI_JAL = 2.U(CFI_SZ.W) // JAL val CFI_JALR = 3.U(CFI_SZ.W) // JALR // PC Select Signal val PC_PLUS4 = 0.U(2.W) // PC + 4 val PC_BRJMP = 1.U(2.W) // brjmp_target val PC_JALR = 2.U(2.W) // jump_reg_target // Branch Type val B_N = 0.U(4.W) // Next val B_NE = 1.U(4.W) // Branch on NotEqual val B_EQ = 2.U(4.W) // Branch on Equal val B_GE = 3.U(4.W) // Branch on Greater/Equal val B_GEU = 4.U(4.W) // Branch on Greater/Equal Unsigned val B_LT = 5.U(4.W) // Branch on Less Than val B_LTU = 6.U(4.W) // Branch on Less Than Unsigned val B_J = 7.U(4.W) // Jump val B_JR = 8.U(4.W) // Jump Register // RS1 Operand Select Signal val OP1_RS1 = 0.U(2.W) // Register Source #1 val OP1_ZERO= 1.U(2.W) val OP1_PC = 2.U(2.W) val OP1_RS1SHL = 3.U(2.W) val OP1_X = BitPat("b??") // RS2 Operand Select Signal val OP2_RS2 = 0.U(3.W) // Register Source #2 val OP2_IMM = 1.U(3.W) // immediate val OP2_ZERO= 2.U(3.W) // constant 0 val OP2_NEXT= 3.U(3.W) // constant 2/4 (for PC+2/4) val OP2_IMMC= 4.U(3.W) // for CSR imm found in RS1 val OP2_RS2OH = 5.U(3.W) val OP2_IMMOH = 6.U(3.W) val OP2_X = BitPat("b???") // Register File Write Enable Signal val REN_0 = false.B val REN_1 = true.B // Is 32b Word or 64b Doubldword? val SZ_DW = 1 val DW_X = true.B // Bool(xLen==64) val DW_32 = false.B val DW_64 = true.B val DW_XPR = true.B // Bool(xLen==64) // Memory Enable Signal val MEN_0 = false.B val MEN_1 = true.B val MEN_X = false.B // Immediate Extend Select val IS_I = 0.U(3.W) // I-Type (LD,ALU) val IS_S = 1.U(3.W) // S-Type (ST) val IS_B = 2.U(3.W) // SB-Type (BR) val IS_U = 3.U(3.W) // U-Type (LUI/AUIPC) val IS_J = 4.U(3.W) // UJ-Type (J/JAL) val IS_SH = 5.U(3.W) // short-type (sign extend from pimm to get imm) val IS_N = 6.U(3.W) // No immediate (zeros immediate) val IS_F3 = 7.U(3.W) // funct3 // Decode Stage Control Signals val RT_FIX = 0.U(2.W) val RT_FLT = 1.U(2.W) val RT_X = 2.U(2.W) // not-a-register (prs1 = lrs1 special case) val RT_ZERO = 3.U(2.W) // IQT type val IQ_SZ = 4 val IQ_MEM = 0 val IQ_UNQ = 1 val IQ_ALU = 2 val IQ_FP = 3 // Functional unit select // bit mask, since a given execution pipeline may support multiple functional units val FC_SZ = 10 val FC_ALU = 0 val FC_AGEN = 1 val FC_DGEN = 2 val FC_MUL = 3 val FC_DIV = 4 val FC_CSR = 5 val FC_FPU = 6 val FC_FDV = 7 val FC_I2F = 8 val FC_F2I = 9 def NullMicroOp(implicit p: Parameters) = 0.U.asTypeOf(new boom.v4.common.MicroOp) } /** * Mixin for RISCV constants */ trait RISCVConstants { // abstract out instruction decode magic numbers val RD_MSB = 11 val RD_LSB = 7 val RS1_MSB = 19 val RS1_LSB = 15 val RS2_MSB = 24 val RS2_LSB = 20 val RS3_MSB = 31 val RS3_LSB = 27 val CSR_ADDR_MSB = 31 val CSR_ADDR_LSB = 20 val CSR_ADDR_SZ = 12 // location of the fifth bit in the shamt (for checking for illegal ops for SRAIW,etc.) val SHAMT_5_BIT = 25 val LONGEST_IMM_SZ = 20 val X0 = 0.U val RA = 1.U // return address register // memory consistency model // The C/C++ atomics MCM requires that two loads to the same address maintain program order. // The Cortex A9 does NOT enforce load/load ordering (which leads to buggy behavior). val MCM_ORDER_DEPENDENT_LOADS = true val jal_opc = (0x6f).U val jalr_opc = (0x67).U def GetUop(inst: UInt): UInt = inst(6,0) def GetRd (inst: UInt): UInt = inst(RD_MSB,RD_LSB) def GetRs1(inst: UInt): UInt = inst(RS1_MSB,RS1_LSB) def ExpandRVC(inst: UInt)(implicit p: Parameters): UInt = { val rvc_exp = Module(new RVCExpander) rvc_exp.io.in := inst Mux(rvc_exp.io.rvc, rvc_exp.io.out.bits, inst) } // Note: Accepts only EXPANDED rvc instructions def ComputeBranchTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val b_imm32 = Cat(Fill(20,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) ((pc.asSInt + b_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def ComputeJALTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val j_imm32 = Cat(Fill(12,inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) ((pc.asSInt + j_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def GetCfiType(inst: UInt)(implicit p: Parameters): UInt = { val bdecode = Module(new boom.v4.exu.BranchDecode) bdecode.io.inst := inst bdecode.io.pc := 0.U bdecode.io.out.cfi_type } } /** * Mixin for exception cause constants */ trait ExcCauseConstants { // a memory disambigious misspeculation occurred val MINI_EXCEPTION_MEM_ORDERING = 16.U val MINI_EXCEPTION_CSR_REPLAY = 17.U require (!freechips.rocketchip.rocket.Causes.all.contains(16)) require (!freechips.rocketchip.rocket.Causes.all.contains(17)) }
module BranchDecode_3( // @[decode.scala:629:7] input clock, // @[decode.scala:629:7] input reset, // @[decode.scala:629:7] input [31:0] io_inst, // @[decode.scala:631:14] input [39:0] io_pc, // @[decode.scala:631:14] output io_out_is_ret, // @[decode.scala:631:14] output io_out_is_call, // @[decode.scala:631:14] output [39:0] io_out_target, // @[decode.scala:631:14] output [2:0] io_out_cfi_type, // @[decode.scala:631:14] output io_out_sfb_offset_valid, // @[decode.scala:631:14] output [5:0] io_out_sfb_offset_bits, // @[decode.scala:631:14] output io_out_shadowable // @[decode.scala:631:14] ); wire [31:0] io_inst_0 = io_inst; // @[decode.scala:629:7] wire [39:0] io_pc_0 = io_pc; // @[decode.scala:629:7] wire [31:0] bpd_csignals_decoded_plaInput = io_inst_0; // @[pla.scala:77:22] wire _io_out_is_ret_T_6; // @[decode.scala:701:72] wire [39:0] _io_out_target_T = io_pc_0; // @[decode.scala:629:7] wire [39:0] _io_out_target_T_8 = io_pc_0; // @[decode.scala:629:7] wire _io_out_is_call_T_3; // @[decode.scala:700:47] wire [39:0] _io_out_target_T_16; // @[decode.scala:703:23] wire [2:0] _io_out_cfi_type_T_2; // @[decode.scala:706:8] wire _io_out_sfb_offset_valid_T_7; // @[decode.scala:716:76] wire _io_out_shadowable_T_11; // @[decode.scala:718:41] wire io_out_sfb_offset_valid_0; // @[decode.scala:629:7] wire [5:0] io_out_sfb_offset_bits_0; // @[decode.scala:629:7] wire io_out_is_ret_0; // @[decode.scala:629:7] wire io_out_is_call_0; // @[decode.scala:629:7] wire [39:0] io_out_target_0; // @[decode.scala:629:7] wire [2:0] io_out_cfi_type_0; // @[decode.scala:629:7] wire io_out_shadowable_0; // @[decode.scala:629:7] wire [31:0] bpd_csignals_decoded_invInputs = ~bpd_csignals_decoded_plaInput; // @[pla.scala:77:22, :78:21] wire [4:0] bpd_csignals_decoded_invMatrixOutputs; // @[pla.scala:120:37] wire [4:0] bpd_csignals_decoded; // @[pla.scala:81:23] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_1 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_2 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_3 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_4 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_5 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_6 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_7 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_8 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_9 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_10 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_11 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_12 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_13 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_14 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_15 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_1 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_2 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_3 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_4 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_5 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_6 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_7 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_8 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_9 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_10 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_11 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_12 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_13 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_14 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_15 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_1 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_2 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_3 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_4 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_6 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_9 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_10 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_11 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_12 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_13 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_14 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_15 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_3 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_5 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_6 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_7 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_9 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_11 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_12 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_13 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_1 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_2 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_3 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_4 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_5 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_9 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_10 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_11 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_13 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_14 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_15 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5 = bpd_csignals_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_1 = bpd_csignals_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_9 = bpd_csignals_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_11 = bpd_csignals_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_13 = bpd_csignals_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_1 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_2 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_3 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_4 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_5 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_9 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_10 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_11 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_13 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_14 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_15 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7 = bpd_csignals_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_1 = bpd_csignals_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_2 = bpd_csignals_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_6 = bpd_csignals_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo = {bpd_csignals_decoded_andMatrixOutputs_lo_hi, bpd_csignals_decoded_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi = {bpd_csignals_decoded_andMatrixOutputs_hi_hi, bpd_csignals_decoded_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53] wire [7:0] _bpd_csignals_decoded_andMatrixOutputs_T = {bpd_csignals_decoded_andMatrixOutputs_hi, bpd_csignals_decoded_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_5_2 = &_bpd_csignals_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_1 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_2 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_4 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_5 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_4 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_5 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_8 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_7 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_12 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_13 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8 = bpd_csignals_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_1 = bpd_csignals_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_4 = bpd_csignals_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_3 = bpd_csignals_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_1}; // @[pla.scala:91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_1 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_1, bpd_csignals_decoded_andMatrixOutputs_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_1}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_1 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_1}; // @[pla.scala:91:29, :98:53] wire [4:0] bpd_csignals_decoded_andMatrixOutputs_hi_1 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_1, bpd_csignals_decoded_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53] wire [8:0] _bpd_csignals_decoded_andMatrixOutputs_T_1 = {bpd_csignals_decoded_andMatrixOutputs_hi_1, bpd_csignals_decoded_andMatrixOutputs_lo_1}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_9_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_2 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_3 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_4 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_5 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_6 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_7 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_8 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_12 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_15 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9 = bpd_csignals_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_3 = bpd_csignals_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_3 = bpd_csignals_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_6 = bpd_csignals_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_7 = bpd_csignals_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_8 = bpd_csignals_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_2 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_2 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_4 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_5 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_5 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_6 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_7 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_1 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_2 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_3 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_4 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_5 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_6 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_7 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_1 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_2 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_3 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_4 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_5 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_6 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_7 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_1 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_2 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_3 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_4 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_5 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_6 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_7 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_1 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_1 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_2 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_3 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_4 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_5 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_6 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13}; // @[pla.scala:91:29, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_2 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9}; // @[pla.scala:91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_2 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo}; // @[pla.scala:98:53] wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_2 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_2, bpd_csignals_decoded_andMatrixOutputs_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_2}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_2 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_2 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_1, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo}; // @[pla.scala:98:53] wire [7:0] bpd_csignals_decoded_andMatrixOutputs_hi_2 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_2, bpd_csignals_decoded_andMatrixOutputs_hi_lo_2}; // @[pla.scala:98:53] wire [14:0] _bpd_csignals_decoded_andMatrixOutputs_T_2 = {bpd_csignals_decoded_andMatrixOutputs_hi_2, bpd_csignals_decoded_andMatrixOutputs_lo_2}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_14_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_1 = bpd_csignals_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_2 = bpd_csignals_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_3 = bpd_csignals_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_4 = bpd_csignals_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_1}; // @[pla.scala:91:29, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_3 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_1}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_1}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_2}; // @[pla.scala:91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_3 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_1, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_1}; // @[pla.scala:98:53] wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_3 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_3, bpd_csignals_decoded_andMatrixOutputs_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_3}; // @[pla.scala:90:45, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_3 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_3}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_3}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_2 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_3}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_3 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_2, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:98:53] wire [6:0] bpd_csignals_decoded_andMatrixOutputs_hi_3 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_3, bpd_csignals_decoded_andMatrixOutputs_hi_lo_3}; // @[pla.scala:98:53] wire [13:0] _bpd_csignals_decoded_andMatrixOutputs_T_3 = {bpd_csignals_decoded_andMatrixOutputs_hi_3, bpd_csignals_decoded_andMatrixOutputs_lo_3}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_0_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_3; // @[pla.scala:98:{53,70}] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_2 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_2}; // @[pla.scala:91:29, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_4 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_1}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_2 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_2}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_2 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_2}; // @[pla.scala:91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_4 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_2, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_4 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_4, bpd_csignals_decoded_andMatrixOutputs_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_4}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_2 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_4}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_4 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_2, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_2 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_4}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_3 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_4}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_4 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_3, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_2}; // @[pla.scala:98:53] wire [7:0] bpd_csignals_decoded_andMatrixOutputs_hi_4 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_4, bpd_csignals_decoded_andMatrixOutputs_hi_lo_4}; // @[pla.scala:98:53] wire [14:0] _bpd_csignals_decoded_andMatrixOutputs_T_4 = {bpd_csignals_decoded_andMatrixOutputs_hi_4, bpd_csignals_decoded_andMatrixOutputs_lo_4}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_2_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_4; // @[pla.scala:98:{53,70}] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_5 = bpd_csignals_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_7 = bpd_csignals_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_8 = bpd_csignals_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_5}; // @[pla.scala:90:45, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_5 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_5}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_5}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_5 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_5, bpd_csignals_decoded_andMatrixOutputs_hi_lo_5}; // @[pla.scala:98:53] wire [6:0] _bpd_csignals_decoded_andMatrixOutputs_T_5 = {bpd_csignals_decoded_andMatrixOutputs_hi_5, bpd_csignals_decoded_andMatrixOutputs_lo_5}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_12_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_5; // @[pla.scala:98:{53,70}] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_6 = bpd_csignals_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_7 = bpd_csignals_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_8 = bpd_csignals_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_12 = bpd_csignals_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_6 = bpd_csignals_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_7 = bpd_csignals_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_8 = bpd_csignals_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_12 = bpd_csignals_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_6 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_6, bpd_csignals_decoded_andMatrixOutputs_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_6}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_6}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_6 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_6, bpd_csignals_decoded_andMatrixOutputs_hi_lo_6}; // @[pla.scala:98:53] wire [7:0] _bpd_csignals_decoded_andMatrixOutputs_T_6 = {bpd_csignals_decoded_andMatrixOutputs_hi_6, bpd_csignals_decoded_andMatrixOutputs_lo_6}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_6_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_6; // @[pla.scala:98:{53,70}] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_3}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_3 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_7}; // @[pla.scala:90:45, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_7 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_6}; // @[pla.scala:91:29, :98:53] wire [4:0] bpd_csignals_decoded_andMatrixOutputs_lo_7 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_7, bpd_csignals_decoded_andMatrixOutputs_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_7 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_7}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_4 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_7}; // @[pla.scala:90:45, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_7 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_7}; // @[pla.scala:90:45, :98:53] wire [4:0] bpd_csignals_decoded_andMatrixOutputs_hi_7 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_7, bpd_csignals_decoded_andMatrixOutputs_hi_lo_7}; // @[pla.scala:98:53] wire [9:0] _bpd_csignals_decoded_andMatrixOutputs_T_7 = {bpd_csignals_decoded_andMatrixOutputs_hi_7, bpd_csignals_decoded_andMatrixOutputs_lo_7}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_15_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_7; // @[pla.scala:98:{53,70}] wire _bpd_csignals_decoded_orMatrixOutputs_T_4 = bpd_csignals_decoded_andMatrixOutputs_15_2; // @[pla.scala:98:70, :114:36] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_8 = bpd_csignals_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_10 = bpd_csignals_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_14 = bpd_csignals_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_8 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_8 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_8}; // @[pla.scala:90:45, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_8 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_8}; // @[pla.scala:90:45, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_8 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_8}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_8 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_8, bpd_csignals_decoded_andMatrixOutputs_hi_lo_8}; // @[pla.scala:98:53] wire [6:0] _bpd_csignals_decoded_andMatrixOutputs_T_8 = {bpd_csignals_decoded_andMatrixOutputs_hi_8, bpd_csignals_decoded_andMatrixOutputs_lo_8}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_11_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_8; // @[pla.scala:98:{53,70}] wire _bpd_csignals_decoded_orMatrixOutputs_T_5 = bpd_csignals_decoded_andMatrixOutputs_11_2; // @[pla.scala:98:70, :114:36] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_7 = bpd_csignals_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_10 = bpd_csignals_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_11 = bpd_csignals_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_14 = bpd_csignals_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_15 = bpd_csignals_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_3 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_3}; // @[pla.scala:91:29, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_7 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_2}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_3 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_3}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_4 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_4}; // @[pla.scala:91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_9 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_4, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_3}; // @[pla.scala:98:53] wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_9 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_9, bpd_csignals_decoded_andMatrixOutputs_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_2 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_3 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_9 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_3, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_3 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_9}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_9}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_9 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_5, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_3}; // @[pla.scala:98:53] wire [7:0] bpd_csignals_decoded_andMatrixOutputs_hi_9 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_9, bpd_csignals_decoded_andMatrixOutputs_hi_lo_9}; // @[pla.scala:98:53] wire [14:0] _bpd_csignals_decoded_andMatrixOutputs_T_9 = {bpd_csignals_decoded_andMatrixOutputs_hi_9, bpd_csignals_decoded_andMatrixOutputs_lo_9}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_3_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_9; // @[pla.scala:98:{53,70}] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_4 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_4}; // @[pla.scala:91:29, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_8 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_3}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_4 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_4}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_5}; // @[pla.scala:91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_10 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_5, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_10 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_10, bpd_csignals_decoded_andMatrixOutputs_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_3 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_4 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_10 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_4, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_4 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_10}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_10 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_6, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_4}; // @[pla.scala:98:53] wire [7:0] bpd_csignals_decoded_andMatrixOutputs_hi_10 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_10, bpd_csignals_decoded_andMatrixOutputs_hi_lo_10}; // @[pla.scala:98:53] wire [14:0] _bpd_csignals_decoded_andMatrixOutputs_T_10 = {bpd_csignals_decoded_andMatrixOutputs_hi_10, bpd_csignals_decoded_andMatrixOutputs_lo_10}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_7_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_10; // @[pla.scala:98:{53,70}] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_9 = bpd_csignals_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_9 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_11, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_11 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_11, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_11 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_11, bpd_csignals_decoded_andMatrixOutputs_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_11 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_11, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_11}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_11 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_11, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_11}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_11 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_11, bpd_csignals_decoded_andMatrixOutputs_hi_lo_11}; // @[pla.scala:98:53] wire [7:0] _bpd_csignals_decoded_andMatrixOutputs_T_11 = {bpd_csignals_decoded_andMatrixOutputs_hi_11, bpd_csignals_decoded_andMatrixOutputs_lo_11}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_1_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_11; // @[pla.scala:98:{53,70}] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_10 = bpd_csignals_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_6 = bpd_csignals_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_8 = bpd_csignals_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_9 = bpd_csignals_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_10 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_10}; // @[pla.scala:90:45, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_12 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_12 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_12, bpd_csignals_decoded_andMatrixOutputs_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_12 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_12}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_12 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_12}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_12 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_12, bpd_csignals_decoded_andMatrixOutputs_hi_lo_12}; // @[pla.scala:98:53] wire [7:0] _bpd_csignals_decoded_andMatrixOutputs_T_12 = {bpd_csignals_decoded_andMatrixOutputs_hi_12, bpd_csignals_decoded_andMatrixOutputs_lo_12}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_13_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_12; // @[pla.scala:98:{53,70}] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_5}; // @[pla.scala:91:29, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_11 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_4}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_5}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_13 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_6, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_5}; // @[pla.scala:98:53] wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_13 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_13, bpd_csignals_decoded_andMatrixOutputs_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_4 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_13, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_13, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_13 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_5, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_13, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_13}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_7 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_13, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_13}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_13 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_7, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] bpd_csignals_decoded_andMatrixOutputs_hi_13 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_13, bpd_csignals_decoded_andMatrixOutputs_hi_lo_13}; // @[pla.scala:98:53] wire [14:0] _bpd_csignals_decoded_andMatrixOutputs_T_13 = {bpd_csignals_decoded_andMatrixOutputs_hi_13, bpd_csignals_decoded_andMatrixOutputs_lo_13}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_4_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_13; // @[pla.scala:98:{53,70}] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_6}; // @[pla.scala:91:29, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_12 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_5}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_6}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_7 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_14 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_7, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_14 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_14, bpd_csignals_decoded_andMatrixOutputs_lo_lo_12}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_14, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_14, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_14 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_6, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_14, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_8 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_14, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_14}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_14 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_8, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_6}; // @[pla.scala:98:53] wire [7:0] bpd_csignals_decoded_andMatrixOutputs_hi_14 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_14, bpd_csignals_decoded_andMatrixOutputs_hi_lo_14}; // @[pla.scala:98:53] wire [14:0] _bpd_csignals_decoded_andMatrixOutputs_T_14 = {bpd_csignals_decoded_andMatrixOutputs_hi_14, bpd_csignals_decoded_andMatrixOutputs_lo_14}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_8_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_14; // @[pla.scala:98:{53,70}] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_7 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_7}; // @[pla.scala:91:29, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_13 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_6}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_7 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_7}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_8 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_15 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_8, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_7}; // @[pla.scala:98:53] wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_15 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_15, bpd_csignals_decoded_andMatrixOutputs_lo_lo_13}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_15, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_7 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_15, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_15 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_7, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_7 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_15, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_9 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_15, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_15}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_15 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_9, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_7}; // @[pla.scala:98:53] wire [7:0] bpd_csignals_decoded_andMatrixOutputs_hi_15 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_15, bpd_csignals_decoded_andMatrixOutputs_hi_lo_15}; // @[pla.scala:98:53] wire [14:0] _bpd_csignals_decoded_andMatrixOutputs_T_15 = {bpd_csignals_decoded_andMatrixOutputs_hi_15, bpd_csignals_decoded_andMatrixOutputs_lo_15}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_10_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_15; // @[pla.scala:98:{53,70}] wire [1:0] bpd_csignals_decoded_orMatrixOutputs_lo = {bpd_csignals_decoded_andMatrixOutputs_2_2, bpd_csignals_decoded_andMatrixOutputs_10_2}; // @[pla.scala:98:70, :114:19] wire [1:0] bpd_csignals_decoded_orMatrixOutputs_hi = {bpd_csignals_decoded_andMatrixOutputs_14_2, bpd_csignals_decoded_andMatrixOutputs_0_2}; // @[pla.scala:98:70, :114:19] wire [3:0] _bpd_csignals_decoded_orMatrixOutputs_T = {bpd_csignals_decoded_orMatrixOutputs_hi, bpd_csignals_decoded_orMatrixOutputs_lo}; // @[pla.scala:114:19] wire _bpd_csignals_decoded_orMatrixOutputs_T_1 = |_bpd_csignals_decoded_orMatrixOutputs_T; // @[pla.scala:114:{19,36}] wire [1:0] bpd_csignals_decoded_orMatrixOutputs_lo_lo = {bpd_csignals_decoded_andMatrixOutputs_8_2, bpd_csignals_decoded_andMatrixOutputs_10_2}; // @[pla.scala:98:70, :114:19] wire [1:0] bpd_csignals_decoded_orMatrixOutputs_lo_hi_hi = {bpd_csignals_decoded_andMatrixOutputs_7_2, bpd_csignals_decoded_andMatrixOutputs_1_2}; // @[pla.scala:98:70, :114:19] wire [2:0] bpd_csignals_decoded_orMatrixOutputs_lo_hi = {bpd_csignals_decoded_orMatrixOutputs_lo_hi_hi, bpd_csignals_decoded_andMatrixOutputs_4_2}; // @[pla.scala:98:70, :114:19] wire [4:0] bpd_csignals_decoded_orMatrixOutputs_lo_1 = {bpd_csignals_decoded_orMatrixOutputs_lo_hi, bpd_csignals_decoded_orMatrixOutputs_lo_lo}; // @[pla.scala:114:19] wire [1:0] bpd_csignals_decoded_orMatrixOutputs_hi_lo_hi = {bpd_csignals_decoded_andMatrixOutputs_0_2, bpd_csignals_decoded_andMatrixOutputs_12_2}; // @[pla.scala:98:70, :114:19] wire [2:0] bpd_csignals_decoded_orMatrixOutputs_hi_lo = {bpd_csignals_decoded_orMatrixOutputs_hi_lo_hi, bpd_csignals_decoded_andMatrixOutputs_3_2}; // @[pla.scala:98:70, :114:19] wire [1:0] bpd_csignals_decoded_orMatrixOutputs_hi_hi_hi = {bpd_csignals_decoded_andMatrixOutputs_5_2, bpd_csignals_decoded_andMatrixOutputs_9_2}; // @[pla.scala:98:70, :114:19] wire [2:0] bpd_csignals_decoded_orMatrixOutputs_hi_hi = {bpd_csignals_decoded_orMatrixOutputs_hi_hi_hi, bpd_csignals_decoded_andMatrixOutputs_14_2}; // @[pla.scala:98:70, :114:19] wire [5:0] bpd_csignals_decoded_orMatrixOutputs_hi_1 = {bpd_csignals_decoded_orMatrixOutputs_hi_hi, bpd_csignals_decoded_orMatrixOutputs_hi_lo}; // @[pla.scala:114:19] wire [10:0] _bpd_csignals_decoded_orMatrixOutputs_T_2 = {bpd_csignals_decoded_orMatrixOutputs_hi_1, bpd_csignals_decoded_orMatrixOutputs_lo_1}; // @[pla.scala:114:19] wire _bpd_csignals_decoded_orMatrixOutputs_T_3 = |_bpd_csignals_decoded_orMatrixOutputs_T_2; // @[pla.scala:114:{19,36}] wire [1:0] _bpd_csignals_decoded_orMatrixOutputs_T_6 = {bpd_csignals_decoded_andMatrixOutputs_6_2, bpd_csignals_decoded_andMatrixOutputs_13_2}; // @[pla.scala:98:70, :114:19] wire _bpd_csignals_decoded_orMatrixOutputs_T_7 = |_bpd_csignals_decoded_orMatrixOutputs_T_6; // @[pla.scala:114:{19,36}] wire [1:0] bpd_csignals_decoded_orMatrixOutputs_lo_2 = {_bpd_csignals_decoded_orMatrixOutputs_T_3, _bpd_csignals_decoded_orMatrixOutputs_T_1}; // @[pla.scala:102:36, :114:36] wire [1:0] bpd_csignals_decoded_orMatrixOutputs_hi_hi_1 = {_bpd_csignals_decoded_orMatrixOutputs_T_7, _bpd_csignals_decoded_orMatrixOutputs_T_5}; // @[pla.scala:102:36, :114:36] wire [2:0] bpd_csignals_decoded_orMatrixOutputs_hi_2 = {bpd_csignals_decoded_orMatrixOutputs_hi_hi_1, _bpd_csignals_decoded_orMatrixOutputs_T_4}; // @[pla.scala:102:36, :114:36] wire [4:0] bpd_csignals_decoded_orMatrixOutputs = {bpd_csignals_decoded_orMatrixOutputs_hi_2, bpd_csignals_decoded_orMatrixOutputs_lo_2}; // @[pla.scala:102:36] wire _bpd_csignals_decoded_invMatrixOutputs_T = bpd_csignals_decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31] wire _bpd_csignals_decoded_invMatrixOutputs_T_1 = bpd_csignals_decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31] wire _bpd_csignals_decoded_invMatrixOutputs_T_2 = bpd_csignals_decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31] wire _bpd_csignals_decoded_invMatrixOutputs_T_3 = bpd_csignals_decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31] wire _bpd_csignals_decoded_invMatrixOutputs_T_4 = bpd_csignals_decoded_orMatrixOutputs[4]; // @[pla.scala:102:36, :124:31] wire [1:0] bpd_csignals_decoded_invMatrixOutputs_lo = {_bpd_csignals_decoded_invMatrixOutputs_T_1, _bpd_csignals_decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31] wire [1:0] bpd_csignals_decoded_invMatrixOutputs_hi_hi = {_bpd_csignals_decoded_invMatrixOutputs_T_4, _bpd_csignals_decoded_invMatrixOutputs_T_3}; // @[pla.scala:120:37, :124:31] wire [2:0] bpd_csignals_decoded_invMatrixOutputs_hi = {bpd_csignals_decoded_invMatrixOutputs_hi_hi, _bpd_csignals_decoded_invMatrixOutputs_T_2}; // @[pla.scala:120:37, :124:31] assign bpd_csignals_decoded_invMatrixOutputs = {bpd_csignals_decoded_invMatrixOutputs_hi, bpd_csignals_decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37] assign bpd_csignals_decoded = bpd_csignals_decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37] wire bpd_csignals_0 = bpd_csignals_decoded[4]; // @[pla.scala:81:23] wire cs_is_br = bpd_csignals_0; // @[Decode.scala:50:77] wire bpd_csignals_1 = bpd_csignals_decoded[3]; // @[pla.scala:81:23] wire cs_is_jal = bpd_csignals_1; // @[Decode.scala:50:77] wire bpd_csignals_2 = bpd_csignals_decoded[2]; // @[pla.scala:81:23] wire cs_is_jalr = bpd_csignals_2; // @[Decode.scala:50:77] wire bpd_csignals_3 = bpd_csignals_decoded[1]; // @[pla.scala:81:23] wire cs_is_shadowable = bpd_csignals_3; // @[Decode.scala:50:77] wire bpd_csignals_4 = bpd_csignals_decoded[0]; // @[pla.scala:81:23] wire cs_has_rs2 = bpd_csignals_4; // @[Decode.scala:50:77] wire _io_out_is_call_T = cs_is_jal | cs_is_jalr; // @[decode.scala:695:34, :696:35, :700:32] wire [4:0] _io_out_is_call_T_1 = io_inst_0[11:7]; // @[decode.scala:629:7] wire [4:0] _io_out_is_ret_T_4 = io_inst_0[11:7]; // @[decode.scala:629:7] wire [4:0] _io_out_shadowable_T_2 = io_inst_0[11:7]; // @[decode.scala:629:7] wire _io_out_is_call_T_2 = _io_out_is_call_T_1 == 5'h1; // @[decode.scala:700:65] assign _io_out_is_call_T_3 = _io_out_is_call_T & _io_out_is_call_T_2; // @[decode.scala:700:{32,47,65}] assign io_out_is_call_0 = _io_out_is_call_T_3; // @[decode.scala:629:7, :700:47] wire [4:0] _io_out_is_ret_T = io_inst_0[19:15]; // @[decode.scala:629:7] wire [4:0] _io_out_shadowable_T_1 = io_inst_0[19:15]; // @[decode.scala:629:7] wire [4:0] _io_out_shadowable_T_7 = io_inst_0[19:15]; // @[decode.scala:629:7] wire [4:0] _io_out_is_ret_T_1 = _io_out_is_ret_T & 5'h1B; // @[decode.scala:701:51] wire _io_out_is_ret_T_2 = _io_out_is_ret_T_1 == 5'h1; // @[decode.scala:701:51] wire _io_out_is_ret_T_3 = cs_is_jalr & _io_out_is_ret_T_2; // @[decode.scala:696:35, :701:{32,51}] wire _io_out_is_ret_T_5 = _io_out_is_ret_T_4 == 5'h0; // @[decode.scala:701:90] assign _io_out_is_ret_T_6 = _io_out_is_ret_T_3 & _io_out_is_ret_T_5; // @[decode.scala:701:{32,72,90}] assign io_out_is_ret_0 = _io_out_is_ret_T_6; // @[decode.scala:629:7, :701:72] wire _io_out_target_b_imm32_T = io_inst_0[31]; // @[decode.scala:629:7] wire _io_out_target_j_imm32_T = io_inst_0[31]; // @[decode.scala:629:7] wire _io_out_sfb_offset_valid_T = io_inst_0[31]; // @[decode.scala:629:7, :716:50] wire [19:0] _io_out_target_b_imm32_T_1 = {20{_io_out_target_b_imm32_T}}; // @[consts.scala:189:{27,35}] wire _io_out_target_b_imm32_T_2 = io_inst_0[7]; // @[decode.scala:629:7] wire _br_offset_T = io_inst_0[7]; // @[decode.scala:629:7, :714:30] wire [5:0] _io_out_target_b_imm32_T_3 = io_inst_0[30:25]; // @[decode.scala:629:7] wire [5:0] _io_out_target_j_imm32_T_4 = io_inst_0[30:25]; // @[decode.scala:629:7] wire [5:0] _br_offset_T_1 = io_inst_0[30:25]; // @[decode.scala:629:7, :714:42] wire [3:0] _io_out_target_b_imm32_T_4 = io_inst_0[11:8]; // @[decode.scala:629:7] wire [3:0] _br_offset_T_2 = io_inst_0[11:8]; // @[decode.scala:629:7, :714:58] wire [4:0] io_out_target_b_imm32_lo = {_io_out_target_b_imm32_T_4, 1'h0}; // @[consts.scala:189:{22,68}] wire [20:0] io_out_target_b_imm32_hi_hi = {_io_out_target_b_imm32_T_1, _io_out_target_b_imm32_T_2}; // @[consts.scala:189:{22,27,46}] wire [26:0] io_out_target_b_imm32_hi = {io_out_target_b_imm32_hi_hi, _io_out_target_b_imm32_T_3}; // @[consts.scala:189:{22,55}] wire [31:0] io_out_target_b_imm32 = {io_out_target_b_imm32_hi, io_out_target_b_imm32_lo}; // @[consts.scala:189:22] wire [31:0] _io_out_target_T_1 = io_out_target_b_imm32; // @[consts.scala:189:22, :190:27] wire [40:0] _io_out_target_T_2 = {_io_out_target_T[39], _io_out_target_T} + {{9{_io_out_target_T_1[31]}}, _io_out_target_T_1}; // @[consts.scala:190:{10,17,27}] wire [39:0] _io_out_target_T_3 = _io_out_target_T_2[39:0]; // @[consts.scala:190:17] wire [39:0] _io_out_target_T_4 = _io_out_target_T_3; // @[consts.scala:190:17] wire [39:0] _io_out_target_T_5 = _io_out_target_T_4 & 40'hFFFFFFFFFE; // @[consts.scala:190:{17,42}] wire [39:0] _io_out_target_T_6 = _io_out_target_T_5; // @[consts.scala:190:42] wire [39:0] _io_out_target_T_7 = _io_out_target_T_6; // @[consts.scala:190:{42,52}] wire [11:0] _io_out_target_j_imm32_T_1 = {12{_io_out_target_j_imm32_T}}; // @[consts.scala:195:{27,35}] wire [7:0] _io_out_target_j_imm32_T_2 = io_inst_0[19:12]; // @[decode.scala:629:7] wire _io_out_target_j_imm32_T_3 = io_inst_0[20]; // @[decode.scala:629:7] wire [3:0] _io_out_target_j_imm32_T_5 = io_inst_0[24:21]; // @[decode.scala:629:7] wire [9:0] io_out_target_j_imm32_lo_hi = {_io_out_target_j_imm32_T_4, _io_out_target_j_imm32_T_5}; // @[consts.scala:195:{22,69,82}] wire [10:0] io_out_target_j_imm32_lo = {io_out_target_j_imm32_lo_hi, 1'h0}; // @[consts.scala:195:22] wire [19:0] io_out_target_j_imm32_hi_hi = {_io_out_target_j_imm32_T_1, _io_out_target_j_imm32_T_2}; // @[consts.scala:195:{22,27,46}] wire [20:0] io_out_target_j_imm32_hi = {io_out_target_j_imm32_hi_hi, _io_out_target_j_imm32_T_3}; // @[consts.scala:195:{22,59}] wire [31:0] io_out_target_j_imm32 = {io_out_target_j_imm32_hi, io_out_target_j_imm32_lo}; // @[consts.scala:195:22] wire [31:0] _io_out_target_T_9 = io_out_target_j_imm32; // @[consts.scala:195:22, :196:27] wire [40:0] _io_out_target_T_10 = {_io_out_target_T_8[39], _io_out_target_T_8} + {{9{_io_out_target_T_9[31]}}, _io_out_target_T_9}; // @[consts.scala:196:{10,17,27}] wire [39:0] _io_out_target_T_11 = _io_out_target_T_10[39:0]; // @[consts.scala:196:17] wire [39:0] _io_out_target_T_12 = _io_out_target_T_11; // @[consts.scala:196:17] wire [39:0] _io_out_target_T_13 = _io_out_target_T_12 & 40'hFFFFFFFFFE; // @[consts.scala:196:{17,42}] wire [39:0] _io_out_target_T_14 = _io_out_target_T_13; // @[consts.scala:196:42] wire [39:0] _io_out_target_T_15 = _io_out_target_T_14; // @[consts.scala:196:{42,52}] assign _io_out_target_T_16 = cs_is_br ? _io_out_target_T_7 : _io_out_target_T_15; // @[decode.scala:694:33, :703:23] assign io_out_target_0 = _io_out_target_T_16; // @[decode.scala:629:7, :703:23] wire [2:0] _io_out_cfi_type_T = {2'h0, cs_is_br}; // @[decode.scala:694:33, :710:8] wire [2:0] _io_out_cfi_type_T_1 = cs_is_jal ? 3'h2 : _io_out_cfi_type_T; // @[decode.scala:695:34, :708:8, :710:8] assign _io_out_cfi_type_T_2 = cs_is_jalr ? 3'h3 : _io_out_cfi_type_T_1; // @[decode.scala:696:35, :706:8, :708:8] assign io_out_cfi_type_0 = _io_out_cfi_type_T_2; // @[decode.scala:629:7, :706:8] wire [4:0] br_offset_lo = {_br_offset_T_2, 1'h0}; // @[decode.scala:714:{22,58}] wire [6:0] br_offset_hi = {_br_offset_T, _br_offset_T_1}; // @[decode.scala:714:{22,30,42}] wire [11:0] br_offset = {br_offset_hi, br_offset_lo}; // @[decode.scala:714:22] wire _io_out_sfb_offset_valid_T_1 = ~_io_out_sfb_offset_valid_T; // @[decode.scala:716:{42,50}] wire _io_out_sfb_offset_valid_T_2 = cs_is_br & _io_out_sfb_offset_valid_T_1; // @[decode.scala:694:33, :716:{39,42}] wire _io_out_sfb_offset_valid_T_3 = |br_offset; // @[decode.scala:714:22, :716:68] wire _io_out_sfb_offset_valid_T_4 = _io_out_sfb_offset_valid_T_2 & _io_out_sfb_offset_valid_T_3; // @[decode.scala:716:{39,55,68}] wire [5:0] _io_out_sfb_offset_valid_T_5 = br_offset[11:6]; // @[decode.scala:714:22, :716:90] wire _io_out_sfb_offset_valid_T_6 = _io_out_sfb_offset_valid_T_5 == 6'h0; // @[decode.scala:716:{90,117}] assign _io_out_sfb_offset_valid_T_7 = _io_out_sfb_offset_valid_T_4 & _io_out_sfb_offset_valid_T_6; // @[decode.scala:716:{55,76,117}] assign io_out_sfb_offset_valid_0 = _io_out_sfb_offset_valid_T_7; // @[decode.scala:629:7, :716:76] assign io_out_sfb_offset_bits_0 = br_offset[5:0]; // @[decode.scala:629:7, :714:22, :717:27] wire _io_out_shadowable_T = ~cs_has_rs2; // @[decode.scala:698:35, :719:5] wire _io_out_shadowable_T_3 = _io_out_shadowable_T_1 == _io_out_shadowable_T_2; // @[decode.scala:720:22] wire _io_out_shadowable_T_4 = _io_out_shadowable_T | _io_out_shadowable_T_3; // @[decode.scala:719:{5,17}, :720:22] wire [31:0] _io_out_shadowable_T_5 = io_inst_0 & 32'hFE00707F; // @[decode.scala:629:7, :721:14] wire _io_out_shadowable_T_6 = _io_out_shadowable_T_5 == 32'h33; // @[decode.scala:721:14] wire _io_out_shadowable_T_8 = _io_out_shadowable_T_7 == 5'h0; // @[decode.scala:701:90, :721:41] wire _io_out_shadowable_T_9 = _io_out_shadowable_T_6 & _io_out_shadowable_T_8; // @[decode.scala:721:{14,22,41}] wire _io_out_shadowable_T_10 = _io_out_shadowable_T_4 | _io_out_shadowable_T_9; // @[decode.scala:719:17, :720:42, :721:22] assign _io_out_shadowable_T_11 = cs_is_shadowable & _io_out_shadowable_T_10; // @[decode.scala:697:41, :718:41, :720:42] assign io_out_shadowable_0 = _io_out_shadowable_T_11; // @[decode.scala:629:7, :718:41] assign io_out_is_ret = io_out_is_ret_0; // @[decode.scala:629:7] assign io_out_is_call = io_out_is_call_0; // @[decode.scala:629:7] assign io_out_target = io_out_target_0; // @[decode.scala:629:7] assign io_out_cfi_type = io_out_cfi_type_0; // @[decode.scala:629:7] assign io_out_sfb_offset_valid = io_out_sfb_offset_valid_0; // @[decode.scala:629:7] assign io_out_sfb_offset_bits = io_out_sfb_offset_bits_0; // @[decode.scala:629:7] assign io_out_shadowable = io_out_shadowable_0; // @[decode.scala:629:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag }
module OptimizationBarrier_EntryData_2( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_0 = io_x_ae; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae = io_x_ae_0; // @[package.scala:267:30] wire io_y_sw = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr = io_x_sr_0; // @[package.scala:267:30] wire io_y_pw = io_x_pw_0; // @[package.scala:267:30] wire io_y_px = io_x_px_0; // @[package.scala:267:30] wire io_y_pr = io_x_pr_0; // @[package.scala:267:30] wire io_y_pal = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff = io_x_eff_0; // @[package.scala:267:30] wire io_y_c = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ChipTop.scala: package chipyard import chisel3._ import scala.collection.mutable.{ArrayBuffer} import freechips.rocketchip.prci.{ClockGroupIdentityNode, ClockSinkParameters, ClockSinkNode, ClockGroup} import org.chipsalliance.cde.config.{Parameters, Field} import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, LazyRawModuleImp, LazyModuleImpLike, BindingScope} import freechips.rocketchip.util.{DontTouch} import chipyard.iobinders._ import chipyard.iocell._ case object BuildSystem extends Field[Parameters => LazyModule]((p: Parameters) => new DigitalTop()(p)) /** * The base class used for building chips. This constructor instantiates a module specified by the BuildSystem parameter, * named "system", which is an instance of DigitalTop by default. The diplomatic clocks of System, as well as its implicit clock, * is aggregated into the clockGroupNode. The parameterized functions controlled by ClockingSchemeKey and GlobalResetSchemeKey * drive clock and reset generation */ class ChipTop(implicit p: Parameters) extends LazyModule with BindingScope with HasIOBinders { // The system module specified by BuildSystem lazy val lazySystem = LazyModule(p(BuildSystem)(p)).suggestName("system") // NOTE: Making this a LazyRawModule is moderately dangerous, as anonymous children // of ChipTop (ex: ClockGroup) do not receive clock or reset. // However. anonymous children of ChipTop should not need an implicit Clock or Reset // anyways, they probably need to be explicitly clocked. lazy val module: LazyModuleImpLike = new LazyRawModuleImp(this) with DontTouch { } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File IOBinders.scala: package chipyard.iobinders import chisel3._ import chisel3.reflect.DataMirror import chisel3.experimental.Analog import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import org.chipsalliance.diplomacy.aop._ import org.chipsalliance.diplomacy.lazymodule._ import org.chipsalliance.diplomacy.bundlebridge._ import freechips.rocketchip.diplomacy.{Resource, ResourceBinding, ResourceAddress, RegionType} import freechips.rocketchip.devices.debug._ import freechips.rocketchip.jtag.{JTAGIO} import freechips.rocketchip.subsystem._ import freechips.rocketchip.system.{SimAXIMem} import freechips.rocketchip.amba.axi4.{AXI4Bundle, AXI4SlaveNode, AXI4MasterNode, AXI4EdgeParameters} import freechips.rocketchip.util._ import freechips.rocketchip.prci._ import freechips.rocketchip.groundtest.{GroundTestSubsystemModuleImp, GroundTestSubsystem} import freechips.rocketchip.tilelink.{TLBundle} import sifive.blocks.devices.gpio._ import sifive.blocks.devices.uart._ import sifive.blocks.devices.spi._ import sifive.blocks.devices.i2c._ import tracegen.{TraceGenSystemModuleImp} import chipyard.iocell._ import testchipip.serdes.{CanHavePeripheryTLSerial, SerialTLKey} import testchipip.spi.{SPIChipIO} import testchipip.boot.{CanHavePeripheryCustomBootPin} import testchipip.soc.{CanHavePeripheryChipIdPin} import testchipip.util.{ClockedIO} import testchipip.iceblk.{CanHavePeripheryBlockDevice, BlockDeviceKey, BlockDeviceIO} import testchipip.cosim.{CanHaveTraceIO, TraceOutputTop, SpikeCosimConfig} import testchipip.tsi.{CanHavePeripheryUARTTSI, UARTTSIIO} import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly} import chipyard.{CanHaveMasterTLMemPort, ChipyardSystem, ChipyardSystemModule} import chipyard.example.{CanHavePeripheryGCD} import scala.reflect.{ClassTag} object IOBinderTypes { type IOBinderTuple = (Seq[Port[_]], Seq[IOCell]) type IOBinderFunction = (Boolean, => Any) => ModuleValue[IOBinderTuple] } import IOBinderTypes._ // System for instantiating binders based // on the scala type of the Target (_not_ its IO). This avoids needing to // duplicate harnesses (essentially test harnesses) for each target. // IOBinders is map between string representations of traits to the desired // IO connection behavior for tops matching that trait. We use strings to enable // composition and overriding of IOBinders, much like how normal Keys in the config // system are used/ At elaboration, the testharness traverses this set of functions, // and functions which match the type of the DigitalTop are evaluated. // You can add your own binder by adding a new (key, fn) pair, typically by using // the OverrideIOBinder or ComposeIOBinder macros case object IOBinders extends Field[Map[String, Seq[IOBinderFunction]]]( Map[String, Seq[IOBinderFunction]]().withDefaultValue(Nil) ) abstract trait HasIOBinders extends HasChipyardPorts { this: LazyModule => val lazySystem: LazyModule private val iobinders = p(IOBinders) // Note: IOBinders cannot rely on the implicit clock/reset, as they may be called from the // context of a LazyRawModuleImp private val lzy = iobinders.map({ case (s,fns) => s -> fns.map(f => f(true, lazySystem)) }) private val imp = iobinders.map({ case (s,fns) => s -> fns.map(f => f(false, lazySystem.module)) }) private lazy val lzyFlattened: Map[String, IOBinderTuple] = lzy.map({ case (s,ms) => s -> (ms.map(_._1).flatten, ms.map(_._2).flatten) }) private lazy val impFlattened: Map[String, IOBinderTuple] = imp.map({ case (s,ms) => s -> (ms.map(_._1).flatten, ms.map(_._2).flatten) }) // A publicly accessible list of IO cells (useful for a floorplanning tool, for example) val iocells = InModuleBody { (lzyFlattened.values ++ impFlattened.values).unzip._2.flatten.toBuffer } // A mapping between stringified DigitalSystem traits and their corresponding ChipTop ports val portMap = InModuleBody { iobinders.keys.map(k => k -> (lzyFlattened(k)._1 ++ impFlattened(k)._1)).toMap } // A mapping between stringified DigitalSystem traits and their corresponding ChipTop iocells val iocellMap = InModuleBody { iobinders.keys.map(k => k -> (lzyFlattened(k)._2 ++ impFlattened(k)._2)).toMap } def ports = portMap.getWrappedValue.values.flatten.toSeq InModuleBody { println("IOCells generated by IOBinders:") for ((k, v) <- iocellMap) { if (!v.isEmpty) { val cells = v.map(_.getClass.getSimpleName).groupBy(identity).mapValues(_.size) println(s" IOBinder for $k generated:") for ((t, c) <- cells) { println(s" $c X $t") } } } println() val totals = iocells.map(_.getClass.getSimpleName).groupBy(identity).mapValues(_.size) println(s" Total generated ${iocells.size} IOCells:") for ((t, c) <- totals) { println(s" $c X $t") } } } // Note: The parameters instance is accessible only through LazyModule // or LazyModuleImpLike. The self-type requirement in traits like // CanHaveMasterAXI4MemPort is insufficient to make it accessible to the IOBinder // As a result, IOBinders only work on Modules which inherit LazyModule or // or LazyModuleImpLike object GetSystemParameters { def apply(s: Any): Parameters = { s match { case s: LazyModule => s.p case s: LazyModuleImpLike => s.p case _ => throw new Exception(s"Trying to get Parameters from a system that is not LazyModule or LazyModuleImpLike") } } } class IOBinder[T](composer: Seq[IOBinderFunction] => Seq[IOBinderFunction])(implicit tag: ClassTag[T]) extends Config((site, here, up) => { case IOBinders => { val upMap = up(IOBinders) upMap + (tag.runtimeClass.toString -> composer(upMap(tag.runtimeClass.toString))) } }) class ConcreteIOBinder[T](composes: Boolean, fn: T => IOBinderTuple)(implicit tag: ClassTag[T]) extends IOBinder[T]( up => (if (composes) up else Nil) ++ Seq(((_, t) => { InModuleBody { t match { case system: T => fn(system) case _ => (Nil, Nil) } }}): IOBinderFunction) ) class LazyIOBinder[T](composes: Boolean, fn: T => ModuleValue[IOBinderTuple])(implicit tag: ClassTag[T]) extends IOBinder[T]( up => (if (composes) up else Nil) ++ Seq(((isLazy, t) => { val empty = new ModuleValue[IOBinderTuple] { def getWrappedValue: IOBinderTuple = (Nil, Nil) } if (isLazy) { t match { case system: T => fn(system) case _ => empty } } else { empty } }): IOBinderFunction) ) // The "Override" binders override any previous IOBinders (lazy or concrete) defined on the same trait. // The "Compose" binders do not override previously defined IOBinders on the same trait // The default IOBinders evaluate only in the concrete "ModuleImp" phase of elaboration // The "Lazy" IOBinders evaluate in the LazyModule phase, but can also generate hardware through InModuleBody class OverrideIOBinder[T](fn: T => IOBinderTuple)(implicit tag: ClassTag[T]) extends ConcreteIOBinder[T](false, fn) class ComposeIOBinder[T](fn: T => IOBinderTuple)(implicit tag: ClassTag[T]) extends ConcreteIOBinder[T](true, fn) class OverrideLazyIOBinder[T](fn: T => ModuleValue[IOBinderTuple])(implicit tag: ClassTag[T]) extends LazyIOBinder[T](false, fn) class ComposeLazyIOBinder[T](fn: T => ModuleValue[IOBinderTuple])(implicit tag: ClassTag[T]) extends LazyIOBinder[T](true, fn) case object IOCellKey extends Field[IOCellTypeParams](GenericIOCellParams()) class WithGPIOCells extends OverrideIOBinder({ (system: HasPeripheryGPIO) => { val (ports2d, cells2d) = system.gpio.zipWithIndex.map({ case (gpio, i) => gpio.pins.zipWithIndex.map({ case (pin, j) => val p = system.asInstanceOf[BaseSubsystem].p val g = IO(Analog(1.W)).suggestName(s"gpio_${i}_${j}") val iocell = p(IOCellKey).gpio().suggestName(s"iocell_gpio_${i}_${j}") iocell.io.o := pin.o.oval iocell.io.oe := pin.o.oe iocell.io.ie := pin.o.ie pin.i.ival := iocell.io.i pin.i.po.foreach(_ := DontCare) iocell.io.pad <> g (GPIOPort(() => g, i, j), iocell) }).unzip }).unzip (ports2d.flatten, cells2d.flatten) } }) class WithGPIOPunchthrough extends OverrideIOBinder({ (system: HasPeripheryGPIO) => { val ports = system.gpio.zipWithIndex.map { case (gpio, i) => val io_gpio = IO(gpio.cloneType).suggestName(s"gpio_$i") io_gpio <> gpio GPIOPinsPort(() => io_gpio, i) } (ports, Nil) } }) class WithI2CPunchthrough extends OverrideIOBinder({ (system: HasPeripheryI2C) => { val ports = system.i2c.zipWithIndex.map { case (i2c, i) => val io_i2c = IO(i2c.cloneType).suggestName(s"i2c_$i") io_i2c <> i2c I2CPort(() => i2c) } (ports, Nil) } }) // DOC include start: WithUARTIOCells class WithUARTIOCells extends OverrideIOBinder({ (system: HasPeripheryUART) => { val (ports: Seq[UARTPort], cells2d) = system.uart.zipWithIndex.map({ case (u, i) => val p = system.asInstanceOf[BaseSubsystem].p val (port, ios) = IOCell.generateIOFromSignal(u, s"uart_${i}", p(IOCellKey), abstractResetAsAsync = true) val where = PBUS // TODO fix val bus = system.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(where) val freqMHz = bus.dtsFrequency.get / 1000000 (UARTPort(() => port, i, freqMHz.toInt), ios) }).unzip (ports, cells2d.flatten) } }) // DOC include end: WithUARTIOCells class WithSPIIOPunchthrough extends OverrideLazyIOBinder({ (system: HasPeripherySPI) => { // attach resource to 1st SPI if (system.tlSpiNodes.size > 0) ResourceBinding { Resource(new MMCDevice(system.tlSpiNodes.head.device, 1), "reg").bind(ResourceAddress(0)) } InModuleBody { val spi = system.spi val ports = spi.zipWithIndex.map({ case (s, i) => val io_spi = IO(s.cloneType).suggestName(s"spi_$i") io_spi <> s SPIPort(() => io_spi) }) (ports, Nil) } } }) class WithSPIFlashIOCells extends OverrideIOBinder({ (system: HasPeripherySPIFlash) => { val (ports: Seq[SPIFlashPort], cells2d) = system.qspi.zipWithIndex.map({ case (s, i) => val p = system.asInstanceOf[BaseSubsystem].p val name = s"spi_${i}" val port = IO(new SPIChipIO(s.c.csWidth)).suggestName(name) val iocellBase = s"iocell_${name}" // SCK and CS are unidirectional outputs val sckIOs = IOCell.generateFromSignal(s.sck, port.sck, Some(s"${iocellBase}_sck"), p(IOCellKey), IOCell.toAsyncReset) val csIOs = IOCell.generateFromSignal(s.cs, port.cs, Some(s"${iocellBase}_cs"), p(IOCellKey), IOCell.toAsyncReset) // DQ are bidirectional, so then need special treatment val dqIOs = s.dq.zip(port.dq).zipWithIndex.map { case ((pin, ana), j) => val iocell = p(IOCellKey).gpio().suggestName(s"${iocellBase}_dq_${j}") iocell.io.o := pin.o iocell.io.oe := pin.oe iocell.io.ie := true.B pin.i := iocell.io.i iocell.io.pad <> ana iocell } (SPIFlashPort(() => port, p(PeripherySPIFlashKey)(i), i), dqIOs ++ csIOs ++ sckIOs) }).unzip (ports, cells2d.flatten) } }) class WithExtInterruptIOCells extends OverrideIOBinder({ (system: HasExtInterruptsModuleImp) => { if (system.outer.nExtInterrupts > 0) { val (port: UInt, cells) = IOCell.generateIOFromSignal(system.interrupts, "ext_interrupts", system.p(IOCellKey), abstractResetAsAsync = true) (Seq(ExtIntPort(() => port)), cells) } else { system.interrupts := DontCare // why do I have to drive this 0-wide wire??? (Nil, Nil) } } }) // Rocketchip's JTAGIO exposes the oe signal, which doesn't go off-chip class JTAGChipIO extends Bundle { val TCK = Input(Clock()) val TMS = Input(Bool()) val TDI = Input(Bool()) val TDO = Output(Bool()) } // WARNING: Don't disable syncReset unless you are trying to // get around bugs in RTL simulators class WithDebugIOCells(syncReset: Boolean = true) extends OverrideLazyIOBinder({ (system: HasPeripheryDebug) => { implicit val p = GetSystemParameters(system) val tlbus = system.asInstanceOf[BaseSubsystem].locateTLBusWrapper(p(ExportDebug).slaveWhere) val clockSinkNode = system.debugOpt.map(_ => ClockSinkNode(Seq(ClockSinkParameters()))) clockSinkNode.map(_ := tlbus.fixedClockNode) def clockBundle = clockSinkNode.get.in.head._1 InModuleBody { system.asInstanceOf[BaseSubsystem] match { case system: HasPeripheryDebug => { system.debug.map({ debug => // We never use the PSDIO, so tie it off on-chip system.psd.psd.foreach { _ <> 0.U.asTypeOf(new PSDTestMode) } system.resetctrl.map { rcio => rcio.hartIsInReset.map { _ := clockBundle.reset.asBool } } system.debug.map { d => // Tie off extTrigger d.extTrigger.foreach { t => t.in.req := false.B t.out.ack := t.out.req } // Tie off disableDebug d.disableDebug.foreach { d => d := false.B } // Drive JTAG on-chip IOs d.systemjtag.map { j => j.reset := (if (syncReset) ResetCatchAndSync(j.jtag.TCK, clockBundle.reset.asBool) else clockBundle.reset.asBool) j.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W) j.part_number := p(JtagDTMKey).idcodePartNum.U(16.W) j.version := p(JtagDTMKey).idcodeVersion.U(4.W) } } Debug.connectDebugClockAndReset(Some(debug), clockBundle.clock) // Add IOCells for the DMI/JTAG/APB ports val dmiTuple = debug.clockeddmi.map { d => val (port, cells) = IOCell.generateIOFromSignal(d, "dmi", p(IOCellKey), abstractResetAsAsync = true) (DMIPort(() => port), cells) } val jtagTuple = debug.systemjtag.map { j => val jtag_wire = Wire(new JTAGChipIO) j.jtag.TCK := jtag_wire.TCK j.jtag.TMS := jtag_wire.TMS j.jtag.TDI := jtag_wire.TDI jtag_wire.TDO := j.jtag.TDO.data val (port, cells) = IOCell.generateIOFromSignal(jtag_wire, "jtag", p(IOCellKey), abstractResetAsAsync = true) (JTAGPort(() => port), cells) } require(!debug.apb.isDefined) val allTuples = (dmiTuple ++ jtagTuple).toSeq (allTuples.map(_._1).toSeq, allTuples.flatMap(_._2).toSeq) }).getOrElse((Nil, Nil)) }}} } }) class WithSerialTLIOCells extends OverrideIOBinder({ (system: CanHavePeripheryTLSerial) => { val (ports, cells) = system.serial_tls.zipWithIndex.map({ case (s, id) => val sys = system.asInstanceOf[BaseSubsystem] val (port, cells) = IOCell.generateIOFromSignal(s.getWrappedValue, s"serial_tl_$id", sys.p(IOCellKey), abstractResetAsAsync = true) (SerialTLPort(() => port, sys.p(SerialTLKey)(id), system.serdessers(id), id), cells) }).unzip (ports.toSeq, cells.flatten.toSeq) } }) class WithChipIdIOCells extends OverrideIOBinder({ (system: CanHavePeripheryChipIdPin) => system.chip_id_pin.map({ p => val sys = system.asInstanceOf[BaseSubsystem] val (port, cells) = IOCell.generateIOFromSignal(p.getWrappedValue, s"chip_id", sys.p(IOCellKey), abstractResetAsAsync = true) (Seq(ChipIdPort(() => port)), cells) }).getOrElse(Nil, Nil) }) class WithSerialTLPunchthrough extends OverrideIOBinder({ (system: CanHavePeripheryTLSerial) => { val (ports, cells) = system.serial_tls.zipWithIndex.map({ case (s, id) => val sys = system.asInstanceOf[BaseSubsystem] val port = IO(chiselTypeOf(s.getWrappedValue)) port <> s.getWrappedValue (SerialTLPort(() => port, sys.p(SerialTLKey)(id), system.serdessers(id), id), Nil) }).unzip (ports.toSeq, cells.flatten.toSeq) } }) class WithAXI4MemPunchthrough extends OverrideLazyIOBinder({ (system: CanHaveMasterAXI4MemPort) => { implicit val p: Parameters = GetSystemParameters(system) val clockSinkNode = p(ExtMem).map(_ => ClockSinkNode(Seq(ClockSinkParameters()))) clockSinkNode.map(_ := system.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(MBUS).fixedClockNode) def clockBundle = clockSinkNode.get.in.head._1 InModuleBody { val ports: Seq[AXI4MemPort] = system.mem_axi4.zipWithIndex.map({ case (m, i) => val port = IO(new ClockedIO(DataMirror.internal.chiselTypeClone[AXI4Bundle](m))).suggestName(s"axi4_mem_${i}") port.bits <> m port.clock := clockBundle.clock AXI4MemPort(() => port, p(ExtMem).get, system.memAXI4Node.edges.in(i), p(MemoryBusKey).dtsFrequency.get.toInt) }).toSeq (ports, Nil) } } }) class WithAXI4MMIOPunchthrough extends OverrideLazyIOBinder({ (system: CanHaveMasterAXI4MMIOPort) => { implicit val p: Parameters = GetSystemParameters(system) val clockSinkNode = p(ExtBus).map(_ => ClockSinkNode(Seq(ClockSinkParameters()))) clockSinkNode.map(_ := system.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(SBUS).fixedClockNode) def clockBundle = clockSinkNode.get.in.head._1 InModuleBody { val ports: Seq[AXI4MMIOPort] = system.mmio_axi4.zipWithIndex.map({ case (m, i) => val port = IO(new ClockedIO(DataMirror.internal.chiselTypeClone[AXI4Bundle](m))).suggestName(s"axi4_mmio_${i}") port.bits <> m port.clock := clockBundle.clock AXI4MMIOPort(() => port, p(ExtBus).get, system.mmioAXI4Node.edges.in(i)) }).toSeq (ports, Nil) } } }) class WithL2FBusAXI4Punchthrough extends OverrideLazyIOBinder({ (system: CanHaveSlaveAXI4Port) => { implicit val p: Parameters = GetSystemParameters(system) val clockSinkNode = p(ExtIn).map(_ => ClockSinkNode(Seq(ClockSinkParameters()))) val fbus = system.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(FBUS) clockSinkNode.map(_ := fbus.fixedClockNode) def clockBundle = clockSinkNode.get.in.head._1 InModuleBody { val ports: Seq[AXI4InPort] = system.l2_frontend_bus_axi4.zipWithIndex.map({ case (m, i) => val port = IO(new ClockedIO(Flipped(DataMirror.internal.chiselTypeClone[AXI4Bundle](m)))).suggestName(s"axi4_fbus_${i}") m <> port.bits port.clock := clockBundle.clock AXI4InPort(() => port, p(ExtIn).get) }).toSeq (ports, Nil) } } }) class WithBlockDeviceIOPunchthrough extends OverrideIOBinder({ (system: CanHavePeripheryBlockDevice) => { val ports: Seq[BlockDevicePort] = system.bdev.map({ bdev => val p = GetSystemParameters(system) val bdParams = p(BlockDeviceKey).get val port = IO(new ClockedIO(new BlockDeviceIO(bdParams))).suggestName("blockdev") port <> bdev BlockDevicePort(() => port, bdParams) }).toSeq (ports, Nil) } }) class WithNICIOPunchthrough extends OverrideIOBinder({ (system: CanHavePeripheryIceNIC) => { val ports: Seq[NICPort] = system.icenicOpt.map({ n => val p = GetSystemParameters(system) val port = IO(new ClockedIO(new NICIOvonly)).suggestName("nic") port <> n NICPort(() => port, p(NICKey).get) }).toSeq (ports, Nil) } }) class WithTraceGenSuccessPunchthrough extends OverrideIOBinder({ (system: TraceGenSystemModuleImp) => { val success: Bool = IO(Output(Bool())).suggestName("success") success := system.success (Seq(SuccessPort(() => success)), Nil) } }) class WithTraceIOPunchthrough extends OverrideLazyIOBinder({ (system: CanHaveTraceIO) => InModuleBody { val ports: Option[TracePort] = system.traceIO.map { t => val trace = IO(DataMirror.internal.chiselTypeClone[TraceOutputTop](t)).suggestName("trace") trace <> t val p = GetSystemParameters(system) val chipyardSystem = system.asInstanceOf[ChipyardSystem] val tiles = chipyardSystem.totalTiles.values val viewpointBus = system.asInstanceOf[HasConfigurableTLNetworkTopology].viewpointBus val mems = viewpointBus.unifyManagers.filter { m => val regionTypes = Seq(RegionType.CACHED, RegionType.TRACKED, RegionType.UNCACHED, RegionType.IDEMPOTENT) val ignoreAddresses = Seq( 0x10000 // bootrom is handled specially ) regionTypes.contains(m.regionType) && !ignoreAddresses.contains(m.address.map(_.base).min) }.map { m => val base = m.address.map(_.base).min val size = m.address.map(_.max).max - base + 1 (base, size) } val useSimDTM = p(ExportDebug).protocols.contains(DMI) // assume that exposing clockeddmi means we will connect SimDTM val cfg = SpikeCosimConfig( isa = tiles.headOption.map(_.isaDTS).getOrElse(""), priv = tiles.headOption.map(t => if (t.usingUser) "MSU" else if (t.usingSupervisor) "MS" else "M").getOrElse(""), maxpglevels = tiles.headOption.map(_.tileParams.core.pgLevels).getOrElse(0), pmpregions = tiles.headOption.map(_.tileParams.core.nPMPs).getOrElse(0), nharts = tiles.size, bootrom = chipyardSystem.bootROM.map(_.module.contents.toArray.mkString(" ")).getOrElse(""), has_dtm = useSimDTM, mems = mems, // Connect using the legacy API for firesim only mem0_base = p(ExtMem).map(_.master.base).getOrElse(BigInt(0)), mem0_size = p(ExtMem).map(_.master.size).getOrElse(BigInt(0)), ) TracePort(() => trace, cfg) } (ports.toSeq, Nil) } }) class WithCustomBootPin extends OverrideIOBinder({ (system: CanHavePeripheryCustomBootPin) => system.custom_boot_pin.map({ p => val sys = system.asInstanceOf[BaseSubsystem] val (port, cells) = IOCell.generateIOFromSignal(p.getWrappedValue, "custom_boot", sys.p(IOCellKey), abstractResetAsAsync = true) (Seq(CustomBootPort(() => port)), cells) }).getOrElse((Nil, Nil)) }) class WithUARTTSIPunchthrough extends OverrideIOBinder({ (system: CanHavePeripheryUARTTSI) => system.uart_tsi.map({ p => val sys = system.asInstanceOf[BaseSubsystem] val uart_tsi = IO(new UARTTSIIO(p.uartParams)) uart_tsi <> p (Seq(UARTTSIPort(() => uart_tsi)), Nil) }).getOrElse((Nil, Nil)) }) class WithTLMemPunchthrough extends OverrideIOBinder({ (system: CanHaveMasterTLMemPort) => { val io_tl_mem_pins_temp = IO(DataMirror.internal.chiselTypeClone[HeterogeneousBag[TLBundle]](system.mem_tl)).suggestName("tl_slave") io_tl_mem_pins_temp <> system.mem_tl (Seq(TLMemPort(() => io_tl_mem_pins_temp)), Nil) } }) class WithDontTouchPorts extends OverrideIOBinder({ (system: DontTouch) => system.dontTouchPorts(); (Nil, Nil) }) class WithNMITiedOff extends ComposeIOBinder({ (system: HasHierarchicalElementsRootContextModuleImp) => { system.nmi.foreach { nmi => nmi.rnmi := false.B nmi.rnmi_interrupt_vector := 0.U nmi.rnmi_exception_vector := 0.U } (Nil, Nil) } }) class WithGCDBusyPunchthrough extends OverrideIOBinder({ (system: CanHavePeripheryGCD) => system.gcd_busy.map { busy => val io_gcd_busy = IO(Output(Bool())) io_gcd_busy := busy (Seq(GCDBusyPort(() => io_gcd_busy)), Nil) }.getOrElse((Nil, Nil)) }) File ClockBinders.scala: package chipyard.clocking import chisel3._ import chisel3.util._ import chipyard.iobinders._ import freechips.rocketchip.prci._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.tilelink._ import chipyard.iocell._ // This uses the FakePLL, which uses a ClockAtFreq Verilog blackbox to generate // the requested clocks. This also adds TileLink ClockDivider and ClockSelector // blocks, which allow memory-mapped control of clock division, and clock muxing // between the FakePLL and the slow off-chip clock // Note: This will not simulate properly with firesim // Unsetting enable will prevent the divider/selector from actually modifying the clock, // while preserving the address map. Unsetting enable should only be done for RTL // simulators (Verilator) which do not model reset properly class WithPLLSelectorDividerClockGenerator(enable: Boolean = true) extends OverrideLazyIOBinder({ (system: HasChipyardPRCI) => { // Connect the implicit clock implicit val p = GetSystemParameters(system) val tlbus = system.asInstanceOf[BaseSubsystem].locateTLBusWrapper(system.prciParams.slaveWhere) val baseAddress = system.prciParams.baseAddress val clockDivider = system.prci_ctrl_domain { LazyModule(new TLClockDivider (baseAddress + 0x20000, tlbus.beatBytes, enable=enable)) } val clockSelector = system.prci_ctrl_domain { LazyModule(new TLClockSelector(baseAddress + 0x30000, tlbus.beatBytes, enable=enable)) } val pllCtrl = system.prci_ctrl_domain { LazyModule(new FakePLLCtrl (baseAddress + 0x40000, tlbus.beatBytes)) } clockDivider.tlNode := system.prci_ctrl_domain { TLFragmenter(tlbus, Some("ClockDivider")) := system.prci_ctrl_bus.get } clockSelector.tlNode := system.prci_ctrl_domain { TLFragmenter(tlbus, Some("ClockSelector")) := system.prci_ctrl_bus.get } pllCtrl.tlNode := system.prci_ctrl_domain { TLFragmenter(tlbus, Some("PLLCtrl")) := system.prci_ctrl_bus.get } system.chiptopClockGroupsNode := clockDivider.clockNode := clockSelector.clockNode // Connect all other requested clocks val slowClockSource = ClockSourceNode(Seq(ClockSourceParameters())) val pllClockSource = ClockSourceNode(Seq(ClockSourceParameters())) // The order of the connections to clockSelector.clockNode configures the inputs // of the clockSelector's clockMux. Default to using the slowClockSource, // software should enable the PLL, then switch to the pllClockSource clockSelector.clockNode := slowClockSource clockSelector.clockNode := pllClockSource val pllCtrlSink = BundleBridgeSink[FakePLLCtrlBundle]() pllCtrlSink := pllCtrl.ctrlNode InModuleBody { val clock_wire = Wire(Input(Clock())) val reset_wire = Wire(Input(AsyncReset())) val (clock_io, clockIOCell) = IOCell.generateIOFromSignal(clock_wire, "clock", p(IOCellKey)) val (reset_io, resetIOCell) = IOCell.generateIOFromSignal(reset_wire, "reset", p(IOCellKey)) slowClockSource.out.unzip._1.map { o => o.clock := clock_wire o.reset := reset_wire } // For a real chip you should replace this ClockSourceAtFreqFromPlusArg // with a blackbox of whatever PLL is being integrated val fake_pll = Module(new ClockSourceAtFreqFromPlusArg("pll_freq_mhz")) fake_pll.io.power := pllCtrlSink.in(0)._1.power fake_pll.io.gate := pllCtrlSink.in(0)._1.gate pllClockSource.out.unzip._1.map { o => o.clock := fake_pll.io.clk o.reset := reset_wire } (Seq(ClockPort(() => clock_io, 100), ResetPort(() => reset_io)), clockIOCell ++ resetIOCell) } } }) // This passes all clocks through to the TestHarness class WithPassthroughClockGenerator extends OverrideLazyIOBinder({ (system: HasChipyardPRCI) => { implicit val p = GetSystemParameters(system) // This aggregate node should do nothing val clockGroupAggNode = ClockGroupAggregateNode("fake") val clockGroupsSourceNode = ClockGroupSourceNode(Seq(ClockGroupSourceParameters())) system.chiptopClockGroupsNode := clockGroupAggNode := clockGroupsSourceNode InModuleBody { val reset_io = IO(Input(AsyncReset())) require(clockGroupAggNode.out.size == 1) val (bundle, edge) = clockGroupAggNode.out(0) val clock_ios = (bundle.member.data zip edge.sink.members).map { case (b, m) => require(m.take.isDefined, s"""Clock ${m.name.get} has no requested frequency |Clocks: ${edge.sink.members.map(_.name.get)}""".stripMargin) val freq = m.take.get.freqMHz val clock_io = IO(Input(Clock())).suggestName(s"clock_${m.name.get}") b.clock := clock_io b.reset := reset_io ClockPort(() => clock_io, freq) }.toSeq ((clock_ios :+ ResetPort(() => reset_io)), Nil) } } }) // Broadcasts a single clock IO to all clock domains. Ignores all requested frequencies class WithSingleClockBroadcastClockGenerator(freqMHz: Int = 100) extends OverrideLazyIOBinder({ (system: HasChipyardPRCI) => { implicit val p = GetSystemParameters(system) val clockGroupsAggregator = LazyModule(new ClockGroupAggregator("single_clock")) val clockGroupsSourceNode = ClockGroupSourceNode(Seq(ClockGroupSourceParameters())) system.chiptopClockGroupsNode :*= clockGroupsAggregator.node := clockGroupsSourceNode InModuleBody { val clock_wire = Wire(Input(Clock())) val reset_wire = Wire(Input(AsyncReset())) val (clock_io, clockIOCell) = IOCell.generateIOFromSignal(clock_wire, "clock", p(IOCellKey)) val (reset_io, resetIOCell) = IOCell.generateIOFromSignal(reset_wire, "reset", p(IOCellKey)) clockGroupsSourceNode.out.foreach { case (bundle, edge) => bundle.member.data.foreach { b => b.clock := clock_io b.reset := reset_io } } (Seq(ClockPort(() => clock_io, freqMHz), ResetPort(() => reset_io)), clockIOCell ++ resetIOCell) } } }) class WithClockTapIOCells extends OverrideIOBinder({ (system: CanHaveClockTap) => { system.clockTapIO.map { tap => val (clock_tap_io, clock_tap_cell) = IOCell.generateIOFromSignal(tap.getWrappedValue, "clock_tap") (Seq(ClockTapPort(() => clock_tap_io)), clock_tap_cell) }.getOrElse((Nil, Nil)) } })
module ChipTop( // @[ChipTop.scala:33:44] input reset_io, // @[ClockBinders.scala:87:24] input clock_uncore, // @[ClockBinders.scala:95:26] output axi4_mem_0_clock, // @[IOBinders.scala:397:22] input axi4_mem_0_bits_aw_ready, // @[IOBinders.scala:397:22] output axi4_mem_0_bits_aw_valid, // @[IOBinders.scala:397:22] output [3:0] axi4_mem_0_bits_aw_bits_id, // @[IOBinders.scala:397:22] output [31:0] axi4_mem_0_bits_aw_bits_addr, // @[IOBinders.scala:397:22] output [7:0] axi4_mem_0_bits_aw_bits_len, // @[IOBinders.scala:397:22] output [2:0] axi4_mem_0_bits_aw_bits_size, // @[IOBinders.scala:397:22] output [1:0] axi4_mem_0_bits_aw_bits_burst, // @[IOBinders.scala:397:22] output axi4_mem_0_bits_aw_bits_lock, // @[IOBinders.scala:397:22] output [3:0] axi4_mem_0_bits_aw_bits_cache, // @[IOBinders.scala:397:22] output [2:0] axi4_mem_0_bits_aw_bits_prot, // @[IOBinders.scala:397:22] output [3:0] axi4_mem_0_bits_aw_bits_qos, // @[IOBinders.scala:397:22] input axi4_mem_0_bits_w_ready, // @[IOBinders.scala:397:22] output axi4_mem_0_bits_w_valid, // @[IOBinders.scala:397:22] output [63:0] axi4_mem_0_bits_w_bits_data, // @[IOBinders.scala:397:22] output [7:0] axi4_mem_0_bits_w_bits_strb, // @[IOBinders.scala:397:22] output axi4_mem_0_bits_w_bits_last, // @[IOBinders.scala:397:22] output axi4_mem_0_bits_b_ready, // @[IOBinders.scala:397:22] input axi4_mem_0_bits_b_valid, // @[IOBinders.scala:397:22] input [3:0] axi4_mem_0_bits_b_bits_id, // @[IOBinders.scala:397:22] input [1:0] axi4_mem_0_bits_b_bits_resp, // @[IOBinders.scala:397:22] input axi4_mem_0_bits_ar_ready, // @[IOBinders.scala:397:22] output axi4_mem_0_bits_ar_valid, // @[IOBinders.scala:397:22] output [3:0] axi4_mem_0_bits_ar_bits_id, // @[IOBinders.scala:397:22] output [31:0] axi4_mem_0_bits_ar_bits_addr, // @[IOBinders.scala:397:22] output [7:0] axi4_mem_0_bits_ar_bits_len, // @[IOBinders.scala:397:22] output [2:0] axi4_mem_0_bits_ar_bits_size, // @[IOBinders.scala:397:22] output [1:0] axi4_mem_0_bits_ar_bits_burst, // @[IOBinders.scala:397:22] output axi4_mem_0_bits_ar_bits_lock, // @[IOBinders.scala:397:22] output [3:0] axi4_mem_0_bits_ar_bits_cache, // @[IOBinders.scala:397:22] output [2:0] axi4_mem_0_bits_ar_bits_prot, // @[IOBinders.scala:397:22] output [3:0] axi4_mem_0_bits_ar_bits_qos, // @[IOBinders.scala:397:22] output axi4_mem_0_bits_r_ready, // @[IOBinders.scala:397:22] input axi4_mem_0_bits_r_valid, // @[IOBinders.scala:397:22] input [3:0] axi4_mem_0_bits_r_bits_id, // @[IOBinders.scala:397:22] input [63:0] axi4_mem_0_bits_r_bits_data, // @[IOBinders.scala:397:22] input [1:0] axi4_mem_0_bits_r_bits_resp, // @[IOBinders.scala:397:22] input axi4_mem_0_bits_r_bits_last, // @[IOBinders.scala:397:22] output success // @[IOBinders.scala:473:27] ); wire axi4_mem_0_bits_aw_ready_0 = axi4_mem_0_bits_aw_ready; // @[ChipTop.scala:33:44] wire axi4_mem_0_bits_w_ready_0 = axi4_mem_0_bits_w_ready; // @[ChipTop.scala:33:44] wire axi4_mem_0_bits_b_valid_0 = axi4_mem_0_bits_b_valid; // @[ChipTop.scala:33:44] wire [3:0] axi4_mem_0_bits_b_bits_id_0 = axi4_mem_0_bits_b_bits_id; // @[ChipTop.scala:33:44] wire [1:0] axi4_mem_0_bits_b_bits_resp_0 = axi4_mem_0_bits_b_bits_resp; // @[ChipTop.scala:33:44] wire axi4_mem_0_bits_ar_ready_0 = axi4_mem_0_bits_ar_ready; // @[ChipTop.scala:33:44] wire axi4_mem_0_bits_r_valid_0 = axi4_mem_0_bits_r_valid; // @[ChipTop.scala:33:44] wire [3:0] axi4_mem_0_bits_r_bits_id_0 = axi4_mem_0_bits_r_bits_id; // @[ChipTop.scala:33:44] wire [63:0] axi4_mem_0_bits_r_bits_data_0 = axi4_mem_0_bits_r_bits_data; // @[ChipTop.scala:33:44] wire [1:0] axi4_mem_0_bits_r_bits_resp_0 = axi4_mem_0_bits_r_bits_resp; // @[ChipTop.scala:33:44] wire axi4_mem_0_bits_r_bits_last_0 = axi4_mem_0_bits_r_bits_last; // @[ChipTop.scala:33:44] wire clockGroupAggNodeOut_member_allClocks_uncore_clock = clock_uncore; // @[MixedNode.scala:542:17] wire clockGroupAggNodeOut_member_allClocks_uncore_reset = reset_io; // @[MixedNode.scala:542:17] wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire clockGroupAggNodeIn_member_fake_uncore_clock = 1'h0; // @[MixedNode.scala:551:17] wire clockGroupAggNodeIn_member_fake_uncore_reset = 1'h0; // @[MixedNode.scala:551:17] wire clockGroupsSourceNodeOut_member_fake_uncore_clock = 1'h0; // @[MixedNode.scala:542:17] wire clockGroupsSourceNodeOut_member_fake_uncore_reset = 1'h0; // @[MixedNode.scala:542:17] wire clockSinkNodeIn_clock; // @[MixedNode.scala:551:17] wire [3:0] axi4_mem_0_bits_aw_bits_id_0; // @[ChipTop.scala:33:44] wire [31:0] axi4_mem_0_bits_aw_bits_addr_0; // @[ChipTop.scala:33:44] wire [7:0] axi4_mem_0_bits_aw_bits_len_0; // @[ChipTop.scala:33:44] wire [2:0] axi4_mem_0_bits_aw_bits_size_0; // @[ChipTop.scala:33:44] wire [1:0] axi4_mem_0_bits_aw_bits_burst_0; // @[ChipTop.scala:33:44] wire axi4_mem_0_bits_aw_bits_lock_0; // @[ChipTop.scala:33:44] wire [3:0] axi4_mem_0_bits_aw_bits_cache_0; // @[ChipTop.scala:33:44] wire [2:0] axi4_mem_0_bits_aw_bits_prot_0; // @[ChipTop.scala:33:44] wire [3:0] axi4_mem_0_bits_aw_bits_qos_0; // @[ChipTop.scala:33:44] wire axi4_mem_0_bits_aw_valid_0; // @[ChipTop.scala:33:44] wire [63:0] axi4_mem_0_bits_w_bits_data_0; // @[ChipTop.scala:33:44] wire [7:0] axi4_mem_0_bits_w_bits_strb_0; // @[ChipTop.scala:33:44] wire axi4_mem_0_bits_w_bits_last_0; // @[ChipTop.scala:33:44] wire axi4_mem_0_bits_w_valid_0; // @[ChipTop.scala:33:44] wire axi4_mem_0_bits_b_ready_0; // @[ChipTop.scala:33:44] wire [3:0] axi4_mem_0_bits_ar_bits_id_0; // @[ChipTop.scala:33:44] wire [31:0] axi4_mem_0_bits_ar_bits_addr_0; // @[ChipTop.scala:33:44] wire [7:0] axi4_mem_0_bits_ar_bits_len_0; // @[ChipTop.scala:33:44] wire [2:0] axi4_mem_0_bits_ar_bits_size_0; // @[ChipTop.scala:33:44] wire [1:0] axi4_mem_0_bits_ar_bits_burst_0; // @[ChipTop.scala:33:44] wire axi4_mem_0_bits_ar_bits_lock_0; // @[ChipTop.scala:33:44] wire [3:0] axi4_mem_0_bits_ar_bits_cache_0; // @[ChipTop.scala:33:44] wire [2:0] axi4_mem_0_bits_ar_bits_prot_0; // @[ChipTop.scala:33:44] wire [3:0] axi4_mem_0_bits_ar_bits_qos_0; // @[ChipTop.scala:33:44] wire axi4_mem_0_bits_ar_valid_0; // @[ChipTop.scala:33:44] wire axi4_mem_0_bits_r_ready_0; // @[ChipTop.scala:33:44] wire axi4_mem_0_clock_0; // @[ChipTop.scala:33:44] wire _success_output; // @[ChipTop.scala:33:44] assign axi4_mem_0_clock_0 = clockSinkNodeIn_clock; // @[MixedNode.scala:551:17] wire clockSinkNodeIn_reset; // @[MixedNode.scala:551:17] TraceGenTop system ( // @[ChipTop.scala:27:35] .auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_clock (clockGroupAggNodeOut_member_allClocks_uncore_clock), // @[MixedNode.scala:542:17] .auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_reset (clockGroupAggNodeOut_member_allClocks_uncore_reset), // @[MixedNode.scala:542:17] .auto_mbus_fixedClockNode_anon_out_clock (clockSinkNodeIn_clock), .auto_mbus_fixedClockNode_anon_out_reset (clockSinkNodeIn_reset), .mem_axi4_0_aw_ready (axi4_mem_0_bits_aw_ready_0), // @[ChipTop.scala:33:44] .mem_axi4_0_aw_valid (axi4_mem_0_bits_aw_valid_0), .mem_axi4_0_aw_bits_id (axi4_mem_0_bits_aw_bits_id_0), .mem_axi4_0_aw_bits_addr (axi4_mem_0_bits_aw_bits_addr_0), .mem_axi4_0_aw_bits_len (axi4_mem_0_bits_aw_bits_len_0), .mem_axi4_0_aw_bits_size (axi4_mem_0_bits_aw_bits_size_0), .mem_axi4_0_aw_bits_burst (axi4_mem_0_bits_aw_bits_burst_0), .mem_axi4_0_aw_bits_lock (axi4_mem_0_bits_aw_bits_lock_0), .mem_axi4_0_aw_bits_cache (axi4_mem_0_bits_aw_bits_cache_0), .mem_axi4_0_aw_bits_prot (axi4_mem_0_bits_aw_bits_prot_0), .mem_axi4_0_aw_bits_qos (axi4_mem_0_bits_aw_bits_qos_0), .mem_axi4_0_w_ready (axi4_mem_0_bits_w_ready_0), // @[ChipTop.scala:33:44] .mem_axi4_0_w_valid (axi4_mem_0_bits_w_valid_0), .mem_axi4_0_w_bits_data (axi4_mem_0_bits_w_bits_data_0), .mem_axi4_0_w_bits_strb (axi4_mem_0_bits_w_bits_strb_0), .mem_axi4_0_w_bits_last (axi4_mem_0_bits_w_bits_last_0), .mem_axi4_0_b_ready (axi4_mem_0_bits_b_ready_0), .mem_axi4_0_b_valid (axi4_mem_0_bits_b_valid_0), // @[ChipTop.scala:33:44] .mem_axi4_0_b_bits_id (axi4_mem_0_bits_b_bits_id_0), // @[ChipTop.scala:33:44] .mem_axi4_0_b_bits_resp (axi4_mem_0_bits_b_bits_resp_0), // @[ChipTop.scala:33:44] .mem_axi4_0_ar_ready (axi4_mem_0_bits_ar_ready_0), // @[ChipTop.scala:33:44] .mem_axi4_0_ar_valid (axi4_mem_0_bits_ar_valid_0), .mem_axi4_0_ar_bits_id (axi4_mem_0_bits_ar_bits_id_0), .mem_axi4_0_ar_bits_addr (axi4_mem_0_bits_ar_bits_addr_0), .mem_axi4_0_ar_bits_len (axi4_mem_0_bits_ar_bits_len_0), .mem_axi4_0_ar_bits_size (axi4_mem_0_bits_ar_bits_size_0), .mem_axi4_0_ar_bits_burst (axi4_mem_0_bits_ar_bits_burst_0), .mem_axi4_0_ar_bits_lock (axi4_mem_0_bits_ar_bits_lock_0), .mem_axi4_0_ar_bits_cache (axi4_mem_0_bits_ar_bits_cache_0), .mem_axi4_0_ar_bits_prot (axi4_mem_0_bits_ar_bits_prot_0), .mem_axi4_0_ar_bits_qos (axi4_mem_0_bits_ar_bits_qos_0), .mem_axi4_0_r_ready (axi4_mem_0_bits_r_ready_0), .mem_axi4_0_r_valid (axi4_mem_0_bits_r_valid_0), // @[ChipTop.scala:33:44] .mem_axi4_0_r_bits_id (axi4_mem_0_bits_r_bits_id_0), // @[ChipTop.scala:33:44] .mem_axi4_0_r_bits_data (axi4_mem_0_bits_r_bits_data_0), // @[ChipTop.scala:33:44] .mem_axi4_0_r_bits_resp (axi4_mem_0_bits_r_bits_resp_0), // @[ChipTop.scala:33:44] .mem_axi4_0_r_bits_last (axi4_mem_0_bits_r_bits_last_0), // @[ChipTop.scala:33:44] .success (_success_output) ); // @[ChipTop.scala:27:35] assign axi4_mem_0_clock = axi4_mem_0_clock_0; // @[ChipTop.scala:33:44] assign axi4_mem_0_bits_aw_valid = axi4_mem_0_bits_aw_valid_0; // @[ChipTop.scala:33:44] assign axi4_mem_0_bits_aw_bits_id = axi4_mem_0_bits_aw_bits_id_0; // @[ChipTop.scala:33:44] assign axi4_mem_0_bits_aw_bits_addr = axi4_mem_0_bits_aw_bits_addr_0; // @[ChipTop.scala:33:44] assign axi4_mem_0_bits_aw_bits_len = axi4_mem_0_bits_aw_bits_len_0; // @[ChipTop.scala:33:44] assign axi4_mem_0_bits_aw_bits_size = axi4_mem_0_bits_aw_bits_size_0; // @[ChipTop.scala:33:44] assign axi4_mem_0_bits_aw_bits_burst = axi4_mem_0_bits_aw_bits_burst_0; // @[ChipTop.scala:33:44] assign axi4_mem_0_bits_aw_bits_lock = axi4_mem_0_bits_aw_bits_lock_0; // @[ChipTop.scala:33:44] assign axi4_mem_0_bits_aw_bits_cache = axi4_mem_0_bits_aw_bits_cache_0; // @[ChipTop.scala:33:44] assign axi4_mem_0_bits_aw_bits_prot = axi4_mem_0_bits_aw_bits_prot_0; // @[ChipTop.scala:33:44] assign axi4_mem_0_bits_aw_bits_qos = axi4_mem_0_bits_aw_bits_qos_0; // @[ChipTop.scala:33:44] assign axi4_mem_0_bits_w_valid = axi4_mem_0_bits_w_valid_0; // @[ChipTop.scala:33:44] assign axi4_mem_0_bits_w_bits_data = axi4_mem_0_bits_w_bits_data_0; // @[ChipTop.scala:33:44] assign axi4_mem_0_bits_w_bits_strb = axi4_mem_0_bits_w_bits_strb_0; // @[ChipTop.scala:33:44] assign axi4_mem_0_bits_w_bits_last = axi4_mem_0_bits_w_bits_last_0; // @[ChipTop.scala:33:44] assign axi4_mem_0_bits_b_ready = axi4_mem_0_bits_b_ready_0; // @[ChipTop.scala:33:44] assign axi4_mem_0_bits_ar_valid = axi4_mem_0_bits_ar_valid_0; // @[ChipTop.scala:33:44] assign axi4_mem_0_bits_ar_bits_id = axi4_mem_0_bits_ar_bits_id_0; // @[ChipTop.scala:33:44] assign axi4_mem_0_bits_ar_bits_addr = axi4_mem_0_bits_ar_bits_addr_0; // @[ChipTop.scala:33:44] assign axi4_mem_0_bits_ar_bits_len = axi4_mem_0_bits_ar_bits_len_0; // @[ChipTop.scala:33:44] assign axi4_mem_0_bits_ar_bits_size = axi4_mem_0_bits_ar_bits_size_0; // @[ChipTop.scala:33:44] assign axi4_mem_0_bits_ar_bits_burst = axi4_mem_0_bits_ar_bits_burst_0; // @[ChipTop.scala:33:44] assign axi4_mem_0_bits_ar_bits_lock = axi4_mem_0_bits_ar_bits_lock_0; // @[ChipTop.scala:33:44] assign axi4_mem_0_bits_ar_bits_cache = axi4_mem_0_bits_ar_bits_cache_0; // @[ChipTop.scala:33:44] assign axi4_mem_0_bits_ar_bits_prot = axi4_mem_0_bits_ar_bits_prot_0; // @[ChipTop.scala:33:44] assign axi4_mem_0_bits_ar_bits_qos = axi4_mem_0_bits_ar_bits_qos_0; // @[ChipTop.scala:33:44] assign axi4_mem_0_bits_r_ready = axi4_mem_0_bits_r_ready_0; // @[ChipTop.scala:33:44] assign success = _success_output; // @[ChipTop.scala:33:44] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ :*=* _) .getOrElse(TLNameNode("no_buffer")) } } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }
module TLBuffer_a32d64s1k3z4c_1( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_b_ready, // @[LazyModuleImp.scala:107:25] output auto_in_b_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_b_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_b_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_b_bits_size, // @[LazyModuleImp.scala:107:25] output auto_in_b_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_b_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_in_b_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_b_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_c_ready, // @[LazyModuleImp.scala:107:25] input auto_in_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_c_bits_size, // @[LazyModuleImp.scala:107:25] input auto_in_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_c_bits_address, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_e_ready, // @[LazyModuleImp.scala:107:25] input auto_in_e_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_out_b_valid, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input auto_out_b_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input auto_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output auto_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_e_ready, // @[LazyModuleImp.scala:107:25] output auto_out_e_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_e_bits_sink // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_b_ready_0 = auto_in_b_ready; // @[Buffer.scala:40:9] wire auto_in_c_valid_0 = auto_in_c_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_c_bits_opcode_0 = auto_in_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_c_bits_param_0 = auto_in_c_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_c_bits_size_0 = auto_in_c_bits_size; // @[Buffer.scala:40:9] wire auto_in_c_bits_source_0 = auto_in_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_c_bits_address_0 = auto_in_c_bits_address; // @[Buffer.scala:40:9] wire [63:0] auto_in_c_bits_data_0 = auto_in_c_bits_data; // @[Buffer.scala:40:9] wire auto_in_c_bits_corrupt_0 = auto_in_c_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_in_e_valid_0 = auto_in_e_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_e_bits_sink_0 = auto_in_e_bits_sink; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_b_valid_0 = auto_out_b_valid; // @[Buffer.scala:40:9] wire [1:0] auto_out_b_bits_param_0 = auto_out_b_bits_param; // @[Buffer.scala:40:9] wire auto_out_b_bits_source_0 = auto_out_b_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_out_b_bits_address_0 = auto_out_b_bits_address; // @[Buffer.scala:40:9] wire auto_out_c_ready_0 = auto_out_c_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire auto_out_e_ready_0 = auto_out_e_ready; // @[Buffer.scala:40:9] wire auto_out_b_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeOut_b_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire [63:0] auto_out_b_bits_data = 64'h0; // @[Decoupled.scala:362:21] wire [63:0] nodeOut_b_bits_data = 64'h0; // @[Decoupled.scala:362:21] wire [7:0] auto_out_b_bits_mask = 8'hFF; // @[Decoupled.scala:362:21] wire [7:0] nodeOut_b_bits_mask = 8'hFF; // @[Decoupled.scala:362:21] wire [3:0] auto_out_b_bits_size = 4'h6; // @[Decoupled.scala:362:21] wire [3:0] nodeOut_b_bits_size = 4'h6; // @[Decoupled.scala:362:21] wire [2:0] auto_out_b_bits_opcode = 3'h6; // @[Decoupled.scala:362:21] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [2:0] nodeOut_b_bits_opcode = 3'h6; // @[Decoupled.scala:362:21] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_b_ready = auto_in_b_ready_0; // @[Buffer.scala:40:9] wire nodeIn_b_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_b_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_b_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_b_bits_size; // @[MixedNode.scala:551:17] wire nodeIn_b_bits_source; // @[MixedNode.scala:551:17] wire [31:0] nodeIn_b_bits_address; // @[MixedNode.scala:551:17] wire [7:0] nodeIn_b_bits_mask; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_b_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_b_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_c_ready; // @[MixedNode.scala:551:17] wire nodeIn_c_valid = auto_in_c_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_c_bits_opcode = auto_in_c_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_c_bits_param = auto_in_c_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_c_bits_size = auto_in_c_bits_size_0; // @[Buffer.scala:40:9] wire nodeIn_c_bits_source = auto_in_c_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_c_bits_address = auto_in_c_bits_address_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_c_bits_data = auto_in_c_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_c_bits_corrupt = auto_in_c_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_e_ready; // @[MixedNode.scala:551:17] wire nodeIn_e_valid = auto_in_e_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_e_bits_sink = auto_in_e_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_b_ready; // @[MixedNode.scala:542:17] wire nodeOut_b_valid = auto_out_b_valid_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_b_bits_param = auto_out_b_bits_param_0; // @[Buffer.scala:40:9] wire nodeOut_b_bits_source = auto_out_b_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeOut_b_bits_address = auto_out_b_bits_address_0; // @[Buffer.scala:40:9] wire nodeOut_c_ready = auto_out_c_ready_0; // @[Buffer.scala:40:9] wire nodeOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_c_bits_size; // @[MixedNode.scala:542:17] wire nodeOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_c_bits_address; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_c_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_c_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeOut_e_ready = auto_out_e_ready_0; // @[Buffer.scala:40:9] wire nodeOut_e_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_e_bits_sink; // @[MixedNode.scala:542:17] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_b_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_b_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_b_bits_size_0; // @[Buffer.scala:40:9] wire auto_in_b_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_in_b_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_in_b_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_b_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_b_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_b_valid_0; // @[Buffer.scala:40:9] wire auto_in_c_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire auto_in_e_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_b_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_c_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_c_bits_size_0; // @[Buffer.scala:40:9] wire auto_out_c_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_c_bits_address_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_c_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_c_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_e_bits_sink_0; // @[Buffer.scala:40:9] wire auto_out_e_valid_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_b_valid_0 = nodeIn_b_valid; // @[Buffer.scala:40:9] assign auto_in_b_bits_opcode_0 = nodeIn_b_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_b_bits_param_0 = nodeIn_b_bits_param; // @[Buffer.scala:40:9] assign auto_in_b_bits_size_0 = nodeIn_b_bits_size; // @[Buffer.scala:40:9] assign auto_in_b_bits_source_0 = nodeIn_b_bits_source; // @[Buffer.scala:40:9] assign auto_in_b_bits_address_0 = nodeIn_b_bits_address; // @[Buffer.scala:40:9] assign auto_in_b_bits_mask_0 = nodeIn_b_bits_mask; // @[Buffer.scala:40:9] assign auto_in_b_bits_data_0 = nodeIn_b_bits_data; // @[Buffer.scala:40:9] assign auto_in_b_bits_corrupt_0 = nodeIn_b_bits_corrupt; // @[Buffer.scala:40:9] assign auto_in_c_ready_0 = nodeIn_c_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_in_e_ready_0 = nodeIn_e_ready; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_b_ready_0 = nodeOut_b_ready; // @[Buffer.scala:40:9] assign auto_out_c_valid_0 = nodeOut_c_valid; // @[Buffer.scala:40:9] assign auto_out_c_bits_opcode_0 = nodeOut_c_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_c_bits_param_0 = nodeOut_c_bits_param; // @[Buffer.scala:40:9] assign auto_out_c_bits_size_0 = nodeOut_c_bits_size; // @[Buffer.scala:40:9] assign auto_out_c_bits_source_0 = nodeOut_c_bits_source; // @[Buffer.scala:40:9] assign auto_out_c_bits_address_0 = nodeOut_c_bits_address; // @[Buffer.scala:40:9] assign auto_out_c_bits_data_0 = nodeOut_c_bits_data; // @[Buffer.scala:40:9] assign auto_out_c_bits_corrupt_0 = nodeOut_c_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] assign auto_out_e_valid_0 = nodeOut_e_valid; // @[Buffer.scala:40:9] assign auto_out_e_bits_sink_0 = nodeOut_e_bits_sink; // @[Buffer.scala:40:9] TLMonitor_8 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_b_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17] .io_in_b_valid (nodeIn_b_valid), // @[MixedNode.scala:551:17] .io_in_b_bits_opcode (nodeIn_b_bits_opcode), // @[MixedNode.scala:551:17] .io_in_b_bits_param (nodeIn_b_bits_param), // @[MixedNode.scala:551:17] .io_in_b_bits_size (nodeIn_b_bits_size), // @[MixedNode.scala:551:17] .io_in_b_bits_source (nodeIn_b_bits_source), // @[MixedNode.scala:551:17] .io_in_b_bits_address (nodeIn_b_bits_address), // @[MixedNode.scala:551:17] .io_in_b_bits_mask (nodeIn_b_bits_mask), // @[MixedNode.scala:551:17] .io_in_b_bits_data (nodeIn_b_bits_data), // @[MixedNode.scala:551:17] .io_in_b_bits_corrupt (nodeIn_b_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_c_ready (nodeIn_c_ready), // @[MixedNode.scala:551:17] .io_in_c_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17] .io_in_c_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17] .io_in_c_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17] .io_in_c_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17] .io_in_c_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17] .io_in_c_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17] .io_in_c_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17] .io_in_c_bits_corrupt (nodeIn_c_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_e_ready (nodeIn_e_ready), // @[MixedNode.scala:551:17] .io_in_e_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17] .io_in_e_bits_sink (nodeIn_e_bits_sink) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a32d64s1k3z4c_1 nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d64s1k3z4c_1 nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleB_a32d64s1k3z4c_1 nodeIn_b_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_b_ready), .io_enq_valid (nodeOut_b_valid), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_b_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_b_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_address (nodeOut_b_bits_address), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_b_valid), .io_deq_bits_opcode (nodeIn_b_bits_opcode), .io_deq_bits_param (nodeIn_b_bits_param), .io_deq_bits_size (nodeIn_b_bits_size), .io_deq_bits_source (nodeIn_b_bits_source), .io_deq_bits_address (nodeIn_b_bits_address), .io_deq_bits_mask (nodeIn_b_bits_mask), .io_deq_bits_data (nodeIn_b_bits_data), .io_deq_bits_corrupt (nodeIn_b_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleC_a32d64s1k3z4c_1 nodeOut_c_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_c_ready), .io_enq_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_c_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_c_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_c_valid), .io_deq_bits_opcode (nodeOut_c_bits_opcode), .io_deq_bits_param (nodeOut_c_bits_param), .io_deq_bits_size (nodeOut_c_bits_size), .io_deq_bits_source (nodeOut_c_bits_source), .io_deq_bits_address (nodeOut_c_bits_address), .io_deq_bits_data (nodeOut_c_bits_data), .io_deq_bits_corrupt (nodeOut_c_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleE_a32d64s1k3z4c_1 nodeOut_e_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_e_ready), .io_enq_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17] .io_enq_bits_sink (nodeIn_e_bits_sink), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_e_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_e_valid), .io_deq_bits_sink (nodeOut_e_bits_sink) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_b_valid = auto_in_b_valid_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_opcode = auto_in_b_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_param = auto_in_b_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_size = auto_in_b_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_source = auto_in_b_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_address = auto_in_b_bits_address_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_mask = auto_in_b_bits_mask_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_data = auto_in_b_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_corrupt = auto_in_b_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_in_c_ready = auto_in_c_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_in_e_ready = auto_in_e_ready_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_b_ready = auto_out_b_ready_0; // @[Buffer.scala:40:9] assign auto_out_c_valid = auto_out_c_valid_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_opcode = auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_param = auto_out_c_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_size = auto_out_c_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_source = auto_out_c_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_address = auto_out_c_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_data = auto_out_c_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_corrupt = auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_out_e_valid = auto_out_e_valid_0; // @[Buffer.scala:40:9] assign auto_out_e_bits_sink = auto_out_e_bits_sink_0; // @[Buffer.scala:40:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File MSHR.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import freechips.rocketchip.tilelink._ import TLPermissions._ import TLMessages._ import MetaData._ import chisel3.PrintableHelper import chisel3.experimental.dataview._ class ScheduleRequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val a = Valid(new SourceARequest(params)) val b = Valid(new SourceBRequest(params)) val c = Valid(new SourceCRequest(params)) val d = Valid(new SourceDRequest(params)) val e = Valid(new SourceERequest(params)) val x = Valid(new SourceXRequest(params)) val dir = Valid(new DirectoryWrite(params)) val reload = Bool() // get next request via allocate (if any) } class MSHRStatus(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val set = UInt(params.setBits.W) val tag = UInt(params.tagBits.W) val way = UInt(params.wayBits.W) val blockB = Bool() val nestB = Bool() val blockC = Bool() val nestC = Bool() } class NestedWriteback(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val set = UInt(params.setBits.W) val tag = UInt(params.tagBits.W) val b_toN = Bool() // nested Probes may unhit us val b_toB = Bool() // nested Probes may demote us val b_clr_dirty = Bool() // nested Probes clear dirty val c_set_dirty = Bool() // nested Releases MAY set dirty } sealed trait CacheState { val code = CacheState.index.U CacheState.index = CacheState.index + 1 } object CacheState { var index = 0 } case object S_INVALID extends CacheState case object S_BRANCH extends CacheState case object S_BRANCH_C extends CacheState case object S_TIP extends CacheState case object S_TIP_C extends CacheState case object S_TIP_CD extends CacheState case object S_TIP_D extends CacheState case object S_TRUNK_C extends CacheState case object S_TRUNK_CD extends CacheState class MSHR(params: InclusiveCacheParameters) extends Module { val io = IO(new Bundle { val allocate = Flipped(Valid(new AllocateRequest(params))) // refills MSHR for next cycle val directory = Flipped(Valid(new DirectoryResult(params))) // triggers schedule setup val status = Valid(new MSHRStatus(params)) val schedule = Decoupled(new ScheduleRequest(params)) val sinkc = Flipped(Valid(new SinkCResponse(params))) val sinkd = Flipped(Valid(new SinkDResponse(params))) val sinke = Flipped(Valid(new SinkEResponse(params))) val nestedwb = Flipped(new NestedWriteback(params)) }) val request_valid = RegInit(false.B) val request = Reg(new FullRequest(params)) val meta_valid = RegInit(false.B) val meta = Reg(new DirectoryResult(params)) // Define which states are valid when (meta_valid) { when (meta.state === INVALID) { assert (!meta.clients.orR) assert (!meta.dirty) } when (meta.state === BRANCH) { assert (!meta.dirty) } when (meta.state === TRUNK) { assert (meta.clients.orR) assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one } when (meta.state === TIP) { // noop } } // Completed transitions (s_ = scheduled), (w_ = waiting) val s_rprobe = RegInit(true.B) // B val w_rprobeackfirst = RegInit(true.B) val w_rprobeacklast = RegInit(true.B) val s_release = RegInit(true.B) // CW w_rprobeackfirst val w_releaseack = RegInit(true.B) val s_pprobe = RegInit(true.B) // B val s_acquire = RegInit(true.B) // A s_release, s_pprobe [1] val s_flush = RegInit(true.B) // X w_releaseack val w_grantfirst = RegInit(true.B) val w_grantlast = RegInit(true.B) val w_grant = RegInit(true.B) // first | last depending on wormhole val w_pprobeackfirst = RegInit(true.B) val w_pprobeacklast = RegInit(true.B) val w_pprobeack = RegInit(true.B) // first | last depending on wormhole val s_probeack = RegInit(true.B) // C w_pprobeackfirst (mutually exclusive with next two s_*) val s_grantack = RegInit(true.B) // E w_grantfirst ... CAN require both outE&inD to service outD val s_execute = RegInit(true.B) // D w_pprobeack, w_grant val w_grantack = RegInit(true.B) val s_writeback = RegInit(true.B) // W w_* // [1]: We cannot issue outer Acquire while holding blockB (=> outA can stall) // However, inB and outC are higher priority than outB, so s_release and s_pprobe // may be safely issued while blockB. Thus we must NOT try to schedule the // potentially stuck s_acquire with either of them (scheduler is all or none). // Meta-data that we discover underway val sink = Reg(UInt(params.outer.bundle.sinkBits.W)) val gotT = Reg(Bool()) val bad_grant = Reg(Bool()) val probes_done = Reg(UInt(params.clientBits.W)) val probes_toN = Reg(UInt(params.clientBits.W)) val probes_noT = Reg(Bool()) // When a nested transaction completes, update our meta data when (meta_valid && meta.state =/= INVALID && io.nestedwb.set === request.set && io.nestedwb.tag === meta.tag) { when (io.nestedwb.b_clr_dirty) { meta.dirty := false.B } when (io.nestedwb.c_set_dirty) { meta.dirty := true.B } when (io.nestedwb.b_toB) { meta.state := BRANCH } when (io.nestedwb.b_toN) { meta.hit := false.B } } // Scheduler status io.status.valid := request_valid io.status.bits.set := request.set io.status.bits.tag := request.tag io.status.bits.way := meta.way io.status.bits.blockB := !meta_valid || ((!w_releaseack || !w_rprobeacklast || !w_pprobeacklast) && !w_grantfirst) io.status.bits.nestB := meta_valid && w_releaseack && w_rprobeacklast && w_pprobeacklast && !w_grantfirst // The above rules ensure we will block and not nest an outer probe while still doing our // own inner probes. Thus every probe wakes exactly one MSHR. io.status.bits.blockC := !meta_valid io.status.bits.nestC := meta_valid && (!w_rprobeackfirst || !w_pprobeackfirst || !w_grantfirst) // The w_grantfirst in nestC is necessary to deal with: // acquire waiting for grant, inner release gets queued, outer probe -> inner probe -> deadlock // ... this is possible because the release+probe can be for same set, but different tag // We can only demand: block, nest, or queue assert (!io.status.bits.nestB || !io.status.bits.blockB) assert (!io.status.bits.nestC || !io.status.bits.blockC) // Scheduler requests val no_wait = w_rprobeacklast && w_releaseack && w_grantlast && w_pprobeacklast && w_grantack io.schedule.bits.a.valid := !s_acquire && s_release && s_pprobe io.schedule.bits.b.valid := !s_rprobe || !s_pprobe io.schedule.bits.c.valid := (!s_release && w_rprobeackfirst) || (!s_probeack && w_pprobeackfirst) io.schedule.bits.d.valid := !s_execute && w_pprobeack && w_grant io.schedule.bits.e.valid := !s_grantack && w_grantfirst io.schedule.bits.x.valid := !s_flush && w_releaseack io.schedule.bits.dir.valid := (!s_release && w_rprobeackfirst) || (!s_writeback && no_wait) io.schedule.bits.reload := no_wait io.schedule.valid := io.schedule.bits.a.valid || io.schedule.bits.b.valid || io.schedule.bits.c.valid || io.schedule.bits.d.valid || io.schedule.bits.e.valid || io.schedule.bits.x.valid || io.schedule.bits.dir.valid // Schedule completions when (io.schedule.ready) { s_rprobe := true.B when (w_rprobeackfirst) { s_release := true.B } s_pprobe := true.B when (s_release && s_pprobe) { s_acquire := true.B } when (w_releaseack) { s_flush := true.B } when (w_pprobeackfirst) { s_probeack := true.B } when (w_grantfirst) { s_grantack := true.B } when (w_pprobeack && w_grant) { s_execute := true.B } when (no_wait) { s_writeback := true.B } // Await the next operation when (no_wait) { request_valid := false.B meta_valid := false.B } } // Resulting meta-data val final_meta_writeback = WireInit(meta) val req_clientBit = params.clientBit(request.source) val req_needT = needT(request.opcode, request.param) val req_acquire = request.opcode === AcquireBlock || request.opcode === AcquirePerm val meta_no_clients = !meta.clients.orR val req_promoteT = req_acquire && Mux(meta.hit, meta_no_clients && meta.state === TIP, gotT) when (request.prio(2) && (!params.firstLevel).B) { // always a hit final_meta_writeback.dirty := meta.dirty || request.opcode(0) final_meta_writeback.state := Mux(request.param =/= TtoT && meta.state === TRUNK, TIP, meta.state) final_meta_writeback.clients := meta.clients & ~Mux(isToN(request.param), req_clientBit, 0.U) final_meta_writeback.hit := true.B // chained requests are hits } .elsewhen (request.control && params.control.B) { // request.prio(0) when (meta.hit) { final_meta_writeback.dirty := false.B final_meta_writeback.state := INVALID final_meta_writeback.clients := meta.clients & ~probes_toN } final_meta_writeback.hit := false.B } .otherwise { final_meta_writeback.dirty := (meta.hit && meta.dirty) || !request.opcode(2) final_meta_writeback.state := Mux(req_needT, Mux(req_acquire, TRUNK, TIP), Mux(!meta.hit, Mux(gotT, Mux(req_acquire, TRUNK, TIP), BRANCH), MuxLookup(meta.state, 0.U(2.W))(Seq( INVALID -> BRANCH, BRANCH -> BRANCH, TRUNK -> TIP, TIP -> Mux(meta_no_clients && req_acquire, TRUNK, TIP))))) final_meta_writeback.clients := Mux(meta.hit, meta.clients & ~probes_toN, 0.U) | Mux(req_acquire, req_clientBit, 0.U) final_meta_writeback.tag := request.tag final_meta_writeback.hit := true.B } when (bad_grant) { when (meta.hit) { // upgrade failed (B -> T) assert (!meta_valid || meta.state === BRANCH) final_meta_writeback.hit := true.B final_meta_writeback.dirty := false.B final_meta_writeback.state := BRANCH final_meta_writeback.clients := meta.clients & ~probes_toN } .otherwise { // failed N -> (T or B) final_meta_writeback.hit := false.B final_meta_writeback.dirty := false.B final_meta_writeback.state := INVALID final_meta_writeback.clients := 0.U } } val invalid = Wire(new DirectoryEntry(params)) invalid.dirty := false.B invalid.state := INVALID invalid.clients := 0.U invalid.tag := 0.U // Just because a client says BtoT, by the time we process the request he may be N. // Therefore, we must consult our own meta-data state to confirm he owns the line still. val honour_BtoT = meta.hit && (meta.clients & req_clientBit).orR // The client asking us to act is proof they don't have permissions. val excluded_client = Mux(meta.hit && request.prio(0) && skipProbeN(request.opcode, params.cache.hintsSkipProbe), req_clientBit, 0.U) io.schedule.bits.a.bits.tag := request.tag io.schedule.bits.a.bits.set := request.set io.schedule.bits.a.bits.param := Mux(req_needT, Mux(meta.hit, BtoT, NtoT), NtoB) io.schedule.bits.a.bits.block := request.size =/= log2Ceil(params.cache.blockBytes).U || !(request.opcode === PutFullData || request.opcode === AcquirePerm) io.schedule.bits.a.bits.source := 0.U io.schedule.bits.b.bits.param := Mux(!s_rprobe, toN, Mux(request.prio(1), request.param, Mux(req_needT, toN, toB))) io.schedule.bits.b.bits.tag := Mux(!s_rprobe, meta.tag, request.tag) io.schedule.bits.b.bits.set := request.set io.schedule.bits.b.bits.clients := meta.clients & ~excluded_client io.schedule.bits.c.bits.opcode := Mux(meta.dirty, ReleaseData, Release) io.schedule.bits.c.bits.param := Mux(meta.state === BRANCH, BtoN, TtoN) io.schedule.bits.c.bits.source := 0.U io.schedule.bits.c.bits.tag := meta.tag io.schedule.bits.c.bits.set := request.set io.schedule.bits.c.bits.way := meta.way io.schedule.bits.c.bits.dirty := meta.dirty io.schedule.bits.d.bits.viewAsSupertype(chiselTypeOf(request)) := request io.schedule.bits.d.bits.param := Mux(!req_acquire, request.param, MuxLookup(request.param, request.param)(Seq( NtoB -> Mux(req_promoteT, NtoT, NtoB), BtoT -> Mux(honour_BtoT, BtoT, NtoT), NtoT -> NtoT))) io.schedule.bits.d.bits.sink := 0.U io.schedule.bits.d.bits.way := meta.way io.schedule.bits.d.bits.bad := bad_grant io.schedule.bits.e.bits.sink := sink io.schedule.bits.x.bits.fail := false.B io.schedule.bits.dir.bits.set := request.set io.schedule.bits.dir.bits.way := meta.way io.schedule.bits.dir.bits.data := Mux(!s_release, invalid, WireInit(new DirectoryEntry(params), init = final_meta_writeback)) // Coverage of state transitions def cacheState(entry: DirectoryEntry, hit: Bool) = { val out = WireDefault(0.U) val c = entry.clients.orR val d = entry.dirty switch (entry.state) { is (BRANCH) { out := Mux(c, S_BRANCH_C.code, S_BRANCH.code) } is (TRUNK) { out := Mux(d, S_TRUNK_CD.code, S_TRUNK_C.code) } is (TIP) { out := Mux(c, Mux(d, S_TIP_CD.code, S_TIP_C.code), Mux(d, S_TIP_D.code, S_TIP.code)) } is (INVALID) { out := S_INVALID.code } } when (!hit) { out := S_INVALID.code } out } val p = !params.lastLevel // can be probed val c = !params.firstLevel // can be acquired val m = params.inner.client.clients.exists(!_.supports.probe) // can be written (or read) val r = params.outer.manager.managers.exists(!_.alwaysGrantsT) // read-only devices exist val f = params.control // flush control register exists val cfg = (p, c, m, r, f) val b = r || p // can reach branch state (via probe downgrade or read-only device) // The cache must be used for something or we would not be here require(c || m) val evict = cacheState(meta, !meta.hit) val before = cacheState(meta, meta.hit) val after = cacheState(final_meta_writeback, true.B) def eviction(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(evict === from.code, s"MSHR_${from}_EVICT", s"State transition from ${from} to evicted ${cfg}") } else { assert(!(evict === from.code), cf"State transition from ${from} to evicted should be impossible ${cfg}") } if (cover && f) { params.ccover(before === from.code, s"MSHR_${from}_FLUSH", s"State transition from ${from} to flushed ${cfg}") } else { assert(!(before === from.code), cf"State transition from ${from} to flushed should be impossible ${cfg}") } } def transition(from: CacheState, to: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(before === from.code && after === to.code, s"MSHR_${from}_${to}", s"State transition from ${from} to ${to} ${cfg}") } else { assert(!(before === from.code && after === to.code), cf"State transition from ${from} to ${to} should be impossible ${cfg}") } } when ((!s_release && w_rprobeackfirst) && io.schedule.ready) { eviction(S_BRANCH, b) // MMIO read to read-only device eviction(S_BRANCH_C, b && c) // you need children to become C eviction(S_TIP, true) // MMIO read || clean release can lead to this state eviction(S_TIP_C, c) // needs two clients || client + mmio || downgrading client eviction(S_TIP_CD, c) // needs two clients || client + mmio || downgrading client eviction(S_TIP_D, true) // MMIO write || dirty release lead here eviction(S_TRUNK_C, c) // acquire for write eviction(S_TRUNK_CD, c) // dirty release then reacquire } when ((!s_writeback && no_wait) && io.schedule.ready) { transition(S_INVALID, S_BRANCH, b && m) // only MMIO can bring us to BRANCH state transition(S_INVALID, S_BRANCH_C, b && c) // C state is only possible if there are inner caches transition(S_INVALID, S_TIP, m) // MMIO read transition(S_INVALID, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_INVALID, S_TIP_CD, false) // acquire does not cause dirty immediately transition(S_INVALID, S_TIP_D, m) // MMIO write transition(S_INVALID, S_TRUNK_C, c) // acquire transition(S_INVALID, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH, S_INVALID, b && p) // probe can do this (flushes run as evictions) transition(S_BRANCH, S_BRANCH_C, b && c) // acquire transition(S_BRANCH, S_TIP, b && m) // prefetch write transition(S_BRANCH, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_BRANCH, S_TIP_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH, S_TIP_D, b && m) // MMIO write transition(S_BRANCH, S_TRUNK_C, b && c) // acquire transition(S_BRANCH, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH_C, S_INVALID, b && c && p) transition(S_BRANCH_C, S_BRANCH, b && c) // clean release (optional) transition(S_BRANCH_C, S_TIP, b && c && m) // prefetch write transition(S_BRANCH_C, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_BRANCH_C, S_TIP_D, b && c && m) // MMIO write transition(S_BRANCH_C, S_TIP_CD, false) // going dirty means we must shoot down clients transition(S_BRANCH_C, S_TRUNK_C, b && c) // acquire transition(S_BRANCH_C, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_TIP, S_INVALID, p) transition(S_TIP, S_BRANCH, p) // losing TIP only possible via probe transition(S_TIP, S_BRANCH_C, false) // we would go S_TRUNK_C instead transition(S_TIP, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP, S_TIP_D, m) // direct dirty only via MMIO write transition(S_TIP, S_TIP_CD, false) // acquire does not make us dirty immediately transition(S_TIP, S_TRUNK_C, c) // acquire transition(S_TIP, S_TRUNK_CD, false) // acquire does not make us dirty immediately transition(S_TIP_C, S_INVALID, c && p) transition(S_TIP_C, S_BRANCH, c && p) // losing TIP only possible via probe transition(S_TIP_C, S_BRANCH_C, c && p) // losing TIP only possible via probe transition(S_TIP_C, S_TIP, c) // probed while MMIO read || clean release (optional) transition(S_TIP_C, S_TIP_D, c && m) // direct dirty only via MMIO write transition(S_TIP_C, S_TIP_CD, false) // going dirty means we must shoot down clients transition(S_TIP_C, S_TRUNK_C, c) // acquire transition(S_TIP_C, S_TRUNK_CD, false) // acquire does not make us immediately dirty transition(S_TIP_D, S_INVALID, p) transition(S_TIP_D, S_BRANCH, p) // losing D is only possible via probe transition(S_TIP_D, S_BRANCH_C, p && c) // probed while acquire shared transition(S_TIP_D, S_TIP, p) // probed while MMIO read || outer probe.toT (optional) transition(S_TIP_D, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP_D, S_TIP_CD, false) // we would go S_TRUNK_CD instead transition(S_TIP_D, S_TRUNK_C, p && c) // probed while acquired transition(S_TIP_D, S_TRUNK_CD, c) // acquire transition(S_TIP_CD, S_INVALID, c && p) transition(S_TIP_CD, S_BRANCH, c && p) // losing D is only possible via probe transition(S_TIP_CD, S_BRANCH_C, c && p) // losing D is only possible via probe transition(S_TIP_CD, S_TIP, c && p) // probed while MMIO read || outer probe.toT (optional) transition(S_TIP_CD, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP_CD, S_TIP_D, c) // MMIO write || clean release (optional) transition(S_TIP_CD, S_TRUNK_C, c && p) // probed while acquire transition(S_TIP_CD, S_TRUNK_CD, c) // acquire transition(S_TRUNK_C, S_INVALID, c && p) transition(S_TRUNK_C, S_BRANCH, c && p) // losing TIP only possible via probe transition(S_TRUNK_C, S_BRANCH_C, c && p) // losing TIP only possible via probe transition(S_TRUNK_C, S_TIP, c) // MMIO read || clean release (optional) transition(S_TRUNK_C, S_TIP_C, c) // bounce shared transition(S_TRUNK_C, S_TIP_D, c) // dirty release transition(S_TRUNK_C, S_TIP_CD, c) // dirty bounce shared transition(S_TRUNK_C, S_TRUNK_CD, c) // dirty bounce transition(S_TRUNK_CD, S_INVALID, c && p) transition(S_TRUNK_CD, S_BRANCH, c && p) // losing D only possible via probe transition(S_TRUNK_CD, S_BRANCH_C, c && p) // losing D only possible via probe transition(S_TRUNK_CD, S_TIP, c && p) // probed while MMIO read || outer probe.toT (optional) transition(S_TRUNK_CD, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TRUNK_CD, S_TIP_D, c) // dirty release transition(S_TRUNK_CD, S_TIP_CD, c) // bounce shared transition(S_TRUNK_CD, S_TRUNK_C, c && p) // probed while acquire } // Handle response messages val probe_bit = params.clientBit(io.sinkc.bits.source) val last_probe = (probes_done | probe_bit) === (meta.clients & ~excluded_client) val probe_toN = isToN(io.sinkc.bits.param) if (!params.firstLevel) when (io.sinkc.valid) { params.ccover( probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_FULL", "Client downgraded to N when asked only to do B") params.ccover(!probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_HALF", "Client downgraded to B when asked only to do B") // Caution: the probe matches us only in set. // We would never allow an outer probe to nest until both w_[rp]probeack complete, so // it is safe to just unguardedly update the probe FSM. probes_done := probes_done | probe_bit probes_toN := probes_toN | Mux(probe_toN, probe_bit, 0.U) probes_noT := probes_noT || io.sinkc.bits.param =/= TtoT w_rprobeackfirst := w_rprobeackfirst || last_probe w_rprobeacklast := w_rprobeacklast || (last_probe && io.sinkc.bits.last) w_pprobeackfirst := w_pprobeackfirst || last_probe w_pprobeacklast := w_pprobeacklast || (last_probe && io.sinkc.bits.last) // Allow wormhole routing from sinkC if the first request beat has offset 0 val set_pprobeack = last_probe && (io.sinkc.bits.last || request.offset === 0.U) w_pprobeack := w_pprobeack || set_pprobeack params.ccover(!set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_SERIAL", "Sequential routing of probe response data") params.ccover( set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_WORMHOLE", "Wormhole routing of probe response data") // However, meta-data updates need to be done more cautiously when (meta.state =/= INVALID && io.sinkc.bits.tag === meta.tag && io.sinkc.bits.data) { meta.dirty := true.B } // !!! } when (io.sinkd.valid) { when (io.sinkd.bits.opcode === Grant || io.sinkd.bits.opcode === GrantData) { sink := io.sinkd.bits.sink w_grantfirst := true.B w_grantlast := io.sinkd.bits.last // Record if we need to prevent taking ownership bad_grant := io.sinkd.bits.denied // Allow wormhole routing for requests whose first beat has offset 0 w_grant := request.offset === 0.U || io.sinkd.bits.last params.ccover(io.sinkd.bits.opcode === GrantData && request.offset === 0.U, "MSHR_GRANT_WORMHOLE", "Wormhole routing of grant response data") params.ccover(io.sinkd.bits.opcode === GrantData && request.offset =/= 0.U, "MSHR_GRANT_SERIAL", "Sequential routing of grant response data") gotT := io.sinkd.bits.param === toT } .elsewhen (io.sinkd.bits.opcode === ReleaseAck) { w_releaseack := true.B } } when (io.sinke.valid) { w_grantack := true.B } // Bootstrap new requests val allocate_as_full = WireInit(new FullRequest(params), init = io.allocate.bits) val new_meta = Mux(io.allocate.valid && io.allocate.bits.repeat, final_meta_writeback, io.directory.bits) val new_request = Mux(io.allocate.valid, allocate_as_full, request) val new_needT = needT(new_request.opcode, new_request.param) val new_clientBit = params.clientBit(new_request.source) val new_skipProbe = Mux(skipProbeN(new_request.opcode, params.cache.hintsSkipProbe), new_clientBit, 0.U) val prior = cacheState(final_meta_writeback, true.B) def bypass(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(prior === from.code, s"MSHR_${from}_BYPASS", s"State bypass transition from ${from} ${cfg}") } else { assert(!(prior === from.code), cf"State bypass from ${from} should be impossible ${cfg}") } } when (io.allocate.valid && io.allocate.bits.repeat) { bypass(S_INVALID, f || p) // Can lose permissions (probe/flush) bypass(S_BRANCH, b) // MMIO read to read-only device bypass(S_BRANCH_C, b && c) // you need children to become C bypass(S_TIP, true) // MMIO read || clean release can lead to this state bypass(S_TIP_C, c) // needs two clients || client + mmio || downgrading client bypass(S_TIP_CD, c) // needs two clients || client + mmio || downgrading client bypass(S_TIP_D, true) // MMIO write || dirty release lead here bypass(S_TRUNK_C, c) // acquire for write bypass(S_TRUNK_CD, c) // dirty release then reacquire } when (io.allocate.valid) { assert (!request_valid || (no_wait && io.schedule.fire)) request_valid := true.B request := io.allocate.bits } // Create execution plan when (io.directory.valid || (io.allocate.valid && io.allocate.bits.repeat)) { meta_valid := true.B meta := new_meta probes_done := 0.U probes_toN := 0.U probes_noT := false.B gotT := false.B bad_grant := false.B // These should already be either true or turning true // We clear them here explicitly to simplify the mux tree s_rprobe := true.B w_rprobeackfirst := true.B w_rprobeacklast := true.B s_release := true.B w_releaseack := true.B s_pprobe := true.B s_acquire := true.B s_flush := true.B w_grantfirst := true.B w_grantlast := true.B w_grant := true.B w_pprobeackfirst := true.B w_pprobeacklast := true.B w_pprobeack := true.B s_probeack := true.B s_grantack := true.B s_execute := true.B w_grantack := true.B s_writeback := true.B // For C channel requests (ie: Release[Data]) when (new_request.prio(2) && (!params.firstLevel).B) { s_execute := false.B // Do we need to go dirty? when (new_request.opcode(0) && !new_meta.dirty) { s_writeback := false.B } // Does our state change? when (isToB(new_request.param) && new_meta.state === TRUNK) { s_writeback := false.B } // Do our clients change? when (isToN(new_request.param) && (new_meta.clients & new_clientBit) =/= 0.U) { s_writeback := false.B } assert (new_meta.hit) } // For X channel requests (ie: flush) .elsewhen (new_request.control && params.control.B) { // new_request.prio(0) s_flush := false.B // Do we need to actually do something? when (new_meta.hit) { s_release := false.B w_releaseack := false.B // Do we need to shoot-down inner caches? when ((!params.firstLevel).B && (new_meta.clients =/= 0.U)) { s_rprobe := false.B w_rprobeackfirst := false.B w_rprobeacklast := false.B } } } // For A channel requests .otherwise { // new_request.prio(0) && !new_request.control s_execute := false.B // Do we need an eviction? when (!new_meta.hit && new_meta.state =/= INVALID) { s_release := false.B w_releaseack := false.B // Do we need to shoot-down inner caches? when ((!params.firstLevel).B & (new_meta.clients =/= 0.U)) { s_rprobe := false.B w_rprobeackfirst := false.B w_rprobeacklast := false.B } } // Do we need an acquire? when (!new_meta.hit || (new_meta.state === BRANCH && new_needT)) { s_acquire := false.B w_grantfirst := false.B w_grantlast := false.B w_grant := false.B s_grantack := false.B s_writeback := false.B } // Do we need a probe? when ((!params.firstLevel).B && (new_meta.hit && (new_needT || new_meta.state === TRUNK) && (new_meta.clients & ~new_skipProbe) =/= 0.U)) { s_pprobe := false.B w_pprobeackfirst := false.B w_pprobeacklast := false.B w_pprobeack := false.B s_writeback := false.B } // Do we need a grantack? when (new_request.opcode === AcquireBlock || new_request.opcode === AcquirePerm) { w_grantack := false.B s_writeback := false.B } // Becomes dirty? when (!new_request.opcode(2) && new_meta.hit && !new_meta.dirty) { s_writeback := false.B } } } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") }
module MSHR_11( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [6:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [12:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input [3:0] io_directory_bits_clients, // @[MSHR.scala:86:14] input [12:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [9:0] io_status_bits_set, // @[MSHR.scala:86:14] output [12:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [2:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [6:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [12:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [6:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [3:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [3:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [12:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [12:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire [3:0] final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [6:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [12:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire [3:0] io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [12:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [12:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [6:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [3:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [3:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [12:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0 = 1'h0; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1 = 1'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0 = 1'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1 = 1'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T = 1'h0; // @[MSHR.scala:279:38] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _excluded_client_T_9 = 1'h0; // @[MSHR.scala:279:57] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire allocate_as_full_prio_0 = 1'h0; // @[MSHR.scala:504:34] wire allocate_as_full_prio_1 = 1'h0; // @[MSHR.scala:504:34] wire new_request_prio_0 = 1'h0; // @[MSHR.scala:506:24] wire new_request_prio_1 = 1'h0; // @[MSHR.scala:506:24] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire [3:0] _io_schedule_bits_b_bits_clients_T = 4'hF; // @[MSHR.scala:289:53] wire [3:0] _last_probe_T_1 = 4'hF; // @[MSHR.scala:459:66] wire [3:0] io_schedule_bits_a_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_c_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_d_bits_sink = 4'h0; // @[MSHR.scala:84:7] wire [3:0] invalid_clients = 4'h0; // @[MSHR.scala:268:21] wire [3:0] excluded_client = 4'h0; // @[MSHR.scala:279:28] wire _req_clientBit_T_4 = 1'h1; // @[Parameters.scala:56:32] wire _req_clientBit_T_10 = 1'h1; // @[Parameters.scala:56:32] wire _probe_bit_T_4 = 1'h1; // @[Parameters.scala:56:32] wire _probe_bit_T_10 = 1'h1; // @[Parameters.scala:56:32] wire _new_clientBit_T_4 = 1'h1; // @[Parameters.scala:56:32] wire _new_clientBit_T_10 = 1'h1; // @[Parameters.scala:56:32] wire [12:0] invalid_tag = 13'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [6:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [12:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [12:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire [3:0] _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire [3:0] _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [12:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [6:0] _probe_bit_uncommonBits_T = io_sinkc_bits_source_0; // @[Parameters.scala:52:29] wire [6:0] _probe_bit_uncommonBits_T_1 = io_sinkc_bits_source_0; // @[Parameters.scala:52:29] wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [12:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [6:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [6:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] wire [6:0] _req_clientBit_uncommonBits_T = request_source; // @[Parameters.scala:52:29] wire [6:0] _req_clientBit_uncommonBits_T_1 = request_source; // @[Parameters.scala:52:29] reg [12:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [9:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg [3:0] meta_clients; // @[MSHR.scala:100:17] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients; // @[MSHR.scala:100:17, :289:51] wire [3:0] _last_probe_T_2 = meta_clients; // @[MSHR.scala:100:17, :459:64] reg [12:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [2:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg [3:0] probes_done; // @[MSHR.scala:150:24] reg [3:0] probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire [3:0] _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire [12:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire _req_clientBit_T = request_source == 7'h44; // @[Parameters.scala:46:9] wire _req_clientBit_T_1 = request_source == 7'h40; // @[Parameters.scala:46:9] wire [2:0] req_clientBit_uncommonBits = _req_clientBit_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _req_clientBit_T_2 = request_source[6:3]; // @[Parameters.scala:54:10] wire [3:0] _req_clientBit_T_8 = request_source[6:3]; // @[Parameters.scala:54:10] wire _req_clientBit_T_3 = _req_clientBit_T_2 == 4'h6; // @[Parameters.scala:54:{10,32}] wire _req_clientBit_T_5 = _req_clientBit_T_3; // @[Parameters.scala:54:{32,67}] wire _req_clientBit_T_6 = req_clientBit_uncommonBits < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _req_clientBit_T_7 = _req_clientBit_T_5 & _req_clientBit_T_6; // @[Parameters.scala:54:67, :56:48, :57:20] wire [2:0] req_clientBit_uncommonBits_1 = _req_clientBit_uncommonBits_T_1[2:0]; // @[Parameters.scala:52:{29,56}] wire _req_clientBit_T_9 = _req_clientBit_T_8 == 4'h4; // @[Parameters.scala:54:{10,32}] wire _req_clientBit_T_11 = _req_clientBit_T_9; // @[Parameters.scala:54:{32,67}] wire _req_clientBit_T_12 = req_clientBit_uncommonBits_1 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _req_clientBit_T_13 = _req_clientBit_T_11 & _req_clientBit_T_12; // @[Parameters.scala:54:67, :56:48, :57:20] wire [1:0] req_clientBit_lo = {_req_clientBit_T_1, _req_clientBit_T}; // @[Parameters.scala:46:9] wire [1:0] req_clientBit_hi = {_req_clientBit_T_13, _req_clientBit_T_7}; // @[Parameters.scala:56:48] wire [3:0] req_clientBit = {req_clientBit_hi, req_clientBit_lo}; // @[Parameters.scala:201:10] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire _meta_no_clients_T = |meta_clients; // @[MSHR.scala:100:17, :220:39] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire [3:0] _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 ? req_clientBit : 4'h0; // @[Parameters.scala:201:10, :282:66] wire [3:0] _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire [3:0] _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire [3:0] _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire [3:0] _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire [3:0] _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire [3:0] _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire [3:0] _final_meta_writeback_clients_T_12 = meta_hit ? _final_meta_writeback_clients_T_11 : 4'h0; // @[MSHR.scala:100:17, :245:{40,64}] wire [3:0] _final_meta_writeback_clients_T_13 = req_acquire ? req_clientBit : 4'h0; // @[Parameters.scala:201:10] wire [3:0] _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire [3:0] _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire [3:0] _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? (meta_hit ? _final_meta_writeback_clients_T_16 : 4'h0) : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire [3:0] _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:201:10] wire _honour_BtoT_T_1 = |_honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = _io_schedule_bits_dir_bits_data_T ? 4'h0 : _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 13'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire evict_c = |meta_clients; // @[MSHR.scala:100:17, :220:39, :315:27] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire before_c = |meta_clients; // @[MSHR.scala:100:17, :220:39, :315:27] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire after_c = |final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _probe_bit_T = io_sinkc_bits_source_0 == 7'h44; // @[Parameters.scala:46:9] wire _probe_bit_T_1 = io_sinkc_bits_source_0 == 7'h40; // @[Parameters.scala:46:9] wire [2:0] probe_bit_uncommonBits = _probe_bit_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _probe_bit_T_2 = io_sinkc_bits_source_0[6:3]; // @[Parameters.scala:54:10] wire [3:0] _probe_bit_T_8 = io_sinkc_bits_source_0[6:3]; // @[Parameters.scala:54:10] wire _probe_bit_T_3 = _probe_bit_T_2 == 4'h6; // @[Parameters.scala:54:{10,32}] wire _probe_bit_T_5 = _probe_bit_T_3; // @[Parameters.scala:54:{32,67}] wire _probe_bit_T_6 = probe_bit_uncommonBits < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _probe_bit_T_7 = _probe_bit_T_5 & _probe_bit_T_6; // @[Parameters.scala:54:67, :56:48, :57:20] wire [2:0] probe_bit_uncommonBits_1 = _probe_bit_uncommonBits_T_1[2:0]; // @[Parameters.scala:52:{29,56}] wire _probe_bit_T_9 = _probe_bit_T_8 == 4'h4; // @[Parameters.scala:54:{10,32}] wire _probe_bit_T_11 = _probe_bit_T_9; // @[Parameters.scala:54:{32,67}] wire _probe_bit_T_12 = probe_bit_uncommonBits_1 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _probe_bit_T_13 = _probe_bit_T_11 & _probe_bit_T_12; // @[Parameters.scala:54:67, :56:48, :57:20] wire [1:0] probe_bit_lo = {_probe_bit_T_1, _probe_bit_T}; // @[Parameters.scala:46:9] wire [1:0] probe_bit_hi = {_probe_bit_T_13, _probe_bit_T_7}; // @[Parameters.scala:56:48] wire [3:0] probe_bit = {probe_bit_hi, probe_bit_lo}; // @[Parameters.scala:201:10] wire [3:0] _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:201:10] wire [3:0] _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire [3:0] _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire [3:0] _probes_toN_T = probe_toN ? probe_bit : 4'h0; // @[Parameters.scala:201:10, :282:66] wire [3:0] _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [3:0] new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [12:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [6:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [12:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [6:0] _new_clientBit_uncommonBits_T = new_request_source; // @[Parameters.scala:52:29] wire [6:0] _new_clientBit_uncommonBits_T_1 = new_request_source; // @[Parameters.scala:52:29] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _new_clientBit_T = new_request_source == 7'h44; // @[Parameters.scala:46:9] wire _new_clientBit_T_1 = new_request_source == 7'h40; // @[Parameters.scala:46:9] wire [2:0] new_clientBit_uncommonBits = _new_clientBit_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _new_clientBit_T_2 = new_request_source[6:3]; // @[Parameters.scala:54:10] wire [3:0] _new_clientBit_T_8 = new_request_source[6:3]; // @[Parameters.scala:54:10] wire _new_clientBit_T_3 = _new_clientBit_T_2 == 4'h6; // @[Parameters.scala:54:{10,32}] wire _new_clientBit_T_5 = _new_clientBit_T_3; // @[Parameters.scala:54:{32,67}] wire _new_clientBit_T_6 = new_clientBit_uncommonBits < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _new_clientBit_T_7 = _new_clientBit_T_5 & _new_clientBit_T_6; // @[Parameters.scala:54:67, :56:48, :57:20] wire [2:0] new_clientBit_uncommonBits_1 = _new_clientBit_uncommonBits_T_1[2:0]; // @[Parameters.scala:52:{29,56}] wire _new_clientBit_T_9 = _new_clientBit_T_8 == 4'h4; // @[Parameters.scala:54:{10,32}] wire _new_clientBit_T_11 = _new_clientBit_T_9; // @[Parameters.scala:54:{32,67}] wire _new_clientBit_T_12 = new_clientBit_uncommonBits_1 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _new_clientBit_T_13 = _new_clientBit_T_11 & _new_clientBit_T_12; // @[Parameters.scala:54:67, :56:48, :57:20] wire [1:0] new_clientBit_lo = {_new_clientBit_T_1, _new_clientBit_T}; // @[Parameters.scala:46:9] wire [1:0] new_clientBit_hi = {_new_clientBit_T_13, _new_clientBit_T_7}; // @[Parameters.scala:56:48] wire [3:0] new_clientBit = {new_clientBit_hi, new_clientBit_lo}; // @[Parameters.scala:201:10] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire [3:0] new_skipProbe = _new_skipProbe_T_7 ? new_clientBit : 4'h0; // @[Parameters.scala:201:10, :279:106] wire [3:0] prior; // @[MSHR.scala:314:26] wire prior_c = |final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_46( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File L2MemHelperLatencyInjection.scala: package compressacc import chisel3._ import chisel3.util._ import chisel3.{Printable} import chisel3.reflect.DataMirror import freechips.rocketchip.tile._ import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.rocket.{TLBConfig, TLBPTWIO, TLB, MStatus, PRV} import freechips.rocketchip.util.DecoupledHelper import freechips.rocketchip.rocket.constants.MemoryOpConstants import freechips.rocketchip.rocket.{RAS} import freechips.rocketchip.tilelink._ class L2MemHelperLatencyInjection(printInfo: String = "", numOutstandingReqs: Int = 32, queueRequests: Boolean = false, queueResponses: Boolean = false, printWriteBytes: Boolean = false)(implicit p: Parameters) extends LazyModule { val numOutstandingRequestsAllowed = numOutstandingReqs val tlTagBits = log2Ceil(numOutstandingRequestsAllowed) lazy val module = new L2MemHelperLatencyInjectionModule(this, printInfo, queueRequests, queueResponses, printWriteBytes) val masterNode = TLClientNode(Seq(TLClientPortParameters( Seq(TLClientParameters(name = printInfo, sourceId = IdRange(0, numOutstandingRequestsAllowed))) ))) } class L2MemHelperLatencyInjectionModule(outer: L2MemHelperLatencyInjection, printInfo: String = "", queueRequests: Boolean = false, queueResponses: Boolean = false, printWriteBytes: Boolean = false)(implicit p: Parameters) extends LazyModuleImp(outer) with HasCoreParameters with MemoryOpConstants { val io = IO(new Bundle { val userif = Flipped(new L2MemHelperBundle) val latency_inject_cycles = Input(UInt(64.W)) val sfence = Input(Bool()) val ptw = new TLBPTWIO val status = Flipped(Valid(new MStatus)) }) val (dmem, edge) = outer.masterNode.out.head val request_input = Wire(Decoupled(new L2ReqInternal)) if (!queueRequests) { request_input <> io.userif.req } else { val requestQueue = Module(new Queue(new L2ReqInternal, 4)) request_input <> requestQueue.io.deq requestQueue.io.enq <> io.userif.req } val response_output = Wire(Decoupled(new L2RespInternal)) if (!queueResponses) { io.userif.resp <> response_output } else { val responseQueue = Module(new Queue(new L2RespInternal, 4)) responseQueue.io.enq <> response_output io.userif.resp <> responseQueue.io.deq } val status = Reg(new MStatus) when (io.status.valid) { CompressAccelLogger.logInfo(printInfo + " setting status.dprv to: %x compare %x\n", io.status.bits.dprv, PRV.M.U) status := io.status.bits } val tlb = Module(new TLB(false, log2Ceil(coreDataBytes), p(CompressAccelTLB).get)(edge, p)) tlb.io.req.valid := request_input.valid tlb.io.req.bits.vaddr := request_input.bits.addr tlb.io.req.bits.size := request_input.bits.size tlb.io.req.bits.cmd := request_input.bits.cmd tlb.io.req.bits.passthrough := false.B val tlb_ready = tlb.io.req.ready && !tlb.io.resp.miss tlb.io.req.bits.prv := DontCare tlb.io.req.bits.v := DontCare tlb.io.sfence.bits.hv := DontCare tlb.io.sfence.bits.hg := DontCare io.ptw <> tlb.io.ptw tlb.io.ptw.status := status tlb.io.sfence.valid := io.sfence tlb.io.sfence.bits.rs1 := false.B tlb.io.sfence.bits.rs2 := false.B tlb.io.sfence.bits.addr := 0.U tlb.io.sfence.bits.asid := 0.U tlb.io.kill := false.B val outstanding_req_addr = Module(new Queue(new L2InternalTracking, outer.numOutstandingRequestsAllowed * 4)) val tags_for_issue_Q = Module(new Queue(UInt(outer.tlTagBits.W), outer.numOutstandingRequestsAllowed * 2)) tags_for_issue_Q.io.enq.valid := false.B tags_for_issue_Q.io.enq.bits := DontCare val tags_init_reg = RegInit(0.U((outer.tlTagBits+1).W)) when (tags_init_reg =/= (outer.numOutstandingRequestsAllowed).U) { tags_for_issue_Q.io.enq.bits := tags_init_reg tags_for_issue_Q.io.enq.valid := true.B when (tags_for_issue_Q.io.enq.ready) { CompressAccelLogger.logInfo(printInfo + " tags_for_issue_Q init with value %d\n", tags_for_issue_Q.io.enq.bits) tags_init_reg := tags_init_reg + 1.U } } val addr_mask_check = (1.U(64.W) << request_input.bits.size) - 1.U val assertcheck = RegNext((!request_input.valid) || ((request_input.bits.addr & addr_mask_check) === 0.U)) when (!assertcheck) { CompressAccelLogger.logInfo(printInfo + " L2IF: access addr must be aligned to write width\n") } assert(assertcheck, printInfo + " L2IF: access addr must be aligned to write width\n") val global_memop_accepted = RegInit(0.U(64.W)) when (io.userif.req.fire) { global_memop_accepted := global_memop_accepted + 1.U } val global_memop_sent = RegInit(0.U(64.W)) val global_memop_ackd = RegInit(0.U(64.W)) val global_memop_resp_to_user = RegInit(0.U(64.W)) io.userif.no_memops_inflight := global_memop_accepted === global_memop_ackd val free_outstanding_op_slots = (global_memop_sent - global_memop_ackd) < (1 << outer.tlTagBits).U val assert_free_outstanding_op_slots = (global_memop_sent - global_memop_ackd) <= (1 << outer.tlTagBits).U when (!assert_free_outstanding_op_slots) { CompressAccelLogger.logInfo(printInfo + " L2IF: Too many outstanding requests for tag count.\n") } assert(assert_free_outstanding_op_slots, printInfo + " L2IF: Too many outstanding requests for tag count.\n") when (request_input.fire) { global_memop_sent := global_memop_sent + 1.U } val sendtag = tags_for_issue_Q.io.deq.bits val cur_cycle = RegInit(0.U(64.W)) cur_cycle := cur_cycle + 1.U val release_cycle_q_depth = 2 * outer.numOutstandingRequestsAllowed val request_latency_injection_q = Module(new LatencyInjectionQueue(DataMirror.internal.chiselTypeClone[TLBundleA](dmem.a.bits), release_cycle_q_depth)) // val req_release_cycle_q = Module(new Queue(UInt(64.W), release_cycle_q_depth, flow=true)) // val req_q = Module(new Queue(DataMirror.internal.chiselTypeClone[TLBundleA](dmem.a.bits), release_cycle_q_depth, flow=true)) // req_release_cycle_q.io.enq.bits := cur_cycle + io.latency_inject_cycles request_latency_injection_q.io.latency_cycles := io.latency_inject_cycles request_latency_injection_q.io.enq.bits := DontCare when (request_input.bits.cmd === M_XRD) { val (legal, bundle) = edge.Get(fromSource=sendtag, toAddress=tlb.io.resp.paddr, lgSize=request_input.bits.size) request_latency_injection_q.io.enq.bits := bundle // dmem.a.bits := bundle } .elsewhen (request_input.bits.cmd === M_XWR) { val (legal, bundle) = edge.Put(fromSource=sendtag, toAddress=tlb.io.resp.paddr, lgSize=request_input.bits.size, data=request_input.bits.data << ((request_input.bits.addr(4, 0) << 3))) request_latency_injection_q.io.enq.bits := bundle // dmem.a.bits := bundle } .elsewhen (request_input.valid) { CompressAccelLogger.logInfo(printInfo + " ERR") assert(false.B, "ERR") } val tl_resp_queues = Seq.fill(outer.numOutstandingRequestsAllowed)( Module(new Queue(new L2RespInternal, 4, flow=true)).io) // val current_request_tag_has_response_space = tl_resp_queues(tags_for_issue_Q.io.deq.bits).enq.ready val current_request_tag_has_response_space = tl_resp_queues.zipWithIndex.map({ case (q, idx) => q.enq.ready && (idx.U === tags_for_issue_Q.io.deq.bits) }).reduce(_ || _) val fire_req = DecoupledHelper( request_input.valid, request_latency_injection_q.io.enq.ready, tlb_ready, outstanding_req_addr.io.enq.ready, free_outstanding_op_slots, tags_for_issue_Q.io.deq.valid, current_request_tag_has_response_space ) outstanding_req_addr.io.enq.bits.addrindex := request_input.bits.addr & 0x1F.U outstanding_req_addr.io.enq.bits.tag := sendtag request_latency_injection_q.io.enq.valid := fire_req.fire(request_latency_injection_q.io.enq.ready) request_input.ready := fire_req.fire(request_input.valid) outstanding_req_addr.io.enq.valid := fire_req.fire(outstanding_req_addr.io.enq.ready) tags_for_issue_Q.io.deq.ready := fire_req.fire(tags_for_issue_Q.io.deq.valid) dmem.a <> request_latency_injection_q.io.deq when (dmem.a.fire) { when (request_input.bits.cmd === M_XRD) { CompressAccelLogger.logInfo(printInfo + " L2IF: req(read) vaddr: 0x%x, paddr: 0x%x, wid: 0x%x, opnum: %d, sendtag: %d\n", request_input.bits.addr, tlb.io.resp.paddr, request_input.bits.size, global_memop_sent, sendtag) } } when (fire_req.fire) { when (request_input.bits.cmd === M_XWR) { CompressAccelLogger.logCritical(printInfo + " L2IF: req(write) vaddr: 0x%x, paddr: 0x%x, wid: 0x%x, data: 0x%x, opnum: %d, sendtag: %d\n", request_input.bits.addr, tlb.io.resp.paddr, request_input.bits.size, request_input.bits.data, global_memop_sent, sendtag) if (printWriteBytes) { for (i <- 0 until 32) { when (i.U < (1.U << request_input.bits.size)) { CompressAccelLogger.logInfo("WRITE_BYTE ADDR: 0x%x BYTE: 0x%x " + printInfo + "\n", request_input.bits.addr + i.U, (request_input.bits.data >> (i*8).U)(7, 0)) } } } } } val response_latency_injection_q = Module(new LatencyInjectionQueue(DataMirror.internal.chiselTypeClone[TLBundleD](dmem.d.bits), release_cycle_q_depth)) response_latency_injection_q.io.latency_cycles := io.latency_inject_cycles response_latency_injection_q.io.enq <> dmem.d // val selectQready = tl_resp_queues(response_latency_injection_q.io.deq.bits.source).enq.ready val selectQready = tl_resp_queues.zipWithIndex.map({ case(q, idx) => q.enq.ready && (idx.U === response_latency_injection_q.io.deq.bits.source) }).reduce(_ || _) val fire_actual_mem_resp = DecoupledHelper( selectQready, response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready ) when (fire_actual_mem_resp.fire(tags_for_issue_Q.io.enq.ready)) { tags_for_issue_Q.io.enq.valid := true.B tags_for_issue_Q.io.enq.bits := response_latency_injection_q.io.deq.bits.source } when (fire_actual_mem_resp.fire(tags_for_issue_Q.io.enq.ready) && tags_for_issue_Q.io.enq.valid) { CompressAccelLogger.logInfo(printInfo + " tags_for_issue_Q add back tag %d\n", tags_for_issue_Q.io.enq.bits) } response_latency_injection_q.io.deq.ready := fire_actual_mem_resp.fire(response_latency_injection_q.io.deq.valid) for (i <- 0 until outer.numOutstandingRequestsAllowed) { tl_resp_queues(i).enq.valid := fire_actual_mem_resp.fire(selectQready) && (response_latency_injection_q.io.deq.bits.source === i.U) tl_resp_queues(i).enq.bits.data := response_latency_injection_q.io.deq.bits.data } // val currentQueue = tl_resp_queues(outstanding_req_addr.io.deq.bits.tag) // val queueValid = currentQueue.deq.valid val queueValid = tl_resp_queues.zipWithIndex.map({ case(q, idx) => q.deq.valid && (idx.U === outstanding_req_addr.io.deq.bits.tag) }).reduce(_ || _) val fire_user_resp = DecoupledHelper( queueValid, response_output.ready, outstanding_req_addr.io.deq.valid ) // val resultdata = currentQueue.deq.bits.data >> (outstanding_req_addr.io.deq.bits.addrindex << 3) val resultdata = tl_resp_queues.zipWithIndex.map({ case(q, idx) => val is_current_q = (idx.U === outstanding_req_addr.io.deq.bits.tag) val data = Wire(q.deq.bits.data.cloneType) when (is_current_q) { data := q.deq.bits.data >> (outstanding_req_addr.io.deq.bits.addrindex << 3) } .otherwise { data := 0.U } data }).reduce(_ | _) response_output.bits.data := resultdata response_output.valid := fire_user_resp.fire(response_output.ready) outstanding_req_addr.io.deq.ready := fire_user_resp.fire(outstanding_req_addr.io.deq.valid) for (i <- 0 until outer.numOutstandingRequestsAllowed) { tl_resp_queues(i).deq.ready := fire_user_resp.fire(queueValid) && (outstanding_req_addr.io.deq.bits.tag === i.U) } when (dmem.d.fire) { when (edge.hasData(dmem.d.bits)) { CompressAccelLogger.logInfo(printInfo + " L2IF: resp(read) data: 0x%x, opnum: %d, gettag: %d\n", dmem.d.bits.data, global_memop_ackd, dmem.d.bits.source) } .otherwise { CompressAccelLogger.logInfo(printInfo + " L2IF: resp(write) opnum: %d, gettag: %d\n", global_memop_ackd, dmem.d.bits.source) } } when (response_output.fire) { CompressAccelLogger.logInfo(printInfo + " L2IF: realresp() data: 0x%x, opnum: %d, gettag: %d\n", resultdata, global_memop_resp_to_user, outstanding_req_addr.io.deq.bits.tag) } when (response_latency_injection_q.io.deq.fire) { global_memop_ackd := global_memop_ackd + 1.U } when (response_output.fire) { global_memop_resp_to_user := global_memop_resp_to_user + 1.U } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Util.scala: package compressacc import chisel3._ import chisel3.util._ import chisel3.{Printable} import freechips.rocketchip.tile._ import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.rocket.{TLBConfig} import freechips.rocketchip.util.DecoupledHelper import freechips.rocketchip.rocket.constants.MemoryOpConstants object CompressAccelLogger { def logInfo(format: String, args: Bits*)(implicit p: Parameters) { val loginfo_cycles = RegInit(0.U(64.W)) loginfo_cycles := loginfo_cycles + 1.U printf("cy: %d, ", loginfo_cycles) printf(Printable.pack(format, args:_*)) } def logCritical(format: String, args: Bits*)(implicit p: Parameters) { val loginfo_cycles = RegInit(0.U(64.W)) loginfo_cycles := loginfo_cycles + 1.U if (p(CompressAccelPrintfEnable)) { printf(midas.targetutils.SynthesizePrintf("cy: %d, ", loginfo_cycles)) printf(midas.targetutils.SynthesizePrintf(format, args:_*)) } else { printf("cy: %d, ", loginfo_cycles) printf(Printable.pack(format, args:_*)) } } def logWaveStyle(format: String, args: Bits*)(implicit p: Parameters) { } } object CompressAccelParams { } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File annotations.scala: // See LICENSE for license details. package midas.targetutils import chisel3.{ dontTouch, fromBooleanToLiteral, when, Bits, Bool, Clock, Data, MemBase, Module, Printable, RegNext, Reset, UInt, Wire, WireDefault, } import chisel3.printf.Printf import chisel3.experimental.{annotate, requireIsHardware, BaseModule, ChiselAnnotation} import firrtl.RenameMap import firrtl.annotations.{ Annotation, ComponentName, HasSerializationHints, InstanceTarget, ModuleTarget, ReferenceTarget, SingleTargetAnnotation, } /** These are consumed by [[midas.passes.AutoILATransform]] to directly instantiate an ILA at the top of simulator's * design hierarchy (the PlatformShim level). */ case class FpgaDebugAnnotation(target: Data) extends ChiselAnnotation { def toFirrtl = FirrtlFpgaDebugAnnotation(target.toNamed) } case class FirrtlFpgaDebugAnnotation(target: ComponentName) extends SingleTargetAnnotation[ComponentName] { def duplicate(n: ComponentName) = this.copy(target = n) } object FpgaDebug { def apply(targets: Data*): Unit = { targets.foreach { requireIsHardware(_, "Target passed to FpgaDebug:") } targets.map({ t => annotate(FpgaDebugAnnotation(t)) }) } } private[midas] class ReferenceTargetRenamer(renames: RenameMap) { // TODO: determine order for multiple renames, or just check of == 1 rename? def exactRename(rt: ReferenceTarget): ReferenceTarget = { val renameMatches = renames.get(rt).getOrElse(Seq(rt)).collect({ case rt: ReferenceTarget => rt }) assert( renameMatches.length <= 1, s"${rt} should be renamed exactly once (or not at all). Suggested renames: ${renameMatches}", ) renameMatches.headOption.getOrElse(rt) } def apply(rt: ReferenceTarget): Seq[ReferenceTarget] = { renames.get(rt).getOrElse(Seq(rt)).collect({ case rt: ReferenceTarget => rt }) } } private[midas] case class SynthPrintfAnnotation( target: ReferenceTarget ) extends firrtl.annotations.SingleTargetAnnotation[ReferenceTarget] { def duplicate(newTarget: ReferenceTarget) = this.copy(newTarget) } object SynthesizePrintf { /** Annotates a chisel printf as a candidate for synthesis. The printf is only synthesized if Printf synthesis is * enabled in Golden Gate. * * See: https://docs.fires.im/en/stable/search.html?q=Printf+Synthesis&check_keywords=yes&area=default * * @param printf * The printf statement to be synthesized. * * @return * The original input, so that this annotator may be applied inline if desired. */ def apply(printf: Printf): Printf = { annotate(new ChiselAnnotation { def toFirrtl = SynthPrintfAnnotation(printf.toTarget) }) printf } private def generateAnnotations(format: String, args: Seq[Bits], name: Option[String]): Printable = { Module.currentModule.getOrElse(throw new RuntimeException("Cannot annotate a printf outside of a Module")) // To preserve the behavior of the printf parameter annotator, generate a // secondary printf and annotate that, instead of the user's printf, which // will be given an empty string. This will be removed with the apply methods in 1.15. val printf = SynthesizePrintf(chisel3.printf(Printable.pack(format, args: _*))) name.foreach { n => printf.suggestName(n) } Printable.pack("") } /** Annotates* a printf by intercepting the parameters to a chisel printf, and returning a printable. As a side * effect, this function generates a ChiselSynthPrintfAnnotation with the format string and references to each of the * args. * * *Note: this isn't actually annotating the statement but instead the arguments. This is a vestige from earlier * versions of chisel / firrtl in which print statements were unnamed, and thus not referenceable from annotations. * * @param format * The format string for the printf * @param args * Hardware references to populate the format string. */ @deprecated("This method will be removed. Annotate the printf statement directly", "FireSim 1.14") def apply(format: String, args: Bits*): Printable = generateAnnotations(format, args, None) /** Like the other apply method, but provides an optional name which can be used by synthesized hardware / bridge. * Generally, users deploy the nameless form. * * @param name * A descriptive name for this printf instance. * @param format * The format string for the printf * @param args * Hardware references to populate the format string. */ @deprecated("This method will be removed. Annotate the printf statement directly", "FireSim 1.14") def apply(name: String, format: String, args: Bits*): Printable = generateAnnotations(format, args, Some(name)) } /** A mixed-in ancestor trait for all FAME annotations, useful for type-casing. */ trait FAMEAnnotation { this: Annotation => } /** This labels an instance so that it is extracted as a separate FAME model. */ case class FAMEModelAnnotation(target: BaseModule) extends ChiselAnnotation { def toFirrtl: FirrtlFAMEModelAnnotation = { val parent = ModuleTarget(target.toNamed.circuit.name, target.parentModName) FirrtlFAMEModelAnnotation(parent.instOf(target.instanceName, target.name)) } } case class FirrtlFAMEModelAnnotation( target: InstanceTarget ) extends SingleTargetAnnotation[InstanceTarget] with FAMEAnnotation { def targets = Seq(target) def duplicate(n: InstanceTarget) = this.copy(n) } /** This specifies that the module should be automatically multi-threaded (Chisel annotator). */ case class EnableModelMultiThreadingAnnotation(target: BaseModule) extends ChiselAnnotation { def toFirrtl: FirrtlEnableModelMultiThreadingAnnotation = { val parent = ModuleTarget(target.toNamed.circuit.name, target.parentModName) FirrtlEnableModelMultiThreadingAnnotation(parent.instOf(target.instanceName, target.name)) } } /** This specifies that the module should be automatically multi-threaded (FIRRTL annotation). */ case class FirrtlEnableModelMultiThreadingAnnotation( target: InstanceTarget ) extends SingleTargetAnnotation[InstanceTarget] with FAMEAnnotation { def targets = Seq(target) def duplicate(n: InstanceTarget) = this.copy(n) } /** This labels a target Mem so that it is extracted and replaced with a separate model. */ case class MemModelAnnotation[T <: Data](target: MemBase[T]) extends ChiselAnnotation { def toFirrtl = FirrtlMemModelAnnotation(target.toNamed.toTarget) } case class FirrtlMemModelAnnotation(target: ReferenceTarget) extends SingleTargetAnnotation[ReferenceTarget] { def duplicate(rt: ReferenceTarget) = this.copy(target = rt) } case class ExcludeInstanceAssertsAnnotation(target: (String, String)) extends firrtl.annotations.NoTargetAnnotation { def duplicate(n: (String, String)) = this.copy(target = n) } // TODO: Actually use a real target and not strings. object ExcludeInstanceAsserts { def apply(target: (String, String)): ChiselAnnotation = new ChiselAnnotation { def toFirrtl = ExcludeInstanceAssertsAnnotation(target) } } sealed trait PerfCounterOpType object PerfCounterOps { /** Takes the annotated UInt and adds it to an accumulation register generated in the bridge */ case object Accumulate extends PerfCounterOpType /** Takes the annotated UInt and exposes it directly to the driver NB: Fields longer than 64b are not supported, and * must be divided into smaller segments that are sepearate annotated */ case object Identity extends PerfCounterOpType } /** AutoCounter annotations. Do not emit the FIRRTL annotations unless you are writing a target transformation, use the * Chisel-side [[PerfCounter]] object instead. */ case class AutoCounterFirrtlAnnotation( target: ReferenceTarget, clock: ReferenceTarget, reset: ReferenceTarget, label: String, description: String, opType: PerfCounterOpType = PerfCounterOps.Accumulate, coverGenerated: Boolean = false, ) extends firrtl.annotations.Annotation with HasSerializationHints { def update(renames: RenameMap): Seq[firrtl.annotations.Annotation] = { val renamer = new ReferenceTargetRenamer(renames) val renamedTarget = renamer.exactRename(target) val renamedClock = renamer.exactRename(clock) val renamedReset = renamer.exactRename(reset) Seq(this.copy(target = renamedTarget, clock = renamedClock, reset = renamedReset)) } // The AutoCounter tranform will reject this annotation if it's not enclosed def shouldBeIncluded(modList: Seq[String]): Boolean = !coverGenerated || modList.contains(target.module) def enclosingModule(): String = target.module def enclosingModuleTarget(): ModuleTarget = ModuleTarget(target.circuit, enclosingModule()) def typeHints: Seq[Class[_]] = Seq(opType.getClass) } case class AutoCounterCoverModuleFirrtlAnnotation(target: ModuleTarget) extends SingleTargetAnnotation[ModuleTarget] with FAMEAnnotation { def duplicate(n: ModuleTarget) = this.copy(target = n) } case class AutoCounterCoverModuleAnnotation(target: ModuleTarget) extends ChiselAnnotation { def toFirrtl = AutoCounterCoverModuleFirrtlAnnotation(target) } object PerfCounter { private def emitAnnotation( target: UInt, clock: Clock, reset: Reset, label: String, description: String, opType: PerfCounterOpType, ): Unit = { requireIsHardware(target, "Target passed to PerfCounter:") requireIsHardware(clock, "Clock passed to PerfCounter:") requireIsHardware(reset, "Reset passed to PerfCounter:") annotate(new ChiselAnnotation { def toFirrtl = AutoCounterFirrtlAnnotation(target.toTarget, clock.toTarget, reset.toTarget, label, description, opType) }) } /** Labels a signal as an event for which an host-side counter (an "AutoCounter") should be generated). Events can be * multi-bit to encode multiple occurances in a cycle (e.g., the number of instructions retired in a superscalar * processor). NB: Golden Gate will not generate the coutner unless AutoCounter is enabled in your the platform * config. See the docs.fires.im for end-to-end usage information. * * @param target * The number of occurances of the event (in the current cycle) * * @param clock * The clock to which this event is sychronized. * * @param reset * If the event is asserted while under the provide reset, it is not counted. TODO: This should be made optional. * * @param label * A verilog-friendly identifier for the event signal * * @param description * A human-friendly description of the event. * * @param opType * Defines how the bridge should be aggregated into a performance counter. */ def apply( target: UInt, clock: Clock, reset: Reset, label: String, description: String, opType: PerfCounterOpType = PerfCounterOps.Accumulate, ): Unit = emitAnnotation(target, clock, reset, label, description, opType) /** A simplified variation of the full apply method above that uses the implicit clock and reset. */ def apply(target: UInt, label: String, description: String): Unit = emitAnnotation(target, Module.clock, Module.reset, label, description, PerfCounterOps.Accumulate) /** Passes the annotated UInt through to the driver without accumulation. Use cases: * - Custom accumulation / counting logic not supported by the driver * - Providing runtime metadata along side standard accumulation registers * * Note: Under reset, the passthrough value is set to 0. This keeps event handling uniform in the transform. */ def identity(target: UInt, label: String, description: String): Unit = { require( target.getWidth <= 64, s"""|PerfCounter.identity can only accept fields <= 64b wide. Provided target for label: | $label |was ${target.getWidth}b.""".stripMargin, ) emitAnnotation(target, Module.clock, Module.reset, label, description, opType = PerfCounterOps.Identity) } } case class PlusArgFirrtlAnnotation( target: InstanceTarget ) extends SingleTargetAnnotation[InstanceTarget] with FAMEAnnotation { def targets = Seq(target) def duplicate(n: InstanceTarget) = this.copy(n) } object PlusArg { private def emitAnnotation( target: BaseModule ): Unit = { annotate(new ChiselAnnotation { def toFirrtl = { val parent = ModuleTarget(target.toNamed.circuit.name, target.parentModName) PlusArgFirrtlAnnotation(parent.instOf(target.instanceName, target.name)) } }) } /** Labels a Rocket Chip 'plusarg_reader' module to synthesize. Must be of the type found in * https://github.com/chipsalliance/rocket-chip/blob/master/src/main/scala/util/PlusArg.scala * * @param target * The 'plusarg_reader' module to synthesize */ def apply(target: BaseModule): Unit = { emitAnnotation(target) } } // Need serialization utils to be upstreamed to FIRRTL before i can use these. //sealed trait TriggerSourceType //case object Credit extends TriggerSourceType //case object Debit extends TriggerSourceType case class TriggerSourceAnnotation( target: ReferenceTarget, clock: ReferenceTarget, reset: Option[ReferenceTarget], sourceType: Boolean, ) extends Annotation with FAMEAnnotation { def update(renames: RenameMap): Seq[firrtl.annotations.Annotation] = { val renamer = new ReferenceTargetRenamer(renames) val renamedTarget = renamer.exactRename(target) val renamedClock = renamer.exactRename(clock) val renamedReset = reset.map(renamer.exactRename) Seq(this.copy(target = renamedTarget, clock = renamedClock, reset = renamedReset)) } def enclosingModuleTarget(): ModuleTarget = ModuleTarget(target.circuit, target.module) def enclosingModule(): String = target.module } case class TriggerSinkAnnotation( target: ReferenceTarget, clock: ReferenceTarget, ) extends Annotation with FAMEAnnotation { def update(renames: RenameMap): Seq[firrtl.annotations.Annotation] = { val renamer = new ReferenceTargetRenamer(renames) val renamedTarget = renamer.exactRename(target) val renamedClock = renamer.exactRename(clock) Seq(this.copy(target = renamedTarget, clock = renamedClock)) } def enclosingModuleTarget(): ModuleTarget = ModuleTarget(target.circuit, target.module) } object TriggerSource { private def annotateTrigger(tpe: Boolean)(target: Bool, reset: Option[Bool]): Unit = { // Hack: Create dummy nodes until chisel-side instance annotations have been improved val clock = WireDefault(Module.clock) reset.map(dontTouch.apply) requireIsHardware(target, "Target passed to TriggerSource:") reset.foreach { requireIsHardware(_, "Reset passed to TriggerSource:") } annotate(new ChiselAnnotation { def toFirrtl = TriggerSourceAnnotation(target.toNamed.toTarget, clock.toNamed.toTarget, reset.map(_.toTarget), tpe) }) } def annotateCredit = annotateTrigger(true) _ def annotateDebit = annotateTrigger(false) _ /** Methods to annotate a Boolean as a trigger credit or debit. Credits and debits issued while the module's implicit * reset is asserted are not counted. */ def credit(credit: Bool): Unit = annotateCredit(credit, Some(Module.reset.asBool)) def debit(debit: Bool): Unit = annotateDebit(debit, Some(Module.reset.asBool)) def apply(creditSig: Bool, debitSig: Bool): Unit = { credit(creditSig) debit(debitSig) } /** Variations of the above methods that count credits and debits provided while the implicit reset is asserted. */ def creditEvenUnderReset(credit: Bool): Unit = annotateCredit(credit, None) def debitEvenUnderReset(debit: Bool): Unit = annotateDebit(debit, None) def evenUnderReset(creditSig: Bool, debitSig: Bool): Unit = { creditEvenUnderReset(creditSig) debitEvenUnderReset(debitSig) } /** Level sensitive trigger sources. Implemented using [[credit]] and [[debit]]. Note: This generated hardware in your * target design. * * @param src * Enables the trigger when asserted. If no other credits have been issued since (e.g., a second level-sensitive * enable was asserted), the trigger is disabled when src is desasserted. */ def levelSensitiveEnable(src: Bool): Unit = { val srcLast = RegNext(src) credit(src && !srcLast) debit(!src && srcLast) } } object TriggerSink { /** Marks a bool as receiving the global trigger signal. * * @param target * A Bool node that will be driven with the trigger * * @param noSourceDefault * The value that the trigger signal should take on if no trigger soruces are found in the target. This is a * temporary parameter required while this apply method generates a wire. Otherwise this can be punted to the * target's RTL. */ def apply(target: Bool, noSourceDefault: => Bool = true.B): Unit = { // Hack: Create dummy nodes until chisel-side instance annotations have been improved val targetWire = WireDefault(noSourceDefault) val clock = Module.clock target := targetWire // Both the provided node and the generated one need to be dontTouched to stop // constProp from optimizing the down stream logic(?) dontTouch(target) annotate(new ChiselAnnotation { def toFirrtl = TriggerSinkAnnotation(targetWire.toTarget, clock.toTarget) }) } /** Syntatic sugar for a when context that is predicated by a trigger sink. Example usage: * {{{ * TriggerSink.whenEnabled { * printf(<...>) * } * }}} * * @param noSourceDefault * See [[TriggerSink.apply]]. */ def whenEnabled(noSourceDefault: => Bool = true.B)(elaborator: => Unit): Unit = { val sinkEnable = Wire(Bool()) apply(sinkEnable, noSourceDefault) when(sinkEnable) { elaborator } } } case class RoCCBusyFirrtlAnnotation( target: ReferenceTarget, ready: ReferenceTarget, valid: ReferenceTarget, ) extends firrtl.annotations.Annotation with FAMEAnnotation { def update(renames: RenameMap): Seq[firrtl.annotations.Annotation] = { val renamer = new ReferenceTargetRenamer(renames) val renamedReady = renamer.exactRename(ready) val renamedValid = renamer.exactRename(valid) val renamedTarget = renamer.exactRename(target) Seq(this.copy(target = renamedTarget, ready = renamedReady, valid = renamedValid)) } def enclosingModuleTarget(): ModuleTarget = ModuleTarget(target.circuit, target.module) def enclosingModule(): String = target.module } object MakeRoCCBusyLatencyInsensitive { def apply( target: Bool, ready: Bool, valid: Bool, ): Unit = { requireIsHardware(target, "Target passed to ..:") requireIsHardware(ready, "Ready passed to ..:") requireIsHardware(valid, "Valid passed to ..:") annotate(new ChiselAnnotation { def toFirrtl = RoCCBusyFirrtlAnnotation(target.toNamed.toTarget, ready.toNamed.toTarget, valid.toNamed.toTarget) }) } } case class FirrtlPartWrapperParentAnnotation( target: InstanceTarget ) extends SingleTargetAnnotation[InstanceTarget] with FAMEAnnotation { def targets = Seq(target) def duplicate(n: InstanceTarget) = this.copy(n) } case class FirrtlPortToNeighborRouterIdxAnno( target: ReferenceTarget, extractNeighborIdx: Int, removeNeighborIdx: Int, ) extends firrtl.annotations.Annotation with FAMEAnnotation { def update(renames: RenameMap): Seq[firrtl.annotations.Annotation] = { val renamer = new ReferenceTargetRenamer(renames) val renameTarget = renamer.exactRename(target) Seq(this.copy(target = renameTarget)) } } case class FirrtlCombLogicInsideModuleAnno( target: ReferenceTarget ) extends firrtl.annotations.Annotation with FAMEAnnotation { def update(renames: RenameMap): Seq[firrtl.annotations.Annotation] = { val renamer = new ReferenceTargetRenamer(renames) val renameTarget = renamer.exactRename(target) Seq(this.copy(target = renameTarget)) } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module L2MemHelperLatencyInjection_15( // @[L2MemHelperLatencyInjection.scala:29:7] input clock, // @[L2MemHelperLatencyInjection.scala:29:7] input reset, // @[L2MemHelperLatencyInjection.scala:29:7] input auto_master_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_master_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_master_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_master_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_master_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_master_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_master_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [31:0] auto_master_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [255:0] auto_master_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_master_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_master_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_master_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_master_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_master_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_master_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_master_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_master_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_master_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [255:0] auto_master_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_master_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output io_userif_req_ready, // @[L2MemHelperLatencyInjection.scala:33:14] input io_userif_req_valid, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_userif_req_bits_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [2:0] io_userif_req_bits_size, // @[L2MemHelperLatencyInjection.scala:33:14] input [255:0] io_userif_req_bits_data, // @[L2MemHelperLatencyInjection.scala:33:14] output io_userif_resp_valid, // @[L2MemHelperLatencyInjection.scala:33:14] output [255:0] io_userif_resp_bits_data, // @[L2MemHelperLatencyInjection.scala:33:14] output io_userif_no_memops_inflight, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_latency_inject_cycles, // @[L2MemHelperLatencyInjection.scala:33:14] input io_sfence, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_req_ready, // @[L2MemHelperLatencyInjection.scala:33:14] output io_ptw_req_valid, // @[L2MemHelperLatencyInjection.scala:33:14] output [26:0] io_ptw_req_bits_bits_addr, // @[L2MemHelperLatencyInjection.scala:33:14] output io_ptw_req_bits_bits_need_gpa, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_valid, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_ae_ptw, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_ae_final, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pf, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_gf, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_hr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_hw, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_hx, // @[L2MemHelperLatencyInjection.scala:33:14] input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[L2MemHelperLatencyInjection.scala:33:14] input [43:0] io_ptw_resp_bits_pte_ppn, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_d, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_g, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_u, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_r, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_v, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_resp_bits_level, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_homogeneous, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_gpa_valid, // @[L2MemHelperLatencyInjection.scala:33:14] input [38:0] io_ptw_resp_bits_gpa_bits, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_gpa_is_pte, // @[L2MemHelperLatencyInjection.scala:33:14] input [3:0] io_ptw_ptbr_mode, // @[L2MemHelperLatencyInjection.scala:33:14] input [43:0] io_ptw_ptbr_ppn, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_debug, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_cease, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_wfi, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_status_isa, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_status_dprv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_dv, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_status_prv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_v, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_mpv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_gva, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_tsr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_tw, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_tvm, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_mxr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_sum, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_mprv, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_status_fs, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_status_mpp, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_spp, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_mpie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_spie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_mie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_sie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_hstatus_spvp, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_hstatus_spv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_hstatus_gva, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_debug, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_cease, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_wfi, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_gstatus_isa, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_gstatus_dprv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_dv, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_gstatus_prv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_v, // @[L2MemHelperLatencyInjection.scala:33:14] input [22:0] io_ptw_gstatus_zero2, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_mpv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_gva, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_mbe, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_sbe, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_gstatus_sxl, // @[L2MemHelperLatencyInjection.scala:33:14] input [7:0] io_ptw_gstatus_zero1, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_tsr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_tw, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_tvm, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_mxr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_sum, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_mprv, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_gstatus_fs, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_gstatus_mpp, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_gstatus_vs, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_spp, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_mpie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_ube, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_spie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_upie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_mie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_hie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_sie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_uie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_0_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_0_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_0_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_0_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_0_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_0_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_0_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_1_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_1_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_1_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_1_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_1_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_1_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_1_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_2_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_2_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_2_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_2_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_2_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_2_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_2_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_3_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_3_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_3_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_3_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_3_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_3_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_3_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_4_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_4_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_4_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_4_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_4_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_4_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_4_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_5_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_5_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_5_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_5_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_5_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_5_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_5_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_6_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_6_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_6_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_6_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_6_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_6_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_6_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_7_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_7_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_7_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_7_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_7_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_7_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_7_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_0_ren, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_0_wen, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_0_wdata, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_0_value, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_1_ren, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_1_wen, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_1_wdata, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_1_value, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_2_ren, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_2_wen, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_2_wdata, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_2_value, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_3_ren, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_3_wen, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_3_wdata, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_3_value, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_valid, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_debug, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_cease, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_wfi, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_status_bits_isa, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_dprv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_dv, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_prv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_v, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_sd, // @[L2MemHelperLatencyInjection.scala:33:14] input [22:0] io_status_bits_zero2, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_mpv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_gva, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_mbe, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_sbe, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_sxl, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_uxl, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_sd_rv32, // @[L2MemHelperLatencyInjection.scala:33:14] input [7:0] io_status_bits_zero1, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_tsr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_tw, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_tvm, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_mxr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_sum, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_mprv, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_xs, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_fs, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_mpp, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_vs, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_spp, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_mpie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_ube, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_spie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_upie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_mie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_hie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_sie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_uie // @[L2MemHelperLatencyInjection.scala:33:14] ); wire _response_latency_injection_q_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:245:44] wire [4:0] _response_latency_injection_q_io_deq_bits_source; // @[L2MemHelperLatencyInjection.scala:245:44] wire [255:0] _response_latency_injection_q_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:245:44] wire _Queue4_L2RespInternal_31_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_31_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_31_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_30_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_30_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_30_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_29_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_29_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_29_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_28_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_28_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_28_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_27_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_27_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_27_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_26_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_26_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_26_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_25_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_25_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_25_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_24_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_24_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_24_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_23_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_23_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_23_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_22_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_22_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_22_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_21_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_21_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_21_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_20_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_20_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_20_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_19_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_19_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_19_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_18_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_18_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_18_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_17_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_17_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_17_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_16_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_16_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_16_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_15_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_15_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_15_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_14_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_14_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_14_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_13_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_13_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_13_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_12_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_12_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_12_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_11_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_11_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_11_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_10_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_10_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_10_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_9_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_9_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_9_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_8_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_8_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_8_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_7_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_7_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_7_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_6_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_6_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_6_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_5_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_5_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_5_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_4_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_4_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_4_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_3_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_3_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_3_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_2_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_2_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_2_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_1_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_1_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_1_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _request_latency_injection_q_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:151:43] wire _tags_for_issue_Q_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:94:32] wire _tags_for_issue_Q_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:94:32] wire [4:0] _tags_for_issue_Q_io_deq_bits; // @[L2MemHelperLatencyInjection.scala:94:32] wire _outstanding_req_addr_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:91:36] wire _outstanding_req_addr_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:91:36] wire [4:0] _outstanding_req_addr_io_deq_bits_addrindex; // @[L2MemHelperLatencyInjection.scala:91:36] wire [4:0] _outstanding_req_addr_io_deq_bits_tag; // @[L2MemHelperLatencyInjection.scala:91:36] wire _tlb_io_req_ready; // @[L2MemHelperLatencyInjection.scala:68:19] wire _tlb_io_resp_miss; // @[L2MemHelperLatencyInjection.scala:68:19] wire [31:0] _tlb_io_resp_paddr; // @[L2MemHelperLatencyInjection.scala:68:19] wire auto_master_out_a_ready_0 = auto_master_out_a_ready; // @[L2MemHelperLatencyInjection.scala:29:7] wire auto_master_out_d_valid_0 = auto_master_out_d_valid; // @[L2MemHelperLatencyInjection.scala:29:7] wire [2:0] auto_master_out_d_bits_opcode_0 = auto_master_out_d_bits_opcode; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] auto_master_out_d_bits_param_0 = auto_master_out_d_bits_param; // @[L2MemHelperLatencyInjection.scala:29:7] wire [3:0] auto_master_out_d_bits_size_0 = auto_master_out_d_bits_size; // @[L2MemHelperLatencyInjection.scala:29:7] wire [4:0] auto_master_out_d_bits_source_0 = auto_master_out_d_bits_source; // @[L2MemHelperLatencyInjection.scala:29:7] wire [2:0] auto_master_out_d_bits_sink_0 = auto_master_out_d_bits_sink; // @[L2MemHelperLatencyInjection.scala:29:7] wire auto_master_out_d_bits_denied_0 = auto_master_out_d_bits_denied; // @[L2MemHelperLatencyInjection.scala:29:7] wire [255:0] auto_master_out_d_bits_data_0 = auto_master_out_d_bits_data; // @[L2MemHelperLatencyInjection.scala:29:7] wire auto_master_out_d_bits_corrupt_0 = auto_master_out_d_bits_corrupt; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_userif_req_valid_0 = io_userif_req_valid; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_userif_req_bits_addr_0 = io_userif_req_bits_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [2:0] io_userif_req_bits_size_0 = io_userif_req_bits_size; // @[L2MemHelperLatencyInjection.scala:29:7] wire [255:0] io_userif_req_bits_data_0 = io_userif_req_bits_data; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_latency_inject_cycles_0 = io_latency_inject_cycles; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_sfence_0 = io_sfence; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[L2MemHelperLatencyInjection.scala:29:7] wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[L2MemHelperLatencyInjection.scala:29:7] wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[L2MemHelperLatencyInjection.scala:29:7] wire [38:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[L2MemHelperLatencyInjection.scala:29:7] wire [3:0] io_ptw_ptbr_mode_0 = io_ptw_ptbr_mode; // @[L2MemHelperLatencyInjection.scala:29:7] wire [43:0] io_ptw_ptbr_ppn_0 = io_ptw_ptbr_ppn; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_status_isa_0 = io_ptw_status_isa; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_dprv_0 = io_ptw_status_dprv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_prv_0 = io_ptw_status_prv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_v_0 = io_ptw_status_v; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_tsr_0 = io_ptw_status_tsr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_tw_0 = io_ptw_status_tw; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_tvm_0 = io_ptw_status_tvm; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_mxr_0 = io_ptw_status_mxr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_sum_0 = io_ptw_status_sum; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_mprv_0 = io_ptw_status_mprv; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_spp_0 = io_ptw_status_spp; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_spie_0 = io_ptw_status_spie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_sie_0 = io_ptw_status_sie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_spvp_0 = io_ptw_hstatus_spvp; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_spv_0 = io_ptw_hstatus_spv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_gva_0 = io_ptw_hstatus_gva; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_debug_0 = io_ptw_gstatus_debug; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_cease_0 = io_ptw_gstatus_cease; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_wfi_0 = io_ptw_gstatus_wfi; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_gstatus_isa_0 = io_ptw_gstatus_isa; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_dprv_0 = io_ptw_gstatus_dprv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_dv_0 = io_ptw_gstatus_dv; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_prv_0 = io_ptw_gstatus_prv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_v_0 = io_ptw_gstatus_v; // @[L2MemHelperLatencyInjection.scala:29:7] wire [22:0] io_ptw_gstatus_zero2_0 = io_ptw_gstatus_zero2; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_mpv_0 = io_ptw_gstatus_mpv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_gva_0 = io_ptw_gstatus_gva; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_mbe_0 = io_ptw_gstatus_mbe; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_sbe_0 = io_ptw_gstatus_sbe; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_sxl_0 = io_ptw_gstatus_sxl; // @[L2MemHelperLatencyInjection.scala:29:7] wire [7:0] io_ptw_gstatus_zero1_0 = io_ptw_gstatus_zero1; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_tsr_0 = io_ptw_gstatus_tsr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_tw_0 = io_ptw_gstatus_tw; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_tvm_0 = io_ptw_gstatus_tvm; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_mxr_0 = io_ptw_gstatus_mxr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_sum_0 = io_ptw_gstatus_sum; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_mprv_0 = io_ptw_gstatus_mprv; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_fs_0 = io_ptw_gstatus_fs; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_mpp_0 = io_ptw_gstatus_mpp; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_vs_0 = io_ptw_gstatus_vs; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_spp_0 = io_ptw_gstatus_spp; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_mpie_0 = io_ptw_gstatus_mpie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_ube_0 = io_ptw_gstatus_ube; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_spie_0 = io_ptw_gstatus_spie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_upie_0 = io_ptw_gstatus_upie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_mie_0 = io_ptw_gstatus_mie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_hie_0 = io_ptw_gstatus_hie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_sie_0 = io_ptw_gstatus_sie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_uie_0 = io_ptw_gstatus_uie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_0_cfg_l_0 = io_ptw_pmp_0_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_0_cfg_a_0 = io_ptw_pmp_0_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_0_cfg_x_0 = io_ptw_pmp_0_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_0_cfg_w_0 = io_ptw_pmp_0_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_0_cfg_r_0 = io_ptw_pmp_0_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_0_addr_0 = io_ptw_pmp_0_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_0_mask_0 = io_ptw_pmp_0_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_1_cfg_l_0 = io_ptw_pmp_1_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_1_cfg_a_0 = io_ptw_pmp_1_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_1_cfg_x_0 = io_ptw_pmp_1_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_1_cfg_w_0 = io_ptw_pmp_1_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_1_cfg_r_0 = io_ptw_pmp_1_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_1_addr_0 = io_ptw_pmp_1_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_1_mask_0 = io_ptw_pmp_1_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_2_cfg_l_0 = io_ptw_pmp_2_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_2_cfg_a_0 = io_ptw_pmp_2_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_2_cfg_x_0 = io_ptw_pmp_2_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_2_cfg_w_0 = io_ptw_pmp_2_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_2_cfg_r_0 = io_ptw_pmp_2_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_2_addr_0 = io_ptw_pmp_2_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_2_mask_0 = io_ptw_pmp_2_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_3_cfg_l_0 = io_ptw_pmp_3_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_3_cfg_a_0 = io_ptw_pmp_3_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_3_cfg_x_0 = io_ptw_pmp_3_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_3_cfg_w_0 = io_ptw_pmp_3_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_3_cfg_r_0 = io_ptw_pmp_3_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_3_addr_0 = io_ptw_pmp_3_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_3_mask_0 = io_ptw_pmp_3_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_4_cfg_l_0 = io_ptw_pmp_4_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_4_cfg_a_0 = io_ptw_pmp_4_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_4_cfg_x_0 = io_ptw_pmp_4_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_4_cfg_w_0 = io_ptw_pmp_4_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_4_cfg_r_0 = io_ptw_pmp_4_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_4_addr_0 = io_ptw_pmp_4_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_4_mask_0 = io_ptw_pmp_4_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_5_cfg_l_0 = io_ptw_pmp_5_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_5_cfg_a_0 = io_ptw_pmp_5_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_5_cfg_x_0 = io_ptw_pmp_5_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_5_cfg_w_0 = io_ptw_pmp_5_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_5_cfg_r_0 = io_ptw_pmp_5_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_5_addr_0 = io_ptw_pmp_5_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_5_mask_0 = io_ptw_pmp_5_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_6_cfg_l_0 = io_ptw_pmp_6_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_6_cfg_a_0 = io_ptw_pmp_6_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_6_cfg_x_0 = io_ptw_pmp_6_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_6_cfg_w_0 = io_ptw_pmp_6_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_6_cfg_r_0 = io_ptw_pmp_6_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_6_addr_0 = io_ptw_pmp_6_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_6_mask_0 = io_ptw_pmp_6_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_7_cfg_l_0 = io_ptw_pmp_7_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_7_cfg_a_0 = io_ptw_pmp_7_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_7_cfg_x_0 = io_ptw_pmp_7_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_7_cfg_w_0 = io_ptw_pmp_7_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_7_cfg_r_0 = io_ptw_pmp_7_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_7_addr_0 = io_ptw_pmp_7_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_7_mask_0 = io_ptw_pmp_7_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_0_ren_0 = io_ptw_customCSRs_csrs_0_ren; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_0_wen_0 = io_ptw_customCSRs_csrs_0_wen; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_0_wdata_0 = io_ptw_customCSRs_csrs_0_wdata; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_0_value_0 = io_ptw_customCSRs_csrs_0_value; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_1_ren_0 = io_ptw_customCSRs_csrs_1_ren; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_1_wen_0 = io_ptw_customCSRs_csrs_1_wen; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_1_wdata_0 = io_ptw_customCSRs_csrs_1_wdata; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_1_value_0 = io_ptw_customCSRs_csrs_1_value; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_2_ren_0 = io_ptw_customCSRs_csrs_2_ren; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_2_wen_0 = io_ptw_customCSRs_csrs_2_wen; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_2_wdata_0 = io_ptw_customCSRs_csrs_2_wdata; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_2_value_0 = io_ptw_customCSRs_csrs_2_value; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_3_ren_0 = io_ptw_customCSRs_csrs_3_ren; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_3_wen_0 = io_ptw_customCSRs_csrs_3_wen; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_3_wdata_0 = io_ptw_customCSRs_csrs_3_wdata; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_3_value_0 = io_ptw_customCSRs_csrs_3_value; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_valid_0 = io_status_valid; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_debug_0 = io_status_bits_debug; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_cease_0 = io_status_bits_cease; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_wfi_0 = io_status_bits_wfi; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_status_bits_isa_0 = io_status_bits_isa; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_dprv_0 = io_status_bits_dprv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_dv_0 = io_status_bits_dv; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_prv_0 = io_status_bits_prv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_v_0 = io_status_bits_v; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_sd_0 = io_status_bits_sd; // @[L2MemHelperLatencyInjection.scala:29:7] wire [22:0] io_status_bits_zero2_0 = io_status_bits_zero2; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_mpv_0 = io_status_bits_mpv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_gva_0 = io_status_bits_gva; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_mbe_0 = io_status_bits_mbe; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_sbe_0 = io_status_bits_sbe; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_sxl_0 = io_status_bits_sxl; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_uxl_0 = io_status_bits_uxl; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_sd_rv32_0 = io_status_bits_sd_rv32; // @[L2MemHelperLatencyInjection.scala:29:7] wire [7:0] io_status_bits_zero1_0 = io_status_bits_zero1; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_tsr_0 = io_status_bits_tsr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_tw_0 = io_status_bits_tw; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_tvm_0 = io_status_bits_tvm; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_mxr_0 = io_status_bits_mxr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_sum_0 = io_status_bits_sum; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_mprv_0 = io_status_bits_mprv; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_xs_0 = io_status_bits_xs; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_fs_0 = io_status_bits_fs; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_mpp_0 = io_status_bits_mpp; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_vs_0 = io_status_bits_vs; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_spp_0 = io_status_bits_spp; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_mpie_0 = io_status_bits_mpie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_ube_0 = io_status_bits_ube; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_spie_0 = io_status_bits_spie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_upie_0 = io_status_bits_upie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_mie_0 = io_status_bits_mie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_hie_0 = io_status_bits_hie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_sie_0 = io_status_bits_sie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_uie_0 = io_status_bits_uie; // @[L2MemHelperLatencyInjection.scala:29:7] wire _printf_T = reset; // @[annotations.scala:102:49] wire _printf_T_2 = reset; // @[annotations.scala:102:49] wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_mbe = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_sbe = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_sd_rv32 = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_ube = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_upie = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_hie = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_uie = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_vtsr = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_vtw = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_vtvm = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_hu = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_vsbe = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_2_set = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_3_set = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire bundle_corrupt = 1'h0; // @[Edges.scala:460:17] wire _legal_T_125 = 1'h0; // @[Parameters.scala:684:29] wire _legal_T_131 = 1'h0; // @[Parameters.scala:684:54] wire bundle_1_corrupt = 1'h0; // @[Edges.scala:480:17] wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_userif_req_bits_cmd = 1'h1; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_userif_resp_ready = 1'h1; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_req_bits_valid = 1'h1; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_sd = 1'h1; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_sd = 1'h1; // @[L2MemHelperLatencyInjection.scala:29:7] wire request_input_bits_cmd = 1'h1; // @[L2MemHelperLatencyInjection.scala:44:27] wire response_output_ready = 1'h1; // @[L2MemHelperLatencyInjection.scala:53:29] wire _legal_T = 1'h1; // @[Parameters.scala:92:28] wire _legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _legal_T_63 = 1'h1; // @[Parameters.scala:92:28] wire _legal_T_64 = 1'h1; // @[Parameters.scala:92:38] wire _legal_T_65 = 1'h1; // @[Parameters.scala:92:33] wire _legal_T_66 = 1'h1; // @[Parameters.scala:684:29] wire _legal_T_73 = 1'h1; // @[Parameters.scala:92:28] wire [22:0] io_ptw_status_zero2 = 23'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [7:0] io_ptw_status_zero1 = 8'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_xs = 2'h3; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_xs = 2'h3; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_vs = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_sxl = 2'h2; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_uxl = 2'h2; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_hstatus_vsxl = 2'h2; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_uxl = 2'h2; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [2:0] bundle_param = 3'h0; // @[Edges.scala:460:17] wire [2:0] bundle_1_opcode = 3'h0; // @[Edges.scala:480:17] wire [2:0] bundle_1_param = 3'h0; // @[Edges.scala:480:17] wire [255:0] bundle_data = 256'h0; // @[Edges.scala:460:17] wire [2:0] bundle_opcode = 3'h4; // @[Edges.scala:460:17] wire masterNodeOut_a_ready = auto_master_out_a_ready_0; // @[MixedNode.scala:542:17] wire masterNodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] masterNodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] masterNodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] masterNodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [4:0] masterNodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] masterNodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] masterNodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [255:0] masterNodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire masterNodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire masterNodeOut_d_ready; // @[MixedNode.scala:542:17] wire masterNodeOut_d_valid = auto_master_out_d_valid_0; // @[MixedNode.scala:542:17] wire [2:0] masterNodeOut_d_bits_opcode = auto_master_out_d_bits_opcode_0; // @[MixedNode.scala:542:17] wire [1:0] masterNodeOut_d_bits_param = auto_master_out_d_bits_param_0; // @[MixedNode.scala:542:17] wire [3:0] masterNodeOut_d_bits_size = auto_master_out_d_bits_size_0; // @[MixedNode.scala:542:17] wire [4:0] masterNodeOut_d_bits_source = auto_master_out_d_bits_source_0; // @[MixedNode.scala:542:17] wire [2:0] masterNodeOut_d_bits_sink = auto_master_out_d_bits_sink_0; // @[MixedNode.scala:542:17] wire masterNodeOut_d_bits_denied = auto_master_out_d_bits_denied_0; // @[MixedNode.scala:542:17] wire [255:0] masterNodeOut_d_bits_data = auto_master_out_d_bits_data_0; // @[MixedNode.scala:542:17] wire masterNodeOut_d_bits_corrupt = auto_master_out_d_bits_corrupt_0; // @[MixedNode.scala:542:17] wire request_input_ready; // @[L2MemHelperLatencyInjection.scala:44:27] wire request_input_valid = io_userif_req_valid_0; // @[L2MemHelperLatencyInjection.scala:29:7, :44:27] wire [63:0] request_input_bits_addr = io_userif_req_bits_addr_0; // @[L2MemHelperLatencyInjection.scala:29:7, :44:27] wire [2:0] request_input_bits_size = io_userif_req_bits_size_0; // @[L2MemHelperLatencyInjection.scala:29:7, :44:27] wire [255:0] request_input_bits_data = io_userif_req_bits_data_0; // @[L2MemHelperLatencyInjection.scala:29:7, :44:27] wire response_output_valid; // @[L2MemHelperLatencyInjection.scala:53:29] wire [255:0] response_output_bits_data; // @[L2MemHelperLatencyInjection.scala:53:29] wire _io_userif_no_memops_inflight_T; // @[L2MemHelperLatencyInjection.scala:128:57] wire [2:0] auto_master_out_a_bits_opcode_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [2:0] auto_master_out_a_bits_param_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [3:0] auto_master_out_a_bits_size_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [4:0] auto_master_out_a_bits_source_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] auto_master_out_a_bits_address_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] auto_master_out_a_bits_mask_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [255:0] auto_master_out_a_bits_data_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire auto_master_out_a_bits_corrupt_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire auto_master_out_a_valid_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire auto_master_out_d_ready_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_userif_req_ready_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [255:0] io_userif_resp_bits_data_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_userif_resp_valid_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_userif_no_memops_inflight_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [26:0] io_ptw_req_bits_bits_addr_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_req_bits_bits_need_gpa_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_req_valid_0; // @[L2MemHelperLatencyInjection.scala:29:7] assign auto_master_out_a_valid_0 = masterNodeOut_a_valid; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_opcode_0 = masterNodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_param_0 = masterNodeOut_a_bits_param; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_size_0 = masterNodeOut_a_bits_size; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_source_0 = masterNodeOut_a_bits_source; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_address_0 = masterNodeOut_a_bits_address; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_mask_0 = masterNodeOut_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_data_0 = masterNodeOut_a_bits_data; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_corrupt_0 = masterNodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign auto_master_out_d_ready_0 = masterNodeOut_d_ready; // @[MixedNode.scala:542:17] wire _request_input_ready_T_4; // @[Misc.scala:26:53] assign io_userif_req_ready_0 = request_input_ready; // @[L2MemHelperLatencyInjection.scala:29:7, :44:27] wire _response_output_valid_T; // @[Misc.scala:26:53] assign io_userif_resp_valid_0 = response_output_valid; // @[L2MemHelperLatencyInjection.scala:29:7, :53:29] wire [255:0] resultdata; // @[L2MemHelperLatencyInjection.scala:307:15] assign io_userif_resp_bits_data_0 = response_output_bits_data; // @[L2MemHelperLatencyInjection.scala:29:7, :53:29] reg status_debug; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_cease; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_wfi; // @[L2MemHelperLatencyInjection.scala:62:19] reg [31:0] status_isa; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_dprv; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_dv; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_prv; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_v; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_sd; // @[L2MemHelperLatencyInjection.scala:62:19] reg [22:0] status_zero2; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_mpv; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_gva; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_mbe; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_sbe; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_sxl; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_uxl; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_sd_rv32; // @[L2MemHelperLatencyInjection.scala:62:19] reg [7:0] status_zero1; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_tsr; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_tw; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_tvm; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_mxr; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_sum; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_mprv; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_xs; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_fs; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_mpp; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_vs; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_spp; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_mpie; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_ube; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_spie; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_upie; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_mie; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_hie; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_sie; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_uie; // @[L2MemHelperLatencyInjection.scala:62:19] reg [63:0] loginfo_cycles; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T = {1'h0, loginfo_cycles} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1 = _loginfo_cycles_T[63:0]; // @[Util.scala:19:38] wire _tlb_ready_T = ~_tlb_io_resp_miss; // @[L2MemHelperLatencyInjection.scala:68:19, :74:39] wire tlb_ready = _tlb_io_req_ready & _tlb_ready_T; // @[L2MemHelperLatencyInjection.scala:68:19, :74:{36,39}] reg [5:0] tags_init_reg; // @[L2MemHelperLatencyInjection.scala:98:30] wire _T_4 = tags_init_reg != 6'h20; // @[L2MemHelperLatencyInjection.scala:98:30, :99:23] reg [63:0] loginfo_cycles_1; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_2 = {1'h0, loginfo_cycles_1} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_3 = _loginfo_cycles_T_2[63:0]; // @[Util.scala:19:38] wire [6:0] _tags_init_reg_T = {1'h0, tags_init_reg} + 7'h1; // @[L2MemHelperLatencyInjection.scala:98:30, :104:38] wire [5:0] _tags_init_reg_T_1 = _tags_init_reg_T[5:0]; // @[L2MemHelperLatencyInjection.scala:104:38] wire [70:0] _addr_mask_check_T = 71'h1 << request_input_bits_size; // @[L2MemHelperLatencyInjection.scala:44:27, :108:36] wire [71:0] _addr_mask_check_T_1 = {1'h0, _addr_mask_check_T} - 72'h1; // @[L2MemHelperLatencyInjection.scala:108:{36,64}] wire [70:0] addr_mask_check = _addr_mask_check_T_1[70:0]; // @[L2MemHelperLatencyInjection.scala:108:64] wire _assertcheck_T = ~request_input_valid; // @[L2MemHelperLatencyInjection.scala:44:27, :109:30] wire [70:0] _assertcheck_T_1 = {7'h0, addr_mask_check[63:0] & request_input_bits_addr}; // @[L2MemHelperLatencyInjection.scala:44:27, :108:64, :109:81] wire _assertcheck_T_2 = _assertcheck_T_1 == 71'h0; // @[L2MemHelperLatencyInjection.scala:108:64, :109:{81,100}] wire _assertcheck_T_3 = _assertcheck_T | _assertcheck_T_2; // @[L2MemHelperLatencyInjection.scala:109:{30,52,100}] reg assertcheck; // @[L2MemHelperLatencyInjection.scala:109:28] reg [63:0] loginfo_cycles_2; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_4 = {1'h0, loginfo_cycles_2} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_5 = _loginfo_cycles_T_4[63:0]; // @[Util.scala:19:38] reg [63:0] global_memop_accepted; // @[L2MemHelperLatencyInjection.scala:117:38] wire [64:0] _global_memop_accepted_T = {1'h0, global_memop_accepted} + 65'h1; // @[L2MemHelperLatencyInjection.scala:117:38, :119:52] wire [63:0] _global_memop_accepted_T_1 = _global_memop_accepted_T[63:0]; // @[L2MemHelperLatencyInjection.scala:119:52] reg [63:0] global_memop_sent; // @[L2MemHelperLatencyInjection.scala:122:34] reg [63:0] global_memop_ackd; // @[L2MemHelperLatencyInjection.scala:124:34] reg [63:0] global_memop_resp_to_user; // @[L2MemHelperLatencyInjection.scala:126:42] assign _io_userif_no_memops_inflight_T = global_memop_accepted == global_memop_ackd; // @[L2MemHelperLatencyInjection.scala:117:38, :124:34, :128:57] assign io_userif_no_memops_inflight_0 = _io_userif_no_memops_inflight_T; // @[L2MemHelperLatencyInjection.scala:29:7, :128:57] wire [64:0] _GEN = {1'h0, global_memop_sent}; // @[L2MemHelperLatencyInjection.scala:122:34, :130:54] wire [64:0] _GEN_0 = {1'h0, global_memop_ackd}; // @[L2MemHelperLatencyInjection.scala:124:34, :130:54] wire [64:0] _GEN_1 = _GEN - _GEN_0; // @[L2MemHelperLatencyInjection.scala:130:54] wire [64:0] _free_outstanding_op_slots_T; // @[L2MemHelperLatencyInjection.scala:130:54] assign _free_outstanding_op_slots_T = _GEN_1; // @[L2MemHelperLatencyInjection.scala:130:54] wire [64:0] _assert_free_outstanding_op_slots_T; // @[L2MemHelperLatencyInjection.scala:131:61] assign _assert_free_outstanding_op_slots_T = _GEN_1; // @[L2MemHelperLatencyInjection.scala:130:54, :131:61] wire [63:0] _free_outstanding_op_slots_T_1 = _free_outstanding_op_slots_T[63:0]; // @[L2MemHelperLatencyInjection.scala:130:54] wire free_outstanding_op_slots = _free_outstanding_op_slots_T_1 < 64'h20; // @[L2MemHelperLatencyInjection.scala:130:{54,75}] wire [63:0] _assert_free_outstanding_op_slots_T_1 = _assert_free_outstanding_op_slots_T[63:0]; // @[L2MemHelperLatencyInjection.scala:131:61] wire assert_free_outstanding_op_slots = _assert_free_outstanding_op_slots_T_1 < 64'h21; // @[L2MemHelperLatencyInjection.scala:131:{61,82}] reg [63:0] loginfo_cycles_3; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_6 = {1'h0, loginfo_cycles_3} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_7 = _loginfo_cycles_T_6[63:0]; // @[Util.scala:19:38] wire [64:0] _global_memop_sent_T = _GEN + 65'h1; // @[L2MemHelperLatencyInjection.scala:130:54, :140:44] wire [63:0] _global_memop_sent_T_1 = _global_memop_sent_T[63:0]; // @[L2MemHelperLatencyInjection.scala:140:44] reg [63:0] cur_cycle; // @[L2MemHelperLatencyInjection.scala:146:26] wire [64:0] _cur_cycle_T = {1'h0, cur_cycle} + 65'h1; // @[L2MemHelperLatencyInjection.scala:146:26, :147:26] wire [63:0] _cur_cycle_T_1 = _cur_cycle_T[63:0]; // @[L2MemHelperLatencyInjection.scala:147:26] wire [31:0] _GEN_2 = {_tlb_io_resp_paddr[31:14], _tlb_io_resp_paddr[13:0] ^ 14'h3000}; // @[Parameters.scala:137:31] wire [31:0] _legal_T_4; // @[Parameters.scala:137:31] assign _legal_T_4 = _GEN_2; // @[Parameters.scala:137:31] wire [31:0] _legal_T_67; // @[Parameters.scala:137:31] assign _legal_T_67 = _GEN_2; // @[Parameters.scala:137:31] wire [32:0] _legal_T_5 = {1'h0, _legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_6 = _legal_T_5 & 33'h9A013000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_7 = _legal_T_6; // @[Parameters.scala:137:46] wire _legal_T_8 = _legal_T_7 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_T_9 = _legal_T_8; // @[Parameters.scala:684:54] wire _legal_T_62 = _legal_T_9; // @[Parameters.scala:684:54, :686:26] wire _GEN_3 = request_input_bits_size != 3'h7; // @[Parameters.scala:92:38] wire _legal_T_11; // @[Parameters.scala:92:38] assign _legal_T_11 = _GEN_3; // @[Parameters.scala:92:38] wire _legal_T_74; // @[Parameters.scala:92:38] assign _legal_T_74 = _GEN_3; // @[Parameters.scala:92:38] wire _legal_T_12 = _legal_T_11; // @[Parameters.scala:92:{33,38}] wire _legal_T_13 = _legal_T_12; // @[Parameters.scala:684:29] wire [31:0] _legal_T_14; // @[Parameters.scala:137:31] wire [32:0] _legal_T_15 = {1'h0, _legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_16 = _legal_T_15 & 33'h9A012000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_17 = _legal_T_16; // @[Parameters.scala:137:46] wire _legal_T_18 = _legal_T_17 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_4 = {_tlb_io_resp_paddr[31:17], _tlb_io_resp_paddr[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31] wire [31:0] _legal_T_19; // @[Parameters.scala:137:31] assign _legal_T_19 = _GEN_4; // @[Parameters.scala:137:31] wire [31:0] _legal_T_24; // @[Parameters.scala:137:31] assign _legal_T_24 = _GEN_4; // @[Parameters.scala:137:31] wire [31:0] _legal_T_126; // @[Parameters.scala:137:31] assign _legal_T_126 = _GEN_4; // @[Parameters.scala:137:31] wire [32:0] _legal_T_20 = {1'h0, _legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_21 = _legal_T_20 & 33'h98013000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_22 = _legal_T_21; // @[Parameters.scala:137:46] wire _legal_T_23 = _legal_T_22 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_25 = {1'h0, _legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_26 = _legal_T_25 & 33'h9A010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_27 = _legal_T_26; // @[Parameters.scala:137:46] wire _legal_T_28 = _legal_T_27 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_5 = {_tlb_io_resp_paddr[31:26], _tlb_io_resp_paddr[25:0] ^ 26'h2000000}; // @[Parameters.scala:137:31] wire [31:0] _legal_T_29; // @[Parameters.scala:137:31] assign _legal_T_29 = _GEN_5; // @[Parameters.scala:137:31] wire [31:0] _legal_T_87; // @[Parameters.scala:137:31] assign _legal_T_87 = _GEN_5; // @[Parameters.scala:137:31] wire [32:0] _legal_T_30 = {1'h0, _legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_31 = _legal_T_30 & 33'h9A010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_32 = _legal_T_31; // @[Parameters.scala:137:46] wire _legal_T_33 = _legal_T_32 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_6 = {_tlb_io_resp_paddr[31:28], _tlb_io_resp_paddr[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31] wire [31:0] _legal_T_34; // @[Parameters.scala:137:31] assign _legal_T_34 = _GEN_6; // @[Parameters.scala:137:31] wire [31:0] _legal_T_39; // @[Parameters.scala:137:31] assign _legal_T_39 = _GEN_6; // @[Parameters.scala:137:31] wire [31:0] _legal_T_97; // @[Parameters.scala:137:31] assign _legal_T_97 = _GEN_6; // @[Parameters.scala:137:31] wire [31:0] _legal_T_102; // @[Parameters.scala:137:31] assign _legal_T_102 = _GEN_6; // @[Parameters.scala:137:31] wire [32:0] _legal_T_35 = {1'h0, _legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_36 = _legal_T_35 & 33'h98000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_37 = _legal_T_36; // @[Parameters.scala:137:46] wire _legal_T_38 = _legal_T_37 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_40 = {1'h0, _legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_41 = _legal_T_40 & 33'h9A010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_42 = _legal_T_41; // @[Parameters.scala:137:46] wire _legal_T_43 = _legal_T_42 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_7 = {_tlb_io_resp_paddr[31:29], _tlb_io_resp_paddr[28:0] ^ 29'h10000000}; // @[Parameters.scala:137:31] wire [31:0] _legal_T_44; // @[Parameters.scala:137:31] assign _legal_T_44 = _GEN_7; // @[Parameters.scala:137:31] wire [31:0] _legal_T_107; // @[Parameters.scala:137:31] assign _legal_T_107 = _GEN_7; // @[Parameters.scala:137:31] wire [32:0] _legal_T_45 = {1'h0, _legal_T_44}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_46 = _legal_T_45 & 33'h9A013000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_47 = _legal_T_46; // @[Parameters.scala:137:46] wire _legal_T_48 = _legal_T_47 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_8 = _tlb_io_resp_paddr ^ 32'h80000000; // @[Parameters.scala:137:31] wire [31:0] _legal_T_49; // @[Parameters.scala:137:31] assign _legal_T_49 = _GEN_8; // @[Parameters.scala:137:31] wire [31:0] _legal_T_112; // @[Parameters.scala:137:31] assign _legal_T_112 = _GEN_8; // @[Parameters.scala:137:31] wire [32:0] _legal_T_50 = {1'h0, _legal_T_49}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_51 = _legal_T_50 & 33'h90000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_52 = _legal_T_51; // @[Parameters.scala:137:46] wire _legal_T_53 = _legal_T_52 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_T_54 = _legal_T_18 | _legal_T_23; // @[Parameters.scala:685:42] wire _legal_T_55 = _legal_T_54 | _legal_T_28; // @[Parameters.scala:685:42] wire _legal_T_56 = _legal_T_55 | _legal_T_33; // @[Parameters.scala:685:42] wire _legal_T_57 = _legal_T_56 | _legal_T_38; // @[Parameters.scala:685:42] wire _legal_T_58 = _legal_T_57 | _legal_T_43; // @[Parameters.scala:685:42] wire _legal_T_59 = _legal_T_58 | _legal_T_48; // @[Parameters.scala:685:42] wire _legal_T_60 = _legal_T_59 | _legal_T_53; // @[Parameters.scala:685:42] wire _legal_T_61 = _legal_T_13 & _legal_T_60; // @[Parameters.scala:684:{29,54}, :685:42] wire legal = _legal_T_62 | _legal_T_61; // @[Parameters.scala:684:54, :686:26] wire [31:0] _a_mask_T; // @[Misc.scala:222:10] wire [3:0] bundle_size; // @[Edges.scala:460:17] wire [4:0] bundle_source; // @[Edges.scala:460:17] wire [31:0] bundle_address; // @[Edges.scala:460:17] wire [31:0] bundle_mask; // @[Edges.scala:460:17] wire [3:0] _GEN_9 = {1'h0, request_input_bits_size}; // @[Edges.scala:463:15] assign bundle_size = _GEN_9; // @[Edges.scala:460:17, :463:15] wire [3:0] bundle_1_size; // @[Edges.scala:480:17] assign bundle_1_size = _GEN_9; // @[Edges.scala:463:15, :480:17] wire [4:0] _GEN_10 = {2'h0, request_input_bits_size}; // @[Misc.scala:202:34] wire [4:0] _a_mask_sizeOH_T; // @[Misc.scala:202:34] assign _a_mask_sizeOH_T = _GEN_10; // @[Misc.scala:202:34] wire [4:0] _a_mask_sizeOH_T_3; // @[Misc.scala:202:34] assign _a_mask_sizeOH_T_3 = _GEN_10; // @[Misc.scala:202:34] wire [4:0] _a_mask_sizeOH_shiftAmount_T = _a_mask_sizeOH_T; // @[OneHot.scala:64:31] wire [2:0] a_mask_sizeOH_shiftAmount = _a_mask_sizeOH_shiftAmount_T[2:0]; // @[OneHot.scala:64:{31,49}] wire [7:0] _a_mask_sizeOH_T_1 = 8'h1 << a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [4:0] _a_mask_sizeOH_T_2 = _a_mask_sizeOH_T_1[4:0]; // @[OneHot.scala:65:{12,27}] wire [4:0] a_mask_sizeOH = {_a_mask_sizeOH_T_2[4:1], 1'h1}; // @[OneHot.scala:65:27] wire _GEN_11 = request_input_bits_size > 3'h4; // @[Misc.scala:206:21] wire a_mask_sub_sub_sub_sub_sub_0_1; // @[Misc.scala:206:21] assign a_mask_sub_sub_sub_sub_sub_0_1 = _GEN_11; // @[Misc.scala:206:21] wire a_mask_sub_sub_sub_sub_sub_0_1_1; // @[Misc.scala:206:21] assign a_mask_sub_sub_sub_sub_sub_0_1_1 = _GEN_11; // @[Misc.scala:206:21] wire a_mask_sub_sub_sub_sub_size = a_mask_sizeOH[4]; // @[Misc.scala:202:81, :209:26] wire a_mask_sub_sub_sub_sub_bit = _tlb_io_resp_paddr[4]; // @[Misc.scala:210:26] wire a_mask_sub_sub_sub_sub_bit_1 = _tlb_io_resp_paddr[4]; // @[Misc.scala:210:26] wire a_mask_sub_sub_sub_sub_1_2 = a_mask_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_sub_sub_sub_nbit = ~a_mask_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_sub_sub_sub_0_2 = a_mask_sub_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_sub_sub_acc_T = a_mask_sub_sub_sub_sub_size & a_mask_sub_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_sub_0_1 = a_mask_sub_sub_sub_sub_sub_0_1 | _a_mask_sub_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _a_mask_sub_sub_sub_sub_acc_T_1 = a_mask_sub_sub_sub_sub_size & a_mask_sub_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_sub_1_1 = a_mask_sub_sub_sub_sub_sub_0_1 | _a_mask_sub_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire a_mask_sub_sub_sub_size = a_mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire a_mask_sub_sub_sub_bit = _tlb_io_resp_paddr[3]; // @[Misc.scala:210:26] wire a_mask_sub_sub_sub_bit_1 = _tlb_io_resp_paddr[3]; // @[Misc.scala:210:26] wire a_mask_sub_sub_sub_nbit = ~a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_sub_sub_0_2 = a_mask_sub_sub_sub_sub_0_2 & a_mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_sub_acc_T = a_mask_sub_sub_sub_size & a_mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_0_1 = a_mask_sub_sub_sub_sub_0_1 | _a_mask_sub_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_sub_1_2 = a_mask_sub_sub_sub_sub_0_2 & a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_sub_acc_T_1 = a_mask_sub_sub_sub_size & a_mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_1_1 = a_mask_sub_sub_sub_sub_0_1 | _a_mask_sub_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_sub_2_2 = a_mask_sub_sub_sub_sub_1_2 & a_mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_sub_acc_T_2 = a_mask_sub_sub_sub_size & a_mask_sub_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_2_1 = a_mask_sub_sub_sub_sub_1_1 | _a_mask_sub_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_sub_3_2 = a_mask_sub_sub_sub_sub_1_2 & a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_sub_acc_T_3 = a_mask_sub_sub_sub_size & a_mask_sub_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_3_1 = a_mask_sub_sub_sub_sub_1_1 | _a_mask_sub_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_size = a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire a_mask_sub_sub_bit = _tlb_io_resp_paddr[2]; // @[Misc.scala:210:26] wire a_mask_sub_sub_bit_1 = _tlb_io_resp_paddr[2]; // @[Misc.scala:210:26] wire a_mask_sub_sub_nbit = ~a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_sub_0_2 = a_mask_sub_sub_sub_0_2 & a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_acc_T = a_mask_sub_sub_size & a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_0_1 = a_mask_sub_sub_sub_0_1 | _a_mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_1_2 = a_mask_sub_sub_sub_0_2 & a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_acc_T_1 = a_mask_sub_sub_size & a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_1_1 = a_mask_sub_sub_sub_0_1 | _a_mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_2_2 = a_mask_sub_sub_sub_1_2 & a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_acc_T_2 = a_mask_sub_sub_size & a_mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_2_1 = a_mask_sub_sub_sub_1_1 | _a_mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_3_2 = a_mask_sub_sub_sub_1_2 & a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_acc_T_3 = a_mask_sub_sub_size & a_mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_3_1 = a_mask_sub_sub_sub_1_1 | _a_mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_4_2 = a_mask_sub_sub_sub_2_2 & a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_acc_T_4 = a_mask_sub_sub_size & a_mask_sub_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_4_1 = a_mask_sub_sub_sub_2_1 | _a_mask_sub_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_5_2 = a_mask_sub_sub_sub_2_2 & a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_acc_T_5 = a_mask_sub_sub_size & a_mask_sub_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_5_1 = a_mask_sub_sub_sub_2_1 | _a_mask_sub_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_6_2 = a_mask_sub_sub_sub_3_2 & a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_acc_T_6 = a_mask_sub_sub_size & a_mask_sub_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_6_1 = a_mask_sub_sub_sub_3_1 | _a_mask_sub_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_7_2 = a_mask_sub_sub_sub_3_2 & a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_acc_T_7 = a_mask_sub_sub_size & a_mask_sub_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_7_1 = a_mask_sub_sub_sub_3_1 | _a_mask_sub_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire a_mask_sub_size = a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire a_mask_sub_bit = _tlb_io_resp_paddr[1]; // @[Misc.scala:210:26] wire a_mask_sub_bit_1 = _tlb_io_resp_paddr[1]; // @[Misc.scala:210:26] wire a_mask_sub_nbit = ~a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_0_2 = a_mask_sub_sub_0_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T = a_mask_sub_size & a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_0_1 = a_mask_sub_sub_0_1 | _a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire a_mask_sub_1_2 = a_mask_sub_sub_0_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_1 = a_mask_sub_size & a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_1_1 = a_mask_sub_sub_0_1 | _a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire a_mask_sub_2_2 = a_mask_sub_sub_1_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_2 = a_mask_sub_size & a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_2_1 = a_mask_sub_sub_1_1 | _a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire a_mask_sub_3_2 = a_mask_sub_sub_1_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_3 = a_mask_sub_size & a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_3_1 = a_mask_sub_sub_1_1 | _a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire a_mask_sub_4_2 = a_mask_sub_sub_2_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_4 = a_mask_sub_size & a_mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_4_1 = a_mask_sub_sub_2_1 | _a_mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire a_mask_sub_5_2 = a_mask_sub_sub_2_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_5 = a_mask_sub_size & a_mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_5_1 = a_mask_sub_sub_2_1 | _a_mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire a_mask_sub_6_2 = a_mask_sub_sub_3_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_6 = a_mask_sub_size & a_mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_6_1 = a_mask_sub_sub_3_1 | _a_mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire a_mask_sub_7_2 = a_mask_sub_sub_3_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_7 = a_mask_sub_size & a_mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_7_1 = a_mask_sub_sub_3_1 | _a_mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire a_mask_sub_8_2 = a_mask_sub_sub_4_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_8 = a_mask_sub_size & a_mask_sub_8_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_8_1 = a_mask_sub_sub_4_1 | _a_mask_sub_acc_T_8; // @[Misc.scala:215:{29,38}] wire a_mask_sub_9_2 = a_mask_sub_sub_4_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_9 = a_mask_sub_size & a_mask_sub_9_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_9_1 = a_mask_sub_sub_4_1 | _a_mask_sub_acc_T_9; // @[Misc.scala:215:{29,38}] wire a_mask_sub_10_2 = a_mask_sub_sub_5_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_10 = a_mask_sub_size & a_mask_sub_10_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_10_1 = a_mask_sub_sub_5_1 | _a_mask_sub_acc_T_10; // @[Misc.scala:215:{29,38}] wire a_mask_sub_11_2 = a_mask_sub_sub_5_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_11 = a_mask_sub_size & a_mask_sub_11_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_11_1 = a_mask_sub_sub_5_1 | _a_mask_sub_acc_T_11; // @[Misc.scala:215:{29,38}] wire a_mask_sub_12_2 = a_mask_sub_sub_6_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_12 = a_mask_sub_size & a_mask_sub_12_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_12_1 = a_mask_sub_sub_6_1 | _a_mask_sub_acc_T_12; // @[Misc.scala:215:{29,38}] wire a_mask_sub_13_2 = a_mask_sub_sub_6_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_13 = a_mask_sub_size & a_mask_sub_13_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_13_1 = a_mask_sub_sub_6_1 | _a_mask_sub_acc_T_13; // @[Misc.scala:215:{29,38}] wire a_mask_sub_14_2 = a_mask_sub_sub_7_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_14 = a_mask_sub_size & a_mask_sub_14_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_14_1 = a_mask_sub_sub_7_1 | _a_mask_sub_acc_T_14; // @[Misc.scala:215:{29,38}] wire a_mask_sub_15_2 = a_mask_sub_sub_7_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_15 = a_mask_sub_size & a_mask_sub_15_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_15_1 = a_mask_sub_sub_7_1 | _a_mask_sub_acc_T_15; // @[Misc.scala:215:{29,38}] wire a_mask_size = a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire a_mask_bit = _tlb_io_resp_paddr[0]; // @[Misc.scala:210:26] wire a_mask_bit_1 = _tlb_io_resp_paddr[0]; // @[Misc.scala:210:26] wire a_mask_nbit = ~a_mask_bit; // @[Misc.scala:210:26, :211:20] wire a_mask_eq = a_mask_sub_0_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T = a_mask_size & a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc = a_mask_sub_0_1 | _a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire a_mask_eq_1 = a_mask_sub_0_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_1 = a_mask_size & a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_1 = a_mask_sub_0_1 | _a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire a_mask_eq_2 = a_mask_sub_1_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_2 = a_mask_size & a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_2 = a_mask_sub_1_1 | _a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire a_mask_eq_3 = a_mask_sub_1_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_3 = a_mask_size & a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_3 = a_mask_sub_1_1 | _a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire a_mask_eq_4 = a_mask_sub_2_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_4 = a_mask_size & a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_4 = a_mask_sub_2_1 | _a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire a_mask_eq_5 = a_mask_sub_2_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_5 = a_mask_size & a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_5 = a_mask_sub_2_1 | _a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire a_mask_eq_6 = a_mask_sub_3_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_6 = a_mask_size & a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_6 = a_mask_sub_3_1 | _a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire a_mask_eq_7 = a_mask_sub_3_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_7 = a_mask_size & a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_7 = a_mask_sub_3_1 | _a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire a_mask_eq_8 = a_mask_sub_4_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_8 = a_mask_size & a_mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_8 = a_mask_sub_4_1 | _a_mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire a_mask_eq_9 = a_mask_sub_4_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_9 = a_mask_size & a_mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_9 = a_mask_sub_4_1 | _a_mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire a_mask_eq_10 = a_mask_sub_5_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_10 = a_mask_size & a_mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_10 = a_mask_sub_5_1 | _a_mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire a_mask_eq_11 = a_mask_sub_5_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_11 = a_mask_size & a_mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_11 = a_mask_sub_5_1 | _a_mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire a_mask_eq_12 = a_mask_sub_6_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_12 = a_mask_size & a_mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_12 = a_mask_sub_6_1 | _a_mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire a_mask_eq_13 = a_mask_sub_6_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_13 = a_mask_size & a_mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_13 = a_mask_sub_6_1 | _a_mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire a_mask_eq_14 = a_mask_sub_7_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_14 = a_mask_size & a_mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_14 = a_mask_sub_7_1 | _a_mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire a_mask_eq_15 = a_mask_sub_7_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_15 = a_mask_size & a_mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_15 = a_mask_sub_7_1 | _a_mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire a_mask_eq_16 = a_mask_sub_8_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_16 = a_mask_size & a_mask_eq_16; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_16 = a_mask_sub_8_1 | _a_mask_acc_T_16; // @[Misc.scala:215:{29,38}] wire a_mask_eq_17 = a_mask_sub_8_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_17 = a_mask_size & a_mask_eq_17; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_17 = a_mask_sub_8_1 | _a_mask_acc_T_17; // @[Misc.scala:215:{29,38}] wire a_mask_eq_18 = a_mask_sub_9_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_18 = a_mask_size & a_mask_eq_18; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_18 = a_mask_sub_9_1 | _a_mask_acc_T_18; // @[Misc.scala:215:{29,38}] wire a_mask_eq_19 = a_mask_sub_9_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_19 = a_mask_size & a_mask_eq_19; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_19 = a_mask_sub_9_1 | _a_mask_acc_T_19; // @[Misc.scala:215:{29,38}] wire a_mask_eq_20 = a_mask_sub_10_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_20 = a_mask_size & a_mask_eq_20; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_20 = a_mask_sub_10_1 | _a_mask_acc_T_20; // @[Misc.scala:215:{29,38}] wire a_mask_eq_21 = a_mask_sub_10_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_21 = a_mask_size & a_mask_eq_21; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_21 = a_mask_sub_10_1 | _a_mask_acc_T_21; // @[Misc.scala:215:{29,38}] wire a_mask_eq_22 = a_mask_sub_11_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_22 = a_mask_size & a_mask_eq_22; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_22 = a_mask_sub_11_1 | _a_mask_acc_T_22; // @[Misc.scala:215:{29,38}] wire a_mask_eq_23 = a_mask_sub_11_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_23 = a_mask_size & a_mask_eq_23; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_23 = a_mask_sub_11_1 | _a_mask_acc_T_23; // @[Misc.scala:215:{29,38}] wire a_mask_eq_24 = a_mask_sub_12_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_24 = a_mask_size & a_mask_eq_24; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_24 = a_mask_sub_12_1 | _a_mask_acc_T_24; // @[Misc.scala:215:{29,38}] wire a_mask_eq_25 = a_mask_sub_12_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_25 = a_mask_size & a_mask_eq_25; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_25 = a_mask_sub_12_1 | _a_mask_acc_T_25; // @[Misc.scala:215:{29,38}] wire a_mask_eq_26 = a_mask_sub_13_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_26 = a_mask_size & a_mask_eq_26; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_26 = a_mask_sub_13_1 | _a_mask_acc_T_26; // @[Misc.scala:215:{29,38}] wire a_mask_eq_27 = a_mask_sub_13_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_27 = a_mask_size & a_mask_eq_27; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_27 = a_mask_sub_13_1 | _a_mask_acc_T_27; // @[Misc.scala:215:{29,38}] wire a_mask_eq_28 = a_mask_sub_14_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_28 = a_mask_size & a_mask_eq_28; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_28 = a_mask_sub_14_1 | _a_mask_acc_T_28; // @[Misc.scala:215:{29,38}] wire a_mask_eq_29 = a_mask_sub_14_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_29 = a_mask_size & a_mask_eq_29; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_29 = a_mask_sub_14_1 | _a_mask_acc_T_29; // @[Misc.scala:215:{29,38}] wire a_mask_eq_30 = a_mask_sub_15_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_30 = a_mask_size & a_mask_eq_30; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_30 = a_mask_sub_15_1 | _a_mask_acc_T_30; // @[Misc.scala:215:{29,38}] wire a_mask_eq_31 = a_mask_sub_15_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_31 = a_mask_size & a_mask_eq_31; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_31 = a_mask_sub_15_1 | _a_mask_acc_T_31; // @[Misc.scala:215:{29,38}] wire [1:0] a_mask_lo_lo_lo_lo = {a_mask_acc_1, a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_lo_lo_lo_hi = {a_mask_acc_3, a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_lo_lo_lo = {a_mask_lo_lo_lo_hi, a_mask_lo_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_lo_hi_lo = {a_mask_acc_5, a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_lo_lo_hi_hi = {a_mask_acc_7, a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_lo_lo_hi = {a_mask_lo_lo_hi_hi, a_mask_lo_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] a_mask_lo_lo = {a_mask_lo_lo_hi, a_mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_hi_lo_lo = {a_mask_acc_9, a_mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_lo_hi_lo_hi = {a_mask_acc_11, a_mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_lo_hi_lo = {a_mask_lo_hi_lo_hi, a_mask_lo_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_hi_hi_lo = {a_mask_acc_13, a_mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_lo_hi_hi_hi = {a_mask_acc_15, a_mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_lo_hi_hi = {a_mask_lo_hi_hi_hi, a_mask_lo_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] a_mask_lo_hi = {a_mask_lo_hi_hi, a_mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [15:0] a_mask_lo = {a_mask_lo_hi, a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_lo_lo_lo = {a_mask_acc_17, a_mask_acc_16}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_hi_lo_lo_hi = {a_mask_acc_19, a_mask_acc_18}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_hi_lo_lo = {a_mask_hi_lo_lo_hi, a_mask_hi_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_lo_hi_lo = {a_mask_acc_21, a_mask_acc_20}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_hi_lo_hi_hi = {a_mask_acc_23, a_mask_acc_22}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_hi_lo_hi = {a_mask_hi_lo_hi_hi, a_mask_hi_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] a_mask_hi_lo = {a_mask_hi_lo_hi, a_mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_hi_lo_lo = {a_mask_acc_25, a_mask_acc_24}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_hi_hi_lo_hi = {a_mask_acc_27, a_mask_acc_26}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_hi_hi_lo = {a_mask_hi_hi_lo_hi, a_mask_hi_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_hi_hi_lo = {a_mask_acc_29, a_mask_acc_28}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_hi_hi_hi_hi = {a_mask_acc_31, a_mask_acc_30}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_hi_hi_hi = {a_mask_hi_hi_hi_hi, a_mask_hi_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] a_mask_hi_hi = {a_mask_hi_hi_hi, a_mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [15:0] a_mask_hi = {a_mask_hi_hi, a_mask_hi_lo}; // @[Misc.scala:222:10] assign _a_mask_T = {a_mask_hi, a_mask_lo}; // @[Misc.scala:222:10] assign bundle_mask = _a_mask_T; // @[Misc.scala:222:10] wire [510:0] _T_31 = {255'h0, request_input_bits_data} << {503'h0, request_input_bits_addr[4:0], 3'h0}; // @[L2MemHelperLatencyInjection.scala:44:27, :172:{58,86}] wire [32:0] _legal_T_68 = {1'h0, _legal_T_67}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_69 = _legal_T_68 & 33'h9A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_70 = _legal_T_69; // @[Parameters.scala:137:46] wire _legal_T_71 = _legal_T_70 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_T_72 = _legal_T_71; // @[Parameters.scala:684:54] wire _legal_T_132 = _legal_T_72; // @[Parameters.scala:684:54, :686:26] wire _legal_T_75 = _legal_T_74; // @[Parameters.scala:92:{33,38}] wire _legal_T_76 = _legal_T_75; // @[Parameters.scala:684:29] wire [31:0] _legal_T_77; // @[Parameters.scala:137:31] wire [32:0] _legal_T_78 = {1'h0, _legal_T_77}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_79 = _legal_T_78 & 33'h9A112000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_80 = _legal_T_79; // @[Parameters.scala:137:46] wire _legal_T_81 = _legal_T_80 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _legal_T_82 = {_tlb_io_resp_paddr[31:21], _tlb_io_resp_paddr[20:0] ^ 21'h100000}; // @[Parameters.scala:137:31] wire [32:0] _legal_T_83 = {1'h0, _legal_T_82}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_84 = _legal_T_83 & 33'h9A103000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_85 = _legal_T_84; // @[Parameters.scala:137:46] wire _legal_T_86 = _legal_T_85 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_88 = {1'h0, _legal_T_87}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_89 = _legal_T_88 & 33'h9A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_90 = _legal_T_89; // @[Parameters.scala:137:46] wire _legal_T_91 = _legal_T_90 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _legal_T_92 = {_tlb_io_resp_paddr[31:26], _tlb_io_resp_paddr[25:0] ^ 26'h2010000}; // @[Parameters.scala:137:31] wire [32:0] _legal_T_93 = {1'h0, _legal_T_92}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_94 = _legal_T_93 & 33'h9A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_95 = _legal_T_94; // @[Parameters.scala:137:46] wire _legal_T_96 = _legal_T_95 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_98 = {1'h0, _legal_T_97}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_99 = _legal_T_98 & 33'h98000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_100 = _legal_T_99; // @[Parameters.scala:137:46] wire _legal_T_101 = _legal_T_100 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_103 = {1'h0, _legal_T_102}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_104 = _legal_T_103 & 33'h9A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_105 = _legal_T_104; // @[Parameters.scala:137:46] wire _legal_T_106 = _legal_T_105 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_108 = {1'h0, _legal_T_107}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_109 = _legal_T_108 & 33'h9A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_110 = _legal_T_109; // @[Parameters.scala:137:46] wire _legal_T_111 = _legal_T_110 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_113 = {1'h0, _legal_T_112}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_114 = _legal_T_113 & 33'h90000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_115 = _legal_T_114; // @[Parameters.scala:137:46] wire _legal_T_116 = _legal_T_115 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_T_117 = _legal_T_81 | _legal_T_86; // @[Parameters.scala:685:42] wire _legal_T_118 = _legal_T_117 | _legal_T_91; // @[Parameters.scala:685:42] wire _legal_T_119 = _legal_T_118 | _legal_T_96; // @[Parameters.scala:685:42] wire _legal_T_120 = _legal_T_119 | _legal_T_101; // @[Parameters.scala:685:42] wire _legal_T_121 = _legal_T_120 | _legal_T_106; // @[Parameters.scala:685:42] wire _legal_T_122 = _legal_T_121 | _legal_T_111; // @[Parameters.scala:685:42] wire _legal_T_123 = _legal_T_122 | _legal_T_116; // @[Parameters.scala:685:42] wire _legal_T_124 = _legal_T_76 & _legal_T_123; // @[Parameters.scala:684:{29,54}, :685:42] wire [32:0] _legal_T_127 = {1'h0, _legal_T_126}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_128 = _legal_T_127 & 33'h9A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_129 = _legal_T_128; // @[Parameters.scala:137:46] wire _legal_T_130 = _legal_T_129 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_T_133 = _legal_T_132 | _legal_T_124; // @[Parameters.scala:684:54, :686:26] wire legal_1 = _legal_T_133; // @[Parameters.scala:686:26] wire [31:0] _a_mask_T_1; // @[Misc.scala:222:10] wire [4:0] bundle_1_source; // @[Edges.scala:480:17] wire [31:0] bundle_1_address; // @[Edges.scala:480:17] wire [31:0] bundle_1_mask; // @[Edges.scala:480:17] wire [255:0] bundle_1_data; // @[Edges.scala:480:17] wire [4:0] _a_mask_sizeOH_shiftAmount_T_1 = _a_mask_sizeOH_T_3; // @[OneHot.scala:64:31] wire [2:0] a_mask_sizeOH_shiftAmount_1 = _a_mask_sizeOH_shiftAmount_T_1[2:0]; // @[OneHot.scala:64:{31,49}] wire [7:0] _a_mask_sizeOH_T_4 = 8'h1 << a_mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12] wire [4:0] _a_mask_sizeOH_T_5 = _a_mask_sizeOH_T_4[4:0]; // @[OneHot.scala:65:{12,27}] wire [4:0] a_mask_sizeOH_1 = {_a_mask_sizeOH_T_5[4:1], 1'h1}; // @[OneHot.scala:65:27] wire a_mask_sub_sub_sub_sub_size_1 = a_mask_sizeOH_1[4]; // @[Misc.scala:202:81, :209:26] wire a_mask_sub_sub_sub_sub_1_2_1 = a_mask_sub_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_sub_sub_sub_nbit_1 = ~a_mask_sub_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_sub_sub_sub_0_2_1 = a_mask_sub_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_sub_sub_acc_T_2 = a_mask_sub_sub_sub_sub_size_1 & a_mask_sub_sub_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_sub_0_1_1 = a_mask_sub_sub_sub_sub_sub_0_1_1 | _a_mask_sub_sub_sub_sub_acc_T_2; // @[Misc.scala:206:21, :215:{29,38}] wire _a_mask_sub_sub_sub_sub_acc_T_3 = a_mask_sub_sub_sub_sub_size_1 & a_mask_sub_sub_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_sub_1_1_1 = a_mask_sub_sub_sub_sub_sub_0_1_1 | _a_mask_sub_sub_sub_sub_acc_T_3; // @[Misc.scala:206:21, :215:{29,38}] wire a_mask_sub_sub_sub_size_1 = a_mask_sizeOH_1[3]; // @[Misc.scala:202:81, :209:26] wire a_mask_sub_sub_sub_nbit_1 = ~a_mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_sub_sub_0_2_1 = a_mask_sub_sub_sub_sub_0_2_1 & a_mask_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_sub_acc_T_4 = a_mask_sub_sub_sub_size_1 & a_mask_sub_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_0_1_1 = a_mask_sub_sub_sub_sub_0_1_1 | _a_mask_sub_sub_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_sub_1_2_1 = a_mask_sub_sub_sub_sub_0_2_1 & a_mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_sub_acc_T_5 = a_mask_sub_sub_sub_size_1 & a_mask_sub_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_1_1_1 = a_mask_sub_sub_sub_sub_0_1_1 | _a_mask_sub_sub_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_sub_2_2_1 = a_mask_sub_sub_sub_sub_1_2_1 & a_mask_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_sub_acc_T_6 = a_mask_sub_sub_sub_size_1 & a_mask_sub_sub_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_2_1_1 = a_mask_sub_sub_sub_sub_1_1_1 | _a_mask_sub_sub_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_sub_3_2_1 = a_mask_sub_sub_sub_sub_1_2_1 & a_mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_sub_acc_T_7 = a_mask_sub_sub_sub_size_1 & a_mask_sub_sub_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_3_1_1 = a_mask_sub_sub_sub_sub_1_1_1 | _a_mask_sub_sub_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_size_1 = a_mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26] wire a_mask_sub_sub_nbit_1 = ~a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_sub_0_2_1 = a_mask_sub_sub_sub_0_2_1 & a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_acc_T_8 = a_mask_sub_sub_size_1 & a_mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_0_1_1 = a_mask_sub_sub_sub_0_1_1 | _a_mask_sub_sub_acc_T_8; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_1_2_1 = a_mask_sub_sub_sub_0_2_1 & a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_acc_T_9 = a_mask_sub_sub_size_1 & a_mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_1_1_1 = a_mask_sub_sub_sub_0_1_1 | _a_mask_sub_sub_acc_T_9; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_2_2_1 = a_mask_sub_sub_sub_1_2_1 & a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_acc_T_10 = a_mask_sub_sub_size_1 & a_mask_sub_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_2_1_1 = a_mask_sub_sub_sub_1_1_1 | _a_mask_sub_sub_acc_T_10; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_3_2_1 = a_mask_sub_sub_sub_1_2_1 & a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_acc_T_11 = a_mask_sub_sub_size_1 & a_mask_sub_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_3_1_1 = a_mask_sub_sub_sub_1_1_1 | _a_mask_sub_sub_acc_T_11; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_4_2_1 = a_mask_sub_sub_sub_2_2_1 & a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_acc_T_12 = a_mask_sub_sub_size_1 & a_mask_sub_sub_4_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_4_1_1 = a_mask_sub_sub_sub_2_1_1 | _a_mask_sub_sub_acc_T_12; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_5_2_1 = a_mask_sub_sub_sub_2_2_1 & a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_acc_T_13 = a_mask_sub_sub_size_1 & a_mask_sub_sub_5_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_5_1_1 = a_mask_sub_sub_sub_2_1_1 | _a_mask_sub_sub_acc_T_13; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_6_2_1 = a_mask_sub_sub_sub_3_2_1 & a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_acc_T_14 = a_mask_sub_sub_size_1 & a_mask_sub_sub_6_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_6_1_1 = a_mask_sub_sub_sub_3_1_1 | _a_mask_sub_sub_acc_T_14; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_7_2_1 = a_mask_sub_sub_sub_3_2_1 & a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_acc_T_15 = a_mask_sub_sub_size_1 & a_mask_sub_sub_7_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_7_1_1 = a_mask_sub_sub_sub_3_1_1 | _a_mask_sub_sub_acc_T_15; // @[Misc.scala:215:{29,38}] wire a_mask_sub_size_1 = a_mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26] wire a_mask_sub_nbit_1 = ~a_mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_0_2_1 = a_mask_sub_sub_0_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_16 = a_mask_sub_size_1 & a_mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_0_1_1 = a_mask_sub_sub_0_1_1 | _a_mask_sub_acc_T_16; // @[Misc.scala:215:{29,38}] wire a_mask_sub_1_2_1 = a_mask_sub_sub_0_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_17 = a_mask_sub_size_1 & a_mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_1_1_1 = a_mask_sub_sub_0_1_1 | _a_mask_sub_acc_T_17; // @[Misc.scala:215:{29,38}] wire a_mask_sub_2_2_1 = a_mask_sub_sub_1_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_18 = a_mask_sub_size_1 & a_mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_2_1_1 = a_mask_sub_sub_1_1_1 | _a_mask_sub_acc_T_18; // @[Misc.scala:215:{29,38}] wire a_mask_sub_3_2_1 = a_mask_sub_sub_1_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_19 = a_mask_sub_size_1 & a_mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_3_1_1 = a_mask_sub_sub_1_1_1 | _a_mask_sub_acc_T_19; // @[Misc.scala:215:{29,38}] wire a_mask_sub_4_2_1 = a_mask_sub_sub_2_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_20 = a_mask_sub_size_1 & a_mask_sub_4_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_4_1_1 = a_mask_sub_sub_2_1_1 | _a_mask_sub_acc_T_20; // @[Misc.scala:215:{29,38}] wire a_mask_sub_5_2_1 = a_mask_sub_sub_2_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_21 = a_mask_sub_size_1 & a_mask_sub_5_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_5_1_1 = a_mask_sub_sub_2_1_1 | _a_mask_sub_acc_T_21; // @[Misc.scala:215:{29,38}] wire a_mask_sub_6_2_1 = a_mask_sub_sub_3_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_22 = a_mask_sub_size_1 & a_mask_sub_6_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_6_1_1 = a_mask_sub_sub_3_1_1 | _a_mask_sub_acc_T_22; // @[Misc.scala:215:{29,38}] wire a_mask_sub_7_2_1 = a_mask_sub_sub_3_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_23 = a_mask_sub_size_1 & a_mask_sub_7_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_7_1_1 = a_mask_sub_sub_3_1_1 | _a_mask_sub_acc_T_23; // @[Misc.scala:215:{29,38}] wire a_mask_sub_8_2_1 = a_mask_sub_sub_4_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_24 = a_mask_sub_size_1 & a_mask_sub_8_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_8_1_1 = a_mask_sub_sub_4_1_1 | _a_mask_sub_acc_T_24; // @[Misc.scala:215:{29,38}] wire a_mask_sub_9_2_1 = a_mask_sub_sub_4_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_25 = a_mask_sub_size_1 & a_mask_sub_9_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_9_1_1 = a_mask_sub_sub_4_1_1 | _a_mask_sub_acc_T_25; // @[Misc.scala:215:{29,38}] wire a_mask_sub_10_2_1 = a_mask_sub_sub_5_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_26 = a_mask_sub_size_1 & a_mask_sub_10_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_10_1_1 = a_mask_sub_sub_5_1_1 | _a_mask_sub_acc_T_26; // @[Misc.scala:215:{29,38}] wire a_mask_sub_11_2_1 = a_mask_sub_sub_5_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_27 = a_mask_sub_size_1 & a_mask_sub_11_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_11_1_1 = a_mask_sub_sub_5_1_1 | _a_mask_sub_acc_T_27; // @[Misc.scala:215:{29,38}] wire a_mask_sub_12_2_1 = a_mask_sub_sub_6_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_28 = a_mask_sub_size_1 & a_mask_sub_12_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_12_1_1 = a_mask_sub_sub_6_1_1 | _a_mask_sub_acc_T_28; // @[Misc.scala:215:{29,38}] wire a_mask_sub_13_2_1 = a_mask_sub_sub_6_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_29 = a_mask_sub_size_1 & a_mask_sub_13_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_13_1_1 = a_mask_sub_sub_6_1_1 | _a_mask_sub_acc_T_29; // @[Misc.scala:215:{29,38}] wire a_mask_sub_14_2_1 = a_mask_sub_sub_7_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_30 = a_mask_sub_size_1 & a_mask_sub_14_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_14_1_1 = a_mask_sub_sub_7_1_1 | _a_mask_sub_acc_T_30; // @[Misc.scala:215:{29,38}] wire a_mask_sub_15_2_1 = a_mask_sub_sub_7_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_31 = a_mask_sub_size_1 & a_mask_sub_15_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_15_1_1 = a_mask_sub_sub_7_1_1 | _a_mask_sub_acc_T_31; // @[Misc.scala:215:{29,38}] wire a_mask_size_1 = a_mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26] wire a_mask_nbit_1 = ~a_mask_bit_1; // @[Misc.scala:210:26, :211:20] wire a_mask_eq_32 = a_mask_sub_0_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_32 = a_mask_size_1 & a_mask_eq_32; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_32 = a_mask_sub_0_1_1 | _a_mask_acc_T_32; // @[Misc.scala:215:{29,38}] wire a_mask_eq_33 = a_mask_sub_0_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_33 = a_mask_size_1 & a_mask_eq_33; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_33 = a_mask_sub_0_1_1 | _a_mask_acc_T_33; // @[Misc.scala:215:{29,38}] wire a_mask_eq_34 = a_mask_sub_1_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_34 = a_mask_size_1 & a_mask_eq_34; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_34 = a_mask_sub_1_1_1 | _a_mask_acc_T_34; // @[Misc.scala:215:{29,38}] wire a_mask_eq_35 = a_mask_sub_1_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_35 = a_mask_size_1 & a_mask_eq_35; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_35 = a_mask_sub_1_1_1 | _a_mask_acc_T_35; // @[Misc.scala:215:{29,38}] wire a_mask_eq_36 = a_mask_sub_2_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_36 = a_mask_size_1 & a_mask_eq_36; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_36 = a_mask_sub_2_1_1 | _a_mask_acc_T_36; // @[Misc.scala:215:{29,38}] wire a_mask_eq_37 = a_mask_sub_2_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_37 = a_mask_size_1 & a_mask_eq_37; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_37 = a_mask_sub_2_1_1 | _a_mask_acc_T_37; // @[Misc.scala:215:{29,38}] wire a_mask_eq_38 = a_mask_sub_3_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_38 = a_mask_size_1 & a_mask_eq_38; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_38 = a_mask_sub_3_1_1 | _a_mask_acc_T_38; // @[Misc.scala:215:{29,38}] wire a_mask_eq_39 = a_mask_sub_3_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_39 = a_mask_size_1 & a_mask_eq_39; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_39 = a_mask_sub_3_1_1 | _a_mask_acc_T_39; // @[Misc.scala:215:{29,38}] wire a_mask_eq_40 = a_mask_sub_4_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_40 = a_mask_size_1 & a_mask_eq_40; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_40 = a_mask_sub_4_1_1 | _a_mask_acc_T_40; // @[Misc.scala:215:{29,38}] wire a_mask_eq_41 = a_mask_sub_4_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_41 = a_mask_size_1 & a_mask_eq_41; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_41 = a_mask_sub_4_1_1 | _a_mask_acc_T_41; // @[Misc.scala:215:{29,38}] wire a_mask_eq_42 = a_mask_sub_5_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_42 = a_mask_size_1 & a_mask_eq_42; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_42 = a_mask_sub_5_1_1 | _a_mask_acc_T_42; // @[Misc.scala:215:{29,38}] wire a_mask_eq_43 = a_mask_sub_5_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_43 = a_mask_size_1 & a_mask_eq_43; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_43 = a_mask_sub_5_1_1 | _a_mask_acc_T_43; // @[Misc.scala:215:{29,38}] wire a_mask_eq_44 = a_mask_sub_6_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_44 = a_mask_size_1 & a_mask_eq_44; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_44 = a_mask_sub_6_1_1 | _a_mask_acc_T_44; // @[Misc.scala:215:{29,38}] wire a_mask_eq_45 = a_mask_sub_6_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_45 = a_mask_size_1 & a_mask_eq_45; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_45 = a_mask_sub_6_1_1 | _a_mask_acc_T_45; // @[Misc.scala:215:{29,38}] wire a_mask_eq_46 = a_mask_sub_7_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_46 = a_mask_size_1 & a_mask_eq_46; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_46 = a_mask_sub_7_1_1 | _a_mask_acc_T_46; // @[Misc.scala:215:{29,38}] wire a_mask_eq_47 = a_mask_sub_7_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_47 = a_mask_size_1 & a_mask_eq_47; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_47 = a_mask_sub_7_1_1 | _a_mask_acc_T_47; // @[Misc.scala:215:{29,38}] wire a_mask_eq_48 = a_mask_sub_8_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_48 = a_mask_size_1 & a_mask_eq_48; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_48 = a_mask_sub_8_1_1 | _a_mask_acc_T_48; // @[Misc.scala:215:{29,38}] wire a_mask_eq_49 = a_mask_sub_8_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_49 = a_mask_size_1 & a_mask_eq_49; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_49 = a_mask_sub_8_1_1 | _a_mask_acc_T_49; // @[Misc.scala:215:{29,38}] wire a_mask_eq_50 = a_mask_sub_9_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_50 = a_mask_size_1 & a_mask_eq_50; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_50 = a_mask_sub_9_1_1 | _a_mask_acc_T_50; // @[Misc.scala:215:{29,38}] wire a_mask_eq_51 = a_mask_sub_9_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_51 = a_mask_size_1 & a_mask_eq_51; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_51 = a_mask_sub_9_1_1 | _a_mask_acc_T_51; // @[Misc.scala:215:{29,38}] wire a_mask_eq_52 = a_mask_sub_10_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_52 = a_mask_size_1 & a_mask_eq_52; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_52 = a_mask_sub_10_1_1 | _a_mask_acc_T_52; // @[Misc.scala:215:{29,38}] wire a_mask_eq_53 = a_mask_sub_10_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_53 = a_mask_size_1 & a_mask_eq_53; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_53 = a_mask_sub_10_1_1 | _a_mask_acc_T_53; // @[Misc.scala:215:{29,38}] wire a_mask_eq_54 = a_mask_sub_11_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_54 = a_mask_size_1 & a_mask_eq_54; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_54 = a_mask_sub_11_1_1 | _a_mask_acc_T_54; // @[Misc.scala:215:{29,38}] wire a_mask_eq_55 = a_mask_sub_11_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_55 = a_mask_size_1 & a_mask_eq_55; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_55 = a_mask_sub_11_1_1 | _a_mask_acc_T_55; // @[Misc.scala:215:{29,38}] wire a_mask_eq_56 = a_mask_sub_12_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_56 = a_mask_size_1 & a_mask_eq_56; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_56 = a_mask_sub_12_1_1 | _a_mask_acc_T_56; // @[Misc.scala:215:{29,38}] wire a_mask_eq_57 = a_mask_sub_12_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_57 = a_mask_size_1 & a_mask_eq_57; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_57 = a_mask_sub_12_1_1 | _a_mask_acc_T_57; // @[Misc.scala:215:{29,38}] wire a_mask_eq_58 = a_mask_sub_13_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_58 = a_mask_size_1 & a_mask_eq_58; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_58 = a_mask_sub_13_1_1 | _a_mask_acc_T_58; // @[Misc.scala:215:{29,38}] wire a_mask_eq_59 = a_mask_sub_13_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_59 = a_mask_size_1 & a_mask_eq_59; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_59 = a_mask_sub_13_1_1 | _a_mask_acc_T_59; // @[Misc.scala:215:{29,38}] wire a_mask_eq_60 = a_mask_sub_14_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_60 = a_mask_size_1 & a_mask_eq_60; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_60 = a_mask_sub_14_1_1 | _a_mask_acc_T_60; // @[Misc.scala:215:{29,38}] wire a_mask_eq_61 = a_mask_sub_14_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_61 = a_mask_size_1 & a_mask_eq_61; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_61 = a_mask_sub_14_1_1 | _a_mask_acc_T_61; // @[Misc.scala:215:{29,38}] wire a_mask_eq_62 = a_mask_sub_15_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_62 = a_mask_size_1 & a_mask_eq_62; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_62 = a_mask_sub_15_1_1 | _a_mask_acc_T_62; // @[Misc.scala:215:{29,38}] wire a_mask_eq_63 = a_mask_sub_15_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_63 = a_mask_size_1 & a_mask_eq_63; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_63 = a_mask_sub_15_1_1 | _a_mask_acc_T_63; // @[Misc.scala:215:{29,38}] wire [1:0] a_mask_lo_lo_lo_lo_1 = {a_mask_acc_33, a_mask_acc_32}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_lo_lo_lo_hi_1 = {a_mask_acc_35, a_mask_acc_34}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_lo_lo_lo_1 = {a_mask_lo_lo_lo_hi_1, a_mask_lo_lo_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_lo_hi_lo_1 = {a_mask_acc_37, a_mask_acc_36}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_lo_lo_hi_hi_1 = {a_mask_acc_39, a_mask_acc_38}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_lo_lo_hi_1 = {a_mask_lo_lo_hi_hi_1, a_mask_lo_lo_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] a_mask_lo_lo_1 = {a_mask_lo_lo_hi_1, a_mask_lo_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_hi_lo_lo_1 = {a_mask_acc_41, a_mask_acc_40}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_lo_hi_lo_hi_1 = {a_mask_acc_43, a_mask_acc_42}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_lo_hi_lo_1 = {a_mask_lo_hi_lo_hi_1, a_mask_lo_hi_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_hi_hi_lo_1 = {a_mask_acc_45, a_mask_acc_44}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_lo_hi_hi_hi_1 = {a_mask_acc_47, a_mask_acc_46}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_lo_hi_hi_1 = {a_mask_lo_hi_hi_hi_1, a_mask_lo_hi_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] a_mask_lo_hi_1 = {a_mask_lo_hi_hi_1, a_mask_lo_hi_lo_1}; // @[Misc.scala:222:10] wire [15:0] a_mask_lo_1 = {a_mask_lo_hi_1, a_mask_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_lo_lo_lo_1 = {a_mask_acc_49, a_mask_acc_48}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_hi_lo_lo_hi_1 = {a_mask_acc_51, a_mask_acc_50}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_hi_lo_lo_1 = {a_mask_hi_lo_lo_hi_1, a_mask_hi_lo_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_lo_hi_lo_1 = {a_mask_acc_53, a_mask_acc_52}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_hi_lo_hi_hi_1 = {a_mask_acc_55, a_mask_acc_54}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_hi_lo_hi_1 = {a_mask_hi_lo_hi_hi_1, a_mask_hi_lo_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] a_mask_hi_lo_1 = {a_mask_hi_lo_hi_1, a_mask_hi_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_hi_lo_lo_1 = {a_mask_acc_57, a_mask_acc_56}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_hi_hi_lo_hi_1 = {a_mask_acc_59, a_mask_acc_58}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_hi_hi_lo_1 = {a_mask_hi_hi_lo_hi_1, a_mask_hi_hi_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_hi_hi_lo_1 = {a_mask_acc_61, a_mask_acc_60}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_hi_hi_hi_hi_1 = {a_mask_acc_63, a_mask_acc_62}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_hi_hi_hi_1 = {a_mask_hi_hi_hi_hi_1, a_mask_hi_hi_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] a_mask_hi_hi_1 = {a_mask_hi_hi_hi_1, a_mask_hi_hi_lo_1}; // @[Misc.scala:222:10] wire [15:0] a_mask_hi_1 = {a_mask_hi_hi_1, a_mask_hi_lo_1}; // @[Misc.scala:222:10] assign _a_mask_T_1 = {a_mask_hi_1, a_mask_lo_1}; // @[Misc.scala:222:10] assign bundle_1_mask = _a_mask_T_1; // @[Misc.scala:222:10] assign bundle_1_data = _T_31[255:0]; // @[Edges.scala:480:17, :489:15] reg [63:0] loginfo_cycles_4; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_8 = {1'h0, loginfo_cycles_4} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_9 = _loginfo_cycles_T_8[63:0]; // @[Util.scala:19:38] wire _current_request_tag_has_response_space_T = _tags_for_issue_Q_io_deq_bits == 5'h0; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_1 = _Queue4_L2RespInternal_io_enq_ready & _current_request_tag_has_response_space_T; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_2 = _tags_for_issue_Q_io_deq_bits == 5'h1; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_3 = _Queue4_L2RespInternal_1_io_enq_ready & _current_request_tag_has_response_space_T_2; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_4 = _tags_for_issue_Q_io_deq_bits == 5'h2; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_5 = _Queue4_L2RespInternal_2_io_enq_ready & _current_request_tag_has_response_space_T_4; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_6 = _tags_for_issue_Q_io_deq_bits == 5'h3; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_7 = _Queue4_L2RespInternal_3_io_enq_ready & _current_request_tag_has_response_space_T_6; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_8 = _tags_for_issue_Q_io_deq_bits == 5'h4; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_9 = _Queue4_L2RespInternal_4_io_enq_ready & _current_request_tag_has_response_space_T_8; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_10 = _tags_for_issue_Q_io_deq_bits == 5'h5; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_11 = _Queue4_L2RespInternal_5_io_enq_ready & _current_request_tag_has_response_space_T_10; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_12 = _tags_for_issue_Q_io_deq_bits == 5'h6; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_13 = _Queue4_L2RespInternal_6_io_enq_ready & _current_request_tag_has_response_space_T_12; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_14 = _tags_for_issue_Q_io_deq_bits == 5'h7; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_15 = _Queue4_L2RespInternal_7_io_enq_ready & _current_request_tag_has_response_space_T_14; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_16 = _tags_for_issue_Q_io_deq_bits == 5'h8; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_17 = _Queue4_L2RespInternal_8_io_enq_ready & _current_request_tag_has_response_space_T_16; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_18 = _tags_for_issue_Q_io_deq_bits == 5'h9; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_19 = _Queue4_L2RespInternal_9_io_enq_ready & _current_request_tag_has_response_space_T_18; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_20 = _tags_for_issue_Q_io_deq_bits == 5'hA; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_21 = _Queue4_L2RespInternal_10_io_enq_ready & _current_request_tag_has_response_space_T_20; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_22 = _tags_for_issue_Q_io_deq_bits == 5'hB; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_23 = _Queue4_L2RespInternal_11_io_enq_ready & _current_request_tag_has_response_space_T_22; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_24 = _tags_for_issue_Q_io_deq_bits == 5'hC; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_25 = _Queue4_L2RespInternal_12_io_enq_ready & _current_request_tag_has_response_space_T_24; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_26 = _tags_for_issue_Q_io_deq_bits == 5'hD; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_27 = _Queue4_L2RespInternal_13_io_enq_ready & _current_request_tag_has_response_space_T_26; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_28 = _tags_for_issue_Q_io_deq_bits == 5'hE; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_29 = _Queue4_L2RespInternal_14_io_enq_ready & _current_request_tag_has_response_space_T_28; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_30 = _tags_for_issue_Q_io_deq_bits == 5'hF; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_31 = _Queue4_L2RespInternal_15_io_enq_ready & _current_request_tag_has_response_space_T_30; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_32 = _tags_for_issue_Q_io_deq_bits == 5'h10; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_33 = _Queue4_L2RespInternal_16_io_enq_ready & _current_request_tag_has_response_space_T_32; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_34 = _tags_for_issue_Q_io_deq_bits == 5'h11; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_35 = _Queue4_L2RespInternal_17_io_enq_ready & _current_request_tag_has_response_space_T_34; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_36 = _tags_for_issue_Q_io_deq_bits == 5'h12; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_37 = _Queue4_L2RespInternal_18_io_enq_ready & _current_request_tag_has_response_space_T_36; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_38 = _tags_for_issue_Q_io_deq_bits == 5'h13; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_39 = _Queue4_L2RespInternal_19_io_enq_ready & _current_request_tag_has_response_space_T_38; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_40 = _tags_for_issue_Q_io_deq_bits == 5'h14; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_41 = _Queue4_L2RespInternal_20_io_enq_ready & _current_request_tag_has_response_space_T_40; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_42 = _tags_for_issue_Q_io_deq_bits == 5'h15; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_43 = _Queue4_L2RespInternal_21_io_enq_ready & _current_request_tag_has_response_space_T_42; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_44 = _tags_for_issue_Q_io_deq_bits == 5'h16; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_45 = _Queue4_L2RespInternal_22_io_enq_ready & _current_request_tag_has_response_space_T_44; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_46 = _tags_for_issue_Q_io_deq_bits == 5'h17; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_47 = _Queue4_L2RespInternal_23_io_enq_ready & _current_request_tag_has_response_space_T_46; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_48 = _tags_for_issue_Q_io_deq_bits == 5'h18; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_49 = _Queue4_L2RespInternal_24_io_enq_ready & _current_request_tag_has_response_space_T_48; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_50 = _tags_for_issue_Q_io_deq_bits == 5'h19; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_51 = _Queue4_L2RespInternal_25_io_enq_ready & _current_request_tag_has_response_space_T_50; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_52 = _tags_for_issue_Q_io_deq_bits == 5'h1A; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_53 = _Queue4_L2RespInternal_26_io_enq_ready & _current_request_tag_has_response_space_T_52; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_54 = _tags_for_issue_Q_io_deq_bits == 5'h1B; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_55 = _Queue4_L2RespInternal_27_io_enq_ready & _current_request_tag_has_response_space_T_54; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_56 = _tags_for_issue_Q_io_deq_bits == 5'h1C; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_57 = _Queue4_L2RespInternal_28_io_enq_ready & _current_request_tag_has_response_space_T_56; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_58 = _tags_for_issue_Q_io_deq_bits == 5'h1D; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_59 = _Queue4_L2RespInternal_29_io_enq_ready & _current_request_tag_has_response_space_T_58; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_60 = _tags_for_issue_Q_io_deq_bits == 5'h1E; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_61 = _Queue4_L2RespInternal_30_io_enq_ready & _current_request_tag_has_response_space_T_60; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_62 = &_tags_for_issue_Q_io_deq_bits; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_63 = _Queue4_L2RespInternal_31_io_enq_ready & _current_request_tag_has_response_space_T_62; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_64 = _current_request_tag_has_response_space_T_1 | _current_request_tag_has_response_space_T_3; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_65 = _current_request_tag_has_response_space_T_64 | _current_request_tag_has_response_space_T_5; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_66 = _current_request_tag_has_response_space_T_65 | _current_request_tag_has_response_space_T_7; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_67 = _current_request_tag_has_response_space_T_66 | _current_request_tag_has_response_space_T_9; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_68 = _current_request_tag_has_response_space_T_67 | _current_request_tag_has_response_space_T_11; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_69 = _current_request_tag_has_response_space_T_68 | _current_request_tag_has_response_space_T_13; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_70 = _current_request_tag_has_response_space_T_69 | _current_request_tag_has_response_space_T_15; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_71 = _current_request_tag_has_response_space_T_70 | _current_request_tag_has_response_space_T_17; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_72 = _current_request_tag_has_response_space_T_71 | _current_request_tag_has_response_space_T_19; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_73 = _current_request_tag_has_response_space_T_72 | _current_request_tag_has_response_space_T_21; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_74 = _current_request_tag_has_response_space_T_73 | _current_request_tag_has_response_space_T_23; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_75 = _current_request_tag_has_response_space_T_74 | _current_request_tag_has_response_space_T_25; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_76 = _current_request_tag_has_response_space_T_75 | _current_request_tag_has_response_space_T_27; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_77 = _current_request_tag_has_response_space_T_76 | _current_request_tag_has_response_space_T_29; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_78 = _current_request_tag_has_response_space_T_77 | _current_request_tag_has_response_space_T_31; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_79 = _current_request_tag_has_response_space_T_78 | _current_request_tag_has_response_space_T_33; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_80 = _current_request_tag_has_response_space_T_79 | _current_request_tag_has_response_space_T_35; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_81 = _current_request_tag_has_response_space_T_80 | _current_request_tag_has_response_space_T_37; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_82 = _current_request_tag_has_response_space_T_81 | _current_request_tag_has_response_space_T_39; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_83 = _current_request_tag_has_response_space_T_82 | _current_request_tag_has_response_space_T_41; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_84 = _current_request_tag_has_response_space_T_83 | _current_request_tag_has_response_space_T_43; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_85 = _current_request_tag_has_response_space_T_84 | _current_request_tag_has_response_space_T_45; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_86 = _current_request_tag_has_response_space_T_85 | _current_request_tag_has_response_space_T_47; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_87 = _current_request_tag_has_response_space_T_86 | _current_request_tag_has_response_space_T_49; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_88 = _current_request_tag_has_response_space_T_87 | _current_request_tag_has_response_space_T_51; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_89 = _current_request_tag_has_response_space_T_88 | _current_request_tag_has_response_space_T_53; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_90 = _current_request_tag_has_response_space_T_89 | _current_request_tag_has_response_space_T_55; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_91 = _current_request_tag_has_response_space_T_90 | _current_request_tag_has_response_space_T_57; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_92 = _current_request_tag_has_response_space_T_91 | _current_request_tag_has_response_space_T_59; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_93 = _current_request_tag_has_response_space_T_92 | _current_request_tag_has_response_space_T_61; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire current_request_tag_has_response_space = _current_request_tag_has_response_space_T_93 | _current_request_tag_has_response_space_T_63; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire [63:0] _outstanding_req_addr_io_enq_bits_addrindex_T = {59'h0, request_input_bits_addr[4:0]}; // @[L2MemHelperLatencyInjection.scala:44:27, :200:73] wire _request_latency_injection_q_io_enq_valid_T = request_input_valid & tlb_ready; // @[Misc.scala:26:53] wire _request_latency_injection_q_io_enq_valid_T_1 = _request_latency_injection_q_io_enq_valid_T & _outstanding_req_addr_io_enq_ready; // @[Misc.scala:26:53] wire _request_latency_injection_q_io_enq_valid_T_2 = _request_latency_injection_q_io_enq_valid_T_1 & free_outstanding_op_slots; // @[Misc.scala:26:53] wire _request_latency_injection_q_io_enq_valid_T_3 = _request_latency_injection_q_io_enq_valid_T_2 & _tags_for_issue_Q_io_deq_valid; // @[Misc.scala:26:53] wire _request_latency_injection_q_io_enq_valid_T_4 = _request_latency_injection_q_io_enq_valid_T_3 & current_request_tag_has_response_space; // @[Misc.scala:26:53] wire _request_input_ready_T = _request_latency_injection_q_io_enq_ready & tlb_ready; // @[Misc.scala:26:53] wire _request_input_ready_T_1 = _request_input_ready_T & _outstanding_req_addr_io_enq_ready; // @[Misc.scala:26:53] wire _request_input_ready_T_2 = _request_input_ready_T_1 & free_outstanding_op_slots; // @[Misc.scala:26:53] wire _request_input_ready_T_3 = _request_input_ready_T_2 & _tags_for_issue_Q_io_deq_valid; // @[Misc.scala:26:53] assign _request_input_ready_T_4 = _request_input_ready_T_3 & current_request_tag_has_response_space; // @[Misc.scala:26:53] assign request_input_ready = _request_input_ready_T_4; // @[Misc.scala:26:53] wire _T_45 = request_input_valid & _request_latency_injection_q_io_enq_ready; // @[Misc.scala:26:53] wire _outstanding_req_addr_io_enq_valid_T; // @[Misc.scala:26:53] assign _outstanding_req_addr_io_enq_valid_T = _T_45; // @[Misc.scala:26:53] wire _tags_for_issue_Q_io_deq_ready_T; // @[Misc.scala:26:53] assign _tags_for_issue_Q_io_deq_ready_T = _T_45; // @[Misc.scala:26:53] wire _outstanding_req_addr_io_enq_valid_T_1 = _outstanding_req_addr_io_enq_valid_T & tlb_ready; // @[Misc.scala:26:53] wire _outstanding_req_addr_io_enq_valid_T_2 = _outstanding_req_addr_io_enq_valid_T_1 & free_outstanding_op_slots; // @[Misc.scala:26:53] wire _outstanding_req_addr_io_enq_valid_T_3 = _outstanding_req_addr_io_enq_valid_T_2 & _tags_for_issue_Q_io_deq_valid; // @[Misc.scala:26:53] wire _outstanding_req_addr_io_enq_valid_T_4 = _outstanding_req_addr_io_enq_valid_T_3 & current_request_tag_has_response_space; // @[Misc.scala:26:53] wire _tags_for_issue_Q_io_deq_ready_T_1 = _tags_for_issue_Q_io_deq_ready_T & tlb_ready; // @[Misc.scala:26:53] wire _tags_for_issue_Q_io_deq_ready_T_2 = _tags_for_issue_Q_io_deq_ready_T_1 & _outstanding_req_addr_io_enq_ready; // @[Misc.scala:26:53] wire _tags_for_issue_Q_io_deq_ready_T_3 = _tags_for_issue_Q_io_deq_ready_T_2 & free_outstanding_op_slots; // @[Misc.scala:26:53] wire _tags_for_issue_Q_io_deq_ready_T_4 = _tags_for_issue_Q_io_deq_ready_T_3 & current_request_tag_has_response_space; // @[Misc.scala:26:53] reg [63:0] loginfo_cycles_5; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_10 = {1'h0, loginfo_cycles_5} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_11 = _loginfo_cycles_T_10[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_6; // @[Util.scala:26:33] wire [64:0] _loginfo_cycles_T_12 = {1'h0, loginfo_cycles_6} + 65'h1; // @[Util.scala:26:33, :27:38] wire [63:0] _loginfo_cycles_T_13 = _loginfo_cycles_T_12[63:0]; // @[Util.scala:27:38] wire _printf_T_1 = ~_printf_T; // @[annotations.scala:102:49] wire _printf_T_3 = ~_printf_T_2; // @[annotations.scala:102:49] reg [63:0] loginfo_cycles_7; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_14 = {1'h0, loginfo_cycles_7} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_15 = _loginfo_cycles_T_14[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_8; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_16 = {1'h0, loginfo_cycles_8} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_17 = _loginfo_cycles_T_16[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_9; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_18 = {1'h0, loginfo_cycles_9} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_19 = _loginfo_cycles_T_18[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_10; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_20 = {1'h0, loginfo_cycles_10} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_21 = _loginfo_cycles_T_20[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_11; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_22 = {1'h0, loginfo_cycles_11} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_23 = _loginfo_cycles_T_22[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_12; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_24 = {1'h0, loginfo_cycles_12} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_25 = _loginfo_cycles_T_24[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_13; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_26 = {1'h0, loginfo_cycles_13} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_27 = _loginfo_cycles_T_26[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_14; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_28 = {1'h0, loginfo_cycles_14} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_29 = _loginfo_cycles_T_28[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_15; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_30 = {1'h0, loginfo_cycles_15} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_31 = _loginfo_cycles_T_30[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_16; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_32 = {1'h0, loginfo_cycles_16} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_33 = _loginfo_cycles_T_32[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_17; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_34 = {1'h0, loginfo_cycles_17} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_35 = _loginfo_cycles_T_34[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_18; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_36 = {1'h0, loginfo_cycles_18} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_37 = _loginfo_cycles_T_36[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_19; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_38 = {1'h0, loginfo_cycles_19} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_39 = _loginfo_cycles_T_38[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_20; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_40 = {1'h0, loginfo_cycles_20} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_41 = _loginfo_cycles_T_40[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_21; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_42 = {1'h0, loginfo_cycles_21} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_43 = _loginfo_cycles_T_42[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_22; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_44 = {1'h0, loginfo_cycles_22} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_45 = _loginfo_cycles_T_44[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_23; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_46 = {1'h0, loginfo_cycles_23} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_47 = _loginfo_cycles_T_46[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_24; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_48 = {1'h0, loginfo_cycles_24} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_49 = _loginfo_cycles_T_48[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_25; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_50 = {1'h0, loginfo_cycles_25} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_51 = _loginfo_cycles_T_50[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_26; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_52 = {1'h0, loginfo_cycles_26} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_53 = _loginfo_cycles_T_52[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_27; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_54 = {1'h0, loginfo_cycles_27} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_55 = _loginfo_cycles_T_54[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_28; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_56 = {1'h0, loginfo_cycles_28} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_57 = _loginfo_cycles_T_56[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_29; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_58 = {1'h0, loginfo_cycles_29} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_59 = _loginfo_cycles_T_58[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_30; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_60 = {1'h0, loginfo_cycles_30} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_61 = _loginfo_cycles_T_60[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_31; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_62 = {1'h0, loginfo_cycles_31} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_63 = _loginfo_cycles_T_62[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_32; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_64 = {1'h0, loginfo_cycles_32} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_65 = _loginfo_cycles_T_64[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_33; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_66 = {1'h0, loginfo_cycles_33} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_67 = _loginfo_cycles_T_66[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_34; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_68 = {1'h0, loginfo_cycles_34} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_69 = _loginfo_cycles_T_68[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_35; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_70 = {1'h0, loginfo_cycles_35} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_71 = _loginfo_cycles_T_70[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_36; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_72 = {1'h0, loginfo_cycles_36} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_73 = _loginfo_cycles_T_72[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_37; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_74 = {1'h0, loginfo_cycles_37} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_75 = _loginfo_cycles_T_74[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_38; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_76 = {1'h0, loginfo_cycles_38} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_77 = _loginfo_cycles_T_76[63:0]; // @[Util.scala:19:38] wire _selectQready_T = _response_latency_injection_q_io_deq_bits_source == 5'h0; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_1 = _Queue4_L2RespInternal_io_enq_ready & _selectQready_T; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_2 = _response_latency_injection_q_io_deq_bits_source == 5'h1; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_3 = _Queue4_L2RespInternal_1_io_enq_ready & _selectQready_T_2; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_4 = _response_latency_injection_q_io_deq_bits_source == 5'h2; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_5 = _Queue4_L2RespInternal_2_io_enq_ready & _selectQready_T_4; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_6 = _response_latency_injection_q_io_deq_bits_source == 5'h3; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_7 = _Queue4_L2RespInternal_3_io_enq_ready & _selectQready_T_6; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_8 = _response_latency_injection_q_io_deq_bits_source == 5'h4; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_9 = _Queue4_L2RespInternal_4_io_enq_ready & _selectQready_T_8; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_10 = _response_latency_injection_q_io_deq_bits_source == 5'h5; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_11 = _Queue4_L2RespInternal_5_io_enq_ready & _selectQready_T_10; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_12 = _response_latency_injection_q_io_deq_bits_source == 5'h6; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_13 = _Queue4_L2RespInternal_6_io_enq_ready & _selectQready_T_12; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_14 = _response_latency_injection_q_io_deq_bits_source == 5'h7; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_15 = _Queue4_L2RespInternal_7_io_enq_ready & _selectQready_T_14; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_16 = _response_latency_injection_q_io_deq_bits_source == 5'h8; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_17 = _Queue4_L2RespInternal_8_io_enq_ready & _selectQready_T_16; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_18 = _response_latency_injection_q_io_deq_bits_source == 5'h9; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_19 = _Queue4_L2RespInternal_9_io_enq_ready & _selectQready_T_18; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_20 = _response_latency_injection_q_io_deq_bits_source == 5'hA; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_21 = _Queue4_L2RespInternal_10_io_enq_ready & _selectQready_T_20; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_22 = _response_latency_injection_q_io_deq_bits_source == 5'hB; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_23 = _Queue4_L2RespInternal_11_io_enq_ready & _selectQready_T_22; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_24 = _response_latency_injection_q_io_deq_bits_source == 5'hC; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_25 = _Queue4_L2RespInternal_12_io_enq_ready & _selectQready_T_24; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_26 = _response_latency_injection_q_io_deq_bits_source == 5'hD; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_27 = _Queue4_L2RespInternal_13_io_enq_ready & _selectQready_T_26; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_28 = _response_latency_injection_q_io_deq_bits_source == 5'hE; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_29 = _Queue4_L2RespInternal_14_io_enq_ready & _selectQready_T_28; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_30 = _response_latency_injection_q_io_deq_bits_source == 5'hF; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_31 = _Queue4_L2RespInternal_15_io_enq_ready & _selectQready_T_30; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_32 = _response_latency_injection_q_io_deq_bits_source == 5'h10; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_33 = _Queue4_L2RespInternal_16_io_enq_ready & _selectQready_T_32; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_34 = _response_latency_injection_q_io_deq_bits_source == 5'h11; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_35 = _Queue4_L2RespInternal_17_io_enq_ready & _selectQready_T_34; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_36 = _response_latency_injection_q_io_deq_bits_source == 5'h12; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_37 = _Queue4_L2RespInternal_18_io_enq_ready & _selectQready_T_36; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_38 = _response_latency_injection_q_io_deq_bits_source == 5'h13; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_39 = _Queue4_L2RespInternal_19_io_enq_ready & _selectQready_T_38; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_40 = _response_latency_injection_q_io_deq_bits_source == 5'h14; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_41 = _Queue4_L2RespInternal_20_io_enq_ready & _selectQready_T_40; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_42 = _response_latency_injection_q_io_deq_bits_source == 5'h15; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_43 = _Queue4_L2RespInternal_21_io_enq_ready & _selectQready_T_42; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_44 = _response_latency_injection_q_io_deq_bits_source == 5'h16; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_45 = _Queue4_L2RespInternal_22_io_enq_ready & _selectQready_T_44; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_46 = _response_latency_injection_q_io_deq_bits_source == 5'h17; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_47 = _Queue4_L2RespInternal_23_io_enq_ready & _selectQready_T_46; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_48 = _response_latency_injection_q_io_deq_bits_source == 5'h18; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_49 = _Queue4_L2RespInternal_24_io_enq_ready & _selectQready_T_48; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_50 = _response_latency_injection_q_io_deq_bits_source == 5'h19; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_51 = _Queue4_L2RespInternal_25_io_enq_ready & _selectQready_T_50; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_52 = _response_latency_injection_q_io_deq_bits_source == 5'h1A; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_53 = _Queue4_L2RespInternal_26_io_enq_ready & _selectQready_T_52; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_54 = _response_latency_injection_q_io_deq_bits_source == 5'h1B; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_55 = _Queue4_L2RespInternal_27_io_enq_ready & _selectQready_T_54; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_56 = _response_latency_injection_q_io_deq_bits_source == 5'h1C; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_57 = _Queue4_L2RespInternal_28_io_enq_ready & _selectQready_T_56; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_58 = _response_latency_injection_q_io_deq_bits_source == 5'h1D; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_59 = _Queue4_L2RespInternal_29_io_enq_ready & _selectQready_T_58; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_60 = _response_latency_injection_q_io_deq_bits_source == 5'h1E; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_61 = _Queue4_L2RespInternal_30_io_enq_ready & _selectQready_T_60; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_62 = &_response_latency_injection_q_io_deq_bits_source; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_63 = _Queue4_L2RespInternal_31_io_enq_ready & _selectQready_T_62; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_64 = _selectQready_T_1 | _selectQready_T_3; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_65 = _selectQready_T_64 | _selectQready_T_5; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_66 = _selectQready_T_65 | _selectQready_T_7; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_67 = _selectQready_T_66 | _selectQready_T_9; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_68 = _selectQready_T_67 | _selectQready_T_11; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_69 = _selectQready_T_68 | _selectQready_T_13; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_70 = _selectQready_T_69 | _selectQready_T_15; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_71 = _selectQready_T_70 | _selectQready_T_17; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_72 = _selectQready_T_71 | _selectQready_T_19; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_73 = _selectQready_T_72 | _selectQready_T_21; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_74 = _selectQready_T_73 | _selectQready_T_23; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_75 = _selectQready_T_74 | _selectQready_T_25; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_76 = _selectQready_T_75 | _selectQready_T_27; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_77 = _selectQready_T_76 | _selectQready_T_29; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_78 = _selectQready_T_77 | _selectQready_T_31; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_79 = _selectQready_T_78 | _selectQready_T_33; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_80 = _selectQready_T_79 | _selectQready_T_35; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_81 = _selectQready_T_80 | _selectQready_T_37; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_82 = _selectQready_T_81 | _selectQready_T_39; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_83 = _selectQready_T_82 | _selectQready_T_41; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_84 = _selectQready_T_83 | _selectQready_T_43; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_85 = _selectQready_T_84 | _selectQready_T_45; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_86 = _selectQready_T_85 | _selectQready_T_47; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_87 = _selectQready_T_86 | _selectQready_T_49; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_88 = _selectQready_T_87 | _selectQready_T_51; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_89 = _selectQready_T_88 | _selectQready_T_53; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_90 = _selectQready_T_89 | _selectQready_T_55; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_91 = _selectQready_T_90 | _selectQready_T_57; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_92 = _selectQready_T_91 | _selectQready_T_59; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_93 = _selectQready_T_92 | _selectQready_T_61; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire selectQready = _selectQready_T_93 | _selectQready_T_63; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _T_377 = selectQready & _response_latency_injection_q_io_deq_valid; // @[Misc.scala:26:53] wire tags_for_issue_Q_io_enq_valid = _T_377 | _T_4; // @[Misc.scala:26:53] wire [4:0] tags_for_issue_Q_io_enq_bits = _T_377 ? _response_latency_injection_q_io_deq_bits_source : tags_init_reg[4:0]; // @[Misc.scala:26:53] reg [63:0] loginfo_cycles_39; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_78 = {1'h0, loginfo_cycles_39} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_79 = _loginfo_cycles_T_78[63:0]; // @[Util.scala:19:38] wire _response_latency_injection_q_io_deq_ready_T = selectQready & _tags_for_issue_Q_io_enq_ready; // @[Misc.scala:26:53] wire _T_476 = _response_latency_injection_q_io_deq_valid & _tags_for_issue_Q_io_enq_ready; // @[Misc.scala:26:53] wire _T_480 = _outstanding_req_addr_io_deq_bits_tag == 5'h0; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T = _T_480; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q = _T_480; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_1 = _Queue4_L2RespInternal_io_deq_valid & _queueValid_T; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_483 = _outstanding_req_addr_io_deq_bits_tag == 5'h1; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_2; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_2 = _T_483; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_1; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_1 = _T_483; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_3 = _Queue4_L2RespInternal_1_io_deq_valid & _queueValid_T_2; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_486 = _outstanding_req_addr_io_deq_bits_tag == 5'h2; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_4; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_4 = _T_486; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_2; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_2 = _T_486; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_5 = _Queue4_L2RespInternal_2_io_deq_valid & _queueValid_T_4; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_489 = _outstanding_req_addr_io_deq_bits_tag == 5'h3; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_6; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_6 = _T_489; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_3; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_3 = _T_489; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_7 = _Queue4_L2RespInternal_3_io_deq_valid & _queueValid_T_6; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_492 = _outstanding_req_addr_io_deq_bits_tag == 5'h4; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_8; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_8 = _T_492; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_4; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_4 = _T_492; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_9 = _Queue4_L2RespInternal_4_io_deq_valid & _queueValid_T_8; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_495 = _outstanding_req_addr_io_deq_bits_tag == 5'h5; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_10; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_10 = _T_495; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_5; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_5 = _T_495; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_11 = _Queue4_L2RespInternal_5_io_deq_valid & _queueValid_T_10; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_498 = _outstanding_req_addr_io_deq_bits_tag == 5'h6; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_12; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_12 = _T_498; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_6; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_6 = _T_498; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_13 = _Queue4_L2RespInternal_6_io_deq_valid & _queueValid_T_12; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_501 = _outstanding_req_addr_io_deq_bits_tag == 5'h7; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_14; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_14 = _T_501; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_7; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_7 = _T_501; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_15 = _Queue4_L2RespInternal_7_io_deq_valid & _queueValid_T_14; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_504 = _outstanding_req_addr_io_deq_bits_tag == 5'h8; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_16; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_16 = _T_504; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_8; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_8 = _T_504; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_17 = _Queue4_L2RespInternal_8_io_deq_valid & _queueValid_T_16; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_507 = _outstanding_req_addr_io_deq_bits_tag == 5'h9; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_18; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_18 = _T_507; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_9; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_9 = _T_507; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_19 = _Queue4_L2RespInternal_9_io_deq_valid & _queueValid_T_18; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_510 = _outstanding_req_addr_io_deq_bits_tag == 5'hA; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_20; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_20 = _T_510; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_10; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_10 = _T_510; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_21 = _Queue4_L2RespInternal_10_io_deq_valid & _queueValid_T_20; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_513 = _outstanding_req_addr_io_deq_bits_tag == 5'hB; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_22; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_22 = _T_513; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_11; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_11 = _T_513; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_23 = _Queue4_L2RespInternal_11_io_deq_valid & _queueValid_T_22; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_516 = _outstanding_req_addr_io_deq_bits_tag == 5'hC; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_24; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_24 = _T_516; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_12; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_12 = _T_516; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_25 = _Queue4_L2RespInternal_12_io_deq_valid & _queueValid_T_24; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_519 = _outstanding_req_addr_io_deq_bits_tag == 5'hD; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_26; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_26 = _T_519; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_13; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_13 = _T_519; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_27 = _Queue4_L2RespInternal_13_io_deq_valid & _queueValid_T_26; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_522 = _outstanding_req_addr_io_deq_bits_tag == 5'hE; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_28; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_28 = _T_522; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_14; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_14 = _T_522; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_29 = _Queue4_L2RespInternal_14_io_deq_valid & _queueValid_T_28; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_525 = _outstanding_req_addr_io_deq_bits_tag == 5'hF; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_30; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_30 = _T_525; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_15; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_15 = _T_525; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_31 = _Queue4_L2RespInternal_15_io_deq_valid & _queueValid_T_30; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_528 = _outstanding_req_addr_io_deq_bits_tag == 5'h10; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_32; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_32 = _T_528; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_16; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_16 = _T_528; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_33 = _Queue4_L2RespInternal_16_io_deq_valid & _queueValid_T_32; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_531 = _outstanding_req_addr_io_deq_bits_tag == 5'h11; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_34; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_34 = _T_531; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_17; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_17 = _T_531; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_35 = _Queue4_L2RespInternal_17_io_deq_valid & _queueValid_T_34; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_534 = _outstanding_req_addr_io_deq_bits_tag == 5'h12; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_36; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_36 = _T_534; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_18; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_18 = _T_534; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_37 = _Queue4_L2RespInternal_18_io_deq_valid & _queueValid_T_36; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_537 = _outstanding_req_addr_io_deq_bits_tag == 5'h13; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_38; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_38 = _T_537; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_19; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_19 = _T_537; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_39 = _Queue4_L2RespInternal_19_io_deq_valid & _queueValid_T_38; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_540 = _outstanding_req_addr_io_deq_bits_tag == 5'h14; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_40; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_40 = _T_540; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_20; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_20 = _T_540; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_41 = _Queue4_L2RespInternal_20_io_deq_valid & _queueValid_T_40; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_543 = _outstanding_req_addr_io_deq_bits_tag == 5'h15; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_42; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_42 = _T_543; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_21; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_21 = _T_543; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_43 = _Queue4_L2RespInternal_21_io_deq_valid & _queueValid_T_42; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_546 = _outstanding_req_addr_io_deq_bits_tag == 5'h16; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_44; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_44 = _T_546; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_22; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_22 = _T_546; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_45 = _Queue4_L2RespInternal_22_io_deq_valid & _queueValid_T_44; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_549 = _outstanding_req_addr_io_deq_bits_tag == 5'h17; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_46; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_46 = _T_549; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_23; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_23 = _T_549; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_47 = _Queue4_L2RespInternal_23_io_deq_valid & _queueValid_T_46; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_552 = _outstanding_req_addr_io_deq_bits_tag == 5'h18; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_48; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_48 = _T_552; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_24; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_24 = _T_552; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_49 = _Queue4_L2RespInternal_24_io_deq_valid & _queueValid_T_48; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_555 = _outstanding_req_addr_io_deq_bits_tag == 5'h19; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_50; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_50 = _T_555; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_25; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_25 = _T_555; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_51 = _Queue4_L2RespInternal_25_io_deq_valid & _queueValid_T_50; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_558 = _outstanding_req_addr_io_deq_bits_tag == 5'h1A; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_52; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_52 = _T_558; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_26; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_26 = _T_558; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_53 = _Queue4_L2RespInternal_26_io_deq_valid & _queueValid_T_52; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_561 = _outstanding_req_addr_io_deq_bits_tag == 5'h1B; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_54; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_54 = _T_561; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_27; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_27 = _T_561; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_55 = _Queue4_L2RespInternal_27_io_deq_valid & _queueValid_T_54; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_564 = _outstanding_req_addr_io_deq_bits_tag == 5'h1C; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_56; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_56 = _T_564; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_28; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_28 = _T_564; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_57 = _Queue4_L2RespInternal_28_io_deq_valid & _queueValid_T_56; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_567 = _outstanding_req_addr_io_deq_bits_tag == 5'h1D; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_58; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_58 = _T_567; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_29; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_29 = _T_567; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_59 = _Queue4_L2RespInternal_29_io_deq_valid & _queueValid_T_58; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_570 = _outstanding_req_addr_io_deq_bits_tag == 5'h1E; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_60; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_60 = _T_570; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_30; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_30 = _T_570; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_61 = _Queue4_L2RespInternal_30_io_deq_valid & _queueValid_T_60; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _queueValid_T_62 = &_outstanding_req_addr_io_deq_bits_tag; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_63 = _Queue4_L2RespInternal_31_io_deq_valid & _queueValid_T_62; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _queueValid_T_64 = _queueValid_T_1 | _queueValid_T_3; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_65 = _queueValid_T_64 | _queueValid_T_5; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_66 = _queueValid_T_65 | _queueValid_T_7; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_67 = _queueValid_T_66 | _queueValid_T_9; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_68 = _queueValid_T_67 | _queueValid_T_11; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_69 = _queueValid_T_68 | _queueValid_T_13; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_70 = _queueValid_T_69 | _queueValid_T_15; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_71 = _queueValid_T_70 | _queueValid_T_17; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_72 = _queueValid_T_71 | _queueValid_T_19; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_73 = _queueValid_T_72 | _queueValid_T_21; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_74 = _queueValid_T_73 | _queueValid_T_23; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_75 = _queueValid_T_74 | _queueValid_T_25; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_76 = _queueValid_T_75 | _queueValid_T_27; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_77 = _queueValid_T_76 | _queueValid_T_29; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_78 = _queueValid_T_77 | _queueValid_T_31; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_79 = _queueValid_T_78 | _queueValid_T_33; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_80 = _queueValid_T_79 | _queueValid_T_35; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_81 = _queueValid_T_80 | _queueValid_T_37; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_82 = _queueValid_T_81 | _queueValid_T_39; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_83 = _queueValid_T_82 | _queueValid_T_41; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_84 = _queueValid_T_83 | _queueValid_T_43; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_85 = _queueValid_T_84 | _queueValid_T_45; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_86 = _queueValid_T_85 | _queueValid_T_47; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_87 = _queueValid_T_86 | _queueValid_T_49; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_88 = _queueValid_T_87 | _queueValid_T_51; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_89 = _queueValid_T_88 | _queueValid_T_53; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_90 = _queueValid_T_89 | _queueValid_T_55; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_91 = _queueValid_T_90 | _queueValid_T_57; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_92 = _queueValid_T_91 | _queueValid_T_59; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_93 = _queueValid_T_92 | _queueValid_T_61; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire queueValid = _queueValid_T_93 | _queueValid_T_63; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _outstanding_req_addr_io_deq_ready_T = queueValid; // @[Misc.scala:26:53] wire [255:0] resultdata_data; // @[L2MemHelperLatencyInjection.scala:300:20] wire [7:0] _GEN_12 = {_outstanding_req_addr_io_deq_bits_addrindex, 3'h0}; // @[L2MemHelperLatencyInjection.scala:91:36, :302:78] wire [7:0] _resultdata_data_T; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_2; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_2 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_4; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_4 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_6; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_6 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_8; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_8 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_10; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_10 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_12; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_12 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_14; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_14 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_16; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_16 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_18; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_18 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_20; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_20 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_22; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_22 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_24; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_24 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_26; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_26 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_28; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_28 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_30; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_30 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_32; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_32 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_34; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_34 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_36; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_36 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_38; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_38 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_40; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_40 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_42; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_42 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_44; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_44 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_46; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_46 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_48; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_48 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_50; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_50 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_52; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_52 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_54; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_54 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_56; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_56 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_58; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_58 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_60; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_60 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_62; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_62 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [255:0] _resultdata_data_T_1 = _Queue4_L2RespInternal_io_deq_bits_data >> _resultdata_data_T; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data = resultdata_is_current_q ? _resultdata_data_T_1 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_1; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_3 = _Queue4_L2RespInternal_1_io_deq_bits_data >> _resultdata_data_T_2; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_1 = resultdata_is_current_q_1 ? _resultdata_data_T_3 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_2; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_5 = _Queue4_L2RespInternal_2_io_deq_bits_data >> _resultdata_data_T_4; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_2 = resultdata_is_current_q_2 ? _resultdata_data_T_5 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_3; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_7 = _Queue4_L2RespInternal_3_io_deq_bits_data >> _resultdata_data_T_6; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_3 = resultdata_is_current_q_3 ? _resultdata_data_T_7 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_4; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_9 = _Queue4_L2RespInternal_4_io_deq_bits_data >> _resultdata_data_T_8; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_4 = resultdata_is_current_q_4 ? _resultdata_data_T_9 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_5; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_11 = _Queue4_L2RespInternal_5_io_deq_bits_data >> _resultdata_data_T_10; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_5 = resultdata_is_current_q_5 ? _resultdata_data_T_11 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_6; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_13 = _Queue4_L2RespInternal_6_io_deq_bits_data >> _resultdata_data_T_12; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_6 = resultdata_is_current_q_6 ? _resultdata_data_T_13 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_7; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_15 = _Queue4_L2RespInternal_7_io_deq_bits_data >> _resultdata_data_T_14; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_7 = resultdata_is_current_q_7 ? _resultdata_data_T_15 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_8; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_17 = _Queue4_L2RespInternal_8_io_deq_bits_data >> _resultdata_data_T_16; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_8 = resultdata_is_current_q_8 ? _resultdata_data_T_17 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_9; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_19 = _Queue4_L2RespInternal_9_io_deq_bits_data >> _resultdata_data_T_18; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_9 = resultdata_is_current_q_9 ? _resultdata_data_T_19 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_10; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_21 = _Queue4_L2RespInternal_10_io_deq_bits_data >> _resultdata_data_T_20; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_10 = resultdata_is_current_q_10 ? _resultdata_data_T_21 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_11; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_23 = _Queue4_L2RespInternal_11_io_deq_bits_data >> _resultdata_data_T_22; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_11 = resultdata_is_current_q_11 ? _resultdata_data_T_23 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_12; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_25 = _Queue4_L2RespInternal_12_io_deq_bits_data >> _resultdata_data_T_24; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_12 = resultdata_is_current_q_12 ? _resultdata_data_T_25 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_13; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_27 = _Queue4_L2RespInternal_13_io_deq_bits_data >> _resultdata_data_T_26; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_13 = resultdata_is_current_q_13 ? _resultdata_data_T_27 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_14; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_29 = _Queue4_L2RespInternal_14_io_deq_bits_data >> _resultdata_data_T_28; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_14 = resultdata_is_current_q_14 ? _resultdata_data_T_29 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_15; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_31 = _Queue4_L2RespInternal_15_io_deq_bits_data >> _resultdata_data_T_30; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_15 = resultdata_is_current_q_15 ? _resultdata_data_T_31 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_16; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_33 = _Queue4_L2RespInternal_16_io_deq_bits_data >> _resultdata_data_T_32; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_16 = resultdata_is_current_q_16 ? _resultdata_data_T_33 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_17; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_35 = _Queue4_L2RespInternal_17_io_deq_bits_data >> _resultdata_data_T_34; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_17 = resultdata_is_current_q_17 ? _resultdata_data_T_35 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_18; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_37 = _Queue4_L2RespInternal_18_io_deq_bits_data >> _resultdata_data_T_36; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_18 = resultdata_is_current_q_18 ? _resultdata_data_T_37 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_19; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_39 = _Queue4_L2RespInternal_19_io_deq_bits_data >> _resultdata_data_T_38; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_19 = resultdata_is_current_q_19 ? _resultdata_data_T_39 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_20; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_41 = _Queue4_L2RespInternal_20_io_deq_bits_data >> _resultdata_data_T_40; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_20 = resultdata_is_current_q_20 ? _resultdata_data_T_41 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_21; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_43 = _Queue4_L2RespInternal_21_io_deq_bits_data >> _resultdata_data_T_42; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_21 = resultdata_is_current_q_21 ? _resultdata_data_T_43 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_22; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_45 = _Queue4_L2RespInternal_22_io_deq_bits_data >> _resultdata_data_T_44; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_22 = resultdata_is_current_q_22 ? _resultdata_data_T_45 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_23; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_47 = _Queue4_L2RespInternal_23_io_deq_bits_data >> _resultdata_data_T_46; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_23 = resultdata_is_current_q_23 ? _resultdata_data_T_47 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_24; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_49 = _Queue4_L2RespInternal_24_io_deq_bits_data >> _resultdata_data_T_48; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_24 = resultdata_is_current_q_24 ? _resultdata_data_T_49 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_25; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_51 = _Queue4_L2RespInternal_25_io_deq_bits_data >> _resultdata_data_T_50; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_25 = resultdata_is_current_q_25 ? _resultdata_data_T_51 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_26; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_53 = _Queue4_L2RespInternal_26_io_deq_bits_data >> _resultdata_data_T_52; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_26 = resultdata_is_current_q_26 ? _resultdata_data_T_53 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_27; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_55 = _Queue4_L2RespInternal_27_io_deq_bits_data >> _resultdata_data_T_54; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_27 = resultdata_is_current_q_27 ? _resultdata_data_T_55 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_28; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_57 = _Queue4_L2RespInternal_28_io_deq_bits_data >> _resultdata_data_T_56; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_28 = resultdata_is_current_q_28 ? _resultdata_data_T_57 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_29; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_59 = _Queue4_L2RespInternal_29_io_deq_bits_data >> _resultdata_data_T_58; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_29 = resultdata_is_current_q_29 ? _resultdata_data_T_59 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_30; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_61 = _Queue4_L2RespInternal_30_io_deq_bits_data >> _resultdata_data_T_60; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_30 = resultdata_is_current_q_30 ? _resultdata_data_T_61 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire resultdata_is_current_q_31 = &_outstanding_req_addr_io_deq_bits_tag; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27, :299:31] wire [255:0] resultdata_data_31; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_63 = _Queue4_L2RespInternal_31_io_deq_bits_data >> _resultdata_data_T_62; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_31 = resultdata_is_current_q_31 ? _resultdata_data_T_63 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] _resultdata_T = resultdata_data | resultdata_data_1; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_1 = _resultdata_T | resultdata_data_2; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_2 = _resultdata_T_1 | resultdata_data_3; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_3 = _resultdata_T_2 | resultdata_data_4; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_4 = _resultdata_T_3 | resultdata_data_5; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_5 = _resultdata_T_4 | resultdata_data_6; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_6 = _resultdata_T_5 | resultdata_data_7; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_7 = _resultdata_T_6 | resultdata_data_8; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_8 = _resultdata_T_7 | resultdata_data_9; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_9 = _resultdata_T_8 | resultdata_data_10; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_10 = _resultdata_T_9 | resultdata_data_11; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_11 = _resultdata_T_10 | resultdata_data_12; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_12 = _resultdata_T_11 | resultdata_data_13; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_13 = _resultdata_T_12 | resultdata_data_14; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_14 = _resultdata_T_13 | resultdata_data_15; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_15 = _resultdata_T_14 | resultdata_data_16; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_16 = _resultdata_T_15 | resultdata_data_17; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_17 = _resultdata_T_16 | resultdata_data_18; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_18 = _resultdata_T_17 | resultdata_data_19; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_19 = _resultdata_T_18 | resultdata_data_20; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_20 = _resultdata_T_19 | resultdata_data_21; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_21 = _resultdata_T_20 | resultdata_data_22; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_22 = _resultdata_T_21 | resultdata_data_23; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_23 = _resultdata_T_22 | resultdata_data_24; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_24 = _resultdata_T_23 | resultdata_data_25; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_25 = _resultdata_T_24 | resultdata_data_26; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_26 = _resultdata_T_25 | resultdata_data_27; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_27 = _resultdata_T_26 | resultdata_data_28; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_28 = _resultdata_T_27 | resultdata_data_29; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_29 = _resultdata_T_28 | resultdata_data_30; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] assign resultdata = _resultdata_T_29 | resultdata_data_31; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] assign response_output_bits_data = resultdata; // @[L2MemHelperLatencyInjection.scala:53:29, :307:15] assign _response_output_valid_T = queueValid & _outstanding_req_addr_io_deq_valid; // @[Misc.scala:26:53] assign response_output_valid = _response_output_valid_T; // @[Misc.scala:26:53] wire opdata = masterNodeOut_d_bits_opcode[0]; // @[Edges.scala:106:36] reg [63:0] loginfo_cycles_40; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_80 = {1'h0, loginfo_cycles_40} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_81 = _loginfo_cycles_T_80[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_41; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_82 = {1'h0, loginfo_cycles_41} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_83 = _loginfo_cycles_T_82[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_42; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_84 = {1'h0, loginfo_cycles_42} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_85 = _loginfo_cycles_T_84[63:0]; // @[Util.scala:19:38]
Generate the Verilog code corresponding to the following Chisel files. File util.scala: //****************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v3.common.{MicroOp} import boom.v3.exu.{BrUpdateInfo} /** * Object to XOR fold a input register of fullLength into a compressedLength. */ object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /** * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks */ object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask) } def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) } } /** * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. */ object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /** * Object to return a BR mask given a MicroOp mask and old BR mask. */ object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask) out } } /** * Object to check if at least 1 bit matches in two masks */ object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /** * Object to clear one bit in a mask given an index */ object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /** * Object to shift a register over by one bit and concat a new one */ object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /** * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. */ object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /** * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. */ object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc | (b-1).U) } } /** * Object to rotate a signal left by one */ object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /** * Object to sext a value to a particular length. */ object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /** * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. */ object ImmGen { import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U} def apply(ip: UInt, isel: UInt): SInt = { val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt } } /** * Object to get the FP rounding mode out of a packed immediate. */ object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } } /** * Object to get the FP function fype from a packed immediate. * Note: only works if !(IS_B or IS_S) */ object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } } /** * Object to see if an instruction is a JALR. */ object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /** * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). */ object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /** * Object to return the lowest bit position after the head. */ object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /** * Object to determine whether queue * index i0 is older than index i1. */ object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } /** * Set all bits at or below the highest order '1'. */ object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_|_) } } /** * Set all bits at or above the lowest order '1'. */ object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_) } } /** * Transpose a matrix of Chisel Vecs. */ object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /** * N-wide one-hot priority encoder. */ object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /** * Connect the first k of n valid input interfaces to k output interfaces. */ class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_)) val out_valids = sels map (col => col.reduce(_||_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /** * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). */ class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v3.common.BoomModule()(p) with boom.v3.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire) val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop) uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop)) io.deq.bits := out io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop) // For flow queue behavior. if (flow) { when (io.empty) { io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop) io.deq.bits := io.enq.bits io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) do_deq := false.B when (io.deq.ready) { do_enq := false.B } } } private val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /** * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" */ def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) */ def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) */ def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) */ def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /** * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line */ def apply(strs: String*)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } File consts.scala: //****************************************************************************** // Copyright (c) 2011 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Constants //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.common.constants import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util.Str import freechips.rocketchip.rocket.RVCExpander /** * Mixin for issue queue types */ trait IQType { val IQT_SZ = 3 val IQT_INT = 1.U(IQT_SZ.W) val IQT_MEM = 2.U(IQT_SZ.W) val IQT_FP = 4.U(IQT_SZ.W) val IQT_MFP = 6.U(IQT_SZ.W) } /** * Mixin for scalar operation constants */ trait ScalarOpConstants { val X = BitPat("b?") val Y = BitPat("b1") val N = BitPat("b0") //************************************ // Extra Constants // Which branch predictor predicted us val BSRC_SZ = 2 val BSRC_1 = 0.U(BSRC_SZ.W) // 1-cycle branch pred val BSRC_2 = 1.U(BSRC_SZ.W) // 2-cycle branch pred val BSRC_3 = 2.U(BSRC_SZ.W) // 3-cycle branch pred val BSRC_C = 3.U(BSRC_SZ.W) // core branch resolution //************************************ // Control Signals // CFI types val CFI_SZ = 3 val CFI_X = 0.U(CFI_SZ.W) // Not a CFI instruction val CFI_BR = 1.U(CFI_SZ.W) // Branch val CFI_JAL = 2.U(CFI_SZ.W) // JAL val CFI_JALR = 3.U(CFI_SZ.W) // JALR // PC Select Signal val PC_PLUS4 = 0.U(2.W) // PC + 4 val PC_BRJMP = 1.U(2.W) // brjmp_target val PC_JALR = 2.U(2.W) // jump_reg_target // Branch Type val BR_N = 0.U(4.W) // Next val BR_NE = 1.U(4.W) // Branch on NotEqual val BR_EQ = 2.U(4.W) // Branch on Equal val BR_GE = 3.U(4.W) // Branch on Greater/Equal val BR_GEU = 4.U(4.W) // Branch on Greater/Equal Unsigned val BR_LT = 5.U(4.W) // Branch on Less Than val BR_LTU = 6.U(4.W) // Branch on Less Than Unsigned val BR_J = 7.U(4.W) // Jump val BR_JR = 8.U(4.W) // Jump Register // RS1 Operand Select Signal val OP1_RS1 = 0.U(2.W) // Register Source #1 val OP1_ZERO= 1.U(2.W) val OP1_PC = 2.U(2.W) val OP1_X = BitPat("b??") // RS2 Operand Select Signal val OP2_RS2 = 0.U(3.W) // Register Source #2 val OP2_IMM = 1.U(3.W) // immediate val OP2_ZERO= 2.U(3.W) // constant 0 val OP2_NEXT= 3.U(3.W) // constant 2/4 (for PC+2/4) val OP2_IMMC= 4.U(3.W) // for CSR imm found in RS1 val OP2_X = BitPat("b???") // Register File Write Enable Signal val REN_0 = false.B val REN_1 = true.B // Is 32b Word or 64b Doubldword? val SZ_DW = 1 val DW_X = true.B // Bool(xLen==64) val DW_32 = false.B val DW_64 = true.B val DW_XPR = true.B // Bool(xLen==64) // Memory Enable Signal val MEN_0 = false.B val MEN_1 = true.B val MEN_X = false.B // Immediate Extend Select val IS_I = 0.U(3.W) // I-Type (LD,ALU) val IS_S = 1.U(3.W) // S-Type (ST) val IS_B = 2.U(3.W) // SB-Type (BR) val IS_U = 3.U(3.W) // U-Type (LUI/AUIPC) val IS_J = 4.U(3.W) // UJ-Type (J/JAL) val IS_X = BitPat("b???") // Decode Stage Control Signals val RT_FIX = 0.U(2.W) val RT_FLT = 1.U(2.W) val RT_PAS = 3.U(2.W) // pass-through (prs1 := lrs1, etc) val RT_X = 2.U(2.W) // not-a-register (but shouldn't get a busy-bit, etc.) // TODO rename RT_NAR // Micro-op opcodes // TODO change micro-op opcodes into using enum val UOPC_SZ = 7 val uopX = BitPat.dontCare(UOPC_SZ) val uopNOP = 0.U(UOPC_SZ.W) val uopLD = 1.U(UOPC_SZ.W) val uopSTA = 2.U(UOPC_SZ.W) // store address generation val uopSTD = 3.U(UOPC_SZ.W) // store data generation val uopLUI = 4.U(UOPC_SZ.W) val uopADDI = 5.U(UOPC_SZ.W) val uopANDI = 6.U(UOPC_SZ.W) val uopORI = 7.U(UOPC_SZ.W) val uopXORI = 8.U(UOPC_SZ.W) val uopSLTI = 9.U(UOPC_SZ.W) val uopSLTIU= 10.U(UOPC_SZ.W) val uopSLLI = 11.U(UOPC_SZ.W) val uopSRAI = 12.U(UOPC_SZ.W) val uopSRLI = 13.U(UOPC_SZ.W) val uopSLL = 14.U(UOPC_SZ.W) val uopADD = 15.U(UOPC_SZ.W) val uopSUB = 16.U(UOPC_SZ.W) val uopSLT = 17.U(UOPC_SZ.W) val uopSLTU = 18.U(UOPC_SZ.W) val uopAND = 19.U(UOPC_SZ.W) val uopOR = 20.U(UOPC_SZ.W) val uopXOR = 21.U(UOPC_SZ.W) val uopSRA = 22.U(UOPC_SZ.W) val uopSRL = 23.U(UOPC_SZ.W) val uopBEQ = 24.U(UOPC_SZ.W) val uopBNE = 25.U(UOPC_SZ.W) val uopBGE = 26.U(UOPC_SZ.W) val uopBGEU = 27.U(UOPC_SZ.W) val uopBLT = 28.U(UOPC_SZ.W) val uopBLTU = 29.U(UOPC_SZ.W) val uopCSRRW= 30.U(UOPC_SZ.W) val uopCSRRS= 31.U(UOPC_SZ.W) val uopCSRRC= 32.U(UOPC_SZ.W) val uopCSRRWI=33.U(UOPC_SZ.W) val uopCSRRSI=34.U(UOPC_SZ.W) val uopCSRRCI=35.U(UOPC_SZ.W) val uopJ = 36.U(UOPC_SZ.W) val uopJAL = 37.U(UOPC_SZ.W) val uopJALR = 38.U(UOPC_SZ.W) val uopAUIPC= 39.U(UOPC_SZ.W) //val uopSRET = 40.U(UOPC_SZ.W) val uopCFLSH= 41.U(UOPC_SZ.W) val uopFENCE= 42.U(UOPC_SZ.W) val uopADDIW= 43.U(UOPC_SZ.W) val uopADDW = 44.U(UOPC_SZ.W) val uopSUBW = 45.U(UOPC_SZ.W) val uopSLLIW= 46.U(UOPC_SZ.W) val uopSLLW = 47.U(UOPC_SZ.W) val uopSRAIW= 48.U(UOPC_SZ.W) val uopSRAW = 49.U(UOPC_SZ.W) val uopSRLIW= 50.U(UOPC_SZ.W) val uopSRLW = 51.U(UOPC_SZ.W) val uopMUL = 52.U(UOPC_SZ.W) val uopMULH = 53.U(UOPC_SZ.W) val uopMULHU= 54.U(UOPC_SZ.W) val uopMULHSU=55.U(UOPC_SZ.W) val uopMULW = 56.U(UOPC_SZ.W) val uopDIV = 57.U(UOPC_SZ.W) val uopDIVU = 58.U(UOPC_SZ.W) val uopREM = 59.U(UOPC_SZ.W) val uopREMU = 60.U(UOPC_SZ.W) val uopDIVW = 61.U(UOPC_SZ.W) val uopDIVUW= 62.U(UOPC_SZ.W) val uopREMW = 63.U(UOPC_SZ.W) val uopREMUW= 64.U(UOPC_SZ.W) val uopFENCEI = 65.U(UOPC_SZ.W) // = 66.U(UOPC_SZ.W) val uopAMO_AG = 67.U(UOPC_SZ.W) // AMO-address gen (use normal STD for datagen) val uopFMV_W_X = 68.U(UOPC_SZ.W) val uopFMV_D_X = 69.U(UOPC_SZ.W) val uopFMV_X_W = 70.U(UOPC_SZ.W) val uopFMV_X_D = 71.U(UOPC_SZ.W) val uopFSGNJ_S = 72.U(UOPC_SZ.W) val uopFSGNJ_D = 73.U(UOPC_SZ.W) val uopFCVT_S_D = 74.U(UOPC_SZ.W) val uopFCVT_D_S = 75.U(UOPC_SZ.W) val uopFCVT_S_X = 76.U(UOPC_SZ.W) val uopFCVT_D_X = 77.U(UOPC_SZ.W) val uopFCVT_X_S = 78.U(UOPC_SZ.W) val uopFCVT_X_D = 79.U(UOPC_SZ.W) val uopCMPR_S = 80.U(UOPC_SZ.W) val uopCMPR_D = 81.U(UOPC_SZ.W) val uopFCLASS_S = 82.U(UOPC_SZ.W) val uopFCLASS_D = 83.U(UOPC_SZ.W) val uopFMINMAX_S = 84.U(UOPC_SZ.W) val uopFMINMAX_D = 85.U(UOPC_SZ.W) // = 86.U(UOPC_SZ.W) val uopFADD_S = 87.U(UOPC_SZ.W) val uopFSUB_S = 88.U(UOPC_SZ.W) val uopFMUL_S = 89.U(UOPC_SZ.W) val uopFADD_D = 90.U(UOPC_SZ.W) val uopFSUB_D = 91.U(UOPC_SZ.W) val uopFMUL_D = 92.U(UOPC_SZ.W) val uopFMADD_S = 93.U(UOPC_SZ.W) val uopFMSUB_S = 94.U(UOPC_SZ.W) val uopFNMADD_S = 95.U(UOPC_SZ.W) val uopFNMSUB_S = 96.U(UOPC_SZ.W) val uopFMADD_D = 97.U(UOPC_SZ.W) val uopFMSUB_D = 98.U(UOPC_SZ.W) val uopFNMADD_D = 99.U(UOPC_SZ.W) val uopFNMSUB_D = 100.U(UOPC_SZ.W) val uopFDIV_S = 101.U(UOPC_SZ.W) val uopFDIV_D = 102.U(UOPC_SZ.W) val uopFSQRT_S = 103.U(UOPC_SZ.W) val uopFSQRT_D = 104.U(UOPC_SZ.W) val uopWFI = 105.U(UOPC_SZ.W) // pass uop down the CSR pipeline val uopERET = 106.U(UOPC_SZ.W) // pass uop down the CSR pipeline, also is ERET val uopSFENCE = 107.U(UOPC_SZ.W) val uopROCC = 108.U(UOPC_SZ.W) val uopMOV = 109.U(UOPC_SZ.W) // conditional mov decoded from "add rd, x0, rs2" // The Bubble Instruction (Machine generated NOP) // Insert (XOR x0,x0,x0) which is different from software compiler // generated NOPs which are (ADDI x0, x0, 0). // Reasoning for this is to let visualizers and stat-trackers differentiate // between software NOPs and machine-generated Bubbles in the pipeline. val BUBBLE = (0x4033).U(32.W) def NullMicroOp()(implicit p: Parameters): boom.v3.common.MicroOp = { val uop = Wire(new boom.v3.common.MicroOp) uop := DontCare // Overridden in the following lines uop.uopc := uopNOP // maybe not required, but helps on asserts that try to catch spurious behavior uop.bypassable := false.B uop.fp_val := false.B uop.uses_stq := false.B uop.uses_ldq := false.B uop.pdst := 0.U uop.dst_rtype := RT_X val cs = Wire(new boom.v3.common.CtrlSignals()) cs := DontCare // Overridden in the following lines cs.br_type := BR_N cs.csr_cmd := freechips.rocketchip.rocket.CSR.N cs.is_load := false.B cs.is_sta := false.B cs.is_std := false.B uop.ctrl := cs uop } } /** * Mixin for RISCV constants */ trait RISCVConstants { // abstract out instruction decode magic numbers val RD_MSB = 11 val RD_LSB = 7 val RS1_MSB = 19 val RS1_LSB = 15 val RS2_MSB = 24 val RS2_LSB = 20 val RS3_MSB = 31 val RS3_LSB = 27 val CSR_ADDR_MSB = 31 val CSR_ADDR_LSB = 20 val CSR_ADDR_SZ = 12 // location of the fifth bit in the shamt (for checking for illegal ops for SRAIW,etc.) val SHAMT_5_BIT = 25 val LONGEST_IMM_SZ = 20 val X0 = 0.U val RA = 1.U // return address register // memory consistency model // The C/C++ atomics MCM requires that two loads to the same address maintain program order. // The Cortex A9 does NOT enforce load/load ordering (which leads to buggy behavior). val MCM_ORDER_DEPENDENT_LOADS = true val jal_opc = (0x6f).U val jalr_opc = (0x67).U def GetUop(inst: UInt): UInt = inst(6,0) def GetRd (inst: UInt): UInt = inst(RD_MSB,RD_LSB) def GetRs1(inst: UInt): UInt = inst(RS1_MSB,RS1_LSB) def ExpandRVC(inst: UInt)(implicit p: Parameters): UInt = { val rvc_exp = Module(new RVCExpander) rvc_exp.io.in := inst Mux(rvc_exp.io.rvc, rvc_exp.io.out.bits, inst) } // Note: Accepts only EXPANDED rvc instructions def ComputeBranchTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val b_imm32 = Cat(Fill(20,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) ((pc.asSInt + b_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def ComputeJALTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val j_imm32 = Cat(Fill(12,inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) ((pc.asSInt + j_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def GetCfiType(inst: UInt)(implicit p: Parameters): UInt = { val bdecode = Module(new boom.v3.exu.BranchDecode) bdecode.io.inst := inst bdecode.io.pc := 0.U bdecode.io.out.cfi_type } } /** * Mixin for exception cause constants */ trait ExcCauseConstants { // a memory disambigious misspeculation occurred val MINI_EXCEPTION_MEM_ORDERING = 16.U val MINI_EXCEPTION_CSR_REPLAY = 17.U require (!freechips.rocketchip.rocket.Causes.all.contains(16)) require (!freechips.rocketchip.rocket.Causes.all.contains(17)) } File issue-slot.scala: //****************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Issue Slot Logic //-------------------------------------------------------------------------- //------------------------------------------------------------------------------ // // Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot. // TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores. // TODO Disable ldspec for FP queue. package boom.v3.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import boom.v3.common._ import boom.v3.util._ import FUConstants._ /** * IO bundle to interact with Issue slot * * @param numWakeupPorts number of wakeup ports for the slot */ class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle { val valid = Output(Bool()) val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely? val request = Output(Bool()) val request_hp = Output(Bool()) val grant = Input(Bool()) val brupdate = Input(new BrUpdateInfo()) val kill = Input(Bool()) // pipeline flush val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant) val ldspec_miss = Input(Bool()) // Previous cycle's speculative load wakeup was mispredicted. val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new IqWakeup(maxPregSz)))) val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W))) val spec_ld_wakeup = Flipped(Vec(memWidth, Valid(UInt(width=maxPregSz.W)))) val in_uop = Flipped(Valid(new MicroOp())) // if valid, this WILL overwrite an entry! val out_uop = Output(new MicroOp()) // the updated slot uop; will be shifted upwards in a collasping queue. val uop = Output(new MicroOp()) // the current Slot's uop. Sent down the pipeline when issued. val debug = { val result = new Bundle { val p1 = Bool() val p2 = Bool() val p3 = Bool() val ppred = Bool() val state = UInt(width=2.W) } Output(result) } } /** * Single issue slot. Holds a uop within the issue queue * * @param numWakeupPorts number of wakeup ports */ class IssueSlot(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomModule with IssueUnitConstants { val io = IO(new IssueSlotIO(numWakeupPorts)) // slot invalid? // slot is valid, holding 1 uop // slot is valid, holds 2 uops (like a store) def is_invalid = state === s_invalid def is_valid = state =/= s_invalid val next_state = Wire(UInt()) // the next state of this slot (which might then get moved to a new slot) val next_uopc = Wire(UInt()) // the next uopc of this slot (which might then get moved to a new slot) val next_lrs1_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot) val next_lrs2_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot) val state = RegInit(s_invalid) val p1 = RegInit(false.B) val p2 = RegInit(false.B) val p3 = RegInit(false.B) val ppred = RegInit(false.B) // Poison if woken up by speculative load. // Poison lasts 1 cycle (as ldMiss will come on the next cycle). // SO if poisoned is true, set it to false! val p1_poisoned = RegInit(false.B) val p2_poisoned = RegInit(false.B) p1_poisoned := false.B p2_poisoned := false.B val next_p1_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned) val next_p2_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned) val slot_uop = RegInit(NullMicroOp) val next_uop = Mux(io.in_uop.valid, io.in_uop.bits, slot_uop) //----------------------------------------------------------------------------- // next slot state computation // compute the next state for THIS entry slot (in a collasping queue, the // current uop may get moved elsewhere, and a new uop can enter when (io.kill) { state := s_invalid } .elsewhen (io.in_uop.valid) { state := io.in_uop.bits.iw_state } .elsewhen (io.clear) { state := s_invalid } .otherwise { state := next_state } //----------------------------------------------------------------------------- // "update" state // compute the next state for the micro-op in this slot. This micro-op may // be moved elsewhere, so the "next_state" travels with it. // defaults next_state := state next_uopc := slot_uop.uopc next_lrs1_rtype := slot_uop.lrs1_rtype next_lrs2_rtype := slot_uop.lrs2_rtype when (io.kill) { next_state := s_invalid } .elsewhen ((io.grant && (state === s_valid_1)) || (io.grant && (state === s_valid_2) && p1 && p2 && ppred)) { // try to issue this uop. when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) { next_state := s_invalid } } .elsewhen (io.grant && (state === s_valid_2)) { when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) { next_state := s_valid_1 when (p1) { slot_uop.uopc := uopSTD next_uopc := uopSTD slot_uop.lrs1_rtype := RT_X next_lrs1_rtype := RT_X } .otherwise { slot_uop.lrs2_rtype := RT_X next_lrs2_rtype := RT_X } } } when (io.in_uop.valid) { slot_uop := io.in_uop.bits assert (is_invalid || io.clear || io.kill, "trying to overwrite a valid issue slot.") } // Wakeup Compare Logic // these signals are the "next_p*" for the current slot's micro-op. // they are important for shifting the current slot_uop up to an other entry. val next_p1 = WireInit(p1) val next_p2 = WireInit(p2) val next_p3 = WireInit(p3) val next_ppred = WireInit(ppred) when (io.in_uop.valid) { p1 := !(io.in_uop.bits.prs1_busy) p2 := !(io.in_uop.bits.prs2_busy) p3 := !(io.in_uop.bits.prs3_busy) ppred := !(io.in_uop.bits.ppred_busy) } when (io.ldspec_miss && next_p1_poisoned) { assert(next_uop.prs1 =/= 0.U, "Poison bit can't be set for prs1=x0!") p1 := false.B } when (io.ldspec_miss && next_p2_poisoned) { assert(next_uop.prs2 =/= 0.U, "Poison bit can't be set for prs2=x0!") p2 := false.B } for (i <- 0 until numWakeupPorts) { when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs1)) { p1 := true.B } when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs2)) { p2 := true.B } when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs3)) { p3 := true.B } } when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === next_uop.ppred) { ppred := true.B } for (w <- 0 until memWidth) { assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U), "Loads to x0 should never speculatively wakeup other instructions") } // TODO disable if FP IQ. for (w <- 0 until memWidth) { when (io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === next_uop.prs1 && next_uop.lrs1_rtype === RT_FIX) { p1 := true.B p1_poisoned := true.B assert (!next_p1_poisoned) } when (io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === next_uop.prs2 && next_uop.lrs2_rtype === RT_FIX) { p2 := true.B p2_poisoned := true.B assert (!next_p2_poisoned) } } // Handle branch misspeculations val next_br_mask = GetNewBrMask(io.brupdate, slot_uop) // was this micro-op killed by a branch? if yes, we can't let it be valid if // we compact it into an other entry when (IsKilledByBranch(io.brupdate, slot_uop)) { next_state := s_invalid } when (!io.in_uop.valid) { slot_uop.br_mask := next_br_mask } //------------------------------------------------------------- // Request Logic io.request := is_valid && p1 && p2 && p3 && ppred && !io.kill val high_priority = slot_uop.is_br || slot_uop.is_jal || slot_uop.is_jalr io.request_hp := io.request && high_priority when (state === s_valid_1) { io.request := p1 && p2 && p3 && ppred && !io.kill } .elsewhen (state === s_valid_2) { io.request := (p1 || p2) && ppred && !io.kill } .otherwise { io.request := false.B } //assign outputs io.valid := is_valid io.uop := slot_uop io.uop.iw_p1_poisoned := p1_poisoned io.uop.iw_p2_poisoned := p2_poisoned // micro-op will vacate due to grant. val may_vacate = io.grant && ((state === s_valid_1) || (state === s_valid_2) && p1 && p2 && ppred) val squash_grant = io.ldspec_miss && (p1_poisoned || p2_poisoned) io.will_be_valid := is_valid && !(may_vacate && !squash_grant) io.out_uop := slot_uop io.out_uop.iw_state := next_state io.out_uop.uopc := next_uopc io.out_uop.lrs1_rtype := next_lrs1_rtype io.out_uop.lrs2_rtype := next_lrs2_rtype io.out_uop.br_mask := next_br_mask io.out_uop.prs1_busy := !p1 io.out_uop.prs2_busy := !p2 io.out_uop.prs3_busy := !p3 io.out_uop.ppred_busy := !ppred io.out_uop.iw_p1_poisoned := p1_poisoned io.out_uop.iw_p2_poisoned := p2_poisoned when (state === s_valid_2) { when (p1 && p2 && ppred) { ; // send out the entire instruction as one uop } .elsewhen (p1 && ppred) { io.uop.uopc := slot_uop.uopc io.uop.lrs2_rtype := RT_X } .elsewhen (p2 && ppred) { io.uop.uopc := uopSTD io.uop.lrs1_rtype := RT_X } } // debug outputs io.debug.p1 := p1 io.debug.p2 := p2 io.debug.p3 := p3 io.debug.ppred := ppred io.debug.state := state }
module IssueSlot_125( // @[issue-slot.scala:69:7] input clock, // @[issue-slot.scala:69:7] input reset, // @[issue-slot.scala:69:7] output io_valid, // @[issue-slot.scala:73:14] output io_will_be_valid, // @[issue-slot.scala:73:14] output io_request, // @[issue-slot.scala:73:14] output io_request_hp, // @[issue-slot.scala:73:14] input io_grant, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14] input io_brupdate_b2_valid, // @[issue-slot.scala:73:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14] input io_brupdate_b2_taken, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14] input io_kill, // @[issue-slot.scala:73:14] input io_clear, // @[issue-slot.scala:73:14] input io_ldspec_miss, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_2_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_3_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_3_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_3_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_4_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_4_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_4_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_5_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_5_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_5_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_6_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_6_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_6_bits_poisoned, // @[issue-slot.scala:73:14] input io_spec_ld_wakeup_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_spec_ld_wakeup_0_bits, // @[issue-slot.scala:73:14] input io_in_uop_valid, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14] input io_in_uop_bits_taken, // @[issue-slot.scala:73:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14] input io_in_uop_bits_exception, // @[issue-slot.scala:73:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14] input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14] output io_out_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14] output io_out_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_is_br, // @[issue-slot.scala:73:14] output io_out_uop_is_jalr, // @[issue-slot.scala:73:14] output io_out_uop_is_jal, // @[issue-slot.scala:73:14] output io_out_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_out_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14] output io_out_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:73:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_out_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14] output io_out_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14] output io_out_uop_mem_signed, // @[issue-slot.scala:73:14] output io_out_uop_is_fence, // @[issue-slot.scala:73:14] output io_out_uop_is_fencei, // @[issue-slot.scala:73:14] output io_out_uop_is_amo, // @[issue-slot.scala:73:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_out_uop_uses_stq, // @[issue-slot.scala:73:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_out_uop_is_unique, // @[issue-slot.scala:73:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14] output io_out_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_out_uop_frs3_en, // @[issue-slot.scala:73:14] output io_out_uop_fp_val, // @[issue-slot.scala:73:14] output io_out_uop_fp_single, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14] output io_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14] output io_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_uop_is_br, // @[issue-slot.scala:73:14] output io_uop_is_jalr, // @[issue-slot.scala:73:14] output io_uop_is_jal, // @[issue-slot.scala:73:14] output io_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14] output io_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_uop_ppred, // @[issue-slot.scala:73:14] output io_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14] output io_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14] output io_uop_mem_signed, // @[issue-slot.scala:73:14] output io_uop_is_fence, // @[issue-slot.scala:73:14] output io_uop_is_fencei, // @[issue-slot.scala:73:14] output io_uop_is_amo, // @[issue-slot.scala:73:14] output io_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_uop_uses_stq, // @[issue-slot.scala:73:14] output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_uop_is_unique, // @[issue-slot.scala:73:14] output io_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14] output io_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_uop_frs3_en, // @[issue-slot.scala:73:14] output io_uop_fp_val, // @[issue-slot.scala:73:14] output io_uop_fp_single, // @[issue-slot.scala:73:14] output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14] output io_debug_p1, // @[issue-slot.scala:73:14] output io_debug_p2, // @[issue-slot.scala:73:14] output io_debug_p3, // @[issue-slot.scala:73:14] output io_debug_ppred, // @[issue-slot.scala:73:14] output [1:0] io_debug_state // @[issue-slot.scala:73:14] ); wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7] wire io_ldspec_miss_0 = io_ldspec_miss; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_bits_poisoned_0 = io_wakeup_ports_0_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_bits_poisoned_0 = io_wakeup_ports_1_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_2_bits_pdst_0 = io_wakeup_ports_2_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_bits_poisoned_0 = io_wakeup_ports_2_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_3_bits_pdst_0 = io_wakeup_ports_3_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_3_bits_poisoned_0 = io_wakeup_ports_3_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_4_bits_pdst_0 = io_wakeup_ports_4_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_4_bits_poisoned_0 = io_wakeup_ports_4_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_5_valid_0 = io_wakeup_ports_5_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_5_bits_pdst_0 = io_wakeup_ports_5_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_5_bits_poisoned_0 = io_wakeup_ports_5_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_6_valid_0 = io_wakeup_ports_6_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_6_bits_pdst_0 = io_wakeup_ports_6_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_6_bits_poisoned_0 = io_wakeup_ports_6_bits_poisoned; // @[issue-slot.scala:69:7] wire io_spec_ld_wakeup_0_valid_0 = io_spec_ld_wakeup_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_spec_ld_wakeup_0_bits_0 = io_spec_ld_wakeup_0_bits; // @[issue-slot.scala:69:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p1_poisoned_0 = io_in_uop_bits_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p2_poisoned_0 = io_in_uop_bits_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7] wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7] wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire _io_valid_T; // @[issue-slot.scala:79:24] wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32] wire _io_request_hp_T; // @[issue-slot.scala:243:31] wire [6:0] next_uopc; // @[issue-slot.scala:82:29] wire [1:0] next_state; // @[issue-slot.scala:81:29] wire [15:0] next_br_mask; // @[util.scala:85:25] wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28] wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28] wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28] wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28] wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29] wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29] wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_out_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_out_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire io_debug_p1_0; // @[issue-slot.scala:69:7] wire io_debug_p2_0; // @[issue-slot.scala:69:7] wire io_debug_p3_0; // @[issue-slot.scala:69:7] wire io_debug_ppred_0; // @[issue-slot.scala:69:7] wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7] wire io_valid_0; // @[issue-slot.scala:69:7] wire io_will_be_valid_0; // @[issue-slot.scala:69:7] wire io_request_0; // @[issue-slot.scala:69:7] wire io_request_hp_0; // @[issue-slot.scala:69:7] assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29] assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29] assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29] assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29] reg [1:0] state; // @[issue-slot.scala:86:22] assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22] reg p1; // @[issue-slot.scala:87:22] assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22] wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25] reg p2; // @[issue-slot.scala:88:22] assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22] wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25] reg p3; // @[issue-slot.scala:89:22] assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22] wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25] reg ppred; // @[issue-slot.scala:90:22] assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22] wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28] reg p1_poisoned; // @[issue-slot.scala:95:28] assign io_out_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] assign io_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] reg p2_poisoned; // @[issue-slot.scala:96:28] assign io_out_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] assign io_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] wire next_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : p1_poisoned; // @[issue-slot.scala:69:7, :95:28, :99:29] wire next_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : p2_poisoned; // @[issue-slot.scala:69:7, :96:28, :100:29] reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25] reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25] assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25] assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_rvc; // @[issue-slot.scala:102:25] assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25] assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25] assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25] assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_is_br; // @[issue-slot.scala:102:25] assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jalr; // @[issue-slot.scala:102:25] assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jal; // @[issue-slot.scala:102:25] assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sfb; // @[issue-slot.scala:102:25] assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25] assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25] assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_edge_inst; // @[issue-slot.scala:102:25] assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25] assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_taken; // @[issue-slot.scala:102:25] assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25] assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25] assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25] assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25] assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25] assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:102:25] assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25] assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25] assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25] assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25] assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_exception; // @[issue-slot.scala:102:25] assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25] assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bypassable; // @[issue-slot.scala:102:25] assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25] assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_mem_signed; // @[issue-slot.scala:102:25] assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fence; // @[issue-slot.scala:102:25] assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fencei; // @[issue-slot.scala:102:25] assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_amo; // @[issue-slot.scala:102:25] assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_stq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25] assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_unique; // @[issue-slot.scala:102:25] assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25] assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25] assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25] assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25] assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_val; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25] assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25] reg slot_uop_frs3_en; // @[issue-slot.scala:102:25] assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_val; // @[issue-slot.scala:102:25] assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_single; // @[issue-slot.scala:102:25] assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25] wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}] wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25] wire _T_14 = io_ldspec_miss_0 & (p1_poisoned | p2_poisoned); // @[issue-slot.scala:69:7, :95:28, :96:28, :140:{28,44}] wire _GEN = _T_12 & ~_T_14; // @[issue-slot.scala:126:14, :139:{25,51}, :140:{11,28,62}, :141:18] wire _GEN_0 = io_kill_0 | _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51] wire _GEN_1 = _GEN_0 | ~(_T_12 & ~_T_14 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:{11,28,62}, :142:17, :143:23] assign next_uopc = _GEN_1 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51] assign next_lrs1_rtype = _GEN_1 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51] wire _GEN_2 = _GEN_0 | ~_GEN | p1; // @[issue-slot.scala:87:22, :102:25, :126:14, :131:18, :134:63, :139:51, :140:62, :141:18, :142:17] assign next_lrs2_rtype = _GEN_2 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17] wire _p1_T = ~io_in_uop_bits_prs1_busy_0; // @[issue-slot.scala:69:7, :169:11] wire _p2_T = ~io_in_uop_bits_prs2_busy_0; // @[issue-slot.scala:69:7, :170:11] wire _p3_T = ~io_in_uop_bits_prs3_busy_0; // @[issue-slot.scala:69:7, :171:11] wire _ppred_T = ~io_in_uop_bits_ppred_busy_0; // @[issue-slot.scala:69:7, :172:14] wire _T_22 = io_ldspec_miss_0 & next_p1_poisoned; // @[issue-slot.scala:69:7, :99:29, :175:24] wire _T_27 = io_ldspec_miss_0 & next_p2_poisoned; // @[issue-slot.scala:69:7, :100:29, :179:24] wire _T_85 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs1 & next_uop_lrs1_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :209:38, :210:{33,51}, :211:27] wire _T_93 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs2 & next_uop_lrs2_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :216:38, :217:{33,51}, :218:27]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_479( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File DescribedSRAM.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3.{Data, SyncReadMem, Vec} import chisel3.util.log2Ceil object DescribedSRAM { def apply[T <: Data]( name: String, desc: String, size: BigInt, // depth data: T ): SyncReadMem[T] = { val mem = SyncReadMem(size, data) mem.suggestName(name) val granWidth = data match { case v: Vec[_] => v.head.getWidth case d => d.getWidth } val uid = 0 Annotated.srams( component = mem, name = name, address_width = log2Ceil(size), data_width = data.getWidth, depth = size, description = desc, write_mask_granularity = granWidth ) mem } }
module tag_array( // @[DescribedSRAM.scala:17:26] input [5:0] RW0_addr, input RW0_en, input RW0_clk, input RW0_wmode, input [159:0] RW0_wdata, output [159:0] RW0_rdata, input [7:0] RW0_wmask ); tag_array_ext tag_array_ext ( // @[DescribedSRAM.scala:17:26] .RW0_addr (RW0_addr), .RW0_en (RW0_en), .RW0_clk (RW0_clk), .RW0_wmode (RW0_wmode), .RW0_wdata (RW0_wdata), .RW0_rdata (RW0_rdata), .RW0_wmask (RW0_wmask) ); // @[DescribedSRAM.scala:17:26] endmodule
Generate the Verilog code corresponding to the following Chisel files. File SourceB.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class SourceBRequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val param = UInt(3.W) val tag = UInt(params.tagBits.W) val set = UInt(params.setBits.W) val clients = UInt(params.clientBits.W) } class SourceB(params: InclusiveCacheParameters) extends Module { val io = IO(new Bundle { val req = Flipped(Decoupled(new SourceBRequest(params))) val b = Decoupled(new TLBundleB(params.inner.bundle)) }) if (params.firstLevel) { // Tie off unused ports io.req.ready := true.B io.b.valid := false.B io.b.bits := DontCare } else { val remain = RegInit(0.U(params.clientBits.W)) val remain_set = WireInit(init = 0.U(params.clientBits.W)) val remain_clr = WireInit(init = 0.U(params.clientBits.W)) remain := (remain | remain_set) & ~remain_clr val busy = remain.orR val todo = Mux(busy, remain, io.req.bits.clients) val next = ~(leftOR(todo) << 1) & todo if (params.clientBits > 1) { params.ccover(PopCount(remain) > 1.U, "SOURCEB_MULTI_PROBE", "Had to probe more than one client") } assert (!io.req.valid || io.req.bits.clients =/= 0.U) io.req.ready := !busy when (io.req.fire) { remain_set := io.req.bits.clients } // No restrictions on the type of buffer used here val b = Wire(chiselTypeOf(io.b)) io.b <> params.micro.innerBuf.b(b) b.valid := busy || io.req.valid when (b.fire) { remain_clr := next } params.ccover(b.valid && !b.ready, "SOURCEB_STALL", "Backpressured when issuing a probe") val tag = Mux(!busy, io.req.bits.tag, RegEnable(io.req.bits.tag, io.req.fire)) val set = Mux(!busy, io.req.bits.set, RegEnable(io.req.bits.set, io.req.fire)) val param = Mux(!busy, io.req.bits.param, RegEnable(io.req.bits.param, io.req.fire)) b.bits.opcode := TLMessages.Probe b.bits.param := param b.bits.size := params.offsetBits .U b.bits.source := params.clientSource(next) b.bits.address := params.expandAddress(tag, set, 0.U) b.bits.mask := ~0.U(params.inner.manager.beatBytes.W) b.bits.data := 0.U b.bits.corrupt := false.B } } File Parameters.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property.cover import scala.math.{min,max} case class CacheParameters( level: Int, ways: Int, sets: Int, blockBytes: Int, beatBytes: Int, // inner hintsSkipProbe: Boolean) { require (ways > 0) require (sets > 0) require (blockBytes > 0 && isPow2(blockBytes)) require (beatBytes > 0 && isPow2(beatBytes)) require (blockBytes >= beatBytes) val blocks = ways * sets val sizeBytes = blocks * blockBytes val blockBeats = blockBytes/beatBytes } case class InclusiveCachePortParameters( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams) { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new TLBuffer(a, b, c, d, e)) } object InclusiveCachePortParameters { val none = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.none) val full = InclusiveCachePortParameters( a = BufferParams.default, b = BufferParams.default, c = BufferParams.default, d = BufferParams.default, e = BufferParams.default) // This removes feed-through paths from C=>A and A=>C val fullC = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.default, d = BufferParams.none, e = BufferParams.none) val flowAD = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.flow, e = BufferParams.none) val flowAE = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.flow) // For innerBuf: // SinkA: no restrictions, flows into scheduler+putbuffer // SourceB: no restrictions, flows out of scheduler // sinkC: no restrictions, flows into scheduler+putbuffer & buffered to bankedStore // SourceD: no restrictions, flows out of bankedStore/regout // SinkE: no restrictions, flows into scheduler // // ... so while none is possible, you probably want at least flowAC to cut ready // from the scheduler delay and flowD to ease SourceD back-pressure // For outerBufer: // SourceA: must not be pipe, flows out of scheduler // SinkB: no restrictions, flows into scheduler // SourceC: pipe is useless, flows out of bankedStore/regout, parameter depth ignored // SinkD: no restrictions, flows into scheduler & bankedStore // SourceE: must not be pipe, flows out of scheduler // // ... AE take the channel ready into the scheduler, so you need at least flowAE } case class InclusiveCacheMicroParameters( writeBytes: Int, // backing store update granularity memCycles: Int = 40, // # of L2 clock cycles for a memory round-trip (50ns @ 800MHz) portFactor: Int = 4, // numSubBanks = (widest TL port * portFactor) / writeBytes dirReg: Boolean = false, innerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.fullC, // or none outerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.full) // or flowAE { require (writeBytes > 0 && isPow2(writeBytes)) require (memCycles > 0) require (portFactor >= 2) // for inner RMW and concurrent outer Relase + Grant } case class InclusiveCacheControlParameters( address: BigInt, beatBytes: Int, bankedControl: Boolean) case class InclusiveCacheParameters( cache: CacheParameters, micro: InclusiveCacheMicroParameters, control: Boolean, inner: TLEdgeIn, outer: TLEdgeOut)(implicit val p: Parameters) { require (cache.ways > 1) require (cache.sets > 1 && isPow2(cache.sets)) require (micro.writeBytes <= inner.manager.beatBytes) require (micro.writeBytes <= outer.manager.beatBytes) require (inner.manager.beatBytes <= cache.blockBytes) require (outer.manager.beatBytes <= cache.blockBytes) // Require that all cached address ranges have contiguous blocks outer.manager.managers.flatMap(_.address).foreach { a => require (a.alignment >= cache.blockBytes) } // If we are the first level cache, we do not need to support inner-BCE val firstLevel = !inner.client.clients.exists(_.supports.probe) // If we are the last level cache, we do not need to support outer-B val lastLevel = !outer.manager.managers.exists(_.regionType > RegionType.UNCACHED) require (lastLevel) // Provision enough resources to achieve full throughput with missing single-beat accesses val mshrs = InclusiveCacheParameters.all_mshrs(cache, micro) val secondary = max(mshrs, micro.memCycles - mshrs) val putLists = micro.memCycles // allow every request to be single beat val putBeats = max(2*cache.blockBeats, micro.memCycles) val relLists = 2 val relBeats = relLists*cache.blockBeats val flatAddresses = AddressSet.unify(outer.manager.managers.flatMap(_.address)) val pickMask = AddressDecoder(flatAddresses.map(Seq(_)), flatAddresses.map(_.mask).reduce(_|_)) def bitOffsets(x: BigInt, offset: Int = 0, tail: List[Int] = List.empty[Int]): List[Int] = if (x == 0) tail.reverse else bitOffsets(x >> 1, offset + 1, if ((x & 1) == 1) offset :: tail else tail) val addressMapping = bitOffsets(pickMask) val addressBits = addressMapping.size // println(s"addresses: ${flatAddresses} => ${pickMask} => ${addressBits}") val allClients = inner.client.clients.size val clientBitsRaw = inner.client.clients.filter(_.supports.probe).size val clientBits = max(1, clientBitsRaw) val stateBits = 2 val wayBits = log2Ceil(cache.ways) val setBits = log2Ceil(cache.sets) val offsetBits = log2Ceil(cache.blockBytes) val tagBits = addressBits - setBits - offsetBits val putBits = log2Ceil(max(putLists, relLists)) require (tagBits > 0) require (offsetBits > 0) val innerBeatBits = (offsetBits - log2Ceil(inner.manager.beatBytes)) max 1 val outerBeatBits = (offsetBits - log2Ceil(outer.manager.beatBytes)) max 1 val innerMaskBits = inner.manager.beatBytes / micro.writeBytes val outerMaskBits = outer.manager.beatBytes / micro.writeBytes def clientBit(source: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Cat(inner.client.clients.filter(_.supports.probe).map(_.sourceId.contains(source)).reverse) } } def clientSource(bit: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Mux1H(bit, inner.client.clients.filter(_.supports.probe).map(c => c.sourceId.start.U)) } } def parseAddress(x: UInt): (UInt, UInt, UInt) = { val offset = Cat(addressMapping.map(o => x(o,o)).reverse) val set = offset >> offsetBits val tag = set >> setBits (tag(tagBits-1, 0), set(setBits-1, 0), offset(offsetBits-1, 0)) } def widen(x: UInt, width: Int): UInt = { val y = x | 0.U(width.W) assert (y >> width === 0.U) y(width-1, 0) } def expandAddress(tag: UInt, set: UInt, offset: UInt): UInt = { val base = Cat(widen(tag, tagBits), widen(set, setBits), widen(offset, offsetBits)) val bits = Array.fill(outer.bundle.addressBits) { 0.U(1.W) } addressMapping.zipWithIndex.foreach { case (a, i) => bits(a) = base(i,i) } Cat(bits.reverse) } def restoreAddress(expanded: UInt): UInt = { val missingBits = flatAddresses .map { a => (a.widen(pickMask).base, a.widen(~pickMask)) } // key is the bits to restore on match .groupBy(_._1) .view .mapValues(_.map(_._2)) val muxMask = AddressDecoder(missingBits.values.toList) val mux = missingBits.toList.map { case (bits, addrs) => val widen = addrs.map(_.widen(~muxMask)) val matches = AddressSet .unify(widen.distinct) .map(_.contains(expanded)) .reduce(_ || _) (matches, bits.U) } expanded | Mux1H(mux) } def dirReg[T <: Data](x: T, en: Bool = true.B): T = { if (micro.dirReg) RegEnable(x, en) else x } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = cover(cond, "CCACHE_L" + cache.level + "_" + label, "MemorySystem;;" + desc) } object MetaData { val stateBits = 2 def INVALID: UInt = 0.U(stateBits.W) // way is empty def BRANCH: UInt = 1.U(stateBits.W) // outer slave cache is trunk def TRUNK: UInt = 2.U(stateBits.W) // unique inner master cache is trunk def TIP: UInt = 3.U(stateBits.W) // we are trunk, inner masters are branch // Does a request need trunk? def needT(opcode: UInt, param: UInt): Bool = { !opcode(2) || (opcode === TLMessages.Hint && param === TLHints.PREFETCH_WRITE) || ((opcode === TLMessages.AcquireBlock || opcode === TLMessages.AcquirePerm) && param =/= TLPermissions.NtoB) } // Does a request prove the client need not be probed? def skipProbeN(opcode: UInt, hintsSkipProbe: Boolean): Bool = { // Acquire(toB) and Get => is N, so no probe // Acquire(*toT) => is N or B, but need T, so no probe // Hint => could be anything, so probe IS needed, if hintsSkipProbe is enabled, skip probe the same client // Put* => is N or B, so probe IS needed opcode === TLMessages.AcquireBlock || opcode === TLMessages.AcquirePerm || opcode === TLMessages.Get || (opcode === TLMessages.Hint && hintsSkipProbe.B) } def isToN(param: UInt): Bool = { param === TLPermissions.TtoN || param === TLPermissions.BtoN || param === TLPermissions.NtoN } def isToB(param: UInt): Bool = { param === TLPermissions.TtoB || param === TLPermissions.BtoB } } object InclusiveCacheParameters { val lfsrBits = 10 val L2ControlAddress = 0x2010000 val L2ControlSize = 0x1000 def out_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = { // We need 2-3 normal MSHRs to cover the Directory latency // To fully exploit memory bandwidth-delay-product, we need memCyles/blockBeats MSHRs max(if (micro.dirReg) 3 else 2, (micro.memCycles + cache.blockBeats - 1) / cache.blockBeats) } def all_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = // We need a dedicated MSHR for B+C each 2 + out_mshrs(cache, micro) } class InclusiveCacheBundle(params: InclusiveCacheParameters) extends Bundle
module SourceB( // @[SourceB.scala:33:7] input clock, // @[SourceB.scala:33:7] input reset, // @[SourceB.scala:33:7] output io_req_ready, // @[SourceB.scala:35:14] input io_req_valid, // @[SourceB.scala:35:14] input [2:0] io_req_bits_param, // @[SourceB.scala:35:14] input [12:0] io_req_bits_tag, // @[SourceB.scala:35:14] input [9:0] io_req_bits_set, // @[SourceB.scala:35:14] input [7:0] io_req_bits_clients, // @[SourceB.scala:35:14] input io_b_ready, // @[SourceB.scala:35:14] output io_b_valid, // @[SourceB.scala:35:14] output [1:0] io_b_bits_param, // @[SourceB.scala:35:14] output [5:0] io_b_bits_source, // @[SourceB.scala:35:14] output [31:0] io_b_bits_address // @[SourceB.scala:35:14] ); wire io_req_valid_0 = io_req_valid; // @[SourceB.scala:33:7] wire [2:0] io_req_bits_param_0 = io_req_bits_param; // @[SourceB.scala:33:7] wire [12:0] io_req_bits_tag_0 = io_req_bits_tag; // @[SourceB.scala:33:7] wire [9:0] io_req_bits_set_0 = io_req_bits_set; // @[SourceB.scala:33:7] wire [7:0] io_req_bits_clients_0 = io_req_bits_clients; // @[SourceB.scala:33:7] wire io_b_ready_0 = io_b_ready; // @[SourceB.scala:33:7] wire _b_bits_address_base_T_2 = reset; // @[Parameters.scala:222:12] wire _b_bits_address_base_T_8 = reset; // @[Parameters.scala:222:12] wire _b_bits_address_base_T_14 = reset; // @[Parameters.scala:222:12] wire [2:0] io_b_bits_opcode = 3'h6; // @[SourceB.scala:33:7] wire [2:0] io_b_bits_size = 3'h6; // @[SourceB.scala:33:7] wire [2:0] b_bits_opcode = 3'h6; // @[SourceB.scala:65:17] wire [2:0] b_bits_size = 3'h6; // @[SourceB.scala:65:17] wire [7:0] io_b_bits_mask = 8'hFF; // @[SourceB.scala:33:7] wire [7:0] b_bits_mask = 8'hFF; // @[SourceB.scala:65:17] wire [7:0] _b_bits_mask_T = 8'hFF; // @[SourceB.scala:81:23] wire [63:0] io_b_bits_data = 64'h0; // @[SourceB.scala:33:7] wire [63:0] b_bits_data = 64'h0; // @[SourceB.scala:65:17] wire io_b_bits_corrupt = 1'h0; // @[SourceB.scala:33:7] wire b_bits_corrupt = 1'h0; // @[SourceB.scala:65:17] wire _b_bits_address_base_T = 1'h0; // @[Parameters.scala:222:15] wire _b_bits_address_base_T_4 = 1'h0; // @[Parameters.scala:222:12] wire _b_bits_address_base_T_6 = 1'h0; // @[Parameters.scala:222:15] wire _b_bits_address_base_T_10 = 1'h0; // @[Parameters.scala:222:12] wire _b_bits_address_base_T_12 = 1'h0; // @[Parameters.scala:222:15] wire _b_bits_address_base_T_16 = 1'h0; // @[Parameters.scala:222:12] wire [1:0] b_bits_address_hi_hi_hi_lo = 2'h0; // @[Parameters.scala:230:8] wire [5:0] b_bits_address_base_y_2 = 6'h0; // @[Parameters.scala:221:15] wire [5:0] _b_bits_address_base_T_17 = 6'h0; // @[Parameters.scala:223:6] wire _b_bits_address_base_T_1 = 1'h1; // @[Parameters.scala:222:24] wire _b_bits_address_base_T_7 = 1'h1; // @[Parameters.scala:222:24] wire _b_bits_address_base_T_13 = 1'h1; // @[Parameters.scala:222:24] wire _io_req_ready_T; // @[SourceB.scala:61:21] wire b_ready = io_b_ready_0; // @[SourceB.scala:33:7, :65:17] wire b_valid; // @[SourceB.scala:65:17] wire [1:0] b_bits_param; // @[SourceB.scala:65:17] wire [5:0] b_bits_source; // @[SourceB.scala:65:17] wire [31:0] b_bits_address; // @[SourceB.scala:65:17] wire io_req_ready_0; // @[SourceB.scala:33:7] wire [1:0] io_b_bits_param_0; // @[SourceB.scala:33:7] wire [5:0] io_b_bits_source_0; // @[SourceB.scala:33:7] wire [31:0] io_b_bits_address_0; // @[SourceB.scala:33:7] wire io_b_valid_0; // @[SourceB.scala:33:7] reg [7:0] remain; // @[SourceB.scala:46:25] wire [7:0] remain_set; // @[SourceB.scala:47:30] wire [7:0] remain_clr; // @[SourceB.scala:48:30] wire [7:0] _remain_T = remain | remain_set; // @[SourceB.scala:46:25, :47:30, :49:23] wire [7:0] _remain_T_1 = ~remain_clr; // @[SourceB.scala:48:30, :49:39] wire [7:0] _remain_T_2 = _remain_T & _remain_T_1; // @[SourceB.scala:49:{23,37,39}] wire busy = |remain; // @[SourceB.scala:46:25, :51:23] wire [7:0] todo = busy ? remain : io_req_bits_clients_0; // @[SourceB.scala:33:7, :46:25, :51:23, :52:19] wire [8:0] _next_T = {todo, 1'h0}; // @[package.scala:253:48] wire [7:0] _next_T_1 = _next_T[7:0]; // @[package.scala:253:{48,53}] wire [7:0] _next_T_2 = todo | _next_T_1; // @[package.scala:253:{43,53}] wire [9:0] _next_T_3 = {_next_T_2, 2'h0}; // @[package.scala:253:{43,48}] wire [7:0] _next_T_4 = _next_T_3[7:0]; // @[package.scala:253:{48,53}] wire [7:0] _next_T_5 = _next_T_2 | _next_T_4; // @[package.scala:253:{43,53}] wire [11:0] _next_T_6 = {_next_T_5, 4'h0}; // @[package.scala:253:{43,48}] wire [7:0] _next_T_7 = _next_T_6[7:0]; // @[package.scala:253:{48,53}] wire [7:0] _next_T_8 = _next_T_5 | _next_T_7; // @[package.scala:253:{43,53}] wire [7:0] _next_T_9 = _next_T_8; // @[package.scala:253:43, :254:17] wire [8:0] _next_T_10 = {_next_T_9, 1'h0}; // @[package.scala:254:17] wire [8:0] _next_T_11 = ~_next_T_10; // @[SourceB.scala:53:{16,31}] wire [8:0] next = {1'h0, _next_T_11[7:0] & todo}; // @[SourceB.scala:52:19, :53:{16,37}]
Generate the Verilog code corresponding to the following Chisel files. File SourceB.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class SourceBRequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val param = UInt(3.W) val tag = UInt(params.tagBits.W) val set = UInt(params.setBits.W) val clients = UInt(params.clientBits.W) } class SourceB(params: InclusiveCacheParameters) extends Module { val io = IO(new Bundle { val req = Flipped(Decoupled(new SourceBRequest(params))) val b = Decoupled(new TLBundleB(params.inner.bundle)) }) if (params.firstLevel) { // Tie off unused ports io.req.ready := true.B io.b.valid := false.B io.b.bits := DontCare } else { val remain = RegInit(0.U(params.clientBits.W)) val remain_set = WireInit(init = 0.U(params.clientBits.W)) val remain_clr = WireInit(init = 0.U(params.clientBits.W)) remain := (remain | remain_set) & ~remain_clr val busy = remain.orR val todo = Mux(busy, remain, io.req.bits.clients) val next = ~(leftOR(todo) << 1) & todo if (params.clientBits > 1) { params.ccover(PopCount(remain) > 1.U, "SOURCEB_MULTI_PROBE", "Had to probe more than one client") } assert (!io.req.valid || io.req.bits.clients =/= 0.U) io.req.ready := !busy when (io.req.fire) { remain_set := io.req.bits.clients } // No restrictions on the type of buffer used here val b = Wire(chiselTypeOf(io.b)) io.b <> params.micro.innerBuf.b(b) b.valid := busy || io.req.valid when (b.fire) { remain_clr := next } params.ccover(b.valid && !b.ready, "SOURCEB_STALL", "Backpressured when issuing a probe") val tag = Mux(!busy, io.req.bits.tag, RegEnable(io.req.bits.tag, io.req.fire)) val set = Mux(!busy, io.req.bits.set, RegEnable(io.req.bits.set, io.req.fire)) val param = Mux(!busy, io.req.bits.param, RegEnable(io.req.bits.param, io.req.fire)) b.bits.opcode := TLMessages.Probe b.bits.param := param b.bits.size := params.offsetBits .U b.bits.source := params.clientSource(next) b.bits.address := params.expandAddress(tag, set, 0.U) b.bits.mask := ~0.U(params.inner.manager.beatBytes.W) b.bits.data := 0.U b.bits.corrupt := false.B } } File Parameters.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property.cover import scala.math.{min,max} case class CacheParameters( level: Int, ways: Int, sets: Int, blockBytes: Int, beatBytes: Int, // inner hintsSkipProbe: Boolean) { require (ways > 0) require (sets > 0) require (blockBytes > 0 && isPow2(blockBytes)) require (beatBytes > 0 && isPow2(beatBytes)) require (blockBytes >= beatBytes) val blocks = ways * sets val sizeBytes = blocks * blockBytes val blockBeats = blockBytes/beatBytes } case class InclusiveCachePortParameters( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams) { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new TLBuffer(a, b, c, d, e)) } object InclusiveCachePortParameters { val none = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.none) val full = InclusiveCachePortParameters( a = BufferParams.default, b = BufferParams.default, c = BufferParams.default, d = BufferParams.default, e = BufferParams.default) // This removes feed-through paths from C=>A and A=>C val fullC = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.default, d = BufferParams.none, e = BufferParams.none) val flowAD = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.flow, e = BufferParams.none) val flowAE = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.flow) // For innerBuf: // SinkA: no restrictions, flows into scheduler+putbuffer // SourceB: no restrictions, flows out of scheduler // sinkC: no restrictions, flows into scheduler+putbuffer & buffered to bankedStore // SourceD: no restrictions, flows out of bankedStore/regout // SinkE: no restrictions, flows into scheduler // // ... so while none is possible, you probably want at least flowAC to cut ready // from the scheduler delay and flowD to ease SourceD back-pressure // For outerBufer: // SourceA: must not be pipe, flows out of scheduler // SinkB: no restrictions, flows into scheduler // SourceC: pipe is useless, flows out of bankedStore/regout, parameter depth ignored // SinkD: no restrictions, flows into scheduler & bankedStore // SourceE: must not be pipe, flows out of scheduler // // ... AE take the channel ready into the scheduler, so you need at least flowAE } case class InclusiveCacheMicroParameters( writeBytes: Int, // backing store update granularity memCycles: Int = 40, // # of L2 clock cycles for a memory round-trip (50ns @ 800MHz) portFactor: Int = 4, // numSubBanks = (widest TL port * portFactor) / writeBytes dirReg: Boolean = false, innerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.fullC, // or none outerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.full) // or flowAE { require (writeBytes > 0 && isPow2(writeBytes)) require (memCycles > 0) require (portFactor >= 2) // for inner RMW and concurrent outer Relase + Grant } case class InclusiveCacheControlParameters( address: BigInt, beatBytes: Int, bankedControl: Boolean) case class InclusiveCacheParameters( cache: CacheParameters, micro: InclusiveCacheMicroParameters, control: Boolean, inner: TLEdgeIn, outer: TLEdgeOut)(implicit val p: Parameters) { require (cache.ways > 1) require (cache.sets > 1 && isPow2(cache.sets)) require (micro.writeBytes <= inner.manager.beatBytes) require (micro.writeBytes <= outer.manager.beatBytes) require (inner.manager.beatBytes <= cache.blockBytes) require (outer.manager.beatBytes <= cache.blockBytes) // Require that all cached address ranges have contiguous blocks outer.manager.managers.flatMap(_.address).foreach { a => require (a.alignment >= cache.blockBytes) } // If we are the first level cache, we do not need to support inner-BCE val firstLevel = !inner.client.clients.exists(_.supports.probe) // If we are the last level cache, we do not need to support outer-B val lastLevel = !outer.manager.managers.exists(_.regionType > RegionType.UNCACHED) require (lastLevel) // Provision enough resources to achieve full throughput with missing single-beat accesses val mshrs = InclusiveCacheParameters.all_mshrs(cache, micro) val secondary = max(mshrs, micro.memCycles - mshrs) val putLists = micro.memCycles // allow every request to be single beat val putBeats = max(2*cache.blockBeats, micro.memCycles) val relLists = 2 val relBeats = relLists*cache.blockBeats val flatAddresses = AddressSet.unify(outer.manager.managers.flatMap(_.address)) val pickMask = AddressDecoder(flatAddresses.map(Seq(_)), flatAddresses.map(_.mask).reduce(_|_)) def bitOffsets(x: BigInt, offset: Int = 0, tail: List[Int] = List.empty[Int]): List[Int] = if (x == 0) tail.reverse else bitOffsets(x >> 1, offset + 1, if ((x & 1) == 1) offset :: tail else tail) val addressMapping = bitOffsets(pickMask) val addressBits = addressMapping.size // println(s"addresses: ${flatAddresses} => ${pickMask} => ${addressBits}") val allClients = inner.client.clients.size val clientBitsRaw = inner.client.clients.filter(_.supports.probe).size val clientBits = max(1, clientBitsRaw) val stateBits = 2 val wayBits = log2Ceil(cache.ways) val setBits = log2Ceil(cache.sets) val offsetBits = log2Ceil(cache.blockBytes) val tagBits = addressBits - setBits - offsetBits val putBits = log2Ceil(max(putLists, relLists)) require (tagBits > 0) require (offsetBits > 0) val innerBeatBits = (offsetBits - log2Ceil(inner.manager.beatBytes)) max 1 val outerBeatBits = (offsetBits - log2Ceil(outer.manager.beatBytes)) max 1 val innerMaskBits = inner.manager.beatBytes / micro.writeBytes val outerMaskBits = outer.manager.beatBytes / micro.writeBytes def clientBit(source: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Cat(inner.client.clients.filter(_.supports.probe).map(_.sourceId.contains(source)).reverse) } } def clientSource(bit: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Mux1H(bit, inner.client.clients.filter(_.supports.probe).map(c => c.sourceId.start.U)) } } def parseAddress(x: UInt): (UInt, UInt, UInt) = { val offset = Cat(addressMapping.map(o => x(o,o)).reverse) val set = offset >> offsetBits val tag = set >> setBits (tag(tagBits-1, 0), set(setBits-1, 0), offset(offsetBits-1, 0)) } def widen(x: UInt, width: Int): UInt = { val y = x | 0.U(width.W) assert (y >> width === 0.U) y(width-1, 0) } def expandAddress(tag: UInt, set: UInt, offset: UInt): UInt = { val base = Cat(widen(tag, tagBits), widen(set, setBits), widen(offset, offsetBits)) val bits = Array.fill(outer.bundle.addressBits) { 0.U(1.W) } addressMapping.zipWithIndex.foreach { case (a, i) => bits(a) = base(i,i) } Cat(bits.reverse) } def restoreAddress(expanded: UInt): UInt = { val missingBits = flatAddresses .map { a => (a.widen(pickMask).base, a.widen(~pickMask)) } // key is the bits to restore on match .groupBy(_._1) .view .mapValues(_.map(_._2)) val muxMask = AddressDecoder(missingBits.values.toList) val mux = missingBits.toList.map { case (bits, addrs) => val widen = addrs.map(_.widen(~muxMask)) val matches = AddressSet .unify(widen.distinct) .map(_.contains(expanded)) .reduce(_ || _) (matches, bits.U) } expanded | Mux1H(mux) } def dirReg[T <: Data](x: T, en: Bool = true.B): T = { if (micro.dirReg) RegEnable(x, en) else x } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = cover(cond, "CCACHE_L" + cache.level + "_" + label, "MemorySystem;;" + desc) } object MetaData { val stateBits = 2 def INVALID: UInt = 0.U(stateBits.W) // way is empty def BRANCH: UInt = 1.U(stateBits.W) // outer slave cache is trunk def TRUNK: UInt = 2.U(stateBits.W) // unique inner master cache is trunk def TIP: UInt = 3.U(stateBits.W) // we are trunk, inner masters are branch // Does a request need trunk? def needT(opcode: UInt, param: UInt): Bool = { !opcode(2) || (opcode === TLMessages.Hint && param === TLHints.PREFETCH_WRITE) || ((opcode === TLMessages.AcquireBlock || opcode === TLMessages.AcquirePerm) && param =/= TLPermissions.NtoB) } // Does a request prove the client need not be probed? def skipProbeN(opcode: UInt, hintsSkipProbe: Boolean): Bool = { // Acquire(toB) and Get => is N, so no probe // Acquire(*toT) => is N or B, but need T, so no probe // Hint => could be anything, so probe IS needed, if hintsSkipProbe is enabled, skip probe the same client // Put* => is N or B, so probe IS needed opcode === TLMessages.AcquireBlock || opcode === TLMessages.AcquirePerm || opcode === TLMessages.Get || (opcode === TLMessages.Hint && hintsSkipProbe.B) } def isToN(param: UInt): Bool = { param === TLPermissions.TtoN || param === TLPermissions.BtoN || param === TLPermissions.NtoN } def isToB(param: UInt): Bool = { param === TLPermissions.TtoB || param === TLPermissions.BtoB } } object InclusiveCacheParameters { val lfsrBits = 10 val L2ControlAddress = 0x2010000 val L2ControlSize = 0x1000 def out_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = { // We need 2-3 normal MSHRs to cover the Directory latency // To fully exploit memory bandwidth-delay-product, we need memCyles/blockBeats MSHRs max(if (micro.dirReg) 3 else 2, (micro.memCycles + cache.blockBeats - 1) / cache.blockBeats) } def all_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = // We need a dedicated MSHR for B+C each 2 + out_mshrs(cache, micro) } class InclusiveCacheBundle(params: InclusiveCacheParameters) extends Bundle
module SourceB( // @[SourceB.scala:33:7] input clock, // @[SourceB.scala:33:7] input reset, // @[SourceB.scala:33:7] output io_req_ready, // @[SourceB.scala:35:14] input io_req_valid, // @[SourceB.scala:35:14] input [2:0] io_req_bits_param, // @[SourceB.scala:35:14] input [12:0] io_req_bits_tag, // @[SourceB.scala:35:14] input [9:0] io_req_bits_set, // @[SourceB.scala:35:14] input io_req_bits_clients, // @[SourceB.scala:35:14] input io_b_ready, // @[SourceB.scala:35:14] output io_b_valid, // @[SourceB.scala:35:14] output [1:0] io_b_bits_param, // @[SourceB.scala:35:14] output [31:0] io_b_bits_address // @[SourceB.scala:35:14] ); wire io_req_valid_0 = io_req_valid; // @[SourceB.scala:33:7] wire [2:0] io_req_bits_param_0 = io_req_bits_param; // @[SourceB.scala:33:7] wire [12:0] io_req_bits_tag_0 = io_req_bits_tag; // @[SourceB.scala:33:7] wire [9:0] io_req_bits_set_0 = io_req_bits_set; // @[SourceB.scala:33:7] wire io_req_bits_clients_0 = io_req_bits_clients; // @[SourceB.scala:33:7] wire io_b_ready_0 = io_b_ready; // @[SourceB.scala:33:7] wire _b_bits_address_base_T_2 = reset; // @[Parameters.scala:222:12] wire _b_bits_address_base_T_8 = reset; // @[Parameters.scala:222:12] wire _b_bits_address_base_T_14 = reset; // @[Parameters.scala:222:12] wire [2:0] io_b_bits_opcode = 3'h6; // @[SourceB.scala:33:7] wire [2:0] io_b_bits_size = 3'h6; // @[SourceB.scala:33:7] wire [2:0] b_bits_opcode = 3'h6; // @[SourceB.scala:65:17] wire [2:0] b_bits_size = 3'h6; // @[SourceB.scala:65:17] wire [5:0] io_b_bits_source = 6'h10; // @[SourceB.scala:33:7] wire [5:0] b_bits_source = 6'h10; // @[SourceB.scala:65:17] wire [7:0] io_b_bits_mask = 8'hFF; // @[SourceB.scala:33:7] wire [7:0] b_bits_mask = 8'hFF; // @[SourceB.scala:65:17] wire [7:0] _b_bits_mask_T = 8'hFF; // @[SourceB.scala:81:23] wire [63:0] io_b_bits_data = 64'h0; // @[SourceB.scala:33:7] wire [63:0] b_bits_data = 64'h0; // @[SourceB.scala:65:17] wire io_b_bits_corrupt = 1'h0; // @[SourceB.scala:33:7] wire b_bits_corrupt = 1'h0; // @[SourceB.scala:65:17] wire _b_bits_address_base_T = 1'h0; // @[Parameters.scala:222:15] wire _b_bits_address_base_T_4 = 1'h0; // @[Parameters.scala:222:12] wire _b_bits_address_base_T_6 = 1'h0; // @[Parameters.scala:222:15] wire _b_bits_address_base_T_10 = 1'h0; // @[Parameters.scala:222:12] wire _b_bits_address_base_T_12 = 1'h0; // @[Parameters.scala:222:15] wire _b_bits_address_base_T_16 = 1'h0; // @[Parameters.scala:222:12] wire [1:0] b_bits_address_hi_hi_hi_lo = 2'h0; // @[Parameters.scala:230:8] wire [5:0] b_bits_address_base_y_2 = 6'h0; // @[Parameters.scala:221:15] wire [5:0] _b_bits_address_base_T_17 = 6'h0; // @[Parameters.scala:223:6] wire _b_bits_address_base_T_1 = 1'h1; // @[Parameters.scala:222:24] wire _b_bits_address_base_T_7 = 1'h1; // @[Parameters.scala:222:24] wire _b_bits_address_base_T_13 = 1'h1; // @[Parameters.scala:222:24] wire _io_req_ready_T; // @[SourceB.scala:61:21] wire b_ready = io_b_ready_0; // @[SourceB.scala:33:7, :65:17] wire b_valid; // @[SourceB.scala:65:17] wire [1:0] b_bits_param; // @[SourceB.scala:65:17] wire [31:0] b_bits_address; // @[SourceB.scala:65:17] wire io_req_ready_0; // @[SourceB.scala:33:7] wire [1:0] io_b_bits_param_0; // @[SourceB.scala:33:7] wire [31:0] io_b_bits_address_0; // @[SourceB.scala:33:7] wire io_b_valid_0; // @[SourceB.scala:33:7] reg remain; // @[SourceB.scala:46:25] wire busy = remain; // @[SourceB.scala:46:25, :51:23] wire remain_set; // @[SourceB.scala:47:30] wire remain_clr; // @[SourceB.scala:48:30] wire _remain_T = remain | remain_set; // @[SourceB.scala:46:25, :47:30, :49:23] wire _remain_T_1 = ~remain_clr; // @[SourceB.scala:48:30, :49:39] wire _remain_T_2 = _remain_T & _remain_T_1; // @[SourceB.scala:49:{23,37,39}] wire todo = busy ? remain : io_req_bits_clients_0; // @[SourceB.scala:33:7, :46:25, :51:23, :52:19] wire _next_T = todo; // @[package.scala:254:17] wire [1:0] _next_T_1 = {_next_T, 1'h0}; // @[package.scala:254:17] wire [1:0] _next_T_2 = ~_next_T_1; // @[SourceB.scala:53:{16,31}] wire [1:0] next = {1'h0, _next_T_2[0] & todo}; // @[SourceB.scala:52:19, :53:{16,37}]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} |acquireB = ${acquireB} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT || supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED || supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED || supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB || supportsGet, w = supportsAcquireT || supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} |Slave Address = ${address} |supports = ${supports.infoString} | |""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ || _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_||_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ || _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B || s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_||_) }.foldLeft(false.B)(_||_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} |visibility = ${visibility} |emits = ${emits.infoString} |sourceId = ${sourceId} | |""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ || _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ || _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ || _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ || _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ || _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ || _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ || _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ || _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_||_) }.foldLeft(false.B)(_||_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE || x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps */ class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_63( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_source, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _source_ok_T_1 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_1; // @[Parameters.scala:1138:31] wire _T_1222 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1222; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1222; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1295 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1295; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1295; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1295; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg [3:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [7:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [3:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [3:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [7:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_1145 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_1145; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_1145; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_1222 & a_first_1; // @[Decoupled.scala:51:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = a_set ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:{28,59}] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :660:52] assign a_sizes_set = a_set ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_3 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_3; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_3; // @[Monitor.scala:673:46, :783:46] wire _T_1194 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [1:0] _GEN_4 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_5 = 2'h1 << _GEN_4; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1194 & ~d_release_ack & _d_clr_wo_ready_T[0]; // @[OneHot.scala:58:35] wire _T_1163 = _T_1295 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1163 & _d_clr_T[0]; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1163 ? _d_opcodes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [30:0] _d_sizes_clr_T_5 = 31'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1163 ? _d_sizes_clr_T_5[7:0] : 8'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [7:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1266 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1266 & d_release_ack_1 & _d_clr_wo_ready_T_1[0]; // @[OneHot.scala:58:35] wire _T_1248 = _T_1295 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1248 & _d_clr_T_1[0]; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1248 ? _d_opcodes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [30:0] _d_sizes_clr_T_11 = 31'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1248 ? _d_sizes_clr_T_11[7:0] : 8'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File ClockDomain.scala: package freechips.rocketchip.prci import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ abstract class Domain(implicit p: Parameters) extends LazyModule with HasDomainCrossing { def clockBundle: ClockBundle lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { childClock := clockBundle.clock childReset := clockBundle.reset override def provideImplicitClockToLazyChildren = true // these are just for backwards compatibility with external devices // that were manually wiring themselves to the domain's clock/reset input: val clock = IO(Output(chiselTypeOf(clockBundle.clock))) val reset = IO(Output(chiselTypeOf(clockBundle.reset))) clock := clockBundle.clock reset := clockBundle.reset } } abstract class ClockDomain(implicit p: Parameters) extends Domain with HasClockDomainCrossing class ClockSinkDomain(val clockSinkParams: ClockSinkParameters)(implicit p: Parameters) extends ClockDomain { def this(take: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSinkParameters(take = take, name = name)) val clockNode = ClockSinkNode(Seq(clockSinkParams)) def clockBundle = clockNode.in.head._1 override lazy val desiredName = (clockSinkParams.name.toSeq :+ "ClockSinkDomain").mkString } class ClockSourceDomain(val clockSourceParams: ClockSourceParameters)(implicit p: Parameters) extends ClockDomain { def this(give: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSourceParameters(give = give, name = name)) val clockNode = ClockSourceNode(Seq(clockSourceParams)) def clockBundle = clockNode.out.head._1 override lazy val desiredName = (clockSourceParams.name.toSeq :+ "ClockSourceDomain").mkString } abstract class ResetDomain(implicit p: Parameters) extends Domain with HasResetDomainCrossing File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File NoC.scala: package constellation.noc import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, BundleBridgeSink, InModuleBody} import freechips.rocketchip.util.ElaborationArtefacts import freechips.rocketchip.prci._ import constellation.router._ import constellation.channel._ import constellation.routing.{RoutingRelation, ChannelRoutingInfo} import constellation.topology.{PhysicalTopology, UnidirectionalLine} class NoCTerminalIO( val ingressParams: Seq[IngressChannelParams], val egressParams: Seq[EgressChannelParams])(implicit val p: Parameters) extends Bundle { val ingress = MixedVec(ingressParams.map { u => Flipped(new IngressChannel(u)) }) val egress = MixedVec(egressParams.map { u => new EgressChannel(u) }) } class NoC(nocParams: NoCParams)(implicit p: Parameters) extends LazyModule { override def shouldBeInlined = nocParams.inlineNoC val internalParams = InternalNoCParams(nocParams) val allChannelParams = internalParams.channelParams val allIngressParams = internalParams.ingressParams val allEgressParams = internalParams.egressParams val allRouterParams = internalParams.routerParams val iP = p.alterPartial({ case InternalNoCKey => internalParams }) val nNodes = nocParams.topology.nNodes val nocName = nocParams.nocName val skipValidationChecks = nocParams.skipValidationChecks val clockSourceNodes = Seq.tabulate(nNodes) { i => ClockSourceNode(Seq(ClockSourceParameters())) } val router_sink_domains = Seq.tabulate(nNodes) { i => val router_sink_domain = LazyModule(new ClockSinkDomain(ClockSinkParameters( name = Some(s"${nocName}_router_$i") ))) router_sink_domain.clockNode := clockSourceNodes(i) router_sink_domain } val routers = Seq.tabulate(nNodes) { i => router_sink_domains(i) { val inParams = allChannelParams.filter(_.destId == i).map( _.copy(payloadBits=allRouterParams(i).user.payloadBits) ) val outParams = allChannelParams.filter(_.srcId == i).map( _.copy(payloadBits=allRouterParams(i).user.payloadBits) ) val ingressParams = allIngressParams.filter(_.destId == i).map( _.copy(payloadBits=allRouterParams(i).user.payloadBits) ) val egressParams = allEgressParams.filter(_.srcId == i).map( _.copy(payloadBits=allRouterParams(i).user.payloadBits) ) val noIn = inParams.size + ingressParams.size == 0 val noOut = outParams.size + egressParams.size == 0 if (noIn || noOut) { println(s"Constellation WARNING: $nocName router $i seems to be unused, it will not be generated") None } else { Some(LazyModule(new Router( routerParams = allRouterParams(i), preDiplomaticInParams = inParams, preDiplomaticIngressParams = ingressParams, outDests = outParams.map(_.destId), egressIds = egressParams.map(_.egressId) )(iP))) } }}.flatten val ingressNodes = allIngressParams.map { u => IngressChannelSourceNode(u.destId) } val egressNodes = allEgressParams.map { u => EgressChannelDestNode(u) } // Generate channels between routers diplomatically Seq.tabulate(nNodes, nNodes) { case (i, j) => if (i != j) { val routerI = routers.find(_.nodeId == i) val routerJ = routers.find(_.nodeId == j) if (routerI.isDefined && routerJ.isDefined) { val sourceNodes: Seq[ChannelSourceNode] = routerI.get.sourceNodes.filter(_.destId == j) val destNodes: Seq[ChannelDestNode] = routerJ.get.destNodes.filter(_.destParams.srcId == i) require (sourceNodes.size == destNodes.size) (sourceNodes zip destNodes).foreach { case (src, dst) => val channelParam = allChannelParams.find(c => c.srcId == i && c.destId == j).get router_sink_domains(j) { implicit val p: Parameters = iP (dst := ChannelWidthWidget(routerJ.get.payloadBits, routerI.get.payloadBits) := channelParam.channelGen(p)(src) ) } } } }} // Generate terminal channels diplomatically routers.foreach { dst => router_sink_domains(dst.nodeId) { implicit val p: Parameters = iP dst.ingressNodes.foreach(n => { val ingressId = n.destParams.ingressId require(dst.payloadBits <= allIngressParams(ingressId).payloadBits) (n := IngressWidthWidget(dst.payloadBits, allIngressParams(ingressId).payloadBits) := ingressNodes(ingressId) ) }) dst.egressNodes.foreach(n => { val egressId = n.egressId require(dst.payloadBits <= allEgressParams(egressId).payloadBits) (egressNodes(egressId) := EgressWidthWidget(allEgressParams(egressId).payloadBits, dst.payloadBits) := n ) }) }} val debugNodes = routers.map { r => val sink = BundleBridgeSink[DebugBundle]() sink := r.debugNode sink } val ctrlNodes = if (nocParams.hasCtrl) { (0 until nNodes).map { i => routers.find(_.nodeId == i).map { r => val sink = BundleBridgeSink[RouterCtrlBundle]() sink := r.ctrlNode.get sink } } } else { Nil } println(s"Constellation: $nocName Finished parameter validation") lazy val module = new Impl class Impl extends LazyModuleImp(this) { println(s"Constellation: $nocName Starting NoC RTL generation") val io = IO(new NoCTerminalIO(allIngressParams, allEgressParams)(iP) { val router_clocks = Vec(nNodes, Input(new ClockBundle(ClockBundleParameters()))) val router_ctrl = if (nocParams.hasCtrl) Vec(nNodes, new RouterCtrlBundle) else Nil }) (io.ingress zip ingressNodes.map(_.out(0)._1)).foreach { case (l,r) => r <> l } (io.egress zip egressNodes .map(_.in (0)._1)).foreach { case (l,r) => l <> r } (io.router_clocks zip clockSourceNodes.map(_.out(0)._1)).foreach { case (l,r) => l <> r } if (nocParams.hasCtrl) { ctrlNodes.zipWithIndex.map { case (c,i) => if (c.isDefined) { io.router_ctrl(i) <> c.get.in(0)._1 } else { io.router_ctrl(i) <> DontCare } } } // TODO: These assume a single clock-domain across the entire noc val debug_va_stall_ctr = RegInit(0.U(64.W)) val debug_sa_stall_ctr = RegInit(0.U(64.W)) val debug_any_stall_ctr = debug_va_stall_ctr + debug_sa_stall_ctr debug_va_stall_ctr := debug_va_stall_ctr + debugNodes.map(_.in(0)._1.va_stall.reduce(_+_)).reduce(_+_) debug_sa_stall_ctr := debug_sa_stall_ctr + debugNodes.map(_.in(0)._1.sa_stall.reduce(_+_)).reduce(_+_) dontTouch(debug_va_stall_ctr) dontTouch(debug_sa_stall_ctr) dontTouch(debug_any_stall_ctr) def prepend(s: String) = Seq(nocName, s).mkString(".") ElaborationArtefacts.add(prepend("noc.graphml"), graphML) val adjList = routers.map { r => val outs = r.outParams.map(o => s"${o.destId}").mkString(" ") val egresses = r.egressParams.map(e => s"e${e.egressId}").mkString(" ") val ingresses = r.ingressParams.map(i => s"i${i.ingressId} ${r.nodeId}") (Seq(s"${r.nodeId} $outs $egresses") ++ ingresses).mkString("\n") }.mkString("\n") ElaborationArtefacts.add(prepend("noc.adjlist"), adjList) val xys = routers.map(r => { val n = r.nodeId val ids = (Seq(r.nodeId.toString) ++ r.egressParams.map(e => s"e${e.egressId}") ++ r.ingressParams.map(i => s"i${i.ingressId}") ) val plotter = nocParams.topology.plotter val coords = (Seq(plotter.node(r.nodeId)) ++ Seq.tabulate(r.egressParams.size ) { i => plotter. egress(i, r. egressParams.size, r.nodeId) } ++ Seq.tabulate(r.ingressParams.size) { i => plotter.ingress(i, r.ingressParams.size, r.nodeId) } ) (ids zip coords).map { case (i, (x, y)) => s"$i $x $y" }.mkString("\n") }).mkString("\n") ElaborationArtefacts.add(prepend("noc.xy"), xys) val edgeProps = routers.map { r => val outs = r.outParams.map { o => (Seq(s"${r.nodeId} ${o.destId}") ++ (if (o.possibleFlows.size == 0) Some("unused") else None)) .mkString(" ") } val egresses = r.egressParams.map { e => (Seq(s"${r.nodeId} e${e.egressId}") ++ (if (e.possibleFlows.size == 0) Some("unused") else None)) .mkString(" ") } val ingresses = r.ingressParams.map { i => (Seq(s"i${i.ingressId} ${r.nodeId}") ++ (if (i.possibleFlows.size == 0) Some("unused") else None)) .mkString(" ") } (outs ++ egresses ++ ingresses).mkString("\n") }.mkString("\n") ElaborationArtefacts.add(prepend("noc.edgeprops"), edgeProps) println(s"Constellation: $nocName Finished NoC RTL generation") } }
module TLSplitACDxBENoC_acd_router_12ClockSinkDomain( // @[ClockDomain.scala:14:9] output [1:0] auto_routers_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_debug_out_va_stall_3, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_debug_out_sa_stall_3, // @[LazyModuleImp.scala:107:25] input auto_routers_egress_nodes_out_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [144:0] auto_routers_egress_nodes_out_flit_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_routers_ingress_nodes_in_1_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_1_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_1_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [144:0] auto_routers_ingress_nodes_in_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_ingress_nodes_in_1_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_routers_ingress_nodes_in_0_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_0_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_0_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [144:0] auto_routers_ingress_nodes_in_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_ingress_nodes_in_0_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [144:0] auto_routers_source_nodes_out_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_source_nodes_out_1_credit_return, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_source_nodes_out_1_vc_free, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [144:0] auto_routers_source_nodes_out_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_source_nodes_out_0_credit_return, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_source_nodes_out_0_vc_free, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [144:0] auto_routers_dest_nodes_in_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_dest_nodes_in_1_credit_return, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_dest_nodes_in_1_vc_free, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [144:0] auto_routers_dest_nodes_in_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_dest_nodes_in_0_credit_return, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_dest_nodes_in_0_vc_free, // @[LazyModuleImp.scala:107:25] input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_reset // @[LazyModuleImp.scala:107:25] ); Router_12 routers ( // @[NoC.scala:67:22] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_debug_out_va_stall_0 (auto_routers_debug_out_va_stall_0), .auto_debug_out_va_stall_1 (auto_routers_debug_out_va_stall_1), .auto_debug_out_va_stall_2 (auto_routers_debug_out_va_stall_2), .auto_debug_out_va_stall_3 (auto_routers_debug_out_va_stall_3), .auto_debug_out_sa_stall_0 (auto_routers_debug_out_sa_stall_0), .auto_debug_out_sa_stall_1 (auto_routers_debug_out_sa_stall_1), .auto_debug_out_sa_stall_2 (auto_routers_debug_out_sa_stall_2), .auto_debug_out_sa_stall_3 (auto_routers_debug_out_sa_stall_3), .auto_egress_nodes_out_flit_ready (auto_routers_egress_nodes_out_flit_ready), .auto_egress_nodes_out_flit_valid (auto_routers_egress_nodes_out_flit_valid), .auto_egress_nodes_out_flit_bits_head (auto_routers_egress_nodes_out_flit_bits_head), .auto_egress_nodes_out_flit_bits_tail (auto_routers_egress_nodes_out_flit_bits_tail), .auto_egress_nodes_out_flit_bits_payload (auto_routers_egress_nodes_out_flit_bits_payload), .auto_ingress_nodes_in_1_flit_ready (auto_routers_ingress_nodes_in_1_flit_ready), .auto_ingress_nodes_in_1_flit_valid (auto_routers_ingress_nodes_in_1_flit_valid), .auto_ingress_nodes_in_1_flit_bits_head (auto_routers_ingress_nodes_in_1_flit_bits_head), .auto_ingress_nodes_in_1_flit_bits_tail (auto_routers_ingress_nodes_in_1_flit_bits_tail), .auto_ingress_nodes_in_1_flit_bits_payload (auto_routers_ingress_nodes_in_1_flit_bits_payload), .auto_ingress_nodes_in_1_flit_bits_egress_id (auto_routers_ingress_nodes_in_1_flit_bits_egress_id), .auto_ingress_nodes_in_0_flit_ready (auto_routers_ingress_nodes_in_0_flit_ready), .auto_ingress_nodes_in_0_flit_valid (auto_routers_ingress_nodes_in_0_flit_valid), .auto_ingress_nodes_in_0_flit_bits_head (auto_routers_ingress_nodes_in_0_flit_bits_head), .auto_ingress_nodes_in_0_flit_bits_tail (auto_routers_ingress_nodes_in_0_flit_bits_tail), .auto_ingress_nodes_in_0_flit_bits_payload (auto_routers_ingress_nodes_in_0_flit_bits_payload), .auto_ingress_nodes_in_0_flit_bits_egress_id (auto_routers_ingress_nodes_in_0_flit_bits_egress_id), .auto_source_nodes_out_1_flit_0_valid (auto_routers_source_nodes_out_1_flit_0_valid), .auto_source_nodes_out_1_flit_0_bits_head (auto_routers_source_nodes_out_1_flit_0_bits_head), .auto_source_nodes_out_1_flit_0_bits_tail (auto_routers_source_nodes_out_1_flit_0_bits_tail), .auto_source_nodes_out_1_flit_0_bits_payload (auto_routers_source_nodes_out_1_flit_0_bits_payload), .auto_source_nodes_out_1_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id), .auto_source_nodes_out_1_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node), .auto_source_nodes_out_1_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id), .auto_source_nodes_out_1_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node), .auto_source_nodes_out_1_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id), .auto_source_nodes_out_1_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id), .auto_source_nodes_out_1_credit_return (auto_routers_source_nodes_out_1_credit_return), .auto_source_nodes_out_1_vc_free (auto_routers_source_nodes_out_1_vc_free), .auto_source_nodes_out_0_flit_0_valid (auto_routers_source_nodes_out_0_flit_0_valid), .auto_source_nodes_out_0_flit_0_bits_head (auto_routers_source_nodes_out_0_flit_0_bits_head), .auto_source_nodes_out_0_flit_0_bits_tail (auto_routers_source_nodes_out_0_flit_0_bits_tail), .auto_source_nodes_out_0_flit_0_bits_payload (auto_routers_source_nodes_out_0_flit_0_bits_payload), .auto_source_nodes_out_0_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id), .auto_source_nodes_out_0_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node), .auto_source_nodes_out_0_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id), .auto_source_nodes_out_0_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node), .auto_source_nodes_out_0_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id), .auto_source_nodes_out_0_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id), .auto_source_nodes_out_0_credit_return (auto_routers_source_nodes_out_0_credit_return), .auto_source_nodes_out_0_vc_free (auto_routers_source_nodes_out_0_vc_free), .auto_dest_nodes_in_1_flit_0_valid (auto_routers_dest_nodes_in_1_flit_0_valid), .auto_dest_nodes_in_1_flit_0_bits_head (auto_routers_dest_nodes_in_1_flit_0_bits_head), .auto_dest_nodes_in_1_flit_0_bits_tail (auto_routers_dest_nodes_in_1_flit_0_bits_tail), .auto_dest_nodes_in_1_flit_0_bits_payload (auto_routers_dest_nodes_in_1_flit_0_bits_payload), .auto_dest_nodes_in_1_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_vnet_id), .auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node), .auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id), .auto_dest_nodes_in_1_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node), .auto_dest_nodes_in_1_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node_id), .auto_dest_nodes_in_1_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_1_flit_0_bits_virt_channel_id), .auto_dest_nodes_in_1_credit_return (auto_routers_dest_nodes_in_1_credit_return), .auto_dest_nodes_in_1_vc_free (auto_routers_dest_nodes_in_1_vc_free), .auto_dest_nodes_in_0_flit_0_valid (auto_routers_dest_nodes_in_0_flit_0_valid), .auto_dest_nodes_in_0_flit_0_bits_head (auto_routers_dest_nodes_in_0_flit_0_bits_head), .auto_dest_nodes_in_0_flit_0_bits_tail (auto_routers_dest_nodes_in_0_flit_0_bits_tail), .auto_dest_nodes_in_0_flit_0_bits_payload (auto_routers_dest_nodes_in_0_flit_0_bits_payload), .auto_dest_nodes_in_0_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_vnet_id), .auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node), .auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id), .auto_dest_nodes_in_0_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node), .auto_dest_nodes_in_0_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node_id), .auto_dest_nodes_in_0_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_0_flit_0_bits_virt_channel_id), .auto_dest_nodes_in_0_credit_return (auto_routers_dest_nodes_in_0_credit_return), .auto_dest_nodes_in_0_vc_free (auto_routers_dest_nodes_in_0_vc_free) ); // @[NoC.scala:67:22] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File WidthWidget.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.AddressSet import freechips.rocketchip.util.{Repeater, UIntToOH1} // innBeatBytes => the new client-facing bus width class TLWidthWidget(innerBeatBytes: Int)(implicit p: Parameters) extends LazyModule { private def noChangeRequired(manager: TLManagerPortParameters) = manager.beatBytes == innerBeatBytes val node = new TLAdapterNode( clientFn = { case c => c }, managerFn = { case m => m.v1copy(beatBytes = innerBeatBytes) }){ override def circuitIdentity = edges.out.map(_.manager).forall(noChangeRequired) } override lazy val desiredName = s"TLWidthWidget$innerBeatBytes" lazy val module = new Impl class Impl extends LazyModuleImp(this) { def merge[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T]) = { val inBytes = edgeIn.manager.beatBytes val outBytes = edgeOut.manager.beatBytes val ratio = outBytes / inBytes val keepBits = log2Ceil(outBytes) val dropBits = log2Ceil(inBytes) val countBits = log2Ceil(ratio) val size = edgeIn.size(in.bits) val hasData = edgeIn.hasData(in.bits) val limit = UIntToOH1(size, keepBits) >> dropBits val count = RegInit(0.U(countBits.W)) val first = count === 0.U val last = count === limit || !hasData val enable = Seq.tabulate(ratio) { i => !((count ^ i.U) & limit).orR } val corrupt_reg = RegInit(false.B) val corrupt_in = edgeIn.corrupt(in.bits) val corrupt_out = corrupt_in || corrupt_reg when (in.fire) { count := count + 1.U corrupt_reg := corrupt_out when (last) { count := 0.U corrupt_reg := false.B } } def helper(idata: UInt): UInt = { // rdata is X until the first time a multi-beat write occurs. // Prevent the X from leaking outside by jamming the mux control until // the first time rdata is written (and hence no longer X). val rdata_written_once = RegInit(false.B) val masked_enable = enable.map(_ || !rdata_written_once) val odata = Seq.fill(ratio) { WireInit(idata) } val rdata = Reg(Vec(ratio-1, chiselTypeOf(idata))) val pdata = rdata :+ idata val mdata = (masked_enable zip (odata zip pdata)) map { case (e, (o, p)) => Mux(e, o, p) } when (in.fire && !last) { rdata_written_once := true.B (rdata zip mdata) foreach { case (r, m) => r := m } } Cat(mdata.reverse) } in.ready := out.ready || !last out.valid := in.valid && last out.bits := in.bits // Don't put down hardware if we never carry data edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits))) edgeOut.corrupt(out.bits) := corrupt_out (out.bits, in.bits) match { case (o: TLBundleA, i: TLBundleA) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W)) case (o: TLBundleB, i: TLBundleB) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W)) case (o: TLBundleC, i: TLBundleC) => () case (o: TLBundleD, i: TLBundleD) => () case _ => require(false, "Impossible bundle combination in WidthWidget") } } def split[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = { val inBytes = edgeIn.manager.beatBytes val outBytes = edgeOut.manager.beatBytes val ratio = inBytes / outBytes val keepBits = log2Ceil(inBytes) val dropBits = log2Ceil(outBytes) val countBits = log2Ceil(ratio) val size = edgeIn.size(in.bits) val hasData = edgeIn.hasData(in.bits) val limit = UIntToOH1(size, keepBits) >> dropBits val count = RegInit(0.U(countBits.W)) val first = count === 0.U val last = count === limit || !hasData when (out.fire) { count := count + 1.U when (last) { count := 0.U } } // For sub-beat transfer, extract which part matters val sel = in.bits match { case a: TLBundleA => a.address(keepBits-1, dropBits) case b: TLBundleB => b.address(keepBits-1, dropBits) case c: TLBundleC => c.address(keepBits-1, dropBits) case d: TLBundleD => { val sel = sourceMap(d.source) val hold = Mux(first, sel, RegEnable(sel, first)) // a_first is not for whole xfer hold & ~limit // if more than one a_first/xfer, the address must be aligned anyway } } val index = sel | count def helper(idata: UInt, width: Int): UInt = { val mux = VecInit.tabulate(ratio) { i => idata((i+1)*outBytes*width-1, i*outBytes*width) } mux(index) } out.bits := in.bits out.valid := in.valid in.ready := out.ready // Don't put down hardware if we never carry data edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits), 8)) (out.bits, in.bits) match { case (o: TLBundleA, i: TLBundleA) => o.mask := helper(i.mask, 1) case (o: TLBundleB, i: TLBundleB) => o.mask := helper(i.mask, 1) case (o: TLBundleC, i: TLBundleC) => () // replicating corrupt to all beats is ok case (o: TLBundleD, i: TLBundleD) => () case _ => require(false, "Impossbile bundle combination in WidthWidget") } // Repeat the input if we're not last !last } def splice[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = { if (edgeIn.manager.beatBytes == edgeOut.manager.beatBytes) { // nothing to do; pass it through out.bits := in.bits out.valid := in.valid in.ready := out.ready } else if (edgeIn.manager.beatBytes > edgeOut.manager.beatBytes) { // split input to output val repeat = Wire(Bool()) val repeated = Repeater(in, repeat) val cated = Wire(chiselTypeOf(repeated)) cated <> repeated edgeIn.data(cated.bits) := Cat( edgeIn.data(repeated.bits)(edgeIn.manager.beatBytes*8-1, edgeOut.manager.beatBytes*8), edgeIn.data(in.bits)(edgeOut.manager.beatBytes*8-1, 0)) repeat := split(edgeIn, cated, edgeOut, out, sourceMap) } else { // merge input to output merge(edgeIn, in, edgeOut, out) } } (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => // If the master is narrower than the slave, the D channel must be narrowed. // This is tricky, because the D channel has no address data. // Thus, you don't know which part of a sub-beat transfer to extract. // To fix this, we record the relevant address bits for all sources. // The assumption is that this sort of situation happens only where // you connect a narrow master to the system bus, so there are few sources. def sourceMap(source_bits: UInt) = { val source = if (edgeIn.client.endSourceId == 1) 0.U(0.W) else source_bits require (edgeOut.manager.beatBytes > edgeIn.manager.beatBytes) val keepBits = log2Ceil(edgeOut.manager.beatBytes) val dropBits = log2Ceil(edgeIn.manager.beatBytes) val sources = Reg(Vec(edgeIn.client.endSourceId, UInt((keepBits-dropBits).W))) val a_sel = in.a.bits.address(keepBits-1, dropBits) when (in.a.fire) { if (edgeIn.client.endSourceId == 1) { // avoid extraction-index-width warning sources(0) := a_sel } else { sources(in.a.bits.source) := a_sel } } // depopulate unused source registers: edgeIn.client.unusedSources.foreach { id => sources(id) := 0.U } val bypass = in.a.valid && in.a.bits.source === source if (edgeIn.manager.minLatency > 0) sources(source) else Mux(bypass, a_sel, sources(source)) } splice(edgeIn, in.a, edgeOut, out.a, sourceMap) splice(edgeOut, out.d, edgeIn, in.d, sourceMap) if (edgeOut.manager.anySupportAcquireB && edgeIn.client.anySupportProbe) { splice(edgeOut, out.b, edgeIn, in.b, sourceMap) splice(edgeIn, in.c, edgeOut, out.c, sourceMap) out.e.valid := in.e.valid out.e.bits := in.e.bits in.e.ready := out.e.ready } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLWidthWidget { def apply(innerBeatBytes: Int)(implicit p: Parameters): TLNode = { val widget = LazyModule(new TLWidthWidget(innerBeatBytes)) widget.node } def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper.beatBytes) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMWidthWidget(first: Int, second: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("WidthWidget")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) (ram.node := TLDelayer(0.1) := TLFragmenter(4, 256) := TLWidthWidget(second) := TLWidthWidget(first) := TLDelayer(0.1) := model.node := fuzz.node) lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMWidthWidgetTest(little: Int, big: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMWidthWidget(little,big,txns)).module) dut.io.start := DontCare io.finished := dut.io.finished } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Repeater.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{Decoupled, DecoupledIO} // A Repeater passes its input to its output, unless repeat is asserted. // When repeat is asserted, the Repeater copies the input and repeats it next cycle. class Repeater[T <: Data](gen: T) extends Module { override def desiredName = s"Repeater_${gen.typeName}" val io = IO( new Bundle { val repeat = Input(Bool()) val full = Output(Bool()) val enq = Flipped(Decoupled(gen.cloneType)) val deq = Decoupled(gen.cloneType) } ) val full = RegInit(false.B) val saved = Reg(gen.cloneType) // When !full, a repeater is pass-through io.deq.valid := io.enq.valid || full io.enq.ready := io.deq.ready && !full io.deq.bits := Mux(full, saved, io.enq.bits) io.full := full when (io.enq.fire && io.repeat) { full := true.B; saved := io.enq.bits } when (io.deq.fire && !io.repeat) { full := false.B } } object Repeater { def apply[T <: Data](enq: DecoupledIO[T], repeat: Bool): DecoupledIO[T] = { val repeater = Module(new Repeater(chiselTypeOf(enq.bits))) repeater.io.repeat := repeat repeater.io.enq <> enq repeater.io.deq } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }
module TLWidthWidget16( // @[WidthWidget.scala:27:9] input clock, // @[WidthWidget.scala:27:9] input reset, // @[WidthWidget.scala:27:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [15:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [127:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [127:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire [127:0] _repeated_repeater_io_deq_bits_data; // @[Repeater.scala:36:26] wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_in_a_bits_param_0 = auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9] wire [6:0] auto_anon_in_a_bits_source_0 = auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9] wire [28:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire [15:0] auto_anon_in_a_bits_mask_0 = auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9] wire [127:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9] wire auto_anon_in_a_bits_corrupt_0 = auto_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[WidthWidget.scala:27:9] wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] auto_anon_out_d_bits_param_0 = auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [6:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_bits_sink_0 = auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_bits_denied_0 = auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_bits_corrupt_0 = auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire anonIn_a_ready; // @[MixedNode.scala:551:17] wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[WidthWidget.scala:27:9] wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [2:0] anonIn_a_bits_param = auto_anon_in_a_bits_param_0; // @[WidthWidget.scala:27:9] wire [3:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[WidthWidget.scala:27:9] wire [6:0] anonIn_a_bits_source = auto_anon_in_a_bits_source_0; // @[WidthWidget.scala:27:9] wire [28:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[WidthWidget.scala:27:9] wire [15:0] anonIn_a_bits_mask = auto_anon_in_a_bits_mask_0; // @[WidthWidget.scala:27:9] wire [127:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[WidthWidget.scala:27:9] wire anonIn_a_bits_corrupt = auto_anon_in_a_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[WidthWidget.scala:27:9] wire anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [6:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [127:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[WidthWidget.scala:27:9] wire anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [6:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[WidthWidget.scala:27:9] wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [1:0] anonOut_d_bits_param = auto_anon_out_d_bits_param_0; // @[WidthWidget.scala:27:9] wire [3:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[WidthWidget.scala:27:9] wire [6:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[WidthWidget.scala:27:9] wire anonOut_d_bits_sink = auto_anon_out_d_bits_sink_0; // @[WidthWidget.scala:27:9] wire anonOut_d_bits_denied = auto_anon_out_d_bits_denied_0; // @[WidthWidget.scala:27:9] wire [63:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[WidthWidget.scala:27:9] wire anonOut_d_bits_corrupt = auto_anon_out_d_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_a_ready_0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_in_d_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [1:0] auto_anon_in_d_bits_param_0; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_in_d_bits_size_0; // @[WidthWidget.scala:27:9] wire [6:0] auto_anon_in_d_bits_source_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_bits_sink_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_bits_denied_0; // @[WidthWidget.scala:27:9] wire [127:0] auto_anon_in_d_bits_data_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_valid_0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_a_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_a_bits_param_0; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_out_a_bits_size_0; // @[WidthWidget.scala:27:9] wire [6:0] auto_anon_out_a_bits_source_0; // @[WidthWidget.scala:27:9] wire [28:0] auto_anon_out_a_bits_address_0; // @[WidthWidget.scala:27:9] wire [7:0] auto_anon_out_a_bits_mask_0; // @[WidthWidget.scala:27:9] wire [63:0] auto_anon_out_a_bits_data_0; // @[WidthWidget.scala:27:9] wire auto_anon_out_a_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire auto_anon_out_a_valid_0; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_ready_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[WidthWidget.scala:27:9] wire _anonIn_d_valid_T; // @[WidthWidget.scala:77:29] assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_param_0 = anonIn_d_bits_param; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_source_0 = anonIn_d_bits_source; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_sink_0 = anonIn_d_bits_sink; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_denied_0 = anonIn_d_bits_denied; // @[WidthWidget.scala:27:9] wire [127:0] _anonIn_d_bits_data_T_3; // @[WidthWidget.scala:73:12] assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data; // @[WidthWidget.scala:27:9] wire corrupt_out; // @[WidthWidget.scala:47:36] assign auto_anon_in_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire cated_ready = anonOut_a_ready; // @[WidthWidget.scala:161:25] wire cated_valid; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] cated_bits_opcode; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] cated_bits_param; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] cated_bits_size; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[WidthWidget.scala:27:9] wire [6:0] cated_bits_source; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[WidthWidget.scala:27:9] wire [28:0] cated_bits_address; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[WidthWidget.scala:27:9] wire cated_bits_corrupt; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire _anonOut_d_ready_T_1; // @[WidthWidget.scala:76:29] assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[WidthWidget.scala:27:9] assign anonIn_d_bits_opcode = anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_param = anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_size = anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_source = anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_sink = anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_denied = anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] anonIn_d_bits_data_odata_0 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47] wire [63:0] anonIn_d_bits_data_odata_1 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47] wire _repeat_T_1; // @[WidthWidget.scala:148:7] wire repeat_0; // @[WidthWidget.scala:159:26] assign anonOut_a_valid = cated_valid; // @[WidthWidget.scala:161:25] assign anonOut_a_bits_opcode = cated_bits_opcode; // @[WidthWidget.scala:161:25] assign anonOut_a_bits_param = cated_bits_param; // @[WidthWidget.scala:161:25] assign anonOut_a_bits_size = cated_bits_size; // @[WidthWidget.scala:161:25] assign anonOut_a_bits_source = cated_bits_source; // @[WidthWidget.scala:161:25] assign anonOut_a_bits_address = cated_bits_address; // @[WidthWidget.scala:161:25] wire [127:0] _cated_bits_data_T_2; // @[WidthWidget.scala:163:39] assign anonOut_a_bits_corrupt = cated_bits_corrupt; // @[WidthWidget.scala:161:25] wire [15:0] cated_bits_mask; // @[WidthWidget.scala:161:25] wire [127:0] cated_bits_data; // @[WidthWidget.scala:161:25] wire [63:0] _cated_bits_data_T = _repeated_repeater_io_deq_bits_data[127:64]; // @[Repeater.scala:36:26] wire [63:0] _cated_bits_data_T_1 = anonIn_a_bits_data[63:0]; // @[WidthWidget.scala:165:31] assign _cated_bits_data_T_2 = {_cated_bits_data_T, _cated_bits_data_T_1}; // @[WidthWidget.scala:163:39, :164:37, :165:31] assign cated_bits_data = _cated_bits_data_T_2; // @[WidthWidget.scala:161:25, :163:39] wire _repeat_hasData_opdata_T = cated_bits_opcode[2]; // @[WidthWidget.scala:161:25] wire repeat_hasData = ~_repeat_hasData_opdata_T; // @[Edges.scala:92:{28,37}] wire [18:0] _repeat_limit_T = 19'hF << cated_bits_size; // @[package.scala:243:71] wire [3:0] _repeat_limit_T_1 = _repeat_limit_T[3:0]; // @[package.scala:243:{71,76}] wire [3:0] _repeat_limit_T_2 = ~_repeat_limit_T_1; // @[package.scala:243:{46,76}] wire repeat_limit = _repeat_limit_T_2[3]; // @[package.scala:243:46] reg repeat_count; // @[WidthWidget.scala:105:26] wire repeat_first = ~repeat_count; // @[WidthWidget.scala:105:26, :106:25] wire _repeat_last_T = repeat_count == repeat_limit; // @[WidthWidget.scala:103:47, :105:26, :107:25] wire _repeat_last_T_1 = ~repeat_hasData; // @[WidthWidget.scala:107:38] wire repeat_last = _repeat_last_T | _repeat_last_T_1; // @[WidthWidget.scala:107:{25,35,38}] wire _repeat_T = anonOut_a_ready & anonOut_a_valid; // @[Decoupled.scala:51:35] wire [1:0] _repeat_count_T = {1'h0, repeat_count} + 2'h1; // @[WidthWidget.scala:105:26, :110:24] wire _repeat_count_T_1 = _repeat_count_T[0]; // @[WidthWidget.scala:110:24] wire repeat_sel = cated_bits_address[3]; // @[WidthWidget.scala:116:39, :161:25] wire repeat_index = repeat_sel | repeat_count; // @[WidthWidget.scala:105:26, :116:39, :126:24] wire [63:0] _repeat_anonOut_a_bits_data_mux_T = cated_bits_data[63:0]; // @[WidthWidget.scala:128:55, :161:25] wire [63:0] repeat_anonOut_a_bits_data_mux_0 = _repeat_anonOut_a_bits_data_mux_T; // @[WidthWidget.scala:128:{43,55}] wire [63:0] _repeat_anonOut_a_bits_data_mux_T_1 = cated_bits_data[127:64]; // @[WidthWidget.scala:128:55, :161:25] wire [63:0] repeat_anonOut_a_bits_data_mux_1 = _repeat_anonOut_a_bits_data_mux_T_1; // @[WidthWidget.scala:128:{43,55}] assign anonOut_a_bits_data = repeat_index ? repeat_anonOut_a_bits_data_mux_1 : repeat_anonOut_a_bits_data_mux_0; // @[WidthWidget.scala:126:24, :128:43, :137:30] wire [7:0] _repeat_anonOut_a_bits_mask_mux_T = cated_bits_mask[7:0]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonOut_a_bits_mask_mux_0 = _repeat_anonOut_a_bits_mask_mux_T; // @[WidthWidget.scala:128:{43,55}] wire [7:0] _repeat_anonOut_a_bits_mask_mux_T_1 = cated_bits_mask[15:8]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonOut_a_bits_mask_mux_1 = _repeat_anonOut_a_bits_mask_mux_T_1; // @[WidthWidget.scala:128:{43,55}] assign anonOut_a_bits_mask = repeat_index ? repeat_anonOut_a_bits_mask_mux_1 : repeat_anonOut_a_bits_mask_mux_0; // @[WidthWidget.scala:126:24, :128:43, :140:53] assign _repeat_T_1 = ~repeat_last; // @[WidthWidget.scala:107:35, :148:7] assign repeat_0 = _repeat_T_1; // @[WidthWidget.scala:148:7, :159:26] wire hasData = anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire [18:0] _limit_T = 19'hF << anonOut_d_bits_size; // @[package.scala:243:71] wire [3:0] _limit_T_1 = _limit_T[3:0]; // @[package.scala:243:{71,76}] wire [3:0] _limit_T_2 = ~_limit_T_1; // @[package.scala:243:{46,76}] wire limit = _limit_T_2[3]; // @[package.scala:243:46] reg count; // @[WidthWidget.scala:40:27] wire _enable_T = count; // @[WidthWidget.scala:40:27, :43:56] wire first = ~count; // @[WidthWidget.scala:40:27, :41:26] wire _last_T = count == limit; // @[WidthWidget.scala:38:47, :40:27, :42:26] wire _last_T_1 = ~hasData; // @[WidthWidget.scala:42:39] wire last = _last_T | _last_T_1; // @[WidthWidget.scala:42:{26,36,39}] wire _enable_T_1 = _enable_T & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_2 = _enable_T_1; // @[WidthWidget.scala:43:{63,72}] wire enable_0 = ~_enable_T_2; // @[WidthWidget.scala:43:{47,72}] wire _enable_T_3 = ~count; // @[WidthWidget.scala:40:27, :41:26, :43:56] wire _enable_T_4 = _enable_T_3 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_5 = _enable_T_4; // @[WidthWidget.scala:43:{63,72}] wire enable_1 = ~_enable_T_5; // @[WidthWidget.scala:43:{47,72}] reg corrupt_reg; // @[WidthWidget.scala:45:32] assign corrupt_out = anonOut_d_bits_corrupt | corrupt_reg; // @[WidthWidget.scala:45:32, :47:36] assign anonIn_d_bits_corrupt = corrupt_out; // @[WidthWidget.scala:47:36] wire _anonIn_d_bits_data_T = anonOut_d_ready & anonOut_d_valid; // @[Decoupled.scala:51:35] wire [1:0] _count_T = {1'h0, count} + 2'h1; // @[WidthWidget.scala:40:27, :50:24] wire _count_T_1 = _count_T[0]; // @[WidthWidget.scala:50:24] wire _anonOut_d_ready_T = ~last; // @[WidthWidget.scala:42:36, :76:32] assign _anonOut_d_ready_T_1 = anonIn_d_ready | _anonOut_d_ready_T; // @[WidthWidget.scala:76:{29,32}] assign anonOut_d_ready = _anonOut_d_ready_T_1; // @[WidthWidget.scala:76:29] assign _anonIn_d_valid_T = anonOut_d_valid & last; // @[WidthWidget.scala:42:36, :77:29] assign anonIn_d_valid = _anonIn_d_valid_T; // @[WidthWidget.scala:77:29] reg anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41] wire _anonIn_d_bits_data_masked_enable_T = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonIn_d_bits_data_masked_enable_0 = enable_0 | _anonIn_d_bits_data_masked_enable_T; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonIn_d_bits_data_masked_enable_T_1 = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonIn_d_bits_data_masked_enable_1 = enable_1 | _anonIn_d_bits_data_masked_enable_T_1; // @[WidthWidget.scala:43:47, :63:{42,45}] reg [63:0] anonIn_d_bits_data_rdata_0; // @[WidthWidget.scala:66:24] wire [63:0] anonIn_d_bits_data_mdata_0 = anonIn_d_bits_data_masked_enable_0 ? anonIn_d_bits_data_odata_0 : anonIn_d_bits_data_rdata_0; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [63:0] anonIn_d_bits_data_mdata_1 = anonIn_d_bits_data_masked_enable_1 ? anonIn_d_bits_data_odata_1 : anonOut_d_bits_data; // @[WidthWidget.scala:63:42, :65:47, :68:88] wire _anonIn_d_bits_data_T_1 = ~last; // @[WidthWidget.scala:42:36, :69:26, :76:32] wire _anonIn_d_bits_data_T_2 = _anonIn_d_bits_data_T & _anonIn_d_bits_data_T_1; // @[Decoupled.scala:51:35] assign _anonIn_d_bits_data_T_3 = {anonIn_d_bits_data_mdata_1, anonIn_d_bits_data_mdata_0}; // @[WidthWidget.scala:68:88, :73:12] assign anonIn_d_bits_data = _anonIn_d_bits_data_T_3; // @[WidthWidget.scala:73:12] always @(posedge clock) begin // @[WidthWidget.scala:27:9] if (reset) begin // @[WidthWidget.scala:27:9] repeat_count <= 1'h0; // @[WidthWidget.scala:105:26] count <= 1'h0; // @[WidthWidget.scala:40:27] corrupt_reg <= 1'h0; // @[WidthWidget.scala:45:32] anonIn_d_bits_data_rdata_written_once <= 1'h0; // @[WidthWidget.scala:62:41] end else begin // @[WidthWidget.scala:27:9] if (_repeat_T) // @[Decoupled.scala:51:35] repeat_count <= ~repeat_last & _repeat_count_T_1; // @[WidthWidget.scala:105:26, :107:35, :110:{15,24}, :111:{21,29}] if (_anonIn_d_bits_data_T) begin // @[Decoupled.scala:51:35] count <= ~last & _count_T_1; // @[WidthWidget.scala:40:27, :42:36, :50:{15,24}, :52:21, :53:17] corrupt_reg <= ~last & corrupt_out; // @[WidthWidget.scala:42:36, :45:32, :47:36, :50:15, :51:21, :52:21, :53:17, :54:23] end anonIn_d_bits_data_rdata_written_once <= _anonIn_d_bits_data_T_2 | anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :69:{23,33}, :70:30] end if (_anonIn_d_bits_data_T_2) // @[WidthWidget.scala:69:23] anonIn_d_bits_data_rdata_0 <= anonIn_d_bits_data_mdata_0; // @[WidthWidget.scala:66:24, :68:88] always @(posedge) TLMonitor_5 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (anonIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (anonIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (anonIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (anonIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (anonIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (anonIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (anonIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (anonIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (anonIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (anonIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (anonIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (anonIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (anonIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (anonIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (anonIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (anonIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (anonIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (anonIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (anonIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (anonIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Repeater_TLBundleA_a29d128s7k1z4u repeated_repeater ( // @[Repeater.scala:36:26] .clock (clock), .reset (reset), .io_repeat (repeat_0), // @[WidthWidget.scala:159:26] .io_enq_ready (anonIn_a_ready), .io_enq_valid (anonIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (anonIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (anonIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (anonIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (anonIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (anonIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (anonIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (anonIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (anonIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (cated_ready), // @[WidthWidget.scala:161:25] .io_deq_valid (cated_valid), .io_deq_bits_opcode (cated_bits_opcode), .io_deq_bits_param (cated_bits_param), .io_deq_bits_size (cated_bits_size), .io_deq_bits_source (cated_bits_source), .io_deq_bits_address (cated_bits_address), .io_deq_bits_mask (cated_bits_mask), .io_deq_bits_data (_repeated_repeater_io_deq_bits_data), .io_deq_bits_corrupt (cated_bits_corrupt) ); // @[Repeater.scala:36:26] assign auto_anon_in_a_ready = auto_anon_in_a_ready_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_valid = auto_anon_in_d_valid_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_opcode = auto_anon_in_d_bits_opcode_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_param = auto_anon_in_d_bits_param_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_size = auto_anon_in_d_bits_size_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_source = auto_anon_in_d_bits_source_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_sink = auto_anon_in_d_bits_sink_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_denied = auto_anon_in_d_bits_denied_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_data = auto_anon_in_d_bits_data_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_corrupt = auto_anon_in_d_bits_corrupt_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_valid = auto_anon_out_a_valid_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_opcode = auto_anon_out_a_bits_opcode_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_param = auto_anon_out_a_bits_param_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_size = auto_anon_out_a_bits_size_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_source = auto_anon_out_a_bits_source_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_address = auto_anon_out_a_bits_address_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_mask = auto_anon_out_a_bits_mask_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_data = auto_anon_out_a_bits_data_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_corrupt = auto_anon_out_a_bits_corrupt_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_d_ready = auto_anon_out_d_ready_0; // @[WidthWidget.scala:27:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Transposer.scala: package gemmini import chisel3._ import chisel3.util._ import Util._ trait Transposer[T <: Data] extends Module { def dim: Int def dataType: T val io = IO(new Bundle { val inRow = Flipped(Decoupled(Vec(dim, dataType))) val outCol = Decoupled(Vec(dim, dataType)) }) } class PipelinedTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { require(isPow2(dim)) val regArray = Seq.fill(dim, dim)(Reg(dataType)) val regArrayT = regArray.transpose val sMoveUp :: sMoveLeft :: Nil = Enum(2) val state = RegInit(sMoveUp) val leftCounter = RegInit(0.U(log2Ceil(dim+1).W)) //(io.inRow.fire && state === sMoveLeft, dim+1) val upCounter = RegInit(0.U(log2Ceil(dim+1).W)) //Counter(io.inRow.fire && state === sMoveUp, dim+1) io.outCol.valid := 0.U io.inRow.ready := 0.U switch(state) { is(sMoveUp) { io.inRow.ready := upCounter <= dim.U io.outCol.valid := leftCounter > 0.U when(io.inRow.fire) { upCounter := upCounter + 1.U } when(upCounter === (dim-1).U) { state := sMoveLeft leftCounter := 0.U } when(io.outCol.fire) { leftCounter := leftCounter - 1.U } } is(sMoveLeft) { io.inRow.ready := leftCounter <= dim.U // TODO: this is naive io.outCol.valid := upCounter > 0.U when(leftCounter === (dim-1).U) { state := sMoveUp } when(io.inRow.fire) { leftCounter := leftCounter + 1.U upCounter := 0.U } when(io.outCol.fire) { upCounter := upCounter - 1.U } } } // Propagate input from bottom row to top row systolically in the move up phase // TODO: need to iterate over columns to connect Chisel values of type T // Should be able to operate directly on the Vec, but Seq and Vec don't mix (try Array?) for (colIdx <- 0 until dim) { regArray.foldRight(io.inRow.bits(colIdx)) { case (regRow, prevReg) => when (state === sMoveUp) { regRow(colIdx) := prevReg } regRow(colIdx) } } // Propagate input from right side to left side systolically in the move left phase for (rowIdx <- 0 until dim) { regArrayT.foldRight(io.inRow.bits(rowIdx)) { case (regCol, prevReg) => when (state === sMoveLeft) { regCol(rowIdx) := prevReg } regCol(rowIdx) } } // Pull from the left side or the top side based on the state for (idx <- 0 until dim) { when (state === sMoveUp) { io.outCol.bits(idx) := regArray(0)(idx) }.elsewhen(state === sMoveLeft) { io.outCol.bits(idx) := regArrayT(0)(idx) }.otherwise { io.outCol.bits(idx) := DontCare } } } class AlwaysOutTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { require(isPow2(dim)) val LEFT_DIR = 0.U(1.W) val UP_DIR = 1.U(1.W) class PE extends Module { val io = IO(new Bundle { val inR = Input(dataType) val inD = Input(dataType) val outL = Output(dataType) val outU = Output(dataType) val dir = Input(UInt(1.W)) val en = Input(Bool()) }) val reg = RegEnable(Mux(io.dir === LEFT_DIR, io.inR, io.inD), io.en) io.outU := reg io.outL := reg } val pes = Seq.fill(dim,dim)(Module(new PE)) val counter = RegInit(0.U((log2Ceil(dim) max 1).W)) // TODO replace this with a standard Chisel counter val dir = RegInit(LEFT_DIR) // Wire up horizontal signals for (row <- 0 until dim; col <- 0 until dim) { val right_in = if (col == dim-1) io.inRow.bits(row) else pes(row)(col+1).io.outL pes(row)(col).io.inR := right_in } // Wire up vertical signals for (row <- 0 until dim; col <- 0 until dim) { val down_in = if (row == dim-1) io.inRow.bits(col) else pes(row+1)(col).io.outU pes(row)(col).io.inD := down_in } // Wire up global signals pes.flatten.foreach(_.io.dir := dir) pes.flatten.foreach(_.io.en := io.inRow.fire) io.outCol.valid := true.B io.inRow.ready := true.B val left_out = VecInit(pes.transpose.head.map(_.io.outL)) val up_out = VecInit(pes.head.map(_.io.outU)) io.outCol.bits := Mux(dir === LEFT_DIR, left_out, up_out) when (io.inRow.fire) { counter := wrappingAdd(counter, 1.U, dim) } when (counter === (dim-1).U && io.inRow.fire) { dir := ~dir } } class NaiveTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { val regArray = Seq.fill(dim, dim)(Reg(dataType)) val regArrayT = regArray.transpose // state = 0 => filling regArray row-wise, state = 1 => draining regArray column-wise val state = RegInit(0.U(1.W)) val countInc = io.inRow.fire || io.outCol.fire val (countValue, countWrap) = Counter(countInc, dim) io.inRow.ready := state === 0.U io.outCol.valid := state === 1.U for (i <- 0 until dim) { for (j <- 0 until dim) { when(countValue === i.U && io.inRow.fire) { regArray(i)(j) := io.inRow.bits(j) } } } for (i <- 0 until dim) { io.outCol.bits(i) := 0.U for (j <- 0 until dim) { when(countValue === j.U) { io.outCol.bits(i) := regArrayT(j)(i) } } } when (io.inRow.fire && countWrap) { state := 1.U } when (io.outCol.fire && countWrap) { state := 0.U } assert(!(state === 0.U) || !io.outCol.fire) assert(!(state === 1.U) || !io.inRow.fire) }
module PE_201( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_14( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [5:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [5:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire [8:0] _c_opcodes_set_T = 9'h0; // @[Monitor.scala:767:79] wire [8:0] _c_sizes_set_T = 9'h0; // @[Monitor.scala:768:77] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_42 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_44 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_48 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_50 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_54 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_56 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_60 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_62 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_66 = 1'h1; // @[Parameters.scala:56:32] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [5:0] _c_first_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_first_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_first_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_first_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_set_wo_ready_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_set_wo_ready_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_opcodes_set_interm_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_opcodes_set_interm_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_sizes_set_interm_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_sizes_set_interm_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_opcodes_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_opcodes_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_sizes_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_sizes_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_probe_ack_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_probe_ack_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_probe_ack_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_probe_ack_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _same_cycle_resp_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _same_cycle_resp_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _same_cycle_resp_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _same_cycle_resp_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _same_cycle_resp_WIRE_4_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _same_cycle_resp_WIRE_5_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [515:0] _c_sizes_set_T_1 = 516'h0; // @[Monitor.scala:768:52] wire [514:0] _c_opcodes_set_T_1 = 515'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [63:0] _c_set_wo_ready_T = 64'h1; // @[OneHot.scala:58:35] wire [63:0] _c_set_T = 64'h1; // @[OneHot.scala:58:35] wire [295:0] c_sizes_set = 296'h0; // @[Monitor.scala:741:34] wire [147:0] c_opcodes_set = 148'h0; // @[Monitor.scala:740:34] wire [36:0] c_set = 37'h0; // @[Monitor.scala:738:34] wire [36:0] c_set_wo_ready = 37'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [5:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 6'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_1 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_7 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_13 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_19 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_25 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 4'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_26 = _source_ok_T_25 == 4'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_29 = source_ok_uncommonBits_4 != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_30 = _source_ok_T_28 & _source_ok_T_29; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire _source_ok_T_31 = io_in_a_bits_source_0 == 6'h23; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_31; // @[Parameters.scala:1138:31] wire _source_ok_T_32 = io_in_a_bits_source_0 == 6'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire _source_ok_T_33 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_34 = _source_ok_T_33 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_35 = _source_ok_T_34 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_36 = _source_ok_T_35 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_37 = _source_ok_T_36 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_38 = _source_ok_T_37 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_38 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [28:0] _is_aligned_T = {17'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_39 = io_in_d_bits_source_0 == 6'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_39; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_40 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_46 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_52 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_58 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_64 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire _source_ok_T_41 = _source_ok_T_40 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_43 = _source_ok_T_41; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_45 = _source_ok_T_43; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_45; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_47 = _source_ok_T_46 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_49 = _source_ok_T_47; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_51 = _source_ok_T_49; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_51; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_53 = _source_ok_T_52 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_55 = _source_ok_T_53; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_57 = _source_ok_T_55; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_57; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_59 = _source_ok_T_58 == 4'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_61 = _source_ok_T_59; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_63 = _source_ok_T_61; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_63; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_65 = _source_ok_T_64 == 4'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_67 = _source_ok_T_65; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_68 = source_ok_uncommonBits_9 != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_69 = _source_ok_T_67 & _source_ok_T_68; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_5 = _source_ok_T_69; // @[Parameters.scala:1138:31] wire _source_ok_T_70 = io_in_d_bits_source_0 == 6'h23; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_70; // @[Parameters.scala:1138:31] wire _source_ok_T_71 = io_in_d_bits_source_0 == 6'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_71; // @[Parameters.scala:1138:31] wire _source_ok_T_72 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_73 = _source_ok_T_72 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_74 = _source_ok_T_73 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_75 = _source_ok_T_74 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_76 = _source_ok_T_75 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_77 = _source_ok_T_76 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_77 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _T_1579 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1579; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1579; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [5:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] wire _T_1652 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1652; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1652; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1652; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [5:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [36:0] inflight; // @[Monitor.scala:614:27] reg [147:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [295:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [36:0] a_set; // @[Monitor.scala:626:34] wire [36:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [147:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [295:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [8:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [8:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [8:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [8:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [8:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [147:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [147:0] _a_opcode_lookup_T_6 = {144'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [147:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[147:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [8:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [8:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [8:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [8:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [8:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [295:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [295:0] _a_size_lookup_T_6 = {288'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [295:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[295:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [63:0] _GEN_3 = 64'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [63:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [63:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[36:0] : 37'h0; // @[OneHot.scala:58:35] wire _T_1505 = _T_1579 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1505 ? _a_set_T[36:0] : 37'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1505 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1505 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [8:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [514:0] _a_opcodes_set_T_1 = {511'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1505 ? _a_opcodes_set_T_1[147:0] : 148'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [8:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [515:0] _a_sizes_set_T_1 = {511'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1505 ? _a_sizes_set_T_1[295:0] : 296'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [36:0] d_clr; // @[Monitor.scala:664:34] wire [36:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [147:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [295:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1551 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [63:0] _GEN_5 = 64'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [63:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [63:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [63:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [63:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1551 & ~d_release_ack ? _d_clr_wo_ready_T[36:0] : 37'h0; // @[OneHot.scala:58:35] wire _T_1520 = _T_1652 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1520 ? _d_clr_T[36:0] : 37'h0; // @[OneHot.scala:58:35] wire [526:0] _d_opcodes_clr_T_5 = 527'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1520 ? _d_opcodes_clr_T_5[147:0] : 148'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [526:0] _d_sizes_clr_T_5 = 527'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1520 ? _d_sizes_clr_T_5[295:0] : 296'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [36:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [36:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [36:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [147:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [147:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [147:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [295:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [295:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [295:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [36:0] inflight_1; // @[Monitor.scala:726:35] wire [36:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [147:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [147:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [295:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [295:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [147:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [147:0] _c_opcode_lookup_T_6 = {144'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [147:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[147:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [295:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [295:0] _c_size_lookup_T_6 = {288'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [295:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[295:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [36:0] d_clr_1; // @[Monitor.scala:774:34] wire [36:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [147:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [295:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1623 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1623 & d_release_ack_1 ? _d_clr_wo_ready_T_1[36:0] : 37'h0; // @[OneHot.scala:58:35] wire _T_1605 = _T_1652 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1605 ? _d_clr_T_1[36:0] : 37'h0; // @[OneHot.scala:58:35] wire [526:0] _d_opcodes_clr_T_11 = 527'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1605 ? _d_opcodes_clr_T_11[147:0] : 148'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [526:0] _d_sizes_clr_T_11 = 527'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1605 ? _d_sizes_clr_T_11[295:0] : 296'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 6'h0; // @[Monitor.scala:36:7, :795:113] wire [36:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [36:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [147:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [147:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [295:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [295:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File Transposer.scala: package gemmini import chisel3._ import chisel3.util._ import Util._ trait Transposer[T <: Data] extends Module { def dim: Int def dataType: T val io = IO(new Bundle { val inRow = Flipped(Decoupled(Vec(dim, dataType))) val outCol = Decoupled(Vec(dim, dataType)) }) } class PipelinedTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { require(isPow2(dim)) val regArray = Seq.fill(dim, dim)(Reg(dataType)) val regArrayT = regArray.transpose val sMoveUp :: sMoveLeft :: Nil = Enum(2) val state = RegInit(sMoveUp) val leftCounter = RegInit(0.U(log2Ceil(dim+1).W)) //(io.inRow.fire && state === sMoveLeft, dim+1) val upCounter = RegInit(0.U(log2Ceil(dim+1).W)) //Counter(io.inRow.fire && state === sMoveUp, dim+1) io.outCol.valid := 0.U io.inRow.ready := 0.U switch(state) { is(sMoveUp) { io.inRow.ready := upCounter <= dim.U io.outCol.valid := leftCounter > 0.U when(io.inRow.fire) { upCounter := upCounter + 1.U } when(upCounter === (dim-1).U) { state := sMoveLeft leftCounter := 0.U } when(io.outCol.fire) { leftCounter := leftCounter - 1.U } } is(sMoveLeft) { io.inRow.ready := leftCounter <= dim.U // TODO: this is naive io.outCol.valid := upCounter > 0.U when(leftCounter === (dim-1).U) { state := sMoveUp } when(io.inRow.fire) { leftCounter := leftCounter + 1.U upCounter := 0.U } when(io.outCol.fire) { upCounter := upCounter - 1.U } } } // Propagate input from bottom row to top row systolically in the move up phase // TODO: need to iterate over columns to connect Chisel values of type T // Should be able to operate directly on the Vec, but Seq and Vec don't mix (try Array?) for (colIdx <- 0 until dim) { regArray.foldRight(io.inRow.bits(colIdx)) { case (regRow, prevReg) => when (state === sMoveUp) { regRow(colIdx) := prevReg } regRow(colIdx) } } // Propagate input from right side to left side systolically in the move left phase for (rowIdx <- 0 until dim) { regArrayT.foldRight(io.inRow.bits(rowIdx)) { case (regCol, prevReg) => when (state === sMoveLeft) { regCol(rowIdx) := prevReg } regCol(rowIdx) } } // Pull from the left side or the top side based on the state for (idx <- 0 until dim) { when (state === sMoveUp) { io.outCol.bits(idx) := regArray(0)(idx) }.elsewhen(state === sMoveLeft) { io.outCol.bits(idx) := regArrayT(0)(idx) }.otherwise { io.outCol.bits(idx) := DontCare } } } class AlwaysOutTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { require(isPow2(dim)) val LEFT_DIR = 0.U(1.W) val UP_DIR = 1.U(1.W) class PE extends Module { val io = IO(new Bundle { val inR = Input(dataType) val inD = Input(dataType) val outL = Output(dataType) val outU = Output(dataType) val dir = Input(UInt(1.W)) val en = Input(Bool()) }) val reg = RegEnable(Mux(io.dir === LEFT_DIR, io.inR, io.inD), io.en) io.outU := reg io.outL := reg } val pes = Seq.fill(dim,dim)(Module(new PE)) val counter = RegInit(0.U((log2Ceil(dim) max 1).W)) // TODO replace this with a standard Chisel counter val dir = RegInit(LEFT_DIR) // Wire up horizontal signals for (row <- 0 until dim; col <- 0 until dim) { val right_in = if (col == dim-1) io.inRow.bits(row) else pes(row)(col+1).io.outL pes(row)(col).io.inR := right_in } // Wire up vertical signals for (row <- 0 until dim; col <- 0 until dim) { val down_in = if (row == dim-1) io.inRow.bits(col) else pes(row+1)(col).io.outU pes(row)(col).io.inD := down_in } // Wire up global signals pes.flatten.foreach(_.io.dir := dir) pes.flatten.foreach(_.io.en := io.inRow.fire) io.outCol.valid := true.B io.inRow.ready := true.B val left_out = VecInit(pes.transpose.head.map(_.io.outL)) val up_out = VecInit(pes.head.map(_.io.outU)) io.outCol.bits := Mux(dir === LEFT_DIR, left_out, up_out) when (io.inRow.fire) { counter := wrappingAdd(counter, 1.U, dim) } when (counter === (dim-1).U && io.inRow.fire) { dir := ~dir } } class NaiveTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { val regArray = Seq.fill(dim, dim)(Reg(dataType)) val regArrayT = regArray.transpose // state = 0 => filling regArray row-wise, state = 1 => draining regArray column-wise val state = RegInit(0.U(1.W)) val countInc = io.inRow.fire || io.outCol.fire val (countValue, countWrap) = Counter(countInc, dim) io.inRow.ready := state === 0.U io.outCol.valid := state === 1.U for (i <- 0 until dim) { for (j <- 0 until dim) { when(countValue === i.U && io.inRow.fire) { regArray(i)(j) := io.inRow.bits(j) } } } for (i <- 0 until dim) { io.outCol.bits(i) := 0.U for (j <- 0 until dim) { when(countValue === j.U) { io.outCol.bits(i) := regArrayT(j)(i) } } } when (io.inRow.fire && countWrap) { state := 1.U } when (io.outCol.fire && countWrap) { state := 0.U } assert(!(state === 0.U) || !io.outCol.fire) assert(!(state === 1.U) || !io.inRow.fire) }
module PE_177( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File IngressUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ class IngressUnit( ingressNodeId: Int, cParam: IngressChannelParams, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams], combineRCVA: Boolean, combineSAST: Boolean, ) (implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) { class IngressUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) { val in = Flipped(Decoupled(new IngressFlit(cParam.payloadBits))) } val io = IO(new IngressUnitIO) val route_buffer = Module(new Queue(new Flit(cParam.payloadBits), 2)) val route_q = Module(new Queue(new RouteComputerResp(outParams, egressParams), 2, flow=combineRCVA)) assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR)) route_buffer.io.enq.bits.head := io.in.bits.head route_buffer.io.enq.bits.tail := io.in.bits.tail val flows = cParam.possibleFlows.toSeq if (flows.size == 0) { route_buffer.io.enq.bits.flow := DontCare } else { route_buffer.io.enq.bits.flow.ingress_node := cParam.destId.U route_buffer.io.enq.bits.flow.ingress_node_id := ingressNodeId.U route_buffer.io.enq.bits.flow.vnet_id := cParam.vNetId.U route_buffer.io.enq.bits.flow.egress_node := Mux1H( flows.map(_.egressId.U === io.in.bits.egress_id), flows.map(_.egressNode.U) ) route_buffer.io.enq.bits.flow.egress_node_id := Mux1H( flows.map(_.egressId.U === io.in.bits.egress_id), flows.map(_.egressNodeId.U) ) } route_buffer.io.enq.bits.payload := io.in.bits.payload route_buffer.io.enq.bits.virt_channel_id := DontCare io.router_req.bits.src_virt_id := 0.U io.router_req.bits.flow := route_buffer.io.enq.bits.flow val at_dest = route_buffer.io.enq.bits.flow.egress_node === nodeId.U route_buffer.io.enq.valid := io.in.valid && ( io.router_req.ready || !io.in.bits.head || at_dest) io.router_req.valid := io.in.valid && route_buffer.io.enq.ready && io.in.bits.head && !at_dest io.in.ready := route_buffer.io.enq.ready && ( io.router_req.ready || !io.in.bits.head || at_dest) route_q.io.enq.valid := io.router_req.fire route_q.io.enq.bits := io.router_resp when (io.in.fire && io.in.bits.head && at_dest) { route_q.io.enq.valid := true.B route_q.io.enq.bits.vc_sel.foreach(_.foreach(_ := false.B)) for (o <- 0 until nEgress) { when (egressParams(o).egressId.U === io.in.bits.egress_id) { route_q.io.enq.bits.vc_sel(o+nOutputs)(0) := true.B } } } assert(!(route_q.io.enq.valid && !route_q.io.enq.ready)) val vcalloc_buffer = Module(new Queue(new Flit(cParam.payloadBits), 2)) val vcalloc_q = Module(new Queue(new VCAllocResp(outParams, egressParams), 1, pipe=true)) vcalloc_buffer.io.enq.bits := route_buffer.io.deq.bits io.vcalloc_req.bits.vc_sel := route_q.io.deq.bits.vc_sel io.vcalloc_req.bits.flow := route_buffer.io.deq.bits.flow io.vcalloc_req.bits.in_vc := 0.U val head = route_buffer.io.deq.bits.head val tail = route_buffer.io.deq.bits.tail vcalloc_buffer.io.enq.valid := (route_buffer.io.deq.valid && (route_q.io.deq.valid || !head) && (io.vcalloc_req.ready || !head) ) io.vcalloc_req.valid := (route_buffer.io.deq.valid && route_q.io.deq.valid && head && vcalloc_buffer.io.enq.ready && vcalloc_q.io.enq.ready) route_buffer.io.deq.ready := (vcalloc_buffer.io.enq.ready && (route_q.io.deq.valid || !head) && (io.vcalloc_req.ready || !head) && (vcalloc_q.io.enq.ready || !head)) route_q.io.deq.ready := (route_buffer.io.deq.fire && tail) vcalloc_q.io.enq.valid := io.vcalloc_req.fire vcalloc_q.io.enq.bits := io.vcalloc_resp assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready)) io.salloc_req(0).bits.vc_sel := vcalloc_q.io.deq.bits.vc_sel io.salloc_req(0).bits.tail := vcalloc_buffer.io.deq.bits.tail val c = (vcalloc_q.io.deq.bits.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U val vcalloc_tail = vcalloc_buffer.io.deq.bits.tail io.salloc_req(0).valid := vcalloc_buffer.io.deq.valid && vcalloc_q.io.deq.valid && c && !io.block vcalloc_buffer.io.deq.ready := io.salloc_req(0).ready && vcalloc_q.io.deq.valid && c && !io.block vcalloc_q.io.deq.ready := vcalloc_tail && vcalloc_buffer.io.deq.fire val out_bundle = if (combineSAST) { Wire(Valid(new SwitchBundle(outParams, egressParams))) } else { Reg(Valid(new SwitchBundle(outParams, egressParams))) } io.out(0) := out_bundle out_bundle.valid := vcalloc_buffer.io.deq.fire out_bundle.bits.flit := vcalloc_buffer.io.deq.bits out_bundle.bits.flit.virt_channel_id := 0.U val out_channel_oh = vcalloc_q.io.deq.bits.vc_sel.map(_.reduce(_||_)).toSeq out_bundle.bits.out_virt_channel := Mux1H(out_channel_oh, vcalloc_q.io.deq.bits.vc_sel.map(v => OHToUInt(v)).toSeq) io.debug.va_stall := io.vcalloc_req.valid && !io.vcalloc_req.ready io.debug.sa_stall := io.salloc_req(0).valid && !io.salloc_req(0).ready // TODO: We should not generate input/ingress/output/egress units for untraversable channels if (!cParam.traversable) { io.in.ready := false.B io.router_req.valid := false.B io.router_req.bits := DontCare io.vcalloc_req.valid := false.B io.vcalloc_req.bits := DontCare io.salloc_req.foreach(_.valid := false.B) io.salloc_req.foreach(_.bits := DontCare) io.out.foreach(_.valid := false.B) io.out.foreach(_.bits := DontCare) } }
module IngressUnit_24( // @[IngressUnit.scala:11:7] input clock, // @[IngressUnit.scala:11:7] input reset, // @[IngressUnit.scala:11:7] input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14] output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_1_1, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_1_2, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_2_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_1_1, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_1_2, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14] input io_out_credit_available_2_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_1_1, // @[IngressUnit.scala:24:14] input io_out_credit_available_1_2, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_2, // @[IngressUnit.scala:24:14] input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14] output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_1_1, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_1_2, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14] output io_out_0_valid, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14] output [144:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14] output io_in_ready, // @[IngressUnit.scala:24:14] input io_in_valid, // @[IngressUnit.scala:24:14] input io_in_bits_head, // @[IngressUnit.scala:24:14] input io_in_bits_tail, // @[IngressUnit.scala:24:14] input [144:0] io_in_bits_payload, // @[IngressUnit.scala:24:14] input [4:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14] ); wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_2_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_1_1; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_1_2; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25] wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30] wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23] wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23] wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28] wire [144:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = io_in_bits_egress_id == 5'h10; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = io_in_bits_egress_id == 5'h12; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = io_in_bits_egress_id == 5'h14; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_7 = io_in_bits_egress_id == 5'h16; // @[IngressUnit.scala:30:72] wire [3:0] _route_buffer_io_enq_bits_flow_egress_node_T_10 = {1'h0, (_route_buffer_io_enq_bits_flow_egress_node_id_T_4 ? 3'h5 : 3'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_5 ? 3'h6 : 3'h0)} | (_route_buffer_io_enq_bits_flow_egress_node_id_T_6 ? 4'h9 : 4'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_7 ? 4'hA : 4'h0); // @[Mux.scala:30:73] wire _GEN = _route_buffer_io_enq_ready & io_in_valid & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_10 == 4'hC; // @[Mux.scala:30:73] wire route_q_io_enq_valid = _GEN | io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_10 != 4'hC; // @[Mux.scala:30:73] wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}] wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid | ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready | ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready | ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29] wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]
Generate the Verilog code corresponding to the following Chisel files. File PMP.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.{Cat, log2Ceil} import org.chipsalliance.cde.config._ import freechips.rocketchip.tile._ import freechips.rocketchip.util._ class PMPConfig extends Bundle { val l = Bool() val res = UInt(2.W) val a = UInt(2.W) val x = Bool() val w = Bool() val r = Bool() } object PMP { def lgAlign = 2 def apply(reg: PMPReg): PMP = { val pmp = Wire(new PMP()(reg.p)) pmp.cfg := reg.cfg pmp.addr := reg.addr pmp.mask := pmp.computeMask pmp } } class PMPReg(implicit p: Parameters) extends CoreBundle()(p) { val cfg = new PMPConfig val addr = UInt((paddrBits - PMP.lgAlign).W) def reset(): Unit = { cfg.a := 0.U cfg.l := 0.U } def readAddr = if (pmpGranularity.log2 == PMP.lgAlign) addr else { val mask = ((BigInt(1) << (pmpGranularity.log2 - PMP.lgAlign)) - 1).U Mux(napot, addr | (mask >> 1), ~(~addr | mask)) } def napot = cfg.a(1) def torNotNAPOT = cfg.a(0) def tor = !napot && torNotNAPOT def cfgLocked = cfg.l def addrLocked(next: PMPReg) = cfgLocked || next.cfgLocked && next.tor } class PMP(implicit p: Parameters) extends PMPReg { val mask = UInt(paddrBits.W) import PMP._ def computeMask = { val base = Cat(addr, cfg.a(0)) | ((pmpGranularity - 1).U >> lgAlign) Cat(base & ~(base + 1.U), ((1 << lgAlign) - 1).U) } private def comparand = ~(~(addr << lgAlign) | (pmpGranularity - 1).U) private def pow2Match(x: UInt, lgSize: UInt, lgMaxSize: Int) = { def eval(a: UInt, b: UInt, m: UInt) = ((a ^ b) & ~m) === 0.U if (lgMaxSize <= pmpGranularity.log2) { eval(x, comparand, mask) } else { // break up the circuit; the MSB part will be CSE'd val lsbMask = mask | UIntToOH1(lgSize, lgMaxSize) val msbMatch = eval(x >> lgMaxSize, comparand >> lgMaxSize, mask >> lgMaxSize) val lsbMatch = eval(x(lgMaxSize-1, 0), comparand(lgMaxSize-1, 0), lsbMask(lgMaxSize-1, 0)) msbMatch && lsbMatch } } private def boundMatch(x: UInt, lsbMask: UInt, lgMaxSize: Int) = { if (lgMaxSize <= pmpGranularity.log2) { x < comparand } else { // break up the circuit; the MSB part will be CSE'd val msbsLess = (x >> lgMaxSize) < (comparand >> lgMaxSize) val msbsEqual = ((x >> lgMaxSize) ^ (comparand >> lgMaxSize)) === 0.U val lsbsLess = (x(lgMaxSize-1, 0) | lsbMask) < comparand(lgMaxSize-1, 0) msbsLess || (msbsEqual && lsbsLess) } } private def lowerBoundMatch(x: UInt, lgSize: UInt, lgMaxSize: Int) = !boundMatch(x, UIntToOH1(lgSize, lgMaxSize), lgMaxSize) private def upperBoundMatch(x: UInt, lgMaxSize: Int) = boundMatch(x, 0.U, lgMaxSize) private def rangeMatch(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP) = prev.lowerBoundMatch(x, lgSize, lgMaxSize) && upperBoundMatch(x, lgMaxSize) private def pow2Homogeneous(x: UInt, pgLevel: UInt) = { val maskHomogeneous = pgLevelMap { idxBits => if (idxBits > paddrBits) false.B else mask(idxBits - 1) } (pgLevel) maskHomogeneous || (pgLevelMap { idxBits => ((x ^ comparand) >> idxBits) =/= 0.U } (pgLevel)) } private def pgLevelMap[T](f: Int => T) = (0 until pgLevels).map { i => f(pgIdxBits + (pgLevels - 1 - i) * pgLevelBits) } private def rangeHomogeneous(x: UInt, pgLevel: UInt, prev: PMP) = { val beginsAfterLower = !(x < prev.comparand) val beginsAfterUpper = !(x < comparand) val pgMask = pgLevelMap { idxBits => (((BigInt(1) << paddrBits) - (BigInt(1) << idxBits)) max 0).U } (pgLevel) val endsBeforeLower = (x & pgMask) < (prev.comparand & pgMask) val endsBeforeUpper = (x & pgMask) < (comparand & pgMask) endsBeforeLower || beginsAfterUpper || (beginsAfterLower && endsBeforeUpper) } // returns whether this PMP completely contains, or contains none of, a page def homogeneous(x: UInt, pgLevel: UInt, prev: PMP): Bool = Mux(napot, pow2Homogeneous(x, pgLevel), !torNotNAPOT || rangeHomogeneous(x, pgLevel, prev)) // returns whether this matching PMP fully contains the access def aligned(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP): Bool = if (lgMaxSize <= pmpGranularity.log2) true.B else { val lsbMask = UIntToOH1(lgSize, lgMaxSize) val straddlesLowerBound = ((x >> lgMaxSize) ^ (prev.comparand >> lgMaxSize)) === 0.U && (prev.comparand(lgMaxSize-1, 0) & ~x(lgMaxSize-1, 0)) =/= 0.U val straddlesUpperBound = ((x >> lgMaxSize) ^ (comparand >> lgMaxSize)) === 0.U && (comparand(lgMaxSize-1, 0) & (x(lgMaxSize-1, 0) | lsbMask)) =/= 0.U val rangeAligned = !(straddlesLowerBound || straddlesUpperBound) val pow2Aligned = (lsbMask & ~mask(lgMaxSize-1, 0)) === 0.U Mux(napot, pow2Aligned, rangeAligned) } // returns whether this PMP matches at least one byte of the access def hit(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP): Bool = Mux(napot, pow2Match(x, lgSize, lgMaxSize), torNotNAPOT && rangeMatch(x, lgSize, lgMaxSize, prev)) } class PMPHomogeneityChecker(pmps: Seq[PMP])(implicit p: Parameters) { def apply(addr: UInt, pgLevel: UInt): Bool = { pmps.foldLeft((true.B, 0.U.asTypeOf(new PMP))) { case ((h, prev), pmp) => (h && pmp.homogeneous(addr, pgLevel, prev), pmp) }._1 } } class PMPChecker(lgMaxSize: Int)(implicit val p: Parameters) extends Module with HasCoreParameters { override def desiredName = s"PMPChecker_s${lgMaxSize}" val io = IO(new Bundle { val prv = Input(UInt(PRV.SZ.W)) val pmp = Input(Vec(nPMPs, new PMP)) val addr = Input(UInt(paddrBits.W)) val size = Input(UInt(log2Ceil(lgMaxSize + 1).W)) val r = Output(Bool()) val w = Output(Bool()) val x = Output(Bool()) }) val default = if (io.pmp.isEmpty) true.B else io.prv > PRV.S.U val pmp0 = WireInit(0.U.asTypeOf(new PMP)) pmp0.cfg.r := default pmp0.cfg.w := default pmp0.cfg.x := default val res = (io.pmp zip (pmp0 +: io.pmp)).reverse.foldLeft(pmp0) { case (prev, (pmp, prevPMP)) => val hit = pmp.hit(io.addr, io.size, lgMaxSize, prevPMP) val ignore = default && !pmp.cfg.l val aligned = pmp.aligned(io.addr, io.size, lgMaxSize, prevPMP) for ((name, idx) <- Seq("no", "TOR", if (pmpGranularity <= 4) "NA4" else "", "NAPOT").zipWithIndex; if name.nonEmpty) property.cover(pmp.cfg.a === idx.U, s"The cfg access is set to ${name} access ", "Cover PMP access mode setting") property.cover(pmp.cfg.l === 0x1.U, s"The cfg lock is set to high ", "Cover PMP lock mode setting") // Not including Write and no Read permission as the combination is reserved for ((name, idx) <- Seq("no", "RO", "", "RW", "X", "RX", "", "RWX").zipWithIndex; if name.nonEmpty) property.cover((Cat(pmp.cfg.x, pmp.cfg.w, pmp.cfg.r) === idx.U), s"The permission is set to ${name} access ", "Cover PMP access permission setting") for ((name, idx) <- Seq("", "TOR", if (pmpGranularity <= 4) "NA4" else "", "NAPOT").zipWithIndex; if name.nonEmpty) { property.cover(!ignore && hit && aligned && pmp.cfg.a === idx.U, s"The access matches ${name} mode ", "Cover PMP access") property.cover(pmp.cfg.l && hit && aligned && pmp.cfg.a === idx.U, s"The access matches ${name} mode with lock bit high", "Cover PMP access with lock bit") } val cur = WireInit(pmp) cur.cfg.r := aligned && (pmp.cfg.r || ignore) cur.cfg.w := aligned && (pmp.cfg.w || ignore) cur.cfg.x := aligned && (pmp.cfg.x || ignore) Mux(hit, cur, prev) } io.r := res.cfg.r io.w := res.cfg.w io.x := res.cfg.x }
module PMPChecker_s3_7( // @[PMP.scala:143:7] input clock, // @[PMP.scala:143:7] input reset, // @[PMP.scala:143:7] input [31:0] io_addr, // @[PMP.scala:146:14] input [1:0] io_size // @[PMP.scala:146:14] ); wire [31:0] io_addr_0 = io_addr; // @[PMP.scala:143:7] wire [1:0] io_size_0 = io_size; // @[PMP.scala:143:7] wire _pmp0_WIRE_cfg_l = 1'h0; // @[PMP.scala:157:35] wire _pmp0_WIRE_cfg_x = 1'h0; // @[PMP.scala:157:35] wire _pmp0_WIRE_cfg_w = 1'h0; // @[PMP.scala:157:35] wire _pmp0_WIRE_cfg_r = 1'h0; // @[PMP.scala:157:35] wire pmp0_cfg_l = 1'h0; // @[PMP.scala:157:22] wire [1:0] _pmp0_WIRE_cfg_res = 2'h0; // @[PMP.scala:157:35] wire [1:0] _pmp0_WIRE_cfg_a = 2'h0; // @[PMP.scala:157:35] wire [1:0] pmp0_cfg_res = 2'h0; // @[PMP.scala:157:22] wire [1:0] pmp0_cfg_a = 2'h0; // @[PMP.scala:157:22] wire [29:0] _pmp0_WIRE_addr = 30'h0; // @[PMP.scala:157:35] wire [29:0] pmp0_addr = 30'h0; // @[PMP.scala:157:22] wire [31:0] _pmp0_WIRE_mask = 32'h0; // @[PMP.scala:157:35] wire [31:0] pmp0_mask = 32'h0; // @[PMP.scala:157:22] wire io_r = 1'h1; // @[PMP.scala:143:7] wire io_w = 1'h1; // @[PMP.scala:143:7] wire io_x = 1'h1; // @[PMP.scala:143:7] wire pmp0_cfg_x = 1'h1; // @[PMP.scala:157:22] wire pmp0_cfg_w = 1'h1; // @[PMP.scala:157:22] wire pmp0_cfg_r = 1'h1; // @[PMP.scala:157:22] wire [1:0] io_prv = 2'h1; // @[PMP.scala:143:7, :146:14] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Tile.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ import Util._ /** * A Tile is a purely combinational 2D array of passThrough PEs. * a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs * @param width The data width of each PE in bits * @param rows Number of PEs on each row * @param columns Number of PEs on each column */ class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module { val io = IO(new Bundle { val in_a = Input(Vec(rows, inputType)) val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it val in_d = Input(Vec(columns, outputType)) val in_control = Input(Vec(columns, new PEControl(accType))) val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val in_last = Input(Vec(columns, Bool())) val out_a = Output(Vec(rows, inputType)) val out_c = Output(Vec(columns, outputType)) val out_b = Output(Vec(columns, outputType)) val out_control = Output(Vec(columns, new PEControl(accType))) val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val out_last = Output(Vec(columns, Bool())) val in_valid = Input(Vec(columns, Bool())) val out_valid = Output(Vec(columns, Bool())) val bad_dataflow = Output(Bool()) }) import ev._ val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls))) val tileT = tile.transpose // TODO: abstract hori/vert broadcast, all these connections look the same // Broadcast 'a' horizontally across the Tile for (r <- 0 until rows) { tile(r).foldLeft(io.in_a(r)) { case (in_a, pe) => pe.io.in_a := in_a pe.io.out_a } } // Broadcast 'b' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_b(c)) { case (in_b, pe) => pe.io.in_b := (if (tree_reduction) in_b.zero else in_b) pe.io.out_b } } // Broadcast 'd' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_d(c)) { case (in_d, pe) => pe.io.in_d := in_d pe.io.out_c } } // Broadcast 'control' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_control(c)) { case (in_ctrl, pe) => pe.io.in_control := in_ctrl pe.io.out_control } } // Broadcast 'garbage' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_valid(c)) { case (v, pe) => pe.io.in_valid := v pe.io.out_valid } } // Broadcast 'id' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_id(c)) { case (id, pe) => pe.io.in_id := id pe.io.out_id } } // Broadcast 'last' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_last(c)) { case (last, pe) => pe.io.in_last := last pe.io.out_last } } // Drive the Tile's bottom IO for (c <- 0 until columns) { io.out_c(c) := tile(rows-1)(c).io.out_c io.out_control(c) := tile(rows-1)(c).io.out_control io.out_id(c) := tile(rows-1)(c).io.out_id io.out_last(c) := tile(rows-1)(c).io.out_last io.out_valid(c) := tile(rows-1)(c).io.out_valid io.out_b(c) := { if (tree_reduction) { val prods = tileT(c).map(_.io.out_b) accumulateTree(prods :+ io.in_b(c)) } else { tile(rows - 1)(c).io.out_b } } } io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_||_)).reduce(_||_) // Drive the Tile's right IO for (r <- 0 until rows) { io.out_a(r) := tile(r)(columns-1).io.out_a } }
module Tile_6( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_262 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }
module AsyncValidSync_126( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_141 io_out_source_extend ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_57( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [2:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [3:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] reg [2:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [3:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [9:0] inflight; // @[Monitor.scala:614:27] reg [39:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [39:0] inflight_sizes; // @[Monitor.scala:618:33] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire [15:0] _GEN_0 = {12'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [15:0] _GEN_3 = {12'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [9:0] inflight_1; // @[Monitor.scala:726:35] reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File scratchpad_adapter.scala: package sodor.common import chisel3._ import chisel3.util._ import chisel3.experimental._ import freechips.rocketchip.rocket._ import org.chipsalliance.cde.config.{Parameters, Field} import freechips.rocketchip.subsystem._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tile._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class SodorScratchpadAdapter(implicit p: Parameters, implicit val sodorConf: SodorCoreParams) extends CoreModule { val io = IO(new Bundle() { val slavePort = Flipped(new HellaCacheIO()) val memPort = new MemPortIo(data_width = coreDataBits) }) // =================== // Slave port signals val slave_req_ready = io.slavePort.req.ready val s2_slave_resp_valid = io.slavePort.resp.valid val slave_req_valid = io.slavePort.req.valid val slave_cmd = io.slavePort.req.bits.cmd val slave_req = io.slavePort.req.bits // All request are delayed for one cycle to avoid being killed val s1_slave_write_kill = io.slavePort.s1_kill val s1_slave_write_data = io.slavePort.s1_data.data val s1_slave_write_mask = io.slavePort.s1_data.mask val s1_slave_req_valid = RegNext(slave_req_valid, false.B) val s1_slave_cmd = RegNext(slave_cmd) val s1_slave_req = RegNext(slave_req) // Note that ScratchpadSlavePort requires 2-cycle delay, or it won't even send the response val s2_slave_read_data = io.slavePort.resp.bits.data_raw val s2_slave_read_mask = io.slavePort.resp.bits.mask val s2_nack = io.slavePort.s2_nack // Tie anything not defined below to DontCare io.slavePort := DontCare // =================== // HellaCacheIO to MemPortIo logic // Connect valid & ready bits slave_req_ready := io.memPort.req.ready io.memPort.req.valid := s1_slave_req_valid & (s1_slave_cmd === M_XRD || !s1_slave_write_kill) s2_slave_resp_valid := RegNext(io.memPort.resp.valid, false.B) // Connect read info s2_slave_read_mask := RegNext(new StoreGen(s1_slave_req.size, s1_slave_req.addr, 0.U, coreDataBytes).mask) s2_slave_read_data := RegNext(io.memPort.resp.bits.data) // Connect write info io.memPort.req.bits.addr := s1_slave_req.addr io.memPort.req.bits.data := s1_slave_write_data // Other connections s2_nack := false.B io.memPort.req.bits.fcn := Mux(s1_slave_cmd === M_XRD, M_XRD, M_XWR) // Since we don't have dword here (the bus only has 32 bits), s1_slave_req.size <= 2. // The expression below convert TileLink size and signedness to Sodor type. require(io.slavePort.req.bits.addr.getWidth == 32, "Slave port only support 32 bit address") assert (s1_slave_req.size <= 2.U, "Slave port received a bus request with unsupported size: %d", s1_slave_req.size) io.memPort.req.bits.setType(s1_slave_req.signed, s1_slave_req.size) } // This class simply route all memory request that doesn't belong to the scratchpad class SodorRequestRouter(cacheAddress: AddressSet)(implicit val conf: SodorCoreParams) extends Module { val io = IO(new Bundle() { val masterPort = new MemPortIo(data_width = conf.xprlen) val scratchPort = new MemPortIo(data_width = conf.xprlen) val corePort = Flipped(new MemPortIo(data_width = conf.xprlen)) val respAddress = Input(UInt(conf.xprlen.W)) }) val in_range = cacheAddress.contains(io.corePort.req.bits.addr) // Connect other signals io.masterPort.req.bits <> io.corePort.req.bits io.scratchPort.req.bits <> io.corePort.req.bits // Connect valid signal io.masterPort.req.valid := io.corePort.req.valid & !in_range io.scratchPort.req.valid := io.corePort.req.valid & in_range // Mux ready and request signal io.corePort.req.ready := Mux(in_range, io.scratchPort.req.ready, io.masterPort.req.ready) // Use respAddress to route response val resp_in_range = cacheAddress.contains(io.respAddress) io.corePort.resp.bits := Mux(resp_in_range, io.scratchPort.resp.bits, io.masterPort.resp.bits) io.corePort.resp.valid := Mux(resp_in_range, io.scratchPort.resp.valid, io.masterPort.resp.valid) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") }
module SodorRequestRouter_1( // @[scratchpad_adapter.scala:75:7] input clock, // @[scratchpad_adapter.scala:75:7] input reset, // @[scratchpad_adapter.scala:75:7] input io_masterPort_req_ready, // @[scratchpad_adapter.scala:76:14] output io_masterPort_req_valid, // @[scratchpad_adapter.scala:76:14] output [31:0] io_masterPort_req_bits_addr, // @[scratchpad_adapter.scala:76:14] input io_masterPort_resp_valid, // @[scratchpad_adapter.scala:76:14] input [31:0] io_masterPort_resp_bits_data, // @[scratchpad_adapter.scala:76:14] output io_scratchPort_req_valid, // @[scratchpad_adapter.scala:76:14] output [31:0] io_scratchPort_req_bits_addr, // @[scratchpad_adapter.scala:76:14] input io_scratchPort_resp_valid, // @[scratchpad_adapter.scala:76:14] input [31:0] io_scratchPort_resp_bits_data, // @[scratchpad_adapter.scala:76:14] output io_corePort_req_ready, // @[scratchpad_adapter.scala:76:14] input io_corePort_req_valid, // @[scratchpad_adapter.scala:76:14] input [31:0] io_corePort_req_bits_addr, // @[scratchpad_adapter.scala:76:14] output io_corePort_resp_valid, // @[scratchpad_adapter.scala:76:14] output [31:0] io_corePort_resp_bits_data, // @[scratchpad_adapter.scala:76:14] input [31:0] io_respAddress // @[scratchpad_adapter.scala:76:14] ); wire io_masterPort_req_ready_0 = io_masterPort_req_ready; // @[scratchpad_adapter.scala:75:7] wire io_masterPort_resp_valid_0 = io_masterPort_resp_valid; // @[scratchpad_adapter.scala:75:7] wire [31:0] io_masterPort_resp_bits_data_0 = io_masterPort_resp_bits_data; // @[scratchpad_adapter.scala:75:7] wire io_scratchPort_resp_valid_0 = io_scratchPort_resp_valid; // @[scratchpad_adapter.scala:75:7] wire [31:0] io_scratchPort_resp_bits_data_0 = io_scratchPort_resp_bits_data; // @[scratchpad_adapter.scala:75:7] wire io_corePort_req_valid_0 = io_corePort_req_valid; // @[scratchpad_adapter.scala:75:7] wire [31:0] io_corePort_req_bits_addr_0 = io_corePort_req_bits_addr; // @[scratchpad_adapter.scala:75:7] wire [31:0] io_respAddress_0 = io_respAddress; // @[scratchpad_adapter.scala:75:7] wire io_scratchPort_req_ready = 1'h1; // @[scratchpad_adapter.scala:75:7, :76:14] wire [2:0] io_masterPort_req_bits_typ = 3'h7; // @[scratchpad_adapter.scala:75:7, :76:14] wire [2:0] io_scratchPort_req_bits_typ = 3'h7; // @[scratchpad_adapter.scala:75:7, :76:14] wire [2:0] io_corePort_req_bits_typ = 3'h7; // @[scratchpad_adapter.scala:75:7, :76:14] wire io_masterPort_req_bits_fcn = 1'h0; // @[scratchpad_adapter.scala:75:7, :76:14] wire io_scratchPort_req_bits_fcn = 1'h0; // @[scratchpad_adapter.scala:75:7, :76:14] wire io_corePort_req_bits_fcn = 1'h0; // @[scratchpad_adapter.scala:75:7, :76:14] wire [31:0] io_masterPort_req_bits_data = 32'h0; // @[scratchpad_adapter.scala:75:7, :76:14] wire [31:0] io_scratchPort_req_bits_data = 32'h0; // @[scratchpad_adapter.scala:75:7, :76:14] wire [31:0] io_corePort_req_bits_data = 32'h0; // @[scratchpad_adapter.scala:75:7, :76:14] wire _io_masterPort_req_valid_T_1; // @[scratchpad_adapter.scala:90:52] wire _io_scratchPort_req_valid_T; // @[scratchpad_adapter.scala:91:53] wire _io_corePort_req_ready_T; // @[scratchpad_adapter.scala:94:31] wire [31:0] io_masterPort_req_bits_addr_0 = io_corePort_req_bits_addr_0; // @[scratchpad_adapter.scala:75:7] wire [31:0] io_scratchPort_req_bits_addr_0 = io_corePort_req_bits_addr_0; // @[scratchpad_adapter.scala:75:7] wire _io_corePort_resp_valid_T; // @[scratchpad_adapter.scala:98:32] wire [31:0] _io_corePort_resp_bits_T_data; // @[scratchpad_adapter.scala:97:31] wire io_masterPort_req_valid_0; // @[scratchpad_adapter.scala:75:7] wire io_scratchPort_req_valid_0; // @[scratchpad_adapter.scala:75:7] wire io_corePort_req_ready_0; // @[scratchpad_adapter.scala:75:7] wire [31:0] io_corePort_resp_bits_data_0; // @[scratchpad_adapter.scala:75:7] wire io_corePort_resp_valid_0; // @[scratchpad_adapter.scala:75:7] wire [31:0] _in_range_T = io_corePort_req_bits_addr_0 ^ 32'h80000000; // @[Parameters.scala:137:31] wire [32:0] _in_range_T_1 = {1'h0, _in_range_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _in_range_T_2 = _in_range_T_1 & 33'h1FFFC0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _in_range_T_3 = _in_range_T_2; // @[Parameters.scala:137:46] wire in_range = _in_range_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _io_masterPort_req_valid_T = ~in_range; // @[Parameters.scala:137:59] assign _io_masterPort_req_valid_T_1 = io_corePort_req_valid_0 & _io_masterPort_req_valid_T; // @[scratchpad_adapter.scala:75:7, :90:{52,54}] assign io_masterPort_req_valid_0 = _io_masterPort_req_valid_T_1; // @[scratchpad_adapter.scala:75:7, :90:52] assign _io_scratchPort_req_valid_T = io_corePort_req_valid_0 & in_range; // @[Parameters.scala:137:59] assign io_scratchPort_req_valid_0 = _io_scratchPort_req_valid_T; // @[scratchpad_adapter.scala:75:7, :91:53] assign _io_corePort_req_ready_T = in_range | io_masterPort_req_ready_0; // @[Parameters.scala:137:59] assign io_corePort_req_ready_0 = _io_corePort_req_ready_T; // @[scratchpad_adapter.scala:75:7, :94:31] wire [31:0] _resp_in_range_T = io_respAddress_0 ^ 32'h80000000; // @[Parameters.scala:137:31] wire [32:0] _resp_in_range_T_1 = {1'h0, _resp_in_range_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _resp_in_range_T_2 = _resp_in_range_T_1 & 33'h1FFFC0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _resp_in_range_T_3 = _resp_in_range_T_2; // @[Parameters.scala:137:46] wire resp_in_range = _resp_in_range_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] assign _io_corePort_resp_bits_T_data = resp_in_range ? io_scratchPort_resp_bits_data_0 : io_masterPort_resp_bits_data_0; // @[Parameters.scala:137:59] assign io_corePort_resp_bits_data_0 = _io_corePort_resp_bits_T_data; // @[scratchpad_adapter.scala:75:7, :97:31] assign _io_corePort_resp_valid_T = resp_in_range ? io_scratchPort_resp_valid_0 : io_masterPort_resp_valid_0; // @[Parameters.scala:137:59] assign io_corePort_resp_valid_0 = _io_corePort_resp_valid_T; // @[scratchpad_adapter.scala:75:7, :98:32] assign io_masterPort_req_valid = io_masterPort_req_valid_0; // @[scratchpad_adapter.scala:75:7] assign io_masterPort_req_bits_addr = io_masterPort_req_bits_addr_0; // @[scratchpad_adapter.scala:75:7] assign io_scratchPort_req_valid = io_scratchPort_req_valid_0; // @[scratchpad_adapter.scala:75:7] assign io_scratchPort_req_bits_addr = io_scratchPort_req_bits_addr_0; // @[scratchpad_adapter.scala:75:7] assign io_corePort_req_ready = io_corePort_req_ready_0; // @[scratchpad_adapter.scala:75:7] assign io_corePort_resp_valid = io_corePort_resp_valid_0; // @[scratchpad_adapter.scala:75:7] assign io_corePort_resp_bits_data = io_corePort_resp_bits_data_0; // @[scratchpad_adapter.scala:75:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File WidthWidget.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.AddressSet import freechips.rocketchip.util.{Repeater, UIntToOH1} // innBeatBytes => the new client-facing bus width class TLWidthWidget(innerBeatBytes: Int)(implicit p: Parameters) extends LazyModule { private def noChangeRequired(manager: TLManagerPortParameters) = manager.beatBytes == innerBeatBytes val node = new TLAdapterNode( clientFn = { case c => c }, managerFn = { case m => m.v1copy(beatBytes = innerBeatBytes) }){ override def circuitIdentity = edges.out.map(_.manager).forall(noChangeRequired) } override lazy val desiredName = s"TLWidthWidget$innerBeatBytes" lazy val module = new Impl class Impl extends LazyModuleImp(this) { def merge[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T]) = { val inBytes = edgeIn.manager.beatBytes val outBytes = edgeOut.manager.beatBytes val ratio = outBytes / inBytes val keepBits = log2Ceil(outBytes) val dropBits = log2Ceil(inBytes) val countBits = log2Ceil(ratio) val size = edgeIn.size(in.bits) val hasData = edgeIn.hasData(in.bits) val limit = UIntToOH1(size, keepBits) >> dropBits val count = RegInit(0.U(countBits.W)) val first = count === 0.U val last = count === limit || !hasData val enable = Seq.tabulate(ratio) { i => !((count ^ i.U) & limit).orR } val corrupt_reg = RegInit(false.B) val corrupt_in = edgeIn.corrupt(in.bits) val corrupt_out = corrupt_in || corrupt_reg when (in.fire) { count := count + 1.U corrupt_reg := corrupt_out when (last) { count := 0.U corrupt_reg := false.B } } def helper(idata: UInt): UInt = { // rdata is X until the first time a multi-beat write occurs. // Prevent the X from leaking outside by jamming the mux control until // the first time rdata is written (and hence no longer X). val rdata_written_once = RegInit(false.B) val masked_enable = enable.map(_ || !rdata_written_once) val odata = Seq.fill(ratio) { WireInit(idata) } val rdata = Reg(Vec(ratio-1, chiselTypeOf(idata))) val pdata = rdata :+ idata val mdata = (masked_enable zip (odata zip pdata)) map { case (e, (o, p)) => Mux(e, o, p) } when (in.fire && !last) { rdata_written_once := true.B (rdata zip mdata) foreach { case (r, m) => r := m } } Cat(mdata.reverse) } in.ready := out.ready || !last out.valid := in.valid && last out.bits := in.bits // Don't put down hardware if we never carry data edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits))) edgeOut.corrupt(out.bits) := corrupt_out (out.bits, in.bits) match { case (o: TLBundleA, i: TLBundleA) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W)) case (o: TLBundleB, i: TLBundleB) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W)) case (o: TLBundleC, i: TLBundleC) => () case (o: TLBundleD, i: TLBundleD) => () case _ => require(false, "Impossible bundle combination in WidthWidget") } } def split[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = { val inBytes = edgeIn.manager.beatBytes val outBytes = edgeOut.manager.beatBytes val ratio = inBytes / outBytes val keepBits = log2Ceil(inBytes) val dropBits = log2Ceil(outBytes) val countBits = log2Ceil(ratio) val size = edgeIn.size(in.bits) val hasData = edgeIn.hasData(in.bits) val limit = UIntToOH1(size, keepBits) >> dropBits val count = RegInit(0.U(countBits.W)) val first = count === 0.U val last = count === limit || !hasData when (out.fire) { count := count + 1.U when (last) { count := 0.U } } // For sub-beat transfer, extract which part matters val sel = in.bits match { case a: TLBundleA => a.address(keepBits-1, dropBits) case b: TLBundleB => b.address(keepBits-1, dropBits) case c: TLBundleC => c.address(keepBits-1, dropBits) case d: TLBundleD => { val sel = sourceMap(d.source) val hold = Mux(first, sel, RegEnable(sel, first)) // a_first is not for whole xfer hold & ~limit // if more than one a_first/xfer, the address must be aligned anyway } } val index = sel | count def helper(idata: UInt, width: Int): UInt = { val mux = VecInit.tabulate(ratio) { i => idata((i+1)*outBytes*width-1, i*outBytes*width) } mux(index) } out.bits := in.bits out.valid := in.valid in.ready := out.ready // Don't put down hardware if we never carry data edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits), 8)) (out.bits, in.bits) match { case (o: TLBundleA, i: TLBundleA) => o.mask := helper(i.mask, 1) case (o: TLBundleB, i: TLBundleB) => o.mask := helper(i.mask, 1) case (o: TLBundleC, i: TLBundleC) => () // replicating corrupt to all beats is ok case (o: TLBundleD, i: TLBundleD) => () case _ => require(false, "Impossbile bundle combination in WidthWidget") } // Repeat the input if we're not last !last } def splice[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = { if (edgeIn.manager.beatBytes == edgeOut.manager.beatBytes) { // nothing to do; pass it through out.bits := in.bits out.valid := in.valid in.ready := out.ready } else if (edgeIn.manager.beatBytes > edgeOut.manager.beatBytes) { // split input to output val repeat = Wire(Bool()) val repeated = Repeater(in, repeat) val cated = Wire(chiselTypeOf(repeated)) cated <> repeated edgeIn.data(cated.bits) := Cat( edgeIn.data(repeated.bits)(edgeIn.manager.beatBytes*8-1, edgeOut.manager.beatBytes*8), edgeIn.data(in.bits)(edgeOut.manager.beatBytes*8-1, 0)) repeat := split(edgeIn, cated, edgeOut, out, sourceMap) } else { // merge input to output merge(edgeIn, in, edgeOut, out) } } (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => // If the master is narrower than the slave, the D channel must be narrowed. // This is tricky, because the D channel has no address data. // Thus, you don't know which part of a sub-beat transfer to extract. // To fix this, we record the relevant address bits for all sources. // The assumption is that this sort of situation happens only where // you connect a narrow master to the system bus, so there are few sources. def sourceMap(source_bits: UInt) = { val source = if (edgeIn.client.endSourceId == 1) 0.U(0.W) else source_bits require (edgeOut.manager.beatBytes > edgeIn.manager.beatBytes) val keepBits = log2Ceil(edgeOut.manager.beatBytes) val dropBits = log2Ceil(edgeIn.manager.beatBytes) val sources = Reg(Vec(edgeIn.client.endSourceId, UInt((keepBits-dropBits).W))) val a_sel = in.a.bits.address(keepBits-1, dropBits) when (in.a.fire) { if (edgeIn.client.endSourceId == 1) { // avoid extraction-index-width warning sources(0) := a_sel } else { sources(in.a.bits.source) := a_sel } } // depopulate unused source registers: edgeIn.client.unusedSources.foreach { id => sources(id) := 0.U } val bypass = in.a.valid && in.a.bits.source === source if (edgeIn.manager.minLatency > 0) sources(source) else Mux(bypass, a_sel, sources(source)) } splice(edgeIn, in.a, edgeOut, out.a, sourceMap) splice(edgeOut, out.d, edgeIn, in.d, sourceMap) if (edgeOut.manager.anySupportAcquireB && edgeIn.client.anySupportProbe) { splice(edgeOut, out.b, edgeIn, in.b, sourceMap) splice(edgeIn, in.c, edgeOut, out.c, sourceMap) out.e.valid := in.e.valid out.e.bits := in.e.bits in.e.ready := out.e.ready } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLWidthWidget { def apply(innerBeatBytes: Int)(implicit p: Parameters): TLNode = { val widget = LazyModule(new TLWidthWidget(innerBeatBytes)) widget.node } def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper.beatBytes) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMWidthWidget(first: Int, second: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("WidthWidget")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) (ram.node := TLDelayer(0.1) := TLFragmenter(4, 256) := TLWidthWidget(second) := TLWidthWidget(first) := TLDelayer(0.1) := model.node := fuzz.node) lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMWidthWidgetTest(little: Int, big: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMWidthWidget(little,big,txns)).module) dut.io.start := DontCare io.finished := dut.io.finished } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Repeater.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{Decoupled, DecoupledIO} // A Repeater passes its input to its output, unless repeat is asserted. // When repeat is asserted, the Repeater copies the input and repeats it next cycle. class Repeater[T <: Data](gen: T) extends Module { override def desiredName = s"Repeater_${gen.typeName}" val io = IO( new Bundle { val repeat = Input(Bool()) val full = Output(Bool()) val enq = Flipped(Decoupled(gen.cloneType)) val deq = Decoupled(gen.cloneType) } ) val full = RegInit(false.B) val saved = Reg(gen.cloneType) // When !full, a repeater is pass-through io.deq.valid := io.enq.valid || full io.enq.ready := io.deq.ready && !full io.deq.bits := Mux(full, saved, io.enq.bits) io.full := full when (io.enq.fire && io.repeat) { full := true.B; saved := io.enq.bits } when (io.deq.fire && !io.repeat) { full := false.B } } object Repeater { def apply[T <: Data](enq: DecoupledIO[T], repeat: Bool): DecoupledIO[T] = { val repeater = Module(new Repeater(chiselTypeOf(enq.bits))) repeater.io.repeat := repeat repeater.io.enq <> enq repeater.io.deq } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }
module TLWidthWidget1( // @[WidthWidget.scala:27:9] input clock, // @[WidthWidget.scala:27:9] input reset, // @[WidthWidget.scala:27:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire [63:0] _repeated_repeater_io_deq_bits_data; // @[Repeater.scala:36:26] wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9] wire [31:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[WidthWidget.scala:27:9] wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] auto_anon_out_d_bits_param_0 = auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_bits_sink_0 = auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_bits_denied_0 = auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_bits_corrupt_0 = auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire [7:0] _anonOut_a_bits_mask_T_5 = 8'hFF; // @[WidthWidget.scala:85:119] wire auto_anon_in_a_bits_mask = 1'h1; // @[WidthWidget.scala:27:9] wire anonIn_a_bits_mask = 1'h1; // @[MixedNode.scala:551:17] wire anonOut_a_bits_mask_odata_0 = 1'h1; // @[WidthWidget.scala:65:47] wire anonOut_a_bits_mask_odata_1 = 1'h1; // @[WidthWidget.scala:65:47] wire anonOut_a_bits_mask_odata_2 = 1'h1; // @[WidthWidget.scala:65:47] wire anonOut_a_bits_mask_odata_3 = 1'h1; // @[WidthWidget.scala:65:47] wire anonOut_a_bits_mask_odata_4 = 1'h1; // @[WidthWidget.scala:65:47] wire anonOut_a_bits_mask_odata_5 = 1'h1; // @[WidthWidget.scala:65:47] wire anonOut_a_bits_mask_odata_6 = 1'h1; // @[WidthWidget.scala:65:47] wire anonOut_a_bits_mask_odata_7 = 1'h1; // @[WidthWidget.scala:65:47] wire anonOut_a_bits_mask_mdata_7 = 1'h1; // @[WidthWidget.scala:68:88] wire _repeat_sel_sel_bypass_T = 1'h1; // @[WidthWidget.scala:200:53] wire [2:0] auto_anon_in_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9] wire [2:0] anonIn_a_bits_param = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] anonOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17] wire auto_anon_in_a_bits_source = 1'h0; // @[WidthWidget.scala:27:9] wire auto_anon_in_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_bits_source = 1'h0; // @[WidthWidget.scala:27:9] wire auto_anon_out_a_bits_source = 1'h0; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_bits_source = 1'h0; // @[WidthWidget.scala:27:9] wire anonIn_a_ready; // @[MixedNode.scala:551:17] wire anonIn_a_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_d_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire anonOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire anonOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire cated_bits_source = 1'h0; // @[WidthWidget.scala:161:25] wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[WidthWidget.scala:27:9] wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [3:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[WidthWidget.scala:27:9] wire [31:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[WidthWidget.scala:27:9] wire [7:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[WidthWidget.scala:27:9] wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[WidthWidget.scala:27:9] wire anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [7:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[WidthWidget.scala:27:9] wire anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [3:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [31:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[WidthWidget.scala:27:9] wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [1:0] anonOut_d_bits_param = auto_anon_out_d_bits_param_0; // @[WidthWidget.scala:27:9] wire [3:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[WidthWidget.scala:27:9] wire anonOut_d_bits_sink = auto_anon_out_d_bits_sink_0; // @[WidthWidget.scala:27:9] wire anonOut_d_bits_denied = auto_anon_out_d_bits_denied_0; // @[WidthWidget.scala:27:9] wire [63:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[WidthWidget.scala:27:9] wire anonOut_d_bits_corrupt = auto_anon_out_d_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_a_ready_0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_in_d_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [1:0] auto_anon_in_d_bits_param_0; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_in_d_bits_size_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_bits_sink_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_bits_denied_0; // @[WidthWidget.scala:27:9] wire [7:0] auto_anon_in_d_bits_data_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_valid_0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_a_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_out_a_bits_size_0; // @[WidthWidget.scala:27:9] wire [31:0] auto_anon_out_a_bits_address_0; // @[WidthWidget.scala:27:9] wire [7:0] auto_anon_out_a_bits_mask_0; // @[WidthWidget.scala:27:9] wire [63:0] auto_anon_out_a_bits_data_0; // @[WidthWidget.scala:27:9] wire auto_anon_out_a_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire auto_anon_out_a_valid_0; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_ready_0; // @[WidthWidget.scala:27:9] wire _anonIn_a_ready_T_1; // @[WidthWidget.scala:76:29] assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[WidthWidget.scala:27:9] wire repeat_sel_sel_bypass = anonIn_a_valid; // @[WidthWidget.scala:200:33] assign anonOut_a_bits_opcode = anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign anonOut_a_bits_size = anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign anonOut_a_bits_address = anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] anonOut_a_bits_data_odata_0 = anonIn_a_bits_data; // @[WidthWidget.scala:65:47] wire [7:0] anonOut_a_bits_data_odata_1 = anonIn_a_bits_data; // @[WidthWidget.scala:65:47] wire [7:0] anonOut_a_bits_data_odata_2 = anonIn_a_bits_data; // @[WidthWidget.scala:65:47] wire [7:0] anonOut_a_bits_data_odata_3 = anonIn_a_bits_data; // @[WidthWidget.scala:65:47] wire [7:0] anonOut_a_bits_data_odata_4 = anonIn_a_bits_data; // @[WidthWidget.scala:65:47] wire [7:0] anonOut_a_bits_data_odata_5 = anonIn_a_bits_data; // @[WidthWidget.scala:65:47] wire [7:0] anonOut_a_bits_data_odata_6 = anonIn_a_bits_data; // @[WidthWidget.scala:65:47] wire [7:0] anonOut_a_bits_data_odata_7 = anonIn_a_bits_data; // @[WidthWidget.scala:65:47] wire cated_ready = anonIn_d_ready; // @[WidthWidget.scala:161:25] wire cated_valid; // @[WidthWidget.scala:161:25] assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] cated_bits_opcode; // @[WidthWidget.scala:161:25] assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] cated_bits_param; // @[WidthWidget.scala:161:25] assign auto_anon_in_d_bits_param_0 = anonIn_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] cated_bits_size; // @[WidthWidget.scala:161:25] assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[WidthWidget.scala:27:9] wire cated_bits_sink; // @[WidthWidget.scala:161:25] assign auto_anon_in_d_bits_sink_0 = anonIn_d_bits_sink; // @[WidthWidget.scala:27:9] wire cated_bits_denied; // @[WidthWidget.scala:161:25] assign auto_anon_in_d_bits_denied_0 = anonIn_d_bits_denied; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data; // @[WidthWidget.scala:27:9] wire cated_bits_corrupt; // @[WidthWidget.scala:161:25] assign auto_anon_in_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire _anonOut_a_valid_T; // @[WidthWidget.scala:77:29] assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[WidthWidget.scala:27:9] wire [3:0] _anonOut_a_bits_mask_sizeOH_T = anonOut_a_bits_size; // @[Misc.scala:202:34] assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] _anonOut_a_bits_mask_T_7; // @[WidthWidget.scala:85:88] assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[WidthWidget.scala:27:9] wire [63:0] _anonOut_a_bits_data_T_3; // @[WidthWidget.scala:73:12] assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[WidthWidget.scala:27:9] wire corrupt_out; // @[WidthWidget.scala:47:36] assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[WidthWidget.scala:27:9] assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[WidthWidget.scala:27:9] wire _hasData_opdata_T = anonIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire hasData = ~_hasData_opdata_T; // @[Edges.scala:92:{28,37}] wire [17:0] _limit_T = 18'h7 << anonIn_a_bits_size; // @[package.scala:243:71] wire [2:0] _limit_T_1 = _limit_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _limit_T_2 = ~_limit_T_1; // @[package.scala:243:{46,76}] wire [2:0] limit = _limit_T_2; // @[package.scala:243:46] reg [2:0] count; // @[WidthWidget.scala:40:27] wire [2:0] _enable_T = count; // @[WidthWidget.scala:40:27, :43:56] wire first = count == 3'h0; // @[WidthWidget.scala:40:27, :41:26] wire _last_T = count == limit; // @[WidthWidget.scala:38:47, :40:27, :42:26] wire _last_T_1 = ~hasData; // @[WidthWidget.scala:42:39] wire last = _last_T | _last_T_1; // @[WidthWidget.scala:42:{26,36,39}] wire [2:0] _enable_T_1 = _enable_T & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_2 = |_enable_T_1; // @[WidthWidget.scala:43:{63,72}] wire enable_0 = ~_enable_T_2; // @[WidthWidget.scala:43:{47,72}] wire [2:0] _enable_T_3 = {count[2:1], ~(count[0])}; // @[WidthWidget.scala:40:27, :43:56] wire [2:0] _enable_T_4 = _enable_T_3 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_5 = |_enable_T_4; // @[WidthWidget.scala:43:{63,72}] wire enable_1 = ~_enable_T_5; // @[WidthWidget.scala:43:{47,72}] wire [2:0] _enable_T_6 = {count[2], count[1:0] ^ 2'h2}; // @[WidthWidget.scala:40:27, :43:56] wire [2:0] _enable_T_7 = _enable_T_6 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_8 = |_enable_T_7; // @[WidthWidget.scala:43:{63,72}] wire enable_2 = ~_enable_T_8; // @[WidthWidget.scala:43:{47,72}] wire [2:0] _enable_T_9 = {count[2], ~(count[1:0])}; // @[WidthWidget.scala:40:27, :43:56] wire [2:0] _enable_T_10 = _enable_T_9 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_11 = |_enable_T_10; // @[WidthWidget.scala:43:{63,72}] wire enable_3 = ~_enable_T_11; // @[WidthWidget.scala:43:{47,72}] wire [2:0] _enable_T_12 = count ^ 3'h4; // @[WidthWidget.scala:40:27, :43:56] wire [2:0] _enable_T_13 = _enable_T_12 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_14 = |_enable_T_13; // @[WidthWidget.scala:43:{63,72}] wire enable_4 = ~_enable_T_14; // @[WidthWidget.scala:43:{47,72}] wire [2:0] _enable_T_15 = count ^ 3'h5; // @[WidthWidget.scala:40:27, :43:56] wire [2:0] _enable_T_16 = _enable_T_15 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_17 = |_enable_T_16; // @[WidthWidget.scala:43:{63,72}] wire enable_5 = ~_enable_T_17; // @[WidthWidget.scala:43:{47,72}] wire [2:0] _enable_T_18 = count ^ 3'h6; // @[WidthWidget.scala:40:27, :43:56] wire [2:0] _enable_T_19 = _enable_T_18 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_20 = |_enable_T_19; // @[WidthWidget.scala:43:{63,72}] wire enable_6 = ~_enable_T_20; // @[WidthWidget.scala:43:{47,72}] wire [2:0] _enable_T_21 = ~count; // @[WidthWidget.scala:40:27, :43:56] wire [2:0] _enable_T_22 = _enable_T_21 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_23 = |_enable_T_22; // @[WidthWidget.scala:43:{63,72}] wire enable_7 = ~_enable_T_23; // @[WidthWidget.scala:43:{47,72}] reg corrupt_reg; // @[WidthWidget.scala:45:32] assign corrupt_out = corrupt_reg; // @[WidthWidget.scala:45:32, :47:36] assign anonOut_a_bits_corrupt = corrupt_out; // @[WidthWidget.scala:47:36] wire _T = anonIn_a_ready & anonIn_a_valid; // @[Decoupled.scala:51:35] wire _anonOut_a_bits_data_T; // @[Decoupled.scala:51:35] assign _anonOut_a_bits_data_T = _T; // @[Decoupled.scala:51:35] wire _anonOut_a_bits_mask_T_1; // @[Decoupled.scala:51:35] assign _anonOut_a_bits_mask_T_1 = _T; // @[Decoupled.scala:51:35] wire _repeat_sel_sel_T; // @[Decoupled.scala:51:35] assign _repeat_sel_sel_T = _T; // @[Decoupled.scala:51:35] wire [3:0] _count_T = {1'h0, count} + 4'h1; // @[WidthWidget.scala:40:27, :50:24] wire [2:0] _count_T_1 = _count_T[2:0]; // @[WidthWidget.scala:50:24] wire _anonIn_a_ready_T = ~last; // @[WidthWidget.scala:42:36, :76:32] assign _anonIn_a_ready_T_1 = anonOut_a_ready | _anonIn_a_ready_T; // @[WidthWidget.scala:76:{29,32}] assign anonIn_a_ready = _anonIn_a_ready_T_1; // @[WidthWidget.scala:76:29] assign _anonOut_a_valid_T = anonIn_a_valid & last; // @[WidthWidget.scala:42:36, :77:29] assign anonOut_a_valid = _anonOut_a_valid_T; // @[WidthWidget.scala:77:29] reg anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41] wire _anonOut_a_bits_data_masked_enable_T = ~anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_data_masked_enable_0 = enable_0 | _anonOut_a_bits_data_masked_enable_T; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_data_masked_enable_T_1 = ~anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_data_masked_enable_1 = enable_1 | _anonOut_a_bits_data_masked_enable_T_1; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_data_masked_enable_T_2 = ~anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_data_masked_enable_2 = enable_2 | _anonOut_a_bits_data_masked_enable_T_2; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_data_masked_enable_T_3 = ~anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_data_masked_enable_3 = enable_3 | _anonOut_a_bits_data_masked_enable_T_3; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_data_masked_enable_T_4 = ~anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_data_masked_enable_4 = enable_4 | _anonOut_a_bits_data_masked_enable_T_4; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_data_masked_enable_T_5 = ~anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_data_masked_enable_5 = enable_5 | _anonOut_a_bits_data_masked_enable_T_5; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_data_masked_enable_T_6 = ~anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_data_masked_enable_6 = enable_6 | _anonOut_a_bits_data_masked_enable_T_6; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_data_masked_enable_T_7 = ~anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_data_masked_enable_7 = enable_7 | _anonOut_a_bits_data_masked_enable_T_7; // @[WidthWidget.scala:43:47, :63:{42,45}] reg [7:0] anonOut_a_bits_data_rdata_0; // @[WidthWidget.scala:66:24] reg [7:0] anonOut_a_bits_data_rdata_1; // @[WidthWidget.scala:66:24] reg [7:0] anonOut_a_bits_data_rdata_2; // @[WidthWidget.scala:66:24] reg [7:0] anonOut_a_bits_data_rdata_3; // @[WidthWidget.scala:66:24] reg [7:0] anonOut_a_bits_data_rdata_4; // @[WidthWidget.scala:66:24] reg [7:0] anonOut_a_bits_data_rdata_5; // @[WidthWidget.scala:66:24] reg [7:0] anonOut_a_bits_data_rdata_6; // @[WidthWidget.scala:66:24] wire [7:0] anonOut_a_bits_data_mdata_0 = anonOut_a_bits_data_masked_enable_0 ? anonOut_a_bits_data_odata_0 : anonOut_a_bits_data_rdata_0; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [7:0] anonOut_a_bits_data_mdata_1 = anonOut_a_bits_data_masked_enable_1 ? anonOut_a_bits_data_odata_1 : anonOut_a_bits_data_rdata_1; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [7:0] anonOut_a_bits_data_mdata_2 = anonOut_a_bits_data_masked_enable_2 ? anonOut_a_bits_data_odata_2 : anonOut_a_bits_data_rdata_2; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [7:0] anonOut_a_bits_data_mdata_3 = anonOut_a_bits_data_masked_enable_3 ? anonOut_a_bits_data_odata_3 : anonOut_a_bits_data_rdata_3; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [7:0] anonOut_a_bits_data_mdata_4 = anonOut_a_bits_data_masked_enable_4 ? anonOut_a_bits_data_odata_4 : anonOut_a_bits_data_rdata_4; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [7:0] anonOut_a_bits_data_mdata_5 = anonOut_a_bits_data_masked_enable_5 ? anonOut_a_bits_data_odata_5 : anonOut_a_bits_data_rdata_5; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [7:0] anonOut_a_bits_data_mdata_6 = anonOut_a_bits_data_masked_enable_6 ? anonOut_a_bits_data_odata_6 : anonOut_a_bits_data_rdata_6; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [7:0] anonOut_a_bits_data_mdata_7 = anonOut_a_bits_data_masked_enable_7 ? anonOut_a_bits_data_odata_7 : anonIn_a_bits_data; // @[WidthWidget.scala:63:42, :65:47, :68:88] wire _anonOut_a_bits_data_T_1 = ~last; // @[WidthWidget.scala:42:36, :69:26, :76:32] wire _anonOut_a_bits_data_T_2 = _anonOut_a_bits_data_T & _anonOut_a_bits_data_T_1; // @[Decoupled.scala:51:35] wire [15:0] anonOut_a_bits_data_lo_lo = {anonOut_a_bits_data_mdata_1, anonOut_a_bits_data_mdata_0}; // @[WidthWidget.scala:68:88, :73:12] wire [15:0] anonOut_a_bits_data_lo_hi = {anonOut_a_bits_data_mdata_3, anonOut_a_bits_data_mdata_2}; // @[WidthWidget.scala:68:88, :73:12] wire [31:0] anonOut_a_bits_data_lo = {anonOut_a_bits_data_lo_hi, anonOut_a_bits_data_lo_lo}; // @[WidthWidget.scala:73:12] wire [15:0] anonOut_a_bits_data_hi_lo = {anonOut_a_bits_data_mdata_5, anonOut_a_bits_data_mdata_4}; // @[WidthWidget.scala:68:88, :73:12] wire [15:0] anonOut_a_bits_data_hi_hi = {anonOut_a_bits_data_mdata_7, anonOut_a_bits_data_mdata_6}; // @[WidthWidget.scala:68:88, :73:12] wire [31:0] anonOut_a_bits_data_hi = {anonOut_a_bits_data_hi_hi, anonOut_a_bits_data_hi_lo}; // @[WidthWidget.scala:73:12] assign _anonOut_a_bits_data_T_3 = {anonOut_a_bits_data_hi, anonOut_a_bits_data_lo}; // @[WidthWidget.scala:73:12] assign anonOut_a_bits_data = _anonOut_a_bits_data_T_3; // @[WidthWidget.scala:73:12] wire [1:0] anonOut_a_bits_mask_sizeOH_shiftAmount = _anonOut_a_bits_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _anonOut_a_bits_mask_sizeOH_T_1 = 4'h1 << anonOut_a_bits_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _anonOut_a_bits_mask_sizeOH_T_2 = _anonOut_a_bits_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] anonOut_a_bits_mask_sizeOH = {_anonOut_a_bits_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire anonOut_a_bits_mask_sub_sub_sub_0_1 = anonOut_a_bits_size > 4'h2; // @[Misc.scala:206:21] wire anonOut_a_bits_mask_sub_sub_size = anonOut_a_bits_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire anonOut_a_bits_mask_sub_sub_bit = anonOut_a_bits_address[2]; // @[Misc.scala:210:26] wire anonOut_a_bits_mask_sub_sub_1_2 = anonOut_a_bits_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire anonOut_a_bits_mask_sub_sub_nbit = ~anonOut_a_bits_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire anonOut_a_bits_mask_sub_sub_0_2 = anonOut_a_bits_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _anonOut_a_bits_mask_sub_sub_acc_T = anonOut_a_bits_mask_sub_sub_size & anonOut_a_bits_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_sub_sub_0_1 = anonOut_a_bits_mask_sub_sub_sub_0_1 | _anonOut_a_bits_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _anonOut_a_bits_mask_sub_sub_acc_T_1 = anonOut_a_bits_mask_sub_sub_size & anonOut_a_bits_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_sub_sub_1_1 = anonOut_a_bits_mask_sub_sub_sub_0_1 | _anonOut_a_bits_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire anonOut_a_bits_mask_sub_size = anonOut_a_bits_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire anonOut_a_bits_mask_sub_bit = anonOut_a_bits_address[1]; // @[Misc.scala:210:26] wire anonOut_a_bits_mask_sub_nbit = ~anonOut_a_bits_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire anonOut_a_bits_mask_sub_0_2 = anonOut_a_bits_mask_sub_sub_0_2 & anonOut_a_bits_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _anonOut_a_bits_mask_sub_acc_T = anonOut_a_bits_mask_sub_size & anonOut_a_bits_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_sub_0_1 = anonOut_a_bits_mask_sub_sub_0_1 | _anonOut_a_bits_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_sub_1_2 = anonOut_a_bits_mask_sub_sub_0_2 & anonOut_a_bits_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _anonOut_a_bits_mask_sub_acc_T_1 = anonOut_a_bits_mask_sub_size & anonOut_a_bits_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_sub_1_1 = anonOut_a_bits_mask_sub_sub_0_1 | _anonOut_a_bits_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_sub_2_2 = anonOut_a_bits_mask_sub_sub_1_2 & anonOut_a_bits_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _anonOut_a_bits_mask_sub_acc_T_2 = anonOut_a_bits_mask_sub_size & anonOut_a_bits_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_sub_2_1 = anonOut_a_bits_mask_sub_sub_1_1 | _anonOut_a_bits_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_sub_3_2 = anonOut_a_bits_mask_sub_sub_1_2 & anonOut_a_bits_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _anonOut_a_bits_mask_sub_acc_T_3 = anonOut_a_bits_mask_sub_size & anonOut_a_bits_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_sub_3_1 = anonOut_a_bits_mask_sub_sub_1_1 | _anonOut_a_bits_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_size = anonOut_a_bits_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire anonOut_a_bits_mask_bit = anonOut_a_bits_address[0]; // @[Misc.scala:210:26] wire anonOut_a_bits_mask_nbit = ~anonOut_a_bits_mask_bit; // @[Misc.scala:210:26, :211:20] wire anonOut_a_bits_mask_eq = anonOut_a_bits_mask_sub_0_2 & anonOut_a_bits_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _anonOut_a_bits_mask_acc_T = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_acc = anonOut_a_bits_mask_sub_0_1 | _anonOut_a_bits_mask_acc_T; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_eq_1 = anonOut_a_bits_mask_sub_0_2 & anonOut_a_bits_mask_bit; // @[Misc.scala:210:26, :214:27] wire _anonOut_a_bits_mask_acc_T_1 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_acc_1 = anonOut_a_bits_mask_sub_0_1 | _anonOut_a_bits_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_eq_2 = anonOut_a_bits_mask_sub_1_2 & anonOut_a_bits_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _anonOut_a_bits_mask_acc_T_2 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_acc_2 = anonOut_a_bits_mask_sub_1_1 | _anonOut_a_bits_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_eq_3 = anonOut_a_bits_mask_sub_1_2 & anonOut_a_bits_mask_bit; // @[Misc.scala:210:26, :214:27] wire _anonOut_a_bits_mask_acc_T_3 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_acc_3 = anonOut_a_bits_mask_sub_1_1 | _anonOut_a_bits_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_eq_4 = anonOut_a_bits_mask_sub_2_2 & anonOut_a_bits_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _anonOut_a_bits_mask_acc_T_4 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_acc_4 = anonOut_a_bits_mask_sub_2_1 | _anonOut_a_bits_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_eq_5 = anonOut_a_bits_mask_sub_2_2 & anonOut_a_bits_mask_bit; // @[Misc.scala:210:26, :214:27] wire _anonOut_a_bits_mask_acc_T_5 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_acc_5 = anonOut_a_bits_mask_sub_2_1 | _anonOut_a_bits_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_eq_6 = anonOut_a_bits_mask_sub_3_2 & anonOut_a_bits_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _anonOut_a_bits_mask_acc_T_6 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_acc_6 = anonOut_a_bits_mask_sub_3_1 | _anonOut_a_bits_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_eq_7 = anonOut_a_bits_mask_sub_3_2 & anonOut_a_bits_mask_bit; // @[Misc.scala:210:26, :214:27] wire _anonOut_a_bits_mask_acc_T_7 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_acc_7 = anonOut_a_bits_mask_sub_3_1 | _anonOut_a_bits_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] anonOut_a_bits_mask_lo_lo = {anonOut_a_bits_mask_acc_1, anonOut_a_bits_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] anonOut_a_bits_mask_lo_hi = {anonOut_a_bits_mask_acc_3, anonOut_a_bits_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] anonOut_a_bits_mask_lo = {anonOut_a_bits_mask_lo_hi, anonOut_a_bits_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] anonOut_a_bits_mask_hi_lo = {anonOut_a_bits_mask_acc_5, anonOut_a_bits_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] anonOut_a_bits_mask_hi_hi = {anonOut_a_bits_mask_acc_7, anonOut_a_bits_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] anonOut_a_bits_mask_hi = {anonOut_a_bits_mask_hi_hi, anonOut_a_bits_mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] _anonOut_a_bits_mask_T = {anonOut_a_bits_mask_hi, anonOut_a_bits_mask_lo}; // @[Misc.scala:222:10] reg anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41] wire _anonOut_a_bits_mask_masked_enable_T = ~anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_mask_masked_enable_0 = enable_0 | _anonOut_a_bits_mask_masked_enable_T; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_mask_masked_enable_T_1 = ~anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_mask_masked_enable_1 = enable_1 | _anonOut_a_bits_mask_masked_enable_T_1; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_mask_masked_enable_T_2 = ~anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_mask_masked_enable_2 = enable_2 | _anonOut_a_bits_mask_masked_enable_T_2; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_mask_masked_enable_T_3 = ~anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_mask_masked_enable_3 = enable_3 | _anonOut_a_bits_mask_masked_enable_T_3; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_mask_masked_enable_T_4 = ~anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_mask_masked_enable_4 = enable_4 | _anonOut_a_bits_mask_masked_enable_T_4; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_mask_masked_enable_T_5 = ~anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_mask_masked_enable_5 = enable_5 | _anonOut_a_bits_mask_masked_enable_T_5; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_mask_masked_enable_T_6 = ~anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_mask_masked_enable_6 = enable_6 | _anonOut_a_bits_mask_masked_enable_T_6; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_mask_masked_enable_T_7 = ~anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_mask_masked_enable_7 = enable_7 | _anonOut_a_bits_mask_masked_enable_T_7; // @[WidthWidget.scala:43:47, :63:{42,45}] reg anonOut_a_bits_mask_rdata_0; // @[WidthWidget.scala:66:24] reg anonOut_a_bits_mask_rdata_1; // @[WidthWidget.scala:66:24] reg anonOut_a_bits_mask_rdata_2; // @[WidthWidget.scala:66:24] reg anonOut_a_bits_mask_rdata_3; // @[WidthWidget.scala:66:24] reg anonOut_a_bits_mask_rdata_4; // @[WidthWidget.scala:66:24] reg anonOut_a_bits_mask_rdata_5; // @[WidthWidget.scala:66:24] reg anonOut_a_bits_mask_rdata_6; // @[WidthWidget.scala:66:24] wire anonOut_a_bits_mask_mdata_0 = anonOut_a_bits_mask_masked_enable_0 | anonOut_a_bits_mask_rdata_0; // @[WidthWidget.scala:63:42, :66:24, :68:88] wire anonOut_a_bits_mask_mdata_1 = anonOut_a_bits_mask_masked_enable_1 | anonOut_a_bits_mask_rdata_1; // @[WidthWidget.scala:63:42, :66:24, :68:88] wire anonOut_a_bits_mask_mdata_2 = anonOut_a_bits_mask_masked_enable_2 | anonOut_a_bits_mask_rdata_2; // @[WidthWidget.scala:63:42, :66:24, :68:88] wire anonOut_a_bits_mask_mdata_3 = anonOut_a_bits_mask_masked_enable_3 | anonOut_a_bits_mask_rdata_3; // @[WidthWidget.scala:63:42, :66:24, :68:88] wire anonOut_a_bits_mask_mdata_4 = anonOut_a_bits_mask_masked_enable_4 | anonOut_a_bits_mask_rdata_4; // @[WidthWidget.scala:63:42, :66:24, :68:88] wire anonOut_a_bits_mask_mdata_5 = anonOut_a_bits_mask_masked_enable_5 | anonOut_a_bits_mask_rdata_5; // @[WidthWidget.scala:63:42, :66:24, :68:88] wire anonOut_a_bits_mask_mdata_6 = anonOut_a_bits_mask_masked_enable_6 | anonOut_a_bits_mask_rdata_6; // @[WidthWidget.scala:63:42, :66:24, :68:88] wire _anonOut_a_bits_mask_T_2 = ~last; // @[WidthWidget.scala:42:36, :69:26, :76:32] wire _anonOut_a_bits_mask_T_3 = _anonOut_a_bits_mask_T_1 & _anonOut_a_bits_mask_T_2; // @[Decoupled.scala:51:35] wire [1:0] anonOut_a_bits_mask_lo_lo_1 = {anonOut_a_bits_mask_mdata_1, anonOut_a_bits_mask_mdata_0}; // @[WidthWidget.scala:68:88, :73:12] wire [1:0] anonOut_a_bits_mask_lo_hi_1 = {anonOut_a_bits_mask_mdata_3, anonOut_a_bits_mask_mdata_2}; // @[WidthWidget.scala:68:88, :73:12] wire [3:0] anonOut_a_bits_mask_lo_1 = {anonOut_a_bits_mask_lo_hi_1, anonOut_a_bits_mask_lo_lo_1}; // @[WidthWidget.scala:73:12] wire [1:0] anonOut_a_bits_mask_hi_lo_1 = {anonOut_a_bits_mask_mdata_5, anonOut_a_bits_mask_mdata_4}; // @[WidthWidget.scala:68:88, :73:12] wire [1:0] anonOut_a_bits_mask_hi_hi_1 = {1'h1, anonOut_a_bits_mask_mdata_6}; // @[WidthWidget.scala:68:88, :73:12] wire [3:0] anonOut_a_bits_mask_hi_1 = {anonOut_a_bits_mask_hi_hi_1, anonOut_a_bits_mask_hi_lo_1}; // @[WidthWidget.scala:73:12] wire [7:0] _anonOut_a_bits_mask_T_4 = {anonOut_a_bits_mask_hi_1, anonOut_a_bits_mask_lo_1}; // @[WidthWidget.scala:73:12] wire [7:0] _anonOut_a_bits_mask_T_6 = hasData ? _anonOut_a_bits_mask_T_4 : 8'hFF; // @[WidthWidget.scala:73:12, :85:93] assign _anonOut_a_bits_mask_T_7 = _anonOut_a_bits_mask_T & _anonOut_a_bits_mask_T_6; // @[Misc.scala:222:10] assign anonOut_a_bits_mask = _anonOut_a_bits_mask_T_7; // @[WidthWidget.scala:85:88] wire _repeat_T_1; // @[WidthWidget.scala:148:7] wire repeat_0; // @[WidthWidget.scala:159:26] assign anonIn_d_valid = cated_valid; // @[WidthWidget.scala:161:25] assign anonIn_d_bits_opcode = cated_bits_opcode; // @[WidthWidget.scala:161:25] assign anonIn_d_bits_param = cated_bits_param; // @[WidthWidget.scala:161:25] assign anonIn_d_bits_size = cated_bits_size; // @[WidthWidget.scala:161:25] assign anonIn_d_bits_sink = cated_bits_sink; // @[WidthWidget.scala:161:25] assign anonIn_d_bits_denied = cated_bits_denied; // @[WidthWidget.scala:161:25] wire [63:0] _cated_bits_data_T_2; // @[WidthWidget.scala:163:39] assign anonIn_d_bits_corrupt = cated_bits_corrupt; // @[WidthWidget.scala:161:25] wire [63:0] cated_bits_data; // @[WidthWidget.scala:161:25] wire [55:0] _cated_bits_data_T = _repeated_repeater_io_deq_bits_data[63:8]; // @[Repeater.scala:36:26] wire [7:0] _cated_bits_data_T_1 = anonOut_d_bits_data[7:0]; // @[WidthWidget.scala:165:31] assign _cated_bits_data_T_2 = {_cated_bits_data_T, _cated_bits_data_T_1}; // @[WidthWidget.scala:163:39, :164:37, :165:31] assign cated_bits_data = _cated_bits_data_T_2; // @[WidthWidget.scala:161:25, :163:39] wire repeat_hasData = cated_bits_opcode[0]; // @[WidthWidget.scala:161:25] wire [17:0] _repeat_limit_T = 18'h7 << cated_bits_size; // @[package.scala:243:71] wire [2:0] _repeat_limit_T_1 = _repeat_limit_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _repeat_limit_T_2 = ~_repeat_limit_T_1; // @[package.scala:243:{46,76}] wire [2:0] repeat_limit = _repeat_limit_T_2; // @[package.scala:243:46] reg [2:0] repeat_count; // @[WidthWidget.scala:105:26] wire repeat_first = repeat_count == 3'h0; // @[WidthWidget.scala:105:26, :106:25] wire _repeat_last_T = repeat_count == repeat_limit; // @[WidthWidget.scala:103:47, :105:26, :107:25] wire _repeat_last_T_1 = ~repeat_hasData; // @[WidthWidget.scala:107:38] wire repeat_last = _repeat_last_T | _repeat_last_T_1; // @[WidthWidget.scala:107:{25,35,38}] wire _repeat_T = anonIn_d_ready & anonIn_d_valid; // @[Decoupled.scala:51:35] wire [3:0] _repeat_count_T = {1'h0, repeat_count} + 4'h1; // @[WidthWidget.scala:105:26, :110:24] wire [2:0] _repeat_count_T_1 = _repeat_count_T[2:0]; // @[WidthWidget.scala:110:24] reg [2:0] repeat_sel_sel_sources_0; // @[WidthWidget.scala:187:27] wire [2:0] repeat_sel_sel_a_sel = anonIn_a_bits_address[2:0]; // @[WidthWidget.scala:188:38] reg [2:0] repeat_sel_hold_r; // @[WidthWidget.scala:121:47] wire [2:0] repeat_sel_hold = repeat_first ? repeat_sel_sel_sources_0 : repeat_sel_hold_r; // @[WidthWidget.scala:106:25, :121:{25,47}, :187:27] wire [2:0] _repeat_sel_T = ~repeat_limit; // @[WidthWidget.scala:103:47, :122:18] wire [2:0] repeat_sel = repeat_sel_hold & _repeat_sel_T; // @[WidthWidget.scala:121:25, :122:{16,18}] wire [2:0] repeat_index = repeat_sel | repeat_count; // @[WidthWidget.scala:105:26, :122:16, :126:24] wire [7:0] _repeat_anonIn_d_bits_data_mux_T = cated_bits_data[7:0]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonIn_d_bits_data_mux_0 = _repeat_anonIn_d_bits_data_mux_T; // @[WidthWidget.scala:128:{43,55}] wire [7:0] _repeat_anonIn_d_bits_data_mux_T_1 = cated_bits_data[15:8]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonIn_d_bits_data_mux_1 = _repeat_anonIn_d_bits_data_mux_T_1; // @[WidthWidget.scala:128:{43,55}] wire [7:0] _repeat_anonIn_d_bits_data_mux_T_2 = cated_bits_data[23:16]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonIn_d_bits_data_mux_2 = _repeat_anonIn_d_bits_data_mux_T_2; // @[WidthWidget.scala:128:{43,55}] wire [7:0] _repeat_anonIn_d_bits_data_mux_T_3 = cated_bits_data[31:24]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonIn_d_bits_data_mux_3 = _repeat_anonIn_d_bits_data_mux_T_3; // @[WidthWidget.scala:128:{43,55}] wire [7:0] _repeat_anonIn_d_bits_data_mux_T_4 = cated_bits_data[39:32]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonIn_d_bits_data_mux_4 = _repeat_anonIn_d_bits_data_mux_T_4; // @[WidthWidget.scala:128:{43,55}] wire [7:0] _repeat_anonIn_d_bits_data_mux_T_5 = cated_bits_data[47:40]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonIn_d_bits_data_mux_5 = _repeat_anonIn_d_bits_data_mux_T_5; // @[WidthWidget.scala:128:{43,55}] wire [7:0] _repeat_anonIn_d_bits_data_mux_T_6 = cated_bits_data[55:48]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonIn_d_bits_data_mux_6 = _repeat_anonIn_d_bits_data_mux_T_6; // @[WidthWidget.scala:128:{43,55}] wire [7:0] _repeat_anonIn_d_bits_data_mux_T_7 = cated_bits_data[63:56]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonIn_d_bits_data_mux_7 = _repeat_anonIn_d_bits_data_mux_T_7; // @[WidthWidget.scala:128:{43,55}] wire [7:0][7:0] _GEN = {{repeat_anonIn_d_bits_data_mux_7}, {repeat_anonIn_d_bits_data_mux_6}, {repeat_anonIn_d_bits_data_mux_5}, {repeat_anonIn_d_bits_data_mux_4}, {repeat_anonIn_d_bits_data_mux_3}, {repeat_anonIn_d_bits_data_mux_2}, {repeat_anonIn_d_bits_data_mux_1}, {repeat_anonIn_d_bits_data_mux_0}}; // @[WidthWidget.scala:128:43, :137:30] assign anonIn_d_bits_data = _GEN[repeat_index]; // @[WidthWidget.scala:126:24, :137:30] assign _repeat_T_1 = ~repeat_last; // @[WidthWidget.scala:107:35, :148:7] assign repeat_0 = _repeat_T_1; // @[WidthWidget.scala:148:7, :159:26] always @(posedge clock) begin // @[WidthWidget.scala:27:9] if (reset) begin // @[WidthWidget.scala:27:9] count <= 3'h0; // @[WidthWidget.scala:40:27] corrupt_reg <= 1'h0; // @[WidthWidget.scala:45:32] anonOut_a_bits_data_rdata_written_once <= 1'h0; // @[WidthWidget.scala:62:41] anonOut_a_bits_mask_rdata_written_once <= 1'h0; // @[WidthWidget.scala:62:41] repeat_count <= 3'h0; // @[WidthWidget.scala:105:26] end else begin // @[WidthWidget.scala:27:9] if (_T) begin // @[Decoupled.scala:51:35] count <= last ? 3'h0 : _count_T_1; // @[WidthWidget.scala:40:27, :42:36, :50:{15,24}, :52:21, :53:17] corrupt_reg <= ~last & corrupt_out; // @[WidthWidget.scala:42:36, :45:32, :47:36, :51:21, :52:21, :54:23] end anonOut_a_bits_data_rdata_written_once <= _anonOut_a_bits_data_T_2 | anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :69:{23,33}, :70:30] anonOut_a_bits_mask_rdata_written_once <= _anonOut_a_bits_mask_T_3 | anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41, :69:{23,33}, :70:30] if (_repeat_T) // @[Decoupled.scala:51:35] repeat_count <= repeat_last ? 3'h0 : _repeat_count_T_1; // @[WidthWidget.scala:105:26, :107:35, :110:{15,24}, :111:{21,29}] end if (_anonOut_a_bits_data_T_2) begin // @[WidthWidget.scala:69:23] anonOut_a_bits_data_rdata_0 <= anonOut_a_bits_data_mdata_0; // @[WidthWidget.scala:66:24, :68:88] anonOut_a_bits_data_rdata_1 <= anonOut_a_bits_data_mdata_1; // @[WidthWidget.scala:66:24, :68:88] anonOut_a_bits_data_rdata_2 <= anonOut_a_bits_data_mdata_2; // @[WidthWidget.scala:66:24, :68:88] anonOut_a_bits_data_rdata_3 <= anonOut_a_bits_data_mdata_3; // @[WidthWidget.scala:66:24, :68:88] anonOut_a_bits_data_rdata_4 <= anonOut_a_bits_data_mdata_4; // @[WidthWidget.scala:66:24, :68:88] anonOut_a_bits_data_rdata_5 <= anonOut_a_bits_data_mdata_5; // @[WidthWidget.scala:66:24, :68:88] anonOut_a_bits_data_rdata_6 <= anonOut_a_bits_data_mdata_6; // @[WidthWidget.scala:66:24, :68:88] end if (_anonOut_a_bits_mask_T_3) begin // @[WidthWidget.scala:69:23] anonOut_a_bits_mask_rdata_0 <= anonOut_a_bits_mask_mdata_0; // @[WidthWidget.scala:66:24, :68:88] anonOut_a_bits_mask_rdata_1 <= anonOut_a_bits_mask_mdata_1; // @[WidthWidget.scala:66:24, :68:88] anonOut_a_bits_mask_rdata_2 <= anonOut_a_bits_mask_mdata_2; // @[WidthWidget.scala:66:24, :68:88] anonOut_a_bits_mask_rdata_3 <= anonOut_a_bits_mask_mdata_3; // @[WidthWidget.scala:66:24, :68:88] anonOut_a_bits_mask_rdata_4 <= anonOut_a_bits_mask_mdata_4; // @[WidthWidget.scala:66:24, :68:88] anonOut_a_bits_mask_rdata_5 <= anonOut_a_bits_mask_mdata_5; // @[WidthWidget.scala:66:24, :68:88] anonOut_a_bits_mask_rdata_6 <= anonOut_a_bits_mask_mdata_6; // @[WidthWidget.scala:66:24, :68:88] end if (_repeat_sel_sel_T) // @[Decoupled.scala:51:35] repeat_sel_sel_sources_0 <= repeat_sel_sel_a_sel; // @[WidthWidget.scala:187:27, :188:38] if (repeat_first) // @[WidthWidget.scala:106:25] repeat_sel_hold_r <= repeat_sel_sel_sources_0; // @[WidthWidget.scala:121:47, :187:27] always @(posedge) TLMonitor_12 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (anonIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (anonIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (anonIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_size (anonIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_address (anonIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_data (anonIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_d_ready (anonIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (anonIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (anonIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (anonIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (anonIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (anonIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (anonIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (anonIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (anonIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Repeater_TLBundleD_a32d64s1k1z4u repeated_repeater ( // @[Repeater.scala:36:26] .clock (clock), .reset (reset), .io_repeat (repeat_0), // @[WidthWidget.scala:159:26] .io_enq_ready (anonOut_d_ready), .io_enq_valid (anonOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (anonOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (anonOut_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (anonOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_sink (anonOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (anonOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (anonOut_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (anonOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (cated_ready), // @[WidthWidget.scala:161:25] .io_deq_valid (cated_valid), .io_deq_bits_opcode (cated_bits_opcode), .io_deq_bits_param (cated_bits_param), .io_deq_bits_size (cated_bits_size), .io_deq_bits_sink (cated_bits_sink), .io_deq_bits_denied (cated_bits_denied), .io_deq_bits_data (_repeated_repeater_io_deq_bits_data), .io_deq_bits_corrupt (cated_bits_corrupt) ); // @[Repeater.scala:36:26] assign auto_anon_in_a_ready = auto_anon_in_a_ready_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_valid = auto_anon_in_d_valid_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_opcode = auto_anon_in_d_bits_opcode_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_param = auto_anon_in_d_bits_param_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_size = auto_anon_in_d_bits_size_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_sink = auto_anon_in_d_bits_sink_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_denied = auto_anon_in_d_bits_denied_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_data = auto_anon_in_d_bits_data_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_corrupt = auto_anon_in_d_bits_corrupt_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_valid = auto_anon_out_a_valid_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_opcode = auto_anon_out_a_bits_opcode_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_size = auto_anon_out_a_bits_size_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_address = auto_anon_out_a_bits_address_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_mask = auto_anon_out_a_bits_mask_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_data = auto_anon_out_a_bits_data_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_corrupt = auto_anon_out_a_bits_corrupt_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_d_ready = auto_anon_out_d_ready_0; // @[WidthWidget.scala:27:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File MulAddRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle { //*** ENCODE SOME OF THESE CASES IN FEWER BITS?: val isSigNaNAny = Bool() val isNaNAOrB = Bool() val isInfA = Bool() val isZeroA = Bool() val isInfB = Bool() val isZeroB = Bool() val signProd = Bool() val isNaNC = Bool() val isInfC = Bool() val isZeroC = Bool() val sExpSum = SInt((expWidth + 2).W) val doSubMags = Bool() val CIsDominant = Bool() val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W) val highAlignedSigC = UInt((sigWidth + 2).W) val bit0AlignedSigC = UInt(1.W) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val mulAddA = Output(UInt(sigWidth.W)) val mulAddB = Output(UInt(sigWidth.W)) val mulAddC = Output(UInt((sigWidth * 2).W)) val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ //*** POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN //*** UNSHIFTED C AND PRODUCT): val sigSumWidth = sigWidth * 3 + 3 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a) val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b) val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c) val signProd = rawA.sign ^ rawB.sign ^ io.op(1) //*** REVIEW THE BIAS FOR 'sExpAlignedProd': val sExpAlignedProd = rawA.sExp +& rawB.sExp + (-(BigInt(1)<<expWidth) + sigWidth + 3).S val doSubMags = signProd ^ rawC.sign ^ io.op(0) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sNatCAlignDist = sExpAlignedProd - rawC.sExp val posNatCAlignDist = sNatCAlignDist(expWidth + 1, 0) val isMinCAlign = rawA.isZero || rawB.isZero || (sNatCAlignDist < 0.S) val CIsDominant = ! rawC.isZero && (isMinCAlign || (posNatCAlignDist <= sigWidth.U)) val CAlignDist = Mux(isMinCAlign, 0.U, Mux(posNatCAlignDist < (sigSumWidth - 1).U, posNatCAlignDist(log2Ceil(sigSumWidth) - 1, 0), (sigSumWidth - 1).U ) ) val mainAlignedSigC = (Mux(doSubMags, ~rawC.sig, rawC.sig) ## Fill(sigSumWidth - sigWidth + 2, doSubMags)).asSInt>>CAlignDist val reduced4CExtra = (orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) & lowMask( CAlignDist>>2, //*** NOT NEEDED?: // (sigSumWidth + 2)>>2, (sigSumWidth - 1)>>2, (sigSumWidth - sigWidth - 1)>>2 ) ).orR val alignedSigC = Cat(mainAlignedSigC>>3, Mux(doSubMags, mainAlignedSigC(2, 0).andR && ! reduced4CExtra, mainAlignedSigC(2, 0).orR || reduced4CExtra ) ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ io.mulAddA := rawA.sig io.mulAddB := rawB.sig io.mulAddC := alignedSigC(sigWidth * 2, 1) io.toPostMul.isSigNaNAny := isSigNaNRawFloat(rawA) || isSigNaNRawFloat(rawB) || isSigNaNRawFloat(rawC) io.toPostMul.isNaNAOrB := rawA.isNaN || rawB.isNaN io.toPostMul.isInfA := rawA.isInf io.toPostMul.isZeroA := rawA.isZero io.toPostMul.isInfB := rawB.isInf io.toPostMul.isZeroB := rawB.isZero io.toPostMul.signProd := signProd io.toPostMul.isNaNC := rawC.isNaN io.toPostMul.isInfC := rawC.isInf io.toPostMul.isZeroC := rawC.isZero io.toPostMul.sExpSum := Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S) io.toPostMul.doSubMags := doSubMags io.toPostMul.CIsDominant := CIsDominant io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0) io.toPostMul.highAlignedSigC := alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1) io.toPostMul.bit0AlignedSigC := alignedSigC(0) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth)) val mulAddResult = Input(UInt((sigWidth * 2 + 1).W)) val roundingMode = Input(UInt(3.W)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth + 2)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigSumWidth = sigWidth * 3 + 3 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_min = (io.roundingMode === round_min) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags val sigSum = Cat(Mux(io.mulAddResult(sigWidth * 2), io.fromPreMul.highAlignedSigC + 1.U, io.fromPreMul.highAlignedSigC ), io.mulAddResult(sigWidth * 2 - 1, 0), io.fromPreMul.bit0AlignedSigC ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val CDom_sign = opSignC val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext val CDom_absSigSum = Mux(io.fromPreMul.doSubMags, ~sigSum(sigSumWidth - 1, sigWidth + 1), 0.U(1.W) ## //*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO: io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ## sigSum(sigSumWidth - 3, sigWidth + 2) ) val CDom_absSigSumExtra = Mux(io.fromPreMul.doSubMags, (~sigSum(sigWidth, 1)).orR, sigSum(sigWidth + 1, 1).orR ) val CDom_mainSig = (CDom_absSigSum<<io.fromPreMul.CDom_CAlignDist)( sigWidth * 2 + 1, sigWidth - 3) val CDom_reduced4SigExtra = (orReduceBy4(CDom_absSigSum(sigWidth - 1, 0)<<(~sigWidth & 3)) & lowMask(io.fromPreMul.CDom_CAlignDist>>2, 0, sigWidth>>2)).orR val CDom_sig = Cat(CDom_mainSig>>3, CDom_mainSig(2, 0).orR || CDom_reduced4SigExtra || CDom_absSigSumExtra ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val notCDom_signSigSum = sigSum(sigWidth * 2 + 3) val notCDom_absSigSum = Mux(notCDom_signSigSum, ~sigSum(sigWidth * 2 + 2, 0), sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags ) val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum) val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum) val notCDom_nearNormDist = notCDom_normDistReduced2<<1 val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext val notCDom_mainSig = (notCDom_absSigSum<<notCDom_nearNormDist)( sigWidth * 2 + 3, sigWidth - 1) val notCDom_reduced4SigExtra = (orReduceBy2( notCDom_reduced2AbsSigSum(sigWidth>>1, 0)<<((sigWidth>>1) & 1)) & lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2) ).orR val notCDom_sig = Cat(notCDom_mainSig>>3, notCDom_mainSig(2, 0).orR || notCDom_reduced4SigExtra ) val notCDom_completeCancellation = (notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U) val notCDom_sign = Mux(notCDom_completeCancellation, roundingMode_min, io.fromPreMul.signProd ^ notCDom_signSigSum ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val notNaN_isInfProd = io.fromPreMul.isInfA || io.fromPreMul.isInfB val notNaN_isInfOut = notNaN_isInfProd || io.fromPreMul.isInfC val notNaN_addZeros = (io.fromPreMul.isZeroA || io.fromPreMul.isZeroB) && io.fromPreMul.isZeroC io.invalidExc := io.fromPreMul.isSigNaNAny || (io.fromPreMul.isInfA && io.fromPreMul.isZeroB) || (io.fromPreMul.isZeroA && io.fromPreMul.isInfB) || (! io.fromPreMul.isNaNAOrB && (io.fromPreMul.isInfA || io.fromPreMul.isInfB) && io.fromPreMul.isInfC && io.fromPreMul.doSubMags) io.rawOut.isNaN := io.fromPreMul.isNaNAOrB || io.fromPreMul.isNaNC io.rawOut.isInf := notNaN_isInfOut //*** IMPROVE?: io.rawOut.isZero := notNaN_addZeros || (! io.fromPreMul.CIsDominant && notCDom_completeCancellation) io.rawOut.sign := (notNaN_isInfProd && io.fromPreMul.signProd) || (io.fromPreMul.isInfC && opSignC) || (notNaN_addZeros && ! roundingMode_min && io.fromPreMul.signProd && opSignC) || (notNaN_addZeros && roundingMode_min && (io.fromPreMul.signProd || opSignC)) || (! notNaN_isInfOut && ! notNaN_addZeros && Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign)) io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp) io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulAddRecFNToRaw_preMul = Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth)) val mulAddRecFNToRaw_postMul = Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth)) mulAddRecFNToRaw_preMul.io.op := io.op mulAddRecFNToRaw_preMul.io.a := io.a mulAddRecFNToRaw_preMul.io.b := io.b mulAddRecFNToRaw_preMul.io.c := io.c val mulAddResult = (mulAddRecFNToRaw_preMul.io.mulAddA * mulAddRecFNToRaw_preMul.io.mulAddB) +& mulAddRecFNToRaw_preMul.io.mulAddC mulAddRecFNToRaw_postMul.io.fromPreMul := mulAddRecFNToRaw_preMul.io.toPostMul mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0)) roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc roundRawFNToRecFN.io.infiniteExc := false.B roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut roundRawFNToRecFN.io.roundingMode := io.roundingMode roundRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags }
module MulAddRecFN_e8_s24_3( // @[MulAddRecFN.scala:300:7] input [32:0] io_a, // @[MulAddRecFN.scala:303:16] output [32:0] io_out // @[MulAddRecFN.scala:303:16] ); wire _mulAddRecFNToRaw_postMul_io_invalidExc; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[MulAddRecFN.scala:319:15] wire [9:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[MulAddRecFN.scala:319:15] wire [26:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[MulAddRecFN.scala:319:15] wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddA; // @[MulAddRecFN.scala:317:15] wire [47:0] _mulAddRecFNToRaw_preMul_io_mulAddC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; // @[MulAddRecFN.scala:317:15] wire [9:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[MulAddRecFN.scala:317:15] wire [4:0] _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; // @[MulAddRecFN.scala:317:15] wire [25:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[MulAddRecFN.scala:317:15] wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:300:7] wire io_detectTininess = 1'h1; // @[MulAddRecFN.scala:300:7, :303:16, :317:15, :319:15, :339:15] wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:300:7, :303:16, :319:15, :339:15] wire [32:0] io_c = 33'h15800000; // @[MulAddRecFN.scala:300:7, :303:16, :317:15] wire [32:0] io_b = 33'h80000000; // @[MulAddRecFN.scala:300:7, :303:16, :317:15] wire [1:0] io_op = 2'h0; // @[MulAddRecFN.scala:300:7, :303:16, :317:15] wire [32:0] io_out_0; // @[MulAddRecFN.scala:300:7] wire [4:0] io_exceptionFlags; // @[MulAddRecFN.scala:300:7] wire [47:0] _mulAddResult_T = {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddA, 23'h0}; // @[MulAddRecFN.scala:317:15, :327:45] wire [48:0] mulAddResult = {1'h0, _mulAddResult_T} + {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddC}; // @[MulAddRecFN.scala:317:15, :327:45, :328:50] MulAddRecFNToRaw_preMul_e8_s24_3 mulAddRecFNToRaw_preMul ( // @[MulAddRecFN.scala:317:15] .io_a (io_a_0), // @[MulAddRecFN.scala:300:7] .io_mulAddA (_mulAddRecFNToRaw_preMul_io_mulAddA), .io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC), .io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), .io_toPostMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB), .io_toPostMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA), .io_toPostMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA), .io_toPostMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd), .io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), .io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), .io_toPostMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist), .io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), .io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC) ); // @[MulAddRecFN.scala:317:15] MulAddRecFNToRaw_postMul_e8_s24_3 mulAddRecFNToRaw_postMul ( // @[MulAddRecFN.scala:319:15] .io_fromPreMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC), // @[MulAddRecFN.scala:317:15] .io_mulAddResult (mulAddResult), // @[MulAddRecFN.scala:328:50] .io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), .io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), .io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), .io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), .io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), .io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), .io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig) ); // @[MulAddRecFN.scala:319:15] RoundRawFNToRecFN_e8_s24_11 roundRawFNToRecFN ( // @[MulAddRecFN.scala:339:15] .io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), // @[MulAddRecFN.scala:319:15] .io_in_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), // @[MulAddRecFN.scala:319:15] .io_in_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), // @[MulAddRecFN.scala:319:15] .io_in_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), // @[MulAddRecFN.scala:319:15] .io_in_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), // @[MulAddRecFN.scala:319:15] .io_in_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), // @[MulAddRecFN.scala:319:15] .io_in_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig), // @[MulAddRecFN.scala:319:15] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags) ); // @[MulAddRecFN.scala:339:15] assign io_out = io_out_0; // @[MulAddRecFN.scala:300:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }
module AsyncResetSynchronizerShiftReg_w1_d3_i0_108( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_176 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Control.scala: package rerocc.manager import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tile._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util._ import freechips.rocketchip.prci._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.regmapper._ case object ReRoCCManagerControlBase extends Field[BigInt](0x20000) case object ReRoCCManagerControlSize extends Field[BigInt](0x1000) // Adjusts the manager ctrl address to be unique globally class ReRoCCManagerControlRemapper(mgrId: Int)(implicit p: Parameters) extends LazyModule()(p) { val node = new TLAdapterNode( clientFn = { cp => cp }, managerFn = { mp => { require(mp.managers.size == 1) val address = AddressSet(p(ReRoCCManagerControlBase) + mgrId * p(ReRoCCManagerControlSize), p(ReRoCCManagerControlSize)-1) mp.v1copy(managers = mp.managers.map(_.v1copy(address = Seq(address)))) }} ) lazy val module = new Impl class Impl extends LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out <> in } } } class ReRoCCManagerControl(mgrId: Int, beatBytes: Int)(implicit p: Parameters) extends LazyModule()(p) { val device: SimpleDevice = new SimpleDevice("rerocc-mgr", Seq("ucb-bar,rerocc-mgr")) val baseRegion = AddressSet(0, p(ReRoCCManagerControlSize)-1) // Integration will remap addresses for us val ctrlNode = TLRegisterNode( address = Seq(baseRegion), device = device, concurrency = 1, beatBytes = beatBytes) lazy val module = new Impl class Impl extends LazyModuleImp(this) { val io = IO(new Bundle { val mgr_busy = Input(Bool()) val rocc_busy = Input(Bool()) }) val regmap = ctrlNode.regmap( 0x000 -> Seq(RegField.r(8, io.mgr_busy, RegFieldDesc("mgr_busy", s"ReRoCC $mgrId Manager busy"))), 0x008 -> Seq(RegField.r(8, io.rocc_busy, RegFieldDesc("rocc_busy", s"ReRoCC $mgrId RoCC busy"))) ) } }
module ReRoCCManagerControlRemapper_1( // @[Control.scala:30:9] input clock, // @[Control.scala:30:9] input reset, // @[Control.scala:30:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [17:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [11:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Control.scala:30:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Control.scala:30:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Control.scala:30:9] wire [2:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Control.scala:30:9] wire [6:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Control.scala:30:9] wire [17:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Control.scala:30:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Control.scala:30:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Control.scala:30:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Control.scala:30:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Control.scala:30:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Control.scala:30:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Control.scala:30:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Control.scala:30:9] wire [2:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Control.scala:30:9] wire [6:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Control.scala:30:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Control.scala:30:9] wire auto_in_d_bits_sink = 1'h0; // @[Nodes.scala:27:25] wire auto_in_d_bits_denied = 1'h0; // @[Nodes.scala:27:25] wire auto_in_d_bits_corrupt = 1'h0; // @[Nodes.scala:27:25] wire auto_out_d_bits_sink = 1'h0; // @[Nodes.scala:27:25] wire auto_out_d_bits_denied = 1'h0; // @[Nodes.scala:27:25] wire auto_out_d_bits_corrupt = 1'h0; // @[Nodes.scala:27:25] wire nodeIn_d_bits_sink = 1'h0; // @[Nodes.scala:27:25] wire nodeIn_d_bits_denied = 1'h0; // @[Nodes.scala:27:25] wire nodeIn_d_bits_corrupt = 1'h0; // @[Nodes.scala:27:25] wire nodeOut_d_bits_sink = 1'h0; // @[Nodes.scala:27:25] wire nodeOut_d_bits_denied = 1'h0; // @[Nodes.scala:27:25] wire nodeOut_d_bits_corrupt = 1'h0; // @[Nodes.scala:27:25] wire [1:0] auto_in_d_bits_param = 2'h0; // @[Nodes.scala:27:25] wire [1:0] auto_out_d_bits_param = 2'h0; // @[Nodes.scala:27:25] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param = 2'h0; // @[Nodes.scala:27:25] wire [1:0] nodeOut_d_bits_param = 2'h0; // @[Nodes.scala:27:25] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Control.scala:30:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Control.scala:30:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Control.scala:30:9] wire [2:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Control.scala:30:9] wire [6:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Control.scala:30:9] wire [17:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Control.scala:30:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Control.scala:30:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Control.scala:30:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Control.scala:30:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Control.scala:30:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [6:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Control.scala:30:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [6:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [11:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Control.scala:30:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Control.scala:30:9] wire [2:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Control.scala:30:9] wire [6:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Control.scala:30:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Control.scala:30:9] wire auto_in_a_ready_0; // @[Control.scala:30:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Control.scala:30:9] wire [2:0] auto_in_d_bits_size_0; // @[Control.scala:30:9] wire [6:0] auto_in_d_bits_source_0; // @[Control.scala:30:9] wire [63:0] auto_in_d_bits_data_0; // @[Control.scala:30:9] wire auto_in_d_valid_0; // @[Control.scala:30:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Control.scala:30:9] wire [2:0] auto_out_a_bits_param_0; // @[Control.scala:30:9] wire [2:0] auto_out_a_bits_size_0; // @[Control.scala:30:9] wire [6:0] auto_out_a_bits_source_0; // @[Control.scala:30:9] wire [11:0] auto_out_a_bits_address_0; // @[Control.scala:30:9] wire [7:0] auto_out_a_bits_mask_0; // @[Control.scala:30:9] wire [63:0] auto_out_a_bits_data_0; // @[Control.scala:30:9] wire auto_out_a_bits_corrupt_0; // @[Control.scala:30:9] wire auto_out_a_valid_0; // @[Control.scala:30:9] wire auto_out_d_ready_0; // @[Control.scala:30:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Control.scala:30:9] assign nodeOut_a_valid = nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_opcode = nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_param = nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_size = nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_source = nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_mask = nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_data = nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_corrupt = nodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_d_ready = nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Control.scala:30:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Control.scala:30:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Control.scala:30:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Control.scala:30:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Control.scala:30:9] assign nodeIn_a_ready = nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Control.scala:30:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Control.scala:30:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Control.scala:30:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Control.scala:30:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Control.scala:30:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Control.scala:30:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Control.scala:30:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Control.scala:30:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Control.scala:30:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Control.scala:30:9] assign nodeIn_d_valid = nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_opcode = nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_size = nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_source = nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_data = nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_address = nodeIn_a_bits_address[11:0]; // @[Control.scala:32:11] TLMonitor_39 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] assign auto_in_a_ready = auto_in_a_ready_0; // @[Control.scala:30:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Control.scala:30:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Control.scala:30:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Control.scala:30:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Control.scala:30:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Control.scala:30:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Control.scala:30:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Control.scala:30:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Control.scala:30:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Control.scala:30:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Control.scala:30:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Control.scala:30:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Control.scala:30:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Control.scala:30:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Control.scala:30:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Control.scala:30:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File FPU.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.tile import chisel3._ import chisel3.util._ import chisel3.{DontCare, WireInit, withClock, withReset} import chisel3.experimental.SourceInfo import chisel3.experimental.dataview._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.rocket._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property case class FPUParams( minFLen: Int = 32, fLen: Int = 64, divSqrt: Boolean = true, sfmaLatency: Int = 3, dfmaLatency: Int = 4, fpmuLatency: Int = 2, ifpuLatency: Int = 2 ) object FPConstants { val RM_SZ = 3 val FLAGS_SZ = 5 } trait HasFPUCtrlSigs { val ldst = Bool() val wen = Bool() val ren1 = Bool() val ren2 = Bool() val ren3 = Bool() val swap12 = Bool() val swap23 = Bool() val typeTagIn = UInt(2.W) val typeTagOut = UInt(2.W) val fromint = Bool() val toint = Bool() val fastpipe = Bool() val fma = Bool() val div = Bool() val sqrt = Bool() val wflags = Bool() val vec = Bool() } class FPUCtrlSigs extends Bundle with HasFPUCtrlSigs class FPUDecoder(implicit p: Parameters) extends FPUModule()(p) { val io = IO(new Bundle { val inst = Input(Bits(32.W)) val sigs = Output(new FPUCtrlSigs()) }) private val X2 = BitPat.dontCare(2) val default = List(X,X,X,X,X,X,X,X2,X2,X,X,X,X,X,X,X,N) val h: Array[(BitPat, List[BitPat])] = Array(FLH -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSH -> List(Y,N,N,Y,N,Y,X, I, H,N,Y,N,N,N,N,N,N), FMV_H_X -> List(N,Y,N,N,N,X,X, H, I,Y,N,N,N,N,N,N,N), FCVT_H_W -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_WU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_L -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_LU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FMV_X_H -> List(N,N,Y,N,N,N,X, I, H,N,Y,N,N,N,N,N,N), FCLASS_H -> List(N,N,Y,N,N,N,X, H, H,N,Y,N,N,N,N,N,N), FCVT_W_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_L_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_S_H -> List(N,Y,Y,N,N,N,X, H, S,N,N,Y,N,N,N,Y,N), FCVT_H_S -> List(N,Y,Y,N,N,N,X, S, H,N,N,Y,N,N,N,Y,N), FEQ_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FLT_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FLE_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FSGNJ_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FSGNJN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FSGNJX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FMIN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N), FMAX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N), FADD_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N), FSUB_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N), FMUL_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,Y,N,N,Y,N), FMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FNMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FNMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FDIV_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,N,Y,N,Y,N), FSQRT_H -> List(N,Y,Y,N,N,N,X, H, H,N,N,N,N,N,Y,Y,N)) val f: Array[(BitPat, List[BitPat])] = Array(FLW -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSW -> List(Y,N,N,Y,N,Y,X, I, S,N,Y,N,N,N,N,N,N), FMV_W_X -> List(N,Y,N,N,N,X,X, S, I,Y,N,N,N,N,N,N,N), FCVT_S_W -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_WU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_L -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_LU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FMV_X_W -> List(N,N,Y,N,N,N,X, I, S,N,Y,N,N,N,N,N,N), FCLASS_S -> List(N,N,Y,N,N,N,X, S, S,N,Y,N,N,N,N,N,N), FCVT_W_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_L_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FEQ_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FLT_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FLE_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FSGNJ_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FSGNJN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FSGNJX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FMIN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N), FMAX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N), FADD_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N), FSUB_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N), FMUL_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,Y,N,N,Y,N), FMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FNMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FNMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FDIV_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,N,Y,N,Y,N), FSQRT_S -> List(N,Y,Y,N,N,N,X, S, S,N,N,N,N,N,Y,Y,N)) val d: Array[(BitPat, List[BitPat])] = Array(FLD -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSD -> List(Y,N,N,Y,N,Y,X, I, D,N,Y,N,N,N,N,N,N), FMV_D_X -> List(N,Y,N,N,N,X,X, D, I,Y,N,N,N,N,N,N,N), FCVT_D_W -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_WU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_L -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_LU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FMV_X_D -> List(N,N,Y,N,N,N,X, I, D,N,Y,N,N,N,N,N,N), FCLASS_D -> List(N,N,Y,N,N,N,X, D, D,N,Y,N,N,N,N,N,N), FCVT_W_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_L_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_S_D -> List(N,Y,Y,N,N,N,X, D, S,N,N,Y,N,N,N,Y,N), FCVT_D_S -> List(N,Y,Y,N,N,N,X, S, D,N,N,Y,N,N,N,Y,N), FEQ_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FLT_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FLE_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FSGNJ_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FSGNJN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FSGNJX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FMIN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N), FMAX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N), FADD_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N), FSUB_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N), FMUL_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,Y,N,N,Y,N), FMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FNMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FNMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FDIV_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,N,Y,N,Y,N), FSQRT_D -> List(N,Y,Y,N,N,N,X, D, D,N,N,N,N,N,Y,Y,N)) val fcvt_hd: Array[(BitPat, List[BitPat])] = Array(FCVT_H_D -> List(N,Y,Y,N,N,N,X, D, H,N,N,Y,N,N,N,Y,N), FCVT_D_H -> List(N,Y,Y,N,N,N,X, H, D,N,N,Y,N,N,N,Y,N)) val vfmv_f_s: Array[(BitPat, List[BitPat])] = Array(VFMV_F_S -> List(N,Y,N,N,N,N,X,X2,X2,N,N,N,N,N,N,N,Y)) val insns = ((minFLen, fLen) match { case (32, 32) => f case (16, 32) => h ++ f case (32, 64) => f ++ d case (16, 64) => h ++ f ++ d ++ fcvt_hd case other => throw new Exception(s"minFLen = ${minFLen} & fLen = ${fLen} is an unsupported configuration") }) ++ (if (usingVector) vfmv_f_s else Array[(BitPat, List[BitPat])]()) val decoder = DecodeLogic(io.inst, default, insns) val s = io.sigs val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12, s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint, s.fastpipe, s.fma, s.div, s.sqrt, s.wflags, s.vec) sigs zip decoder map {case(s,d) => s := d} } class FPUCoreIO(implicit p: Parameters) extends CoreBundle()(p) { val hartid = Input(UInt(hartIdLen.W)) val time = Input(UInt(xLen.W)) val inst = Input(Bits(32.W)) val fromint_data = Input(Bits(xLen.W)) val fcsr_rm = Input(Bits(FPConstants.RM_SZ.W)) val fcsr_flags = Valid(Bits(FPConstants.FLAGS_SZ.W)) val v_sew = Input(UInt(3.W)) val store_data = Output(Bits(fLen.W)) val toint_data = Output(Bits(xLen.W)) val ll_resp_val = Input(Bool()) val ll_resp_type = Input(Bits(3.W)) val ll_resp_tag = Input(UInt(5.W)) val ll_resp_data = Input(Bits(fLen.W)) val valid = Input(Bool()) val fcsr_rdy = Output(Bool()) val nack_mem = Output(Bool()) val illegal_rm = Output(Bool()) val killx = Input(Bool()) val killm = Input(Bool()) val dec = Output(new FPUCtrlSigs()) val sboard_set = Output(Bool()) val sboard_clr = Output(Bool()) val sboard_clra = Output(UInt(5.W)) val keep_clock_enabled = Input(Bool()) } class FPUIO(implicit p: Parameters) extends FPUCoreIO ()(p) { val cp_req = Flipped(Decoupled(new FPInput())) //cp doesn't pay attn to kill sigs val cp_resp = Decoupled(new FPResult()) } class FPResult(implicit p: Parameters) extends CoreBundle()(p) { val data = Bits((fLen+1).W) val exc = Bits(FPConstants.FLAGS_SZ.W) } class IntToFPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs { val rm = Bits(FPConstants.RM_SZ.W) val typ = Bits(2.W) val in1 = Bits(xLen.W) } class FPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs { val rm = Bits(FPConstants.RM_SZ.W) val fmaCmd = Bits(2.W) val typ = Bits(2.W) val fmt = Bits(2.W) val in1 = Bits((fLen+1).W) val in2 = Bits((fLen+1).W) val in3 = Bits((fLen+1).W) } case class FType(exp: Int, sig: Int) { def ieeeWidth = exp + sig def recodedWidth = ieeeWidth + 1 def ieeeQNaN = ((BigInt(1) << (ieeeWidth - 1)) - (BigInt(1) << (sig - 2))).U(ieeeWidth.W) def qNaN = ((BigInt(7) << (exp + sig - 3)) + (BigInt(1) << (sig - 2))).U(recodedWidth.W) def isNaN(x: UInt) = x(sig + exp - 1, sig + exp - 3).andR def isSNaN(x: UInt) = isNaN(x) && !x(sig - 2) def classify(x: UInt) = { val sign = x(sig + exp) val code = x(exp + sig - 1, exp + sig - 3) val codeHi = code(2, 1) val isSpecial = codeHi === 3.U val isHighSubnormalIn = x(exp + sig - 3, sig - 1) < 2.U val isSubnormal = code === 1.U || codeHi === 1.U && isHighSubnormalIn val isNormal = codeHi === 1.U && !isHighSubnormalIn || codeHi === 2.U val isZero = code === 0.U val isInf = isSpecial && !code(0) val isNaN = code.andR val isSNaN = isNaN && !x(sig-2) val isQNaN = isNaN && x(sig-2) Cat(isQNaN, isSNaN, isInf && !sign, isNormal && !sign, isSubnormal && !sign, isZero && !sign, isZero && sign, isSubnormal && sign, isNormal && sign, isInf && sign) } // convert between formats, ignoring rounding, range, NaN def unsafeConvert(x: UInt, to: FType) = if (this == to) x else { val sign = x(sig + exp) val fractIn = x(sig - 2, 0) val expIn = x(sig + exp - 1, sig - 1) val fractOut = fractIn << to.sig >> sig val expOut = { val expCode = expIn(exp, exp - 2) val commonCase = (expIn + (1 << to.exp).U) - (1 << exp).U Mux(expCode === 0.U || expCode >= 6.U, Cat(expCode, commonCase(to.exp - 3, 0)), commonCase(to.exp, 0)) } Cat(sign, expOut, fractOut) } private def ieeeBundle = { val expWidth = exp class IEEEBundle extends Bundle { val sign = Bool() val exp = UInt(expWidth.W) val sig = UInt((ieeeWidth-expWidth-1).W) } new IEEEBundle } def unpackIEEE(x: UInt) = x.asTypeOf(ieeeBundle) def recode(x: UInt) = hardfloat.recFNFromFN(exp, sig, x) def ieee(x: UInt) = hardfloat.fNFromRecFN(exp, sig, x) } object FType { val H = new FType(5, 11) val S = new FType(8, 24) val D = new FType(11, 53) val all = List(H, S, D) } trait HasFPUParameters { require(fLen == 0 || FType.all.exists(_.ieeeWidth == fLen)) val minFLen: Int val fLen: Int def xLen: Int val minXLen = 32 val nIntTypes = log2Ceil(xLen/minXLen) + 1 def floatTypes = FType.all.filter(t => minFLen <= t.ieeeWidth && t.ieeeWidth <= fLen) def minType = floatTypes.head def maxType = floatTypes.last def prevType(t: FType) = floatTypes(typeTag(t) - 1) def maxExpWidth = maxType.exp def maxSigWidth = maxType.sig def typeTag(t: FType) = floatTypes.indexOf(t) def typeTagWbOffset = (FType.all.indexOf(minType) + 1).U def typeTagGroup(t: FType) = (if (floatTypes.contains(t)) typeTag(t) else typeTag(maxType)).U // typeTag def H = typeTagGroup(FType.H) def S = typeTagGroup(FType.S) def D = typeTagGroup(FType.D) def I = typeTag(maxType).U private def isBox(x: UInt, t: FType): Bool = x(t.sig + t.exp, t.sig + t.exp - 4).andR private def box(x: UInt, xt: FType, y: UInt, yt: FType): UInt = { require(xt.ieeeWidth == 2 * yt.ieeeWidth) val swizzledNaN = Cat( x(xt.sig + xt.exp, xt.sig + xt.exp - 3), x(xt.sig - 2, yt.recodedWidth - 1).andR, x(xt.sig + xt.exp - 5, xt.sig), y(yt.recodedWidth - 2), x(xt.sig - 2, yt.recodedWidth - 1), y(yt.recodedWidth - 1), y(yt.recodedWidth - 3, 0)) Mux(xt.isNaN(x), swizzledNaN, x) } // implement NaN unboxing for FU inputs def unbox(x: UInt, tag: UInt, exactType: Option[FType]): UInt = { val outType = exactType.getOrElse(maxType) def helper(x: UInt, t: FType): Seq[(Bool, UInt)] = { val prev = if (t == minType) { Seq() } else { val prevT = prevType(t) val unswizzled = Cat( x(prevT.sig + prevT.exp - 1), x(t.sig - 1), x(prevT.sig + prevT.exp - 2, 0)) val prev = helper(unswizzled, prevT) val isbox = isBox(x, t) prev.map(p => (isbox && p._1, p._2)) } prev :+ (true.B, t.unsafeConvert(x, outType)) } val (oks, floats) = helper(x, maxType).unzip if (exactType.isEmpty || floatTypes.size == 1) { Mux(oks(tag), floats(tag), maxType.qNaN) } else { val t = exactType.get floats(typeTag(t)) | Mux(oks(typeTag(t)), 0.U, t.qNaN) } } // make sure that the redundant bits in the NaN-boxed encoding are consistent def consistent(x: UInt): Bool = { def helper(x: UInt, t: FType): Bool = if (typeTag(t) == 0) true.B else { val prevT = prevType(t) val unswizzled = Cat( x(prevT.sig + prevT.exp - 1), x(t.sig - 1), x(prevT.sig + prevT.exp - 2, 0)) val prevOK = !isBox(x, t) || helper(unswizzled, prevT) val curOK = !t.isNaN(x) || x(t.sig + t.exp - 4) === x(t.sig - 2, prevT.recodedWidth - 1).andR prevOK && curOK } helper(x, maxType) } // generate a NaN box from an FU result def box(x: UInt, t: FType): UInt = { if (t == maxType) { x } else { val nt = floatTypes(typeTag(t) + 1) val bigger = box(((BigInt(1) << nt.recodedWidth)-1).U, nt, x, t) bigger | ((BigInt(1) << maxType.recodedWidth) - (BigInt(1) << nt.recodedWidth)).U } } // generate a NaN box from an FU result def box(x: UInt, tag: UInt): UInt = { val opts = floatTypes.map(t => box(x, t)) opts(tag) } // zap bits that hardfloat thinks are don't-cares, but we do care about def sanitizeNaN(x: UInt, t: FType): UInt = { if (typeTag(t) == 0) { x } else { val maskedNaN = x & ~((BigInt(1) << (t.sig-1)) | (BigInt(1) << (t.sig+t.exp-4))).U(t.recodedWidth.W) Mux(t.isNaN(x), maskedNaN, x) } } // implement NaN boxing and recoding for FL*/fmv.*.x def recode(x: UInt, tag: UInt): UInt = { def helper(x: UInt, t: FType): UInt = { if (typeTag(t) == 0) { t.recode(x) } else { val prevT = prevType(t) box(t.recode(x), t, helper(x, prevT), prevT) } } // fill MSBs of subword loads to emulate a wider load of a NaN-boxed value val boxes = floatTypes.map(t => ((BigInt(1) << maxType.ieeeWidth) - (BigInt(1) << t.ieeeWidth)).U) helper(boxes(tag) | x, maxType) } // implement NaN unboxing and un-recoding for FS*/fmv.x.* def ieee(x: UInt, t: FType = maxType): UInt = { if (typeTag(t) == 0) { t.ieee(x) } else { val unrecoded = t.ieee(x) val prevT = prevType(t) val prevRecoded = Cat( x(prevT.recodedWidth-2), x(t.sig-1), x(prevT.recodedWidth-3, 0)) val prevUnrecoded = ieee(prevRecoded, prevT) Cat(unrecoded >> prevT.ieeeWidth, Mux(t.isNaN(x), prevUnrecoded, unrecoded(prevT.ieeeWidth-1, 0))) } } } abstract class FPUModule(implicit val p: Parameters) extends Module with HasCoreParameters with HasFPUParameters class FPToInt(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { class Output extends Bundle { val in = new FPInput val lt = Bool() val store = Bits(fLen.W) val toint = Bits(xLen.W) val exc = Bits(FPConstants.FLAGS_SZ.W) } val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new Output) }) val in = RegEnable(io.in.bits, io.in.valid) val valid = RegNext(io.in.valid) val dcmp = Module(new hardfloat.CompareRecFN(maxExpWidth, maxSigWidth)) dcmp.io.a := in.in1 dcmp.io.b := in.in2 dcmp.io.signaling := !in.rm(1) val tag = in.typeTagOut val toint_ieee = (floatTypes.map(t => if (t == FType.H) Fill(maxType.ieeeWidth / minXLen, ieee(in.in1)(15, 0).sextTo(minXLen)) else Fill(maxType.ieeeWidth / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag) val toint = WireDefault(toint_ieee) val intType = WireDefault(in.fmt(0)) io.out.bits.store := (floatTypes.map(t => Fill(fLen / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag) io.out.bits.toint := ((0 until nIntTypes).map(i => toint((minXLen << i) - 1, 0).sextTo(xLen)): Seq[UInt])(intType) io.out.bits.exc := 0.U when (in.rm(0)) { val classify_out = (floatTypes.map(t => t.classify(maxType.unsafeConvert(in.in1, t))): Seq[UInt])(tag) toint := classify_out | (toint_ieee >> minXLen << minXLen) intType := false.B } when (in.wflags) { // feq/flt/fle, fcvt toint := (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR | (toint_ieee >> minXLen << minXLen) io.out.bits.exc := dcmp.io.exceptionFlags intType := false.B when (!in.ren2) { // fcvt val cvtType = in.typ.extract(log2Ceil(nIntTypes), 1) intType := cvtType val conv = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, xLen)) conv.io.in := in.in1 conv.io.roundingMode := in.rm conv.io.signedOut := ~in.typ(0) toint := conv.io.out io.out.bits.exc := Cat(conv.io.intExceptionFlags(2, 1).orR, 0.U(3.W), conv.io.intExceptionFlags(0)) for (i <- 0 until nIntTypes-1) { val w = minXLen << i when (cvtType === i.U) { val narrow = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, w)) narrow.io.in := in.in1 narrow.io.roundingMode := in.rm narrow.io.signedOut := ~in.typ(0) val excSign = in.in1(maxExpWidth + maxSigWidth) && !maxType.isNaN(in.in1) val excOut = Cat(conv.io.signedOut === excSign, Fill(w-1, !excSign)) val invalid = conv.io.intExceptionFlags(2) || narrow.io.intExceptionFlags(1) when (invalid) { toint := Cat(conv.io.out >> w, excOut) } io.out.bits.exc := Cat(invalid, 0.U(3.W), !invalid && conv.io.intExceptionFlags(0)) } } } } io.out.valid := valid io.out.bits.lt := dcmp.io.lt || (dcmp.io.a.asSInt < 0.S && dcmp.io.b.asSInt >= 0.S) io.out.bits.in := in } class IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { val io = IO(new Bundle { val in = Flipped(Valid(new IntToFPInput)) val out = Valid(new FPResult) }) val in = Pipe(io.in) val tag = in.bits.typeTagIn val mux = Wire(new FPResult) mux.exc := 0.U mux.data := recode(in.bits.in1, tag) val intValue = { val res = WireDefault(in.bits.in1.asSInt) for (i <- 0 until nIntTypes-1) { val smallInt = in.bits.in1((minXLen << i) - 1, 0) when (in.bits.typ.extract(log2Ceil(nIntTypes), 1) === i.U) { res := Mux(in.bits.typ(0), smallInt.zext, smallInt.asSInt) } } res.asUInt } when (in.bits.wflags) { // fcvt // could be improved for RVD/RVQ with a single variable-position rounding // unit, rather than N fixed-position ones val i2fResults = for (t <- floatTypes) yield { val i2f = Module(new hardfloat.INToRecFN(xLen, t.exp, t.sig)) i2f.io.signedIn := ~in.bits.typ(0) i2f.io.in := intValue i2f.io.roundingMode := in.bits.rm i2f.io.detectTininess := hardfloat.consts.tininess_afterRounding (sanitizeNaN(i2f.io.out, t), i2f.io.exceptionFlags) } val (data, exc) = i2fResults.unzip val dataPadded = data.init.map(d => Cat(data.last >> d.getWidth, d)) :+ data.last mux.data := dataPadded(tag) mux.exc := exc(tag) } io.out <> Pipe(in.valid, mux, latency-1) } class FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new FPResult) val lt = Input(Bool()) // from FPToInt }) val in = Pipe(io.in) val signNum = Mux(in.bits.rm(1), in.bits.in1 ^ in.bits.in2, Mux(in.bits.rm(0), ~in.bits.in2, in.bits.in2)) val fsgnj = Cat(signNum(fLen), in.bits.in1(fLen-1, 0)) val fsgnjMux = Wire(new FPResult) fsgnjMux.exc := 0.U fsgnjMux.data := fsgnj when (in.bits.wflags) { // fmin/fmax val isnan1 = maxType.isNaN(in.bits.in1) val isnan2 = maxType.isNaN(in.bits.in2) val isInvalid = maxType.isSNaN(in.bits.in1) || maxType.isSNaN(in.bits.in2) val isNaNOut = isnan1 && isnan2 val isLHS = isnan2 || in.bits.rm(0) =/= io.lt && !isnan1 fsgnjMux.exc := isInvalid << 4 fsgnjMux.data := Mux(isNaNOut, maxType.qNaN, Mux(isLHS, in.bits.in1, in.bits.in2)) } val inTag = in.bits.typeTagIn val outTag = in.bits.typeTagOut val mux = WireDefault(fsgnjMux) for (t <- floatTypes.init) { when (outTag === typeTag(t).U) { mux.data := Cat(fsgnjMux.data >> t.recodedWidth, maxType.unsafeConvert(fsgnjMux.data, t)) } } when (in.bits.wflags && !in.bits.ren2) { // fcvt if (floatTypes.size > 1) { // widening conversions simply canonicalize NaN operands val widened = Mux(maxType.isNaN(in.bits.in1), maxType.qNaN, in.bits.in1) fsgnjMux.data := widened fsgnjMux.exc := maxType.isSNaN(in.bits.in1) << 4 // narrowing conversions require rounding (for RVQ, this could be // optimized to use a single variable-position rounding unit, rather // than two fixed-position ones) for (outType <- floatTypes.init) when (outTag === typeTag(outType).U && ((typeTag(outType) == 0).B || outTag < inTag)) { val narrower = Module(new hardfloat.RecFNToRecFN(maxType.exp, maxType.sig, outType.exp, outType.sig)) narrower.io.in := in.bits.in1 narrower.io.roundingMode := in.bits.rm narrower.io.detectTininess := hardfloat.consts.tininess_afterRounding val narrowed = sanitizeNaN(narrower.io.out, outType) mux.data := Cat(fsgnjMux.data >> narrowed.getWidth, narrowed) mux.exc := narrower.io.exceptionFlags } } } io.out <> Pipe(in.valid, mux, latency-1) } class MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module { override def desiredName = s"MulAddRecFNPipe_l${latency}_e${expWidth}_s${sigWidth}" require(latency<=2) val io = IO(new Bundle { val validin = Input(Bool()) val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) val validout = Output(Bool()) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulAddRecFNToRaw_preMul = Module(new hardfloat.MulAddRecFNToRaw_preMul(expWidth, sigWidth)) val mulAddRecFNToRaw_postMul = Module(new hardfloat.MulAddRecFNToRaw_postMul(expWidth, sigWidth)) mulAddRecFNToRaw_preMul.io.op := io.op mulAddRecFNToRaw_preMul.io.a := io.a mulAddRecFNToRaw_preMul.io.b := io.b mulAddRecFNToRaw_preMul.io.c := io.c val mulAddResult = (mulAddRecFNToRaw_preMul.io.mulAddA * mulAddRecFNToRaw_preMul.io.mulAddB) +& mulAddRecFNToRaw_preMul.io.mulAddC val valid_stage0 = Wire(Bool()) val roundingMode_stage0 = Wire(UInt(3.W)) val detectTininess_stage0 = Wire(UInt(1.W)) val postmul_regs = if(latency>0) 1 else 0 mulAddRecFNToRaw_postMul.io.fromPreMul := Pipe(io.validin, mulAddRecFNToRaw_preMul.io.toPostMul, postmul_regs).bits mulAddRecFNToRaw_postMul.io.mulAddResult := Pipe(io.validin, mulAddResult, postmul_regs).bits mulAddRecFNToRaw_postMul.io.roundingMode := Pipe(io.validin, io.roundingMode, postmul_regs).bits roundingMode_stage0 := Pipe(io.validin, io.roundingMode, postmul_regs).bits detectTininess_stage0 := Pipe(io.validin, io.detectTininess, postmul_regs).bits valid_stage0 := Pipe(io.validin, false.B, postmul_regs).valid //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new hardfloat.RoundRawFNToRecFN(expWidth, sigWidth, 0)) val round_regs = if(latency==2) 1 else 0 roundRawFNToRecFN.io.invalidExc := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.invalidExc, round_regs).bits roundRawFNToRecFN.io.in := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.rawOut, round_regs).bits roundRawFNToRecFN.io.roundingMode := Pipe(valid_stage0, roundingMode_stage0, round_regs).bits roundRawFNToRecFN.io.detectTininess := Pipe(valid_stage0, detectTininess_stage0, round_regs).bits io.validout := Pipe(valid_stage0, false.B, round_regs).valid roundRawFNToRecFN.io.infiniteExc := false.B io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags } class FPUFMAPipe(val latency: Int, val t: FType) (implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { override def desiredName = s"FPUFMAPipe_l${latency}_f${t.ieeeWidth}" require(latency>0) val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new FPResult) }) val valid = RegNext(io.in.valid) val in = Reg(new FPInput) when (io.in.valid) { val one = 1.U << (t.sig + t.exp - 1) val zero = (io.in.bits.in1 ^ io.in.bits.in2) & (1.U << (t.sig + t.exp)) val cmd_fma = io.in.bits.ren3 val cmd_addsub = io.in.bits.swap23 in := io.in.bits when (cmd_addsub) { in.in2 := one } when (!(cmd_fma || cmd_addsub)) { in.in3 := zero } } val fma = Module(new MulAddRecFNPipe((latency-1) min 2, t.exp, t.sig)) fma.io.validin := valid fma.io.op := in.fmaCmd fma.io.roundingMode := in.rm fma.io.detectTininess := hardfloat.consts.tininess_afterRounding fma.io.a := in.in1 fma.io.b := in.in2 fma.io.c := in.in3 val res = Wire(new FPResult) res.data := sanitizeNaN(fma.io.out, t) res.exc := fma.io.exceptionFlags io.out := Pipe(fma.io.validout, res, (latency-3) max 0) } class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) { val io = IO(new FPUIO) val (useClockGating, useDebugROB) = coreParams match { case r: RocketCoreParams => val sz = if (r.debugROB.isDefined) r.debugROB.get.size else 1 (r.clockGate, sz < 1) case _ => (false, false) } val clock_en_reg = Reg(Bool()) val clock_en = clock_en_reg || io.cp_req.valid val gated_clock = if (!useClockGating) clock else ClockGate(clock, clock_en, "fpu_clock_gate") val fp_decoder = Module(new FPUDecoder) fp_decoder.io.inst := io.inst val id_ctrl = WireInit(fp_decoder.io.sigs) coreParams match { case r: RocketCoreParams => r.vector.map(v => { val v_decode = v.decoder(p) // Only need to get ren1 v_decode.io.inst := io.inst v_decode.io.vconfig := DontCare // core deals with this when (v_decode.io.legal && v_decode.io.read_frs1) { id_ctrl.ren1 := true.B id_ctrl.swap12 := false.B id_ctrl.toint := true.B id_ctrl.typeTagIn := I id_ctrl.typeTagOut := Mux(io.v_sew === 3.U, D, S) } when (v_decode.io.write_frd) { id_ctrl.wen := true.B } })} val ex_reg_valid = RegNext(io.valid, false.B) val ex_reg_inst = RegEnable(io.inst, io.valid) val ex_reg_ctrl = RegEnable(id_ctrl, io.valid) val ex_ra = List.fill(3)(Reg(UInt())) // load/vector response val load_wb = RegNext(io.ll_resp_val) val load_wb_typeTag = RegEnable(io.ll_resp_type(1,0) - typeTagWbOffset, io.ll_resp_val) val load_wb_data = RegEnable(io.ll_resp_data, io.ll_resp_val) val load_wb_tag = RegEnable(io.ll_resp_tag, io.ll_resp_val) class FPUImpl { // entering gated-clock domain val req_valid = ex_reg_valid || io.cp_req.valid val ex_cp_valid = io.cp_req.fire val mem_cp_valid = RegNext(ex_cp_valid, false.B) val wb_cp_valid = RegNext(mem_cp_valid, false.B) val mem_reg_valid = RegInit(false.B) val killm = (io.killm || io.nack_mem) && !mem_cp_valid // Kill X-stage instruction if M-stage is killed. This prevents it from // speculatively being sent to the div-sqrt unit, which can cause priority // inversion for two back-to-back divides, the first of which is killed. val killx = io.killx || mem_reg_valid && killm mem_reg_valid := ex_reg_valid && !killx || ex_cp_valid val mem_reg_inst = RegEnable(ex_reg_inst, ex_reg_valid) val wb_reg_valid = RegNext(mem_reg_valid && (!killm || mem_cp_valid), false.B) val cp_ctrl = Wire(new FPUCtrlSigs) cp_ctrl :<>= io.cp_req.bits.viewAsSupertype(new FPUCtrlSigs) io.cp_resp.valid := false.B io.cp_resp.bits.data := 0.U io.cp_resp.bits.exc := DontCare val ex_ctrl = Mux(ex_cp_valid, cp_ctrl, ex_reg_ctrl) val mem_ctrl = RegEnable(ex_ctrl, req_valid) val wb_ctrl = RegEnable(mem_ctrl, mem_reg_valid) // CoreMonitorBundle to monitor fp register file writes val frfWriteBundle = Seq.fill(2)(WireInit(new CoreMonitorBundle(xLen, fLen), DontCare)) frfWriteBundle.foreach { i => i.clock := clock i.reset := reset i.hartid := io.hartid i.timer := io.time(31,0) i.valid := false.B i.wrenx := false.B i.wrenf := false.B i.excpt := false.B } // regfile val regfile = Mem(32, Bits((fLen+1).W)) when (load_wb) { val wdata = recode(load_wb_data, load_wb_typeTag) regfile(load_wb_tag) := wdata assert(consistent(wdata)) if (enableCommitLog) printf("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + 32.U, ieee(wdata)) if (useDebugROB) DebugROB.pushWb(clock, reset, io.hartid, load_wb, load_wb_tag + 32.U, ieee(wdata)) frfWriteBundle(0).wrdst := load_wb_tag frfWriteBundle(0).wrenf := true.B frfWriteBundle(0).wrdata := ieee(wdata) } val ex_rs = ex_ra.map(a => regfile(a)) when (io.valid) { when (id_ctrl.ren1) { when (!id_ctrl.swap12) { ex_ra(0) := io.inst(19,15) } when (id_ctrl.swap12) { ex_ra(1) := io.inst(19,15) } } when (id_ctrl.ren2) { when (id_ctrl.swap12) { ex_ra(0) := io.inst(24,20) } when (id_ctrl.swap23) { ex_ra(2) := io.inst(24,20) } when (!id_ctrl.swap12 && !id_ctrl.swap23) { ex_ra(1) := io.inst(24,20) } } when (id_ctrl.ren3) { ex_ra(2) := io.inst(31,27) } } val ex_rm = Mux(ex_reg_inst(14,12) === 7.U, io.fcsr_rm, ex_reg_inst(14,12)) def fuInput(minT: Option[FType]): FPInput = { val req = Wire(new FPInput) val tag = ex_ctrl.typeTagIn req.viewAsSupertype(new Bundle with HasFPUCtrlSigs) :#= ex_ctrl.viewAsSupertype(new Bundle with HasFPUCtrlSigs) req.rm := ex_rm req.in1 := unbox(ex_rs(0), tag, minT) req.in2 := unbox(ex_rs(1), tag, minT) req.in3 := unbox(ex_rs(2), tag, minT) req.typ := ex_reg_inst(21,20) req.fmt := ex_reg_inst(26,25) req.fmaCmd := ex_reg_inst(3,2) | (!ex_ctrl.ren3 && ex_reg_inst(27)) when (ex_cp_valid) { req := io.cp_req.bits when (io.cp_req.bits.swap12) { req.in1 := io.cp_req.bits.in2 req.in2 := io.cp_req.bits.in1 } when (io.cp_req.bits.swap23) { req.in2 := io.cp_req.bits.in3 req.in3 := io.cp_req.bits.in2 } } req } val sfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.S)) sfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === S sfma.io.in.bits := fuInput(Some(sfma.t)) val fpiu = Module(new FPToInt) fpiu.io.in.valid := req_valid && (ex_ctrl.toint || ex_ctrl.div || ex_ctrl.sqrt || (ex_ctrl.fastpipe && ex_ctrl.wflags)) fpiu.io.in.bits := fuInput(None) io.store_data := fpiu.io.out.bits.store io.toint_data := fpiu.io.out.bits.toint when(fpiu.io.out.valid && mem_cp_valid && mem_ctrl.toint){ io.cp_resp.bits.data := fpiu.io.out.bits.toint io.cp_resp.valid := true.B } val ifpu = Module(new IntToFP(cfg.ifpuLatency)) ifpu.io.in.valid := req_valid && ex_ctrl.fromint ifpu.io.in.bits := fpiu.io.in.bits ifpu.io.in.bits.in1 := Mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data) val fpmu = Module(new FPToFP(cfg.fpmuLatency)) fpmu.io.in.valid := req_valid && ex_ctrl.fastpipe fpmu.io.in.bits := fpiu.io.in.bits fpmu.io.lt := fpiu.io.out.bits.lt val divSqrt_wen = WireDefault(false.B) val divSqrt_inFlight = WireDefault(false.B) val divSqrt_waddr = Reg(UInt(5.W)) val divSqrt_cp = Reg(Bool()) val divSqrt_typeTag = Wire(UInt(log2Up(floatTypes.size).W)) val divSqrt_wdata = Wire(UInt((fLen+1).W)) val divSqrt_flags = Wire(UInt(FPConstants.FLAGS_SZ.W)) divSqrt_typeTag := DontCare divSqrt_wdata := DontCare divSqrt_flags := DontCare // writeback arbitration case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, res: FPResult) val pipes = List( Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits), Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits), Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === S, sfma.io.out.bits)) ++ (fLen > 32).option({ val dfma = Module(new FPUFMAPipe(cfg.dfmaLatency, FType.D)) dfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === D dfma.io.in.bits := fuInput(Some(dfma.t)) Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === D, dfma.io.out.bits) }) ++ (minFLen == 16).option({ val hfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.H)) hfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === H hfma.io.in.bits := fuInput(Some(hfma.t)) Pipe(hfma, hfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === H, hfma.io.out.bits) }) def latencyMask(c: FPUCtrlSigs, offset: Int) = { require(pipes.forall(_.lat >= offset)) pipes.map(p => Mux(p.cond(c), (1 << p.lat-offset).U, 0.U)).reduce(_|_) } def pipeid(c: FPUCtrlSigs) = pipes.zipWithIndex.map(p => Mux(p._1.cond(c), p._2.U, 0.U)).reduce(_|_) val maxLatency = pipes.map(_.lat).max val memLatencyMask = latencyMask(mem_ctrl, 2) class WBInfo extends Bundle { val rd = UInt(5.W) val typeTag = UInt(log2Up(floatTypes.size).W) val cp = Bool() val pipeid = UInt(log2Ceil(pipes.size).W) } val wen = RegInit(0.U((maxLatency-1).W)) val wbInfo = Reg(Vec(maxLatency-1, new WBInfo)) val mem_wen = mem_reg_valid && (mem_ctrl.fma || mem_ctrl.fastpipe || mem_ctrl.fromint) val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR || (wen & latencyMask(ex_ctrl, 0)).orR, req_valid) ccover(mem_reg_valid && write_port_busy, "WB_STRUCTURAL", "structural hazard on writeback") for (i <- 0 until maxLatency-2) { when (wen(i+1)) { wbInfo(i) := wbInfo(i+1) } } wen := wen >> 1 when (mem_wen) { when (!killm) { wen := wen >> 1 | memLatencyMask } for (i <- 0 until maxLatency-1) { when (!write_port_busy && memLatencyMask(i)) { wbInfo(i).cp := mem_cp_valid wbInfo(i).typeTag := mem_ctrl.typeTagOut wbInfo(i).pipeid := pipeid(mem_ctrl) wbInfo(i).rd := mem_reg_inst(11,7) } } } val waddr = Mux(divSqrt_wen, divSqrt_waddr, wbInfo(0).rd) val wb_cp = Mux(divSqrt_wen, divSqrt_cp, wbInfo(0).cp) val wtypeTag = Mux(divSqrt_wen, divSqrt_typeTag, wbInfo(0).typeTag) val wdata = box(Mux(divSqrt_wen, divSqrt_wdata, (pipes.map(_.res.data): Seq[UInt])(wbInfo(0).pipeid)), wtypeTag) val wexc = (pipes.map(_.res.exc): Seq[UInt])(wbInfo(0).pipeid) when ((!wbInfo(0).cp && wen(0)) || divSqrt_wen) { assert(consistent(wdata)) regfile(waddr) := wdata if (enableCommitLog) { printf("f%d p%d 0x%x\n", waddr, waddr + 32.U, ieee(wdata)) } frfWriteBundle(1).wrdst := waddr frfWriteBundle(1).wrenf := true.B frfWriteBundle(1).wrdata := ieee(wdata) } if (useDebugROB) { DebugROB.pushWb(clock, reset, io.hartid, (!wbInfo(0).cp && wen(0)) || divSqrt_wen, waddr + 32.U, ieee(wdata)) } when (wb_cp && (wen(0) || divSqrt_wen)) { io.cp_resp.bits.data := wdata io.cp_resp.valid := true.B } assert(!io.cp_req.valid || pipes.forall(_.lat == pipes.head.lat).B, s"FPU only supports coprocessor if FMA pipes have uniform latency ${pipes.map(_.lat)}") // Avoid structural hazards and nacking of external requests // toint responds in the MEM stage, so an incoming toint can induce a structural hazard against inflight FMAs io.cp_req.ready := !ex_reg_valid && !(cp_ctrl.toint && wen =/= 0.U) && !divSqrt_inFlight val wb_toint_valid = wb_reg_valid && wb_ctrl.toint val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint) io.fcsr_flags.valid := wb_toint_valid || divSqrt_wen || wen(0) io.fcsr_flags.bits := Mux(wb_toint_valid, wb_toint_exc, 0.U) | Mux(divSqrt_wen, divSqrt_flags, 0.U) | Mux(wen(0), wexc, 0.U) val divSqrt_write_port_busy = (mem_ctrl.div || mem_ctrl.sqrt) && wen.orR io.fcsr_rdy := !(ex_reg_valid && ex_ctrl.wflags || mem_reg_valid && mem_ctrl.wflags || wb_reg_valid && wb_ctrl.toint || wen.orR || divSqrt_inFlight) io.nack_mem := (write_port_busy || divSqrt_write_port_busy || divSqrt_inFlight) && !mem_cp_valid io.dec <> id_ctrl def useScoreboard(f: ((Pipe, Int)) => Bool) = pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(false.B)(_||_) io.sboard_set := wb_reg_valid && !wb_cp_valid && RegNext(useScoreboard(_._1.cond(mem_ctrl)) || mem_ctrl.div || mem_ctrl.sqrt || mem_ctrl.vec) io.sboard_clr := !wb_cp_valid && (divSqrt_wen || (wen(0) && useScoreboard(x => wbInfo(0).pipeid === x._2.U))) io.sboard_clra := waddr ccover(io.sboard_clr && load_wb, "DUAL_WRITEBACK", "load and FMA writeback on same cycle") // we don't currently support round-max-magnitude (rm=4) io.illegal_rm := io.inst(14,12).isOneOf(5.U, 6.U) || io.inst(14,12) === 7.U && io.fcsr_rm >= 5.U if (cfg.divSqrt) { val divSqrt_inValid = mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt) && !divSqrt_inFlight val divSqrt_killed = RegNext(divSqrt_inValid && killm, true.B) when (divSqrt_inValid) { divSqrt_waddr := mem_reg_inst(11,7) divSqrt_cp := mem_cp_valid } ccover(divSqrt_inFlight && divSqrt_killed, "DIV_KILLED", "divide killed after issued to divider") ccover(divSqrt_inFlight && mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt), "DIV_BUSY", "divider structural hazard") ccover(mem_reg_valid && divSqrt_write_port_busy, "DIV_WB_STRUCTURAL", "structural hazard on division writeback") for (t <- floatTypes) { val tag = mem_ctrl.typeTagOut val divSqrt = withReset(divSqrt_killed) { Module(new hardfloat.DivSqrtRecFN_small(t.exp, t.sig, 0)) } divSqrt.io.inValid := divSqrt_inValid && tag === typeTag(t).U divSqrt.io.sqrtOp := mem_ctrl.sqrt divSqrt.io.a := maxType.unsafeConvert(fpiu.io.out.bits.in.in1, t) divSqrt.io.b := maxType.unsafeConvert(fpiu.io.out.bits.in.in2, t) divSqrt.io.roundingMode := fpiu.io.out.bits.in.rm divSqrt.io.detectTininess := hardfloat.consts.tininess_afterRounding when (!divSqrt.io.inReady) { divSqrt_inFlight := true.B } // only 1 in flight when (divSqrt.io.outValid_div || divSqrt.io.outValid_sqrt) { divSqrt_wen := !divSqrt_killed divSqrt_wdata := sanitizeNaN(divSqrt.io.out, t) divSqrt_flags := divSqrt.io.exceptionFlags divSqrt_typeTag := typeTag(t).U } } when (divSqrt_killed) { divSqrt_inFlight := false.B } } else { when (id_ctrl.div || id_ctrl.sqrt) { io.illegal_rm := true.B } } // gate the clock clock_en_reg := !useClockGating.B || io.keep_clock_enabled || // chicken bit io.valid || // ID stage req_valid || // EX stage mem_reg_valid || mem_cp_valid || // MEM stage wb_reg_valid || wb_cp_valid || // WB stage wen.orR || divSqrt_inFlight || // post-WB stage io.ll_resp_val // load writeback } // leaving gated-clock domain val fpuImpl = withClock (gated_clock) { new FPUImpl } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = property.cover(cond, s"FPU_$label", "Core;;" + desc) }
module FPUFMAPipe_l3_f64( // @[FPU.scala:697:7] input clock, // @[FPU.scala:697:7] input reset, // @[FPU.scala:697:7] input io_in_valid, // @[FPU.scala:702:14] input io_in_bits_ren3, // @[FPU.scala:702:14] input io_in_bits_swap23, // @[FPU.scala:702:14] input [2:0] io_in_bits_rm, // @[FPU.scala:702:14] input [1:0] io_in_bits_fmaCmd, // @[FPU.scala:702:14] input [64:0] io_in_bits_in1, // @[FPU.scala:702:14] input [64:0] io_in_bits_in2, // @[FPU.scala:702:14] input [64:0] io_in_bits_in3, // @[FPU.scala:702:14] output [64:0] io_out_bits_data, // @[FPU.scala:702:14] output [4:0] io_out_bits_exc // @[FPU.scala:702:14] ); wire [64:0] _fma_io_out; // @[FPU.scala:719:19] reg valid; // @[FPU.scala:707:22] reg [2:0] in_rm; // @[FPU.scala:708:15] reg [1:0] in_fmaCmd; // @[FPU.scala:708:15] reg [64:0] in_in1; // @[FPU.scala:708:15] reg [64:0] in_in2; // @[FPU.scala:708:15] reg [64:0] in_in3; // @[FPU.scala:708:15] always @(posedge clock) begin // @[FPU.scala:697:7] valid <= io_in_valid; // @[FPU.scala:707:22] if (io_in_valid) begin // @[FPU.scala:702:14] in_rm <= io_in_bits_rm; // @[FPU.scala:708:15] in_fmaCmd <= io_in_bits_fmaCmd; // @[FPU.scala:708:15] in_in1 <= io_in_bits_in1; // @[FPU.scala:708:15] in_in2 <= io_in_bits_swap23 ? 65'h8000000000000000 : io_in_bits_in2; // @[FPU.scala:708:15, :714:8, :715:{23,32}] in_in3 <= io_in_bits_ren3 | io_in_bits_swap23 ? io_in_bits_in3 : (io_in_bits_in1 ^ io_in_bits_in2) & 65'h10000000000000000; // @[FPU.scala:708:15, :711:{32,50}, :714:8, :716:{21,37,46}] end always @(posedge)
Generate the Verilog code corresponding to the following Chisel files. File OutputUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import constellation.channel._ import constellation.routing.{FlowRoutingBundle} import constellation.noc.{HasNoCParams} class OutputCreditAlloc extends Bundle { val alloc = Bool() val tail = Bool() } class OutputChannelStatus(implicit val p: Parameters) extends Bundle with HasNoCParams { val occupied = Bool() def available = !occupied val flow = new FlowRoutingBundle } class OutputChannelAlloc(implicit val p: Parameters) extends Bundle with HasNoCParams { val alloc = Bool() val flow = new FlowRoutingBundle } class AbstractOutputUnitIO( val inParams: Seq[ChannelParams], val ingressParams: Seq[IngressChannelParams], val cParam: BaseChannelParams )(implicit val p: Parameters) extends Bundle with HasRouterInputParams { val nodeId = cParam.srcId val nVirtualChannels = cParam.nVirtualChannels val in = Flipped(Vec(cParam.srcSpeedup, Valid(new Flit(cParam.payloadBits)))) val credit_available = Output(Vec(nVirtualChannels, Bool())) val channel_status = Output(Vec(nVirtualChannels, new OutputChannelStatus)) val allocs = Input(Vec(nVirtualChannels, new OutputChannelAlloc)) val credit_alloc = Input(Vec(nVirtualChannels, new OutputCreditAlloc)) } abstract class AbstractOutputUnit( val inParams: Seq[ChannelParams], val ingressParams: Seq[IngressChannelParams], val cParam: BaseChannelParams )(implicit val p: Parameters) extends Module with HasRouterInputParams with HasNoCParams { val nodeId = cParam.srcId def io: AbstractOutputUnitIO } class OutputUnit(inParams: Seq[ChannelParams], ingressParams: Seq[IngressChannelParams], cParam: ChannelParams) (implicit p: Parameters) extends AbstractOutputUnit(inParams, ingressParams, cParam)(p) { class OutputUnitIO extends AbstractOutputUnitIO(inParams, ingressParams, cParam) { val out = new Channel(cParam.asInstanceOf[ChannelParams]) } val io = IO(new OutputUnitIO) class OutputState(val bufferSize: Int) extends Bundle { val occupied = Bool() val c = UInt(log2Up(1+bufferSize).W) val flow = new FlowRoutingBundle } val states = Reg(MixedVec(cParam.virtualChannelParams.map { u => new OutputState(u.bufferSize) })) (states zip io.channel_status).map { case (s,a) => a.occupied := s.occupied a.flow := s.flow } io.out.flit := io.in states.zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) { when (io.out.vc_free(i)) { assert(s.occupied) s.occupied := false.B } } } (states zip io.allocs).zipWithIndex.map { case ((s,a),i) => if (cParam.virtualChannelParams(i).traversable) { when (a.alloc) { s.occupied := true.B s.flow := a.flow } } } (io.credit_available zip states).zipWithIndex.map { case ((c,s),i) => c := s.c =/= 0.U //|| (io.out.credit_return.valid && io.out.credit_return.bits === i.U) } states.zipWithIndex.map { case (s,i) => val free = io.out.credit_return(i) val alloc = io.credit_alloc(i).alloc if (cParam.virtualChannelParams(i).traversable) { s.c := s.c +& free - alloc } } when (reset.asBool) { states.foreach(_.occupied := false.B) states.foreach(s => s.c := s.bufferSize.U) } }
module OutputUnit_4( // @[OutputUnit.scala:52:7] input clock, // @[OutputUnit.scala:52:7] input reset, // @[OutputUnit.scala:52:7] input io_in_0_valid, // @[OutputUnit.scala:58:14] input io_in_0_bits_head, // @[OutputUnit.scala:58:14] input io_in_0_bits_tail, // @[OutputUnit.scala:58:14] input [72:0] io_in_0_bits_payload, // @[OutputUnit.scala:58:14] input [2:0] io_in_0_bits_flow_vnet_id, // @[OutputUnit.scala:58:14] input [3:0] io_in_0_bits_flow_ingress_node, // @[OutputUnit.scala:58:14] input [2:0] io_in_0_bits_flow_ingress_node_id, // @[OutputUnit.scala:58:14] input [3:0] io_in_0_bits_flow_egress_node, // @[OutputUnit.scala:58:14] input [2:0] io_in_0_bits_flow_egress_node_id, // @[OutputUnit.scala:58:14] input [3:0] io_in_0_bits_virt_channel_id, // @[OutputUnit.scala:58:14] output io_credit_available_0, // @[OutputUnit.scala:58:14] output io_credit_available_1, // @[OutputUnit.scala:58:14] output io_credit_available_3, // @[OutputUnit.scala:58:14] output io_credit_available_4, // @[OutputUnit.scala:58:14] output io_credit_available_5, // @[OutputUnit.scala:58:14] output io_credit_available_8, // @[OutputUnit.scala:58:14] output io_credit_available_9, // @[OutputUnit.scala:58:14] output io_channel_status_0_occupied, // @[OutputUnit.scala:58:14] output io_channel_status_1_occupied, // @[OutputUnit.scala:58:14] output io_channel_status_3_occupied, // @[OutputUnit.scala:58:14] output io_channel_status_4_occupied, // @[OutputUnit.scala:58:14] output io_channel_status_5_occupied, // @[OutputUnit.scala:58:14] output io_channel_status_8_occupied, // @[OutputUnit.scala:58:14] output io_channel_status_9_occupied, // @[OutputUnit.scala:58:14] input io_allocs_0_alloc, // @[OutputUnit.scala:58:14] input io_allocs_1_alloc, // @[OutputUnit.scala:58:14] input io_allocs_3_alloc, // @[OutputUnit.scala:58:14] input io_allocs_4_alloc, // @[OutputUnit.scala:58:14] input io_allocs_5_alloc, // @[OutputUnit.scala:58:14] input io_allocs_8_alloc, // @[OutputUnit.scala:58:14] input io_allocs_9_alloc, // @[OutputUnit.scala:58:14] input io_credit_alloc_0_alloc, // @[OutputUnit.scala:58:14] input io_credit_alloc_1_alloc, // @[OutputUnit.scala:58:14] input io_credit_alloc_3_alloc, // @[OutputUnit.scala:58:14] input io_credit_alloc_4_alloc, // @[OutputUnit.scala:58:14] input io_credit_alloc_5_alloc, // @[OutputUnit.scala:58:14] input io_credit_alloc_8_alloc, // @[OutputUnit.scala:58:14] input io_credit_alloc_9_alloc, // @[OutputUnit.scala:58:14] output io_out_flit_0_valid, // @[OutputUnit.scala:58:14] output io_out_flit_0_bits_head, // @[OutputUnit.scala:58:14] output io_out_flit_0_bits_tail, // @[OutputUnit.scala:58:14] output [72:0] io_out_flit_0_bits_payload, // @[OutputUnit.scala:58:14] output [2:0] io_out_flit_0_bits_flow_vnet_id, // @[OutputUnit.scala:58:14] output [3:0] io_out_flit_0_bits_flow_ingress_node, // @[OutputUnit.scala:58:14] output [2:0] io_out_flit_0_bits_flow_ingress_node_id, // @[OutputUnit.scala:58:14] output [3:0] io_out_flit_0_bits_flow_egress_node, // @[OutputUnit.scala:58:14] output [2:0] io_out_flit_0_bits_flow_egress_node_id, // @[OutputUnit.scala:58:14] output [3:0] io_out_flit_0_bits_virt_channel_id, // @[OutputUnit.scala:58:14] input [9:0] io_out_credit_return, // @[OutputUnit.scala:58:14] input [9:0] io_out_vc_free // @[OutputUnit.scala:58:14] ); reg states_9_occupied; // @[OutputUnit.scala:66:19] reg [2:0] states_9_c; // @[OutputUnit.scala:66:19] reg states_8_occupied; // @[OutputUnit.scala:66:19] reg [2:0] states_8_c; // @[OutputUnit.scala:66:19] reg states_5_occupied; // @[OutputUnit.scala:66:19] reg [2:0] states_5_c; // @[OutputUnit.scala:66:19] reg states_4_occupied; // @[OutputUnit.scala:66:19] reg [2:0] states_4_c; // @[OutputUnit.scala:66:19] reg states_3_occupied; // @[OutputUnit.scala:66:19] reg [2:0] states_3_c; // @[OutputUnit.scala:66:19] reg states_1_occupied; // @[OutputUnit.scala:66:19] reg [2:0] states_1_c; // @[OutputUnit.scala:66:19] reg states_0_occupied; // @[OutputUnit.scala:66:19] reg [2:0] states_0_c; // @[OutputUnit.scala:66:19]
Generate the Verilog code corresponding to the following Chisel files. File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def *(t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def *(t: UInt) = self * t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros | ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def *(t: SInt) = self * t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros | ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid || output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def *(t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def *(t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } } File AccumulatorMem.scala: package gemmini import chisel3._ import chisel3.util._ import Util._ class AccumulatorReadReq[T <: Data: Arithmetic, U <: Data](n: Int, acc_t: T, scale_t: U) extends Bundle { val addr = UInt(log2Ceil(n).W) val scale = scale_t val igelu_qb = acc_t.cloneType val igelu_qc = acc_t.cloneType val iexp_qln2 = acc_t.cloneType val iexp_qln2_inv = acc_t.cloneType val act = UInt(Activation.bitwidth.W) // TODO magic number val full = Bool() // Whether or not we return the full bitwidth output val fromDMA = Bool() } class AccumulatorReadResp[T <: Data: Arithmetic, U <: Data](fullDataType: Vec[Vec[T]], scale_t: U) extends Bundle { val data = fullDataType.cloneType val fromDMA = Bool() val scale = scale_t.cloneType val igelu_qb = fullDataType.head.head.cloneType val igelu_qc = fullDataType.head.head.cloneType val iexp_qln2 = fullDataType.head.head.cloneType val iexp_qln2_inv = fullDataType.head.head.cloneType val act = UInt(Activation.bitwidth.W) // TODO magic number val acc_bank_id = UInt(2.W) // TODO magic number } class AccumulatorReadIO[T <: Data: Arithmetic, U <: Data](n: Int, fullDataType: Vec[Vec[T]], scale_t: U) extends Bundle { val req = Decoupled(new AccumulatorReadReq[T, U](n, fullDataType.head.head.cloneType, scale_t)) val resp = Flipped(Decoupled(new AccumulatorReadResp[T, U](fullDataType, scale_t))) } class AccumulatorWriteReq[T <: Data: Arithmetic](n: Int, t: Vec[Vec[T]]) extends Bundle { val addr = UInt(log2Up(n).W) val data = t.cloneType val acc = Bool() val mask = Vec(t.getWidth / 8, Bool()) // TODO Use aligned_to here } class AccumulatorMemIO [T <: Data: Arithmetic, U <: Data](n: Int, t: Vec[Vec[T]], scale_t: U, acc_sub_banks: Int, use_shared_ext_mem: Boolean ) extends Bundle { val read = Flipped(new AccumulatorReadIO(n, t, scale_t)) val write = Flipped(Decoupled(new AccumulatorWriteReq(n, t))) val ext_mem = if (use_shared_ext_mem) Some(Vec(acc_sub_banks, new ExtMemIO)) else None val adder = new Bundle { val valid = Output(Bool()) val op1 = Output(t.cloneType) val op2 = Output(t.cloneType) val sum = Input(t.cloneType) } } class AccPipe[T <: Data : Arithmetic](latency: Int, t: T)(implicit ev: Arithmetic[T]) extends Module { val io = IO(new Bundle { val op1 = Input(t.cloneType) val op2 = Input(t.cloneType) val sum = Output(t.cloneType) }) import ev._ io.sum := ShiftRegister(io.op1 + io.op2, latency) } class AccPipeShared[T <: Data : Arithmetic](latency: Int, t: Vec[Vec[T]], banks: Int) extends Module { val io = IO(new Bundle { val in_sel = Input(Vec(banks, Bool())) val ina = Input(Vec(banks, t.cloneType)) val inb = Input(Vec(banks, t.cloneType)) val out = Output(t.cloneType) }) val ina = Mux1H(io.in_sel, io.ina) val inb = Mux1H(io.in_sel, io.inb) io.out := VecInit((ina zip inb).map { case (rv, wv) => VecInit((rv zip wv).map { case (re, we) => val m = Module(new AccPipe(latency, t.head.head.cloneType)) m.io.op1 := re m.io.op2 := we m.io.sum }) }) } class AccumulatorMem[T <: Data, U <: Data]( n: Int, t: Vec[Vec[T]], scale_func: (T, U) => T, scale_t: U, acc_singleported: Boolean, acc_sub_banks: Int, use_shared_ext_mem: Boolean, acc_latency: Int, acc_type: T, is_dummy: Boolean ) (implicit ev: Arithmetic[T]) extends Module { // TODO Do writes in this module work with matrices of size 2? If we try to read from an address right after writing // to it, then we might not get the written data. We might need some kind of cooldown counter after addresses in the // accumulator have been written to for configurations with such small matrices // TODO make a new aligned_to variable specifically for AccumulatorMem. We should assume that inputs are at least // accType.getWidth/8 aligned, because it won't make sense to do matrix additions directly in the DMA otherwise. import ev._ // TODO unify this with TwoPortSyncMemIO val io = IO(new AccumulatorMemIO(n, t, scale_t, acc_sub_banks, use_shared_ext_mem)) require (acc_latency >= 2) val pipelined_writes = Reg(Vec(acc_latency, Valid(new AccumulatorWriteReq(n, t)))) val oldest_pipelined_write = pipelined_writes(acc_latency-1) pipelined_writes(0).valid := io.write.fire pipelined_writes(0).bits := io.write.bits for (i <- 1 until acc_latency) { pipelined_writes(i) := pipelined_writes(i-1) } val rdata_for_adder = Wire(t) rdata_for_adder := DontCare val rdata_for_read_resp = Wire(t) rdata_for_read_resp := DontCare val adder_sum = io.adder.sum io.adder.valid := pipelined_writes(0).valid && pipelined_writes(0).bits.acc io.adder.op1 := rdata_for_adder io.adder.op2 := pipelined_writes(0).bits.data val block_read_req = WireInit(false.B) val block_write_req = WireInit(false.B) val mask_len = t.getWidth / 8 val mask_elem = UInt((t.getWidth / mask_len).W) if (!acc_singleported && !is_dummy) { require(!use_shared_ext_mem) val mem = TwoPortSyncMem(n, t, mask_len) // TODO We assume byte-alignment here. Use aligned_to instead mem.io.waddr := oldest_pipelined_write.bits.addr mem.io.wen := oldest_pipelined_write.valid mem.io.wdata := Mux(oldest_pipelined_write.bits.acc, adder_sum, oldest_pipelined_write.bits.data) mem.io.mask := oldest_pipelined_write.bits.mask rdata_for_adder := mem.io.rdata rdata_for_read_resp := mem.io.rdata mem.io.raddr := Mux(io.write.fire && io.write.bits.acc, io.write.bits.addr, io.read.req.bits.addr) mem.io.ren := io.read.req.fire || (io.write.fire && io.write.bits.acc) } else if (!is_dummy) { val rmw_req = Wire(Decoupled(UInt())) rmw_req.valid := io.write.valid && io.write.bits.acc rmw_req.bits := io.write.bits.addr rmw_req.ready := true.B block_write_req := !rmw_req.ready val only_read_req = Wire(Decoupled(UInt())) only_read_req.valid := io.read.req.valid only_read_req.bits := io.read.req.bits.addr only_read_req.ready := true.B block_read_req := !only_read_req.ready for (i <- 0 until acc_sub_banks) { def isThisBank(addr: UInt) = addr(log2Ceil(acc_sub_banks)-1,0) === i.U def getBankIdx(addr: UInt) = addr >> log2Ceil(acc_sub_banks) val (read, write) = if (use_shared_ext_mem) { def read(addr: UInt, ren: Bool): Data = { io.ext_mem.get(i).read_en := ren io.ext_mem.get(i).read_addr := addr io.ext_mem.get(i).read_data } io.ext_mem.get(i).write_en := false.B io.ext_mem.get(i).write_addr := DontCare io.ext_mem.get(i).write_data := DontCare io.ext_mem.get(i).write_mask := DontCare def write(addr: UInt, wdata: Vec[UInt], wmask: Vec[Bool]) = { io.ext_mem.get(i).write_en := true.B io.ext_mem.get(i).write_addr := addr io.ext_mem.get(i).write_data := wdata.asUInt io.ext_mem.get(i).write_mask := wmask.asUInt } (read _, write _) } else { val mem = SyncReadMem(n / acc_sub_banks, Vec(mask_len, mask_elem)) def read(addr: UInt, ren: Bool): Data = mem.read(addr, ren) def write(addr: UInt, wdata: Vec[UInt], wmask: Vec[Bool]) = mem.write(addr, wdata, wmask) (read _, write _) } val ren = WireInit(false.B) val raddr = WireInit(getBankIdx(rmw_req.bits)) val nEntries = 3 // Writes coming 2 cycles after read leads to bad bank behavior // Add another buffer here class W_Q_Entry[T <: Data](mask_len: Int, mask_elem: T) extends Bundle { val valid = Bool() val data = Vec(mask_len, mask_elem) val mask = Vec(mask_len, Bool()) val addr = UInt(log2Ceil(n/acc_sub_banks).W) } val w_q = Reg(Vec(nEntries, new W_Q_Entry(mask_len, mask_elem))) for (e <- w_q) { when (e.valid) { assert(!( io.write.fire && io.write.bits.acc && isThisBank(io.write.bits.addr) && getBankIdx(io.write.bits.addr) === e.addr && ((io.write.bits.mask.asUInt & e.mask.asUInt) =/= 0.U) ), "you cannot accumulate to an AccumulatorMem address until previous writes to that address have completed") when (io.write.bits.acc && isThisBank(io.write.bits.addr) && getBankIdx(io.write.bits.addr) === e.addr) { rmw_req.ready := false.B } when (isThisBank(io.read.req.bits.addr) && getBankIdx(io.read.req.bits.addr) === e.addr) { only_read_req.ready := false.B } } } val w_q_head = RegInit(1.U(nEntries.W)) val w_q_tail = RegInit(1.U(nEntries.W)) val w_q_full = (w_q_tail.asBools zip w_q.map(_.valid)).map({ case (h,v) => h && v }).reduce(_||_) val w_q_empty = !(w_q_head.asBools zip w_q.map(_.valid)).map({ case (h,v) => h && v }).reduce(_||_) val wen = WireInit(false.B) val wdata = Mux1H(w_q_head.asBools, w_q.map(_.data)) val wmask = Mux1H(w_q_head.asBools, w_q.map(_.mask)) val waddr = Mux1H(w_q_head.asBools, w_q.map(_.addr)) when (wen) { w_q_head := (w_q_head << 1).asUInt | w_q_head(nEntries-1) for (i <- 0 until nEntries) { when (w_q_head(i)) { w_q(i).valid := false.B } } } val w_q_push = oldest_pipelined_write.valid && isThisBank(oldest_pipelined_write.bits.addr) when (w_q_push) { assert(!w_q_full || wen, "we ran out of acc-sub-bank write q entries") w_q_tail := (w_q_tail << 1).asUInt | w_q_tail(nEntries-1) for (i <- 0 until nEntries) { when (w_q_tail(i)) { w_q(i).valid := true.B w_q(i).data := Mux(oldest_pipelined_write.bits.acc, adder_sum, oldest_pipelined_write.bits.data).asTypeOf(Vec(mask_len, mask_elem)) w_q(i).mask := oldest_pipelined_write.bits.mask w_q(i).addr := getBankIdx(oldest_pipelined_write.bits.addr) } } } val bank_rdata = read(raddr, ren && !wen).asTypeOf(t) when (RegNext(ren && rmw_req.valid && isThisBank(rmw_req.bits))) { rdata_for_adder := bank_rdata } .elsewhen (RegNext(ren)) { rdata_for_read_resp := bank_rdata } when (wen) { write(waddr, wdata, wmask) } // Three requestors, 1 slot // Priority is (in descending order): // 1. incoming reads for RMW // 2. writes from RMW // 3. incoming reads when (rmw_req.fire && isThisBank(rmw_req.bits)) { ren := true.B when (isThisBank(only_read_req.bits)) { only_read_req.ready := false.B } } .elsewhen (!w_q_empty) { wen := true.B when (isThisBank(only_read_req.bits)) { only_read_req.ready := false.B } } .otherwise { ren := isThisBank(only_read_req.bits) && only_read_req.fire raddr := getBankIdx(only_read_req.bits) } when (reset.asBool) { w_q.foreach(_.valid := false.B) } } } val q = Module(new Queue(new AccumulatorReadResp(t, scale_t), 1, true, true)) q.io.enq.bits.data := rdata_for_read_resp if (is_dummy) { rdata_for_read_resp := DontCare rdata_for_adder := DontCare } q.io.enq.bits.scale := RegNext(io.read.req.bits.scale) q.io.enq.bits.igelu_qb := RegNext(io.read.req.bits.igelu_qb) q.io.enq.bits.igelu_qc := RegNext(io.read.req.bits.igelu_qc) q.io.enq.bits.iexp_qln2 := RegNext(io.read.req.bits.iexp_qln2) q.io.enq.bits.iexp_qln2_inv := RegNext(io.read.req.bits.iexp_qln2_inv) q.io.enq.bits.act := RegNext(io.read.req.bits.act) q.io.enq.bits.fromDMA := RegNext(io.read.req.bits.fromDMA) q.io.enq.bits.acc_bank_id := DontCare q.io.enq.valid := RegNext(io.read.req.fire) val p = q.io.deq io.read.resp.bits.data := p.bits.data io.read.resp.bits.fromDMA := p.bits.fromDMA io.read.resp.bits.igelu_qb := p.bits.igelu_qb io.read.resp.bits.igelu_qc := p.bits.igelu_qc io.read.resp.bits.iexp_qln2 := p.bits.iexp_qln2 io.read.resp.bits.iexp_qln2_inv := p.bits.iexp_qln2_inv io.read.resp.bits.act := p.bits.act io.read.resp.bits.scale := p.bits.scale io.read.resp.bits.acc_bank_id := DontCare // This is set in Scratchpad io.read.resp.valid := p.valid p.ready := io.read.resp.ready val q_will_be_empty = (q.io.count +& q.io.enq.fire) - q.io.deq.fire === 0.U io.read.req.ready := q_will_be_empty && ( // Make sure we aren't accumulating, which would take over both ports !(io.write.valid && io.write.bits.acc) && !pipelined_writes.map(r => r.valid && r.bits.addr === io.read.req.bits.addr).reduce(_||_) && !block_read_req ) io.write.ready := !block_write_req && !pipelined_writes.map(r => r.valid && r.bits.addr === io.write.bits.addr && io.write.bits.acc).reduce(_||_) when (reset.asBool) { pipelined_writes.foreach(_.valid := false.B) } // assert(!(io.read.req.valid && io.write.en && io.write.acc), "reading and accumulating simultaneously is not supported") assert(!(io.read.req.fire && io.write.fire && io.read.req.bits.addr === io.write.bits.addr), "reading from and writing to same address is not supported") }
module AccPipe_6( // @[AccumulatorMem.scala:63:7] input clock, // @[AccumulatorMem.scala:63:7] input reset, // @[AccumulatorMem.scala:63:7] input [31:0] io_op1, // @[AccumulatorMem.scala:64:14] input [31:0] io_op2, // @[AccumulatorMem.scala:64:14] output [31:0] io_sum // @[AccumulatorMem.scala:64:14] ); wire [31:0] io_op1_0 = io_op1; // @[AccumulatorMem.scala:63:7] wire [31:0] io_op2_0 = io_op2; // @[AccumulatorMem.scala:63:7] wire [31:0] io_sum_0; // @[AccumulatorMem.scala:63:7] wire [32:0] _io_sum_T = {io_op1_0[31], io_op1_0} + {io_op2_0[31], io_op2_0}; // @[Arithmetic.scala:94:38] wire [31:0] _io_sum_T_1 = _io_sum_T[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _io_sum_T_2 = _io_sum_T_1; // @[Arithmetic.scala:94:38] reg [31:0] io_sum_r; // @[AccumulatorMem.scala:70:26] assign io_sum_0 = io_sum_r; // @[AccumulatorMem.scala:63:7, :70:26] always @(posedge clock) // @[AccumulatorMem.scala:63:7] io_sum_r <= _io_sum_T_2; // @[Arithmetic.scala:94:38] assign io_sum = io_sum_0; // @[AccumulatorMem.scala:63:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File MulRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (ported from Verilog to Chisel by Andrew Waterman). Copyright 2019, 2020 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulFullRawFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val a = Input(new RawFloat(expWidth, sigWidth)) val b = Input(new RawFloat(expWidth, sigWidth)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth*2 - 1)) }) /*------------------------------------------------------------------------ *------------------------------------------------------------------------*/ val notSigNaN_invalidExc = (io.a.isInf && io.b.isZero) || (io.a.isZero && io.b.isInf) val notNaN_isInfOut = io.a.isInf || io.b.isInf val notNaN_isZeroOut = io.a.isZero || io.b.isZero val notNaN_signOut = io.a.sign ^ io.b.sign val common_sExpOut = io.a.sExp + io.b.sExp - (1<<expWidth).S val common_sigOut = (io.a.sig * io.b.sig)(sigWidth*2 - 1, 0) /*------------------------------------------------------------------------ *------------------------------------------------------------------------*/ io.invalidExc := isSigNaNRawFloat(io.a) || isSigNaNRawFloat(io.b) || notSigNaN_invalidExc io.rawOut.isInf := notNaN_isInfOut io.rawOut.isZero := notNaN_isZeroOut io.rawOut.sExp := common_sExpOut io.rawOut.isNaN := io.a.isNaN || io.b.isNaN io.rawOut.sign := notNaN_signOut io.rawOut.sig := common_sigOut } class MulRawFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val a = Input(new RawFloat(expWidth, sigWidth)) val b = Input(new RawFloat(expWidth, sigWidth)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth + 2)) }) val mulFullRaw = Module(new MulFullRawFN(expWidth, sigWidth)) mulFullRaw.io.a := io.a mulFullRaw.io.b := io.b io.invalidExc := mulFullRaw.io.invalidExc io.rawOut := mulFullRaw.io.rawOut io.rawOut.sig := { val sig = mulFullRaw.io.rawOut.sig Cat(sig >> (sigWidth - 2), sig(sigWidth - 3, 0).orR) } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulRecFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val a = Input(UInt((expWidth + sigWidth + 1).W)) val b = Input(UInt((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(Bool()) val out = Output(UInt((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(UInt(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulRawFN = Module(new MulRawFN(expWidth, sigWidth)) mulRawFN.io.a := rawFloatFromRecFN(expWidth, sigWidth, io.a) mulRawFN.io.b := rawFloatFromRecFN(expWidth, sigWidth, io.b) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0)) roundRawFNToRecFN.io.invalidExc := mulRawFN.io.invalidExc roundRawFNToRecFN.io.infiniteExc := false.B roundRawFNToRecFN.io.in := mulRawFN.io.rawOut roundRawFNToRecFN.io.roundingMode := io.roundingMode roundRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags }
module MulFullRawFN_33( // @[MulRecFN.scala:47:7] input io_a_isNaN, // @[MulRecFN.scala:49:16] input io_a_isInf, // @[MulRecFN.scala:49:16] input io_a_isZero, // @[MulRecFN.scala:49:16] input io_a_sign, // @[MulRecFN.scala:49:16] input [9:0] io_a_sExp, // @[MulRecFN.scala:49:16] input [24:0] io_a_sig, // @[MulRecFN.scala:49:16] input io_b_isNaN, // @[MulRecFN.scala:49:16] input io_b_isInf, // @[MulRecFN.scala:49:16] input io_b_isZero, // @[MulRecFN.scala:49:16] input io_b_sign, // @[MulRecFN.scala:49:16] input [9:0] io_b_sExp, // @[MulRecFN.scala:49:16] input [24:0] io_b_sig, // @[MulRecFN.scala:49:16] output io_invalidExc, // @[MulRecFN.scala:49:16] output io_rawOut_isNaN, // @[MulRecFN.scala:49:16] output io_rawOut_isInf, // @[MulRecFN.scala:49:16] output io_rawOut_isZero, // @[MulRecFN.scala:49:16] output io_rawOut_sign, // @[MulRecFN.scala:49:16] output [9:0] io_rawOut_sExp, // @[MulRecFN.scala:49:16] output [47:0] io_rawOut_sig // @[MulRecFN.scala:49:16] ); wire io_a_isNaN_0 = io_a_isNaN; // @[MulRecFN.scala:47:7] wire io_a_isInf_0 = io_a_isInf; // @[MulRecFN.scala:47:7] wire io_a_isZero_0 = io_a_isZero; // @[MulRecFN.scala:47:7] wire io_a_sign_0 = io_a_sign; // @[MulRecFN.scala:47:7] wire [9:0] io_a_sExp_0 = io_a_sExp; // @[MulRecFN.scala:47:7] wire [24:0] io_a_sig_0 = io_a_sig; // @[MulRecFN.scala:47:7] wire io_b_isNaN_0 = io_b_isNaN; // @[MulRecFN.scala:47:7] wire io_b_isInf_0 = io_b_isInf; // @[MulRecFN.scala:47:7] wire io_b_isZero_0 = io_b_isZero; // @[MulRecFN.scala:47:7] wire io_b_sign_0 = io_b_sign; // @[MulRecFN.scala:47:7] wire [9:0] io_b_sExp_0 = io_b_sExp; // @[MulRecFN.scala:47:7] wire [24:0] io_b_sig_0 = io_b_sig; // @[MulRecFN.scala:47:7] wire _io_invalidExc_T_7; // @[MulRecFN.scala:66:71] wire _io_rawOut_isNaN_T; // @[MulRecFN.scala:70:35] wire notNaN_isInfOut; // @[MulRecFN.scala:59:38] wire notNaN_isZeroOut; // @[MulRecFN.scala:60:40] wire notNaN_signOut; // @[MulRecFN.scala:61:36] wire [9:0] common_sExpOut; // @[MulRecFN.scala:62:48] wire [47:0] common_sigOut; // @[MulRecFN.scala:63:46] wire io_rawOut_isNaN_0; // @[MulRecFN.scala:47:7] wire io_rawOut_isInf_0; // @[MulRecFN.scala:47:7] wire io_rawOut_isZero_0; // @[MulRecFN.scala:47:7] wire io_rawOut_sign_0; // @[MulRecFN.scala:47:7] wire [9:0] io_rawOut_sExp_0; // @[MulRecFN.scala:47:7] wire [47:0] io_rawOut_sig_0; // @[MulRecFN.scala:47:7] wire io_invalidExc_0; // @[MulRecFN.scala:47:7] wire _notSigNaN_invalidExc_T = io_a_isInf_0 & io_b_isZero_0; // @[MulRecFN.scala:47:7, :58:44] wire _notSigNaN_invalidExc_T_1 = io_a_isZero_0 & io_b_isInf_0; // @[MulRecFN.scala:47:7, :58:76] wire notSigNaN_invalidExc = _notSigNaN_invalidExc_T | _notSigNaN_invalidExc_T_1; // @[MulRecFN.scala:58:{44,60,76}] assign notNaN_isInfOut = io_a_isInf_0 | io_b_isInf_0; // @[MulRecFN.scala:47:7, :59:38] assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulRecFN.scala:47:7, :59:38] assign notNaN_isZeroOut = io_a_isZero_0 | io_b_isZero_0; // @[MulRecFN.scala:47:7, :60:40] assign io_rawOut_isZero_0 = notNaN_isZeroOut; // @[MulRecFN.scala:47:7, :60:40] assign notNaN_signOut = io_a_sign_0 ^ io_b_sign_0; // @[MulRecFN.scala:47:7, :61:36] assign io_rawOut_sign_0 = notNaN_signOut; // @[MulRecFN.scala:47:7, :61:36] wire [10:0] _common_sExpOut_T = {io_a_sExp_0[9], io_a_sExp_0} + {io_b_sExp_0[9], io_b_sExp_0}; // @[MulRecFN.scala:47:7, :62:36] wire [9:0] _common_sExpOut_T_1 = _common_sExpOut_T[9:0]; // @[MulRecFN.scala:62:36] wire [9:0] _common_sExpOut_T_2 = _common_sExpOut_T_1; // @[MulRecFN.scala:62:36] wire [10:0] _common_sExpOut_T_3 = {_common_sExpOut_T_2[9], _common_sExpOut_T_2} - 11'h100; // @[MulRecFN.scala:62:{36,48}] wire [9:0] _common_sExpOut_T_4 = _common_sExpOut_T_3[9:0]; // @[MulRecFN.scala:62:48] assign common_sExpOut = _common_sExpOut_T_4; // @[MulRecFN.scala:62:48] assign io_rawOut_sExp_0 = common_sExpOut; // @[MulRecFN.scala:47:7, :62:48] wire [49:0] _common_sigOut_T = {25'h0, io_a_sig_0} * {25'h0, io_b_sig_0}; // @[MulRecFN.scala:47:7, :63:35] assign common_sigOut = _common_sigOut_T[47:0]; // @[MulRecFN.scala:63:{35,46}] assign io_rawOut_sig_0 = common_sigOut; // @[MulRecFN.scala:47:7, :63:46] wire _io_invalidExc_T = io_a_sig_0[22]; // @[common.scala:82:56] wire _io_invalidExc_T_1 = ~_io_invalidExc_T; // @[common.scala:82:{49,56}] wire _io_invalidExc_T_2 = io_a_isNaN_0 & _io_invalidExc_T_1; // @[common.scala:82:{46,49}] wire _io_invalidExc_T_3 = io_b_sig_0[22]; // @[common.scala:82:56] wire _io_invalidExc_T_4 = ~_io_invalidExc_T_3; // @[common.scala:82:{49,56}] wire _io_invalidExc_T_5 = io_b_isNaN_0 & _io_invalidExc_T_4; // @[common.scala:82:{46,49}] wire _io_invalidExc_T_6 = _io_invalidExc_T_2 | _io_invalidExc_T_5; // @[common.scala:82:46] assign _io_invalidExc_T_7 = _io_invalidExc_T_6 | notSigNaN_invalidExc; // @[MulRecFN.scala:58:60, :66:{45,71}] assign io_invalidExc_0 = _io_invalidExc_T_7; // @[MulRecFN.scala:47:7, :66:71] assign _io_rawOut_isNaN_T = io_a_isNaN_0 | io_b_isNaN_0; // @[MulRecFN.scala:47:7, :70:35] assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulRecFN.scala:47:7, :70:35] assign io_invalidExc = io_invalidExc_0; // @[MulRecFN.scala:47:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulRecFN.scala:47:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulRecFN.scala:47:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulRecFN.scala:47:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[MulRecFN.scala:47:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulRecFN.scala:47:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[MulRecFN.scala:47:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} |acquireB = ${acquireB} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT || supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED || supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED || supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB || supportsGet, w = supportsAcquireT || supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} |Slave Address = ${address} |supports = ${supports.infoString} | |""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ || _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_||_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ || _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B || s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_||_) }.foldLeft(false.B)(_||_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} |visibility = ${visibility} |emits = ${emits.infoString} |sourceId = ${sourceId} | |""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ || _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ || _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ || _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ || _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ || _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ || _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ || _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ || _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_||_) }.foldLeft(false.B)(_||_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE || x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps */ class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_36( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [255:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [255:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_c_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [4:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [255:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [4:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [255:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7] wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7] wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [255:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [4:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [255:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [4:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire io_in_e_ready = 1'h1; // @[Monitor.scala:36:7] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_28 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_30 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_34 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_36 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_49 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_61 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_63 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_67 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_69 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_74 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_76 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_80 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_82 = 1'h1; // @[Parameters.scala:57:20] wire mask_sub_sub_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_4_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_5_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_6_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_7_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_4_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_5_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_6_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_7_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_8_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_9_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_10_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_11_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_12_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_13_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_14_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_15_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_acc_32 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_33 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_34 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_35 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_36 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_37 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_38 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_39 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_40 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_41 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_42 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_43 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_44 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_45 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_46 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_47 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_48 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_49 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_50 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_51 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_52 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_53 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_54 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_55 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_56 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_57 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_58 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_59 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_60 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_61 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_62 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_63 = 1'h1; // @[Misc.scala:215:29] wire _legal_source_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_25 = 1'h1; // @[Parameters.scala:46:9] wire _legal_source_T_28 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_30 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_34 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_36 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_WIRE_5 = 1'h1; // @[Parameters.scala:1138:31] wire legal_source = 1'h1; // @[Monitor.scala:168:113] wire _source_ok_T_95 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_97 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_101 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_103 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_107 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_109 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_113 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_115 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_120 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_122 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_126 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_128 = 1'h1; // @[Parameters.scala:57:20] wire b_first_beats1_decode = 1'h1; // @[Edges.scala:220:59] wire _b_first_beats1_opdata_T = 1'h1; // @[Edges.scala:97:37] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire [7:0] io_in_b_bits_source = 8'h40; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_66 = 8'h40; // @[Parameters.scala:52:29] wire [7:0] _uncommonBits_T_67 = 8'h40; // @[Parameters.scala:52:29] wire [7:0] _uncommonBits_T_68 = 8'h40; // @[Parameters.scala:52:29] wire [7:0] _uncommonBits_T_69 = 8'h40; // @[Parameters.scala:52:29] wire [7:0] _uncommonBits_T_70 = 8'h40; // @[Parameters.scala:52:29] wire [7:0] _uncommonBits_T_71 = 8'h40; // @[Parameters.scala:52:29] wire [7:0] _mask_sizeOH_T_4 = 8'h40; // @[OneHot.scala:65:12] wire [7:0] _legal_source_uncommonBits_T = 8'h40; // @[Parameters.scala:52:29] wire [7:0] _legal_source_uncommonBits_T_1 = 8'h40; // @[Parameters.scala:52:29] wire [7:0] _legal_source_uncommonBits_T_2 = 8'h40; // @[Parameters.scala:52:29] wire [7:0] _legal_source_uncommonBits_T_3 = 8'h40; // @[Parameters.scala:52:29] wire [7:0] _legal_source_uncommonBits_T_4 = 8'h40; // @[Parameters.scala:52:29] wire [7:0] _legal_source_uncommonBits_T_5 = 8'h40; // @[Parameters.scala:52:29] wire [7:0] _legal_source_T_52 = 8'h40; // @[Mux.scala:30:73] wire [7:0] _legal_source_T_53 = 8'h40; // @[Mux.scala:30:73] wire [7:0] _legal_source_T_54 = 8'h40; // @[Mux.scala:30:73] wire [7:0] _legal_source_T_55 = 8'h40; // @[Mux.scala:30:73] wire [7:0] _legal_source_WIRE_1 = 8'h40; // @[Mux.scala:30:73] wire [7:0] _uncommonBits_T_72 = 8'h40; // @[Parameters.scala:52:29] wire [7:0] _uncommonBits_T_73 = 8'h40; // @[Parameters.scala:52:29] wire [7:0] _uncommonBits_T_74 = 8'h40; // @[Parameters.scala:52:29] wire [7:0] _uncommonBits_T_75 = 8'h40; // @[Parameters.scala:52:29] wire [7:0] _uncommonBits_T_76 = 8'h40; // @[Parameters.scala:52:29] wire [7:0] _uncommonBits_T_77 = 8'h40; // @[Parameters.scala:52:29] wire [2:0] io_in_b_bits_opcode = 3'h6; // @[Monitor.scala:36:7] wire [2:0] io_in_b_bits_size = 3'h6; // @[Monitor.scala:36:7] wire [2:0] mask_sizeOH_shiftAmount_1 = 3'h6; // @[OneHot.scala:64:49] wire [31:0] io_in_b_bits_mask = 32'hFFFFFFFF; // @[Monitor.scala:36:7] wire [31:0] mask_1 = 32'hFFFFFFFF; // @[Misc.scala:222:10] wire [255:0] io_in_b_bits_data = 256'h0; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire mask_sub_sub_sub_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_sub_sub_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_sub_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire mask_sub_sub_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_sub_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire mask_sub_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_sub_acc_T_8 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_acc_T_9 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_acc_T_10 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_acc_T_11 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_acc_T_12 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_acc_T_13 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_acc_T_14 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_acc_T_15 = 1'h0; // @[Misc.scala:215:38] wire mask_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T_16 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_17 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_18 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_19 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_20 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_21 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_22 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_23 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_24 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_25 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_26 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_27 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_28 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_29 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_30 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_31 = 1'h0; // @[Misc.scala:215:38] wire _legal_source_T = 1'h0; // @[Parameters.scala:46:9] wire _legal_source_T_2 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_4 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_6 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_8 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_10 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_12 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_14 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_16 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_18 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_20 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_22 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_24 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_27 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_29 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_31 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_33 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_35 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_37 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_38 = 1'h0; // @[Parameters.scala:46:9] wire _legal_source_WIRE_0 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_1_0 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_2 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_3 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_4 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_6 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_7 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_8 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_T_46 = 1'h0; // @[Mux.scala:30:73] wire b_first_beats1_opdata = 1'h0; // @[Edges.scala:97:28] wire b_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire b_first_count = 1'h0; // @[Edges.scala:234:25] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] _legal_source_T_26 = 3'h2; // @[Parameters.scala:54:10] wire [2:0] _legal_source_T_32 = 3'h2; // @[Parameters.scala:54:10] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [5:0] is_aligned_mask_1 = 6'h3F; // @[package.scala:243:46] wire [5:0] _b_first_beats1_decode_T_2 = 6'h3F; // @[package.scala:243:46] wire [5:0] _is_aligned_mask_T_3 = 6'h0; // @[package.scala:243:76] wire [5:0] _legal_source_T_45 = 6'h0; // @[Mux.scala:30:73] wire [5:0] _b_first_beats1_decode_T_1 = 6'h0; // @[package.scala:243:76] wire [12:0] _is_aligned_mask_T_2 = 13'hFC0; // @[package.scala:243:71] wire [12:0] _b_first_beats1_decode_T = 13'hFC0; // @[package.scala:243:71] wire [4:0] uncommonBits_70 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] uncommonBits_71 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] _mask_sizeOH_T_5 = 5'h0; // @[OneHot.scala:65:27] wire [4:0] legal_source_uncommonBits_4 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] legal_source_uncommonBits_5 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] uncommonBits_76 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] uncommonBits_77 = 5'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_66 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_67 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_68 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_69 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] legal_source_uncommonBits = 2'h0; // @[Parameters.scala:52:56] wire [1:0] legal_source_uncommonBits_1 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] legal_source_uncommonBits_2 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] legal_source_uncommonBits_3 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_72 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_73 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_74 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_75 = 2'h0; // @[Parameters.scala:52:56] wire [7:0] _legal_source_T_39 = 8'h0; // @[Mux.scala:30:73] wire [7:0] _legal_source_T_40 = 8'h0; // @[Mux.scala:30:73] wire [7:0] _legal_source_T_41 = 8'h0; // @[Mux.scala:30:73] wire [7:0] _legal_source_T_42 = 8'h0; // @[Mux.scala:30:73] wire [7:0] _legal_source_T_43 = 8'h0; // @[Mux.scala:30:73] wire [7:0] _legal_source_T_48 = 8'h0; // @[Mux.scala:30:73] wire [7:0] _legal_source_T_49 = 8'h0; // @[Mux.scala:30:73] wire [7:0] _legal_source_T_50 = 8'h0; // @[Mux.scala:30:73] wire [7:0] _legal_source_T_51 = 8'h0; // @[Mux.scala:30:73] wire [6:0] _legal_source_T_47 = 7'h0; // @[Mux.scala:30:73] wire [6:0] _legal_source_T_44 = 7'h40; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_1 = 6'h10; // @[Parameters.scala:54:10] wire [5:0] _legal_source_T_7 = 6'h10; // @[Parameters.scala:54:10] wire [5:0] _legal_source_T_13 = 6'h10; // @[Parameters.scala:54:10] wire [5:0] _legal_source_T_19 = 6'h10; // @[Parameters.scala:54:10] wire [15:0] mask_lo_1 = 16'hFFFF; // @[Misc.scala:222:10] wire [15:0] mask_hi_1 = 16'hFFFF; // @[Misc.scala:222:10] wire [7:0] mask_lo_lo_1 = 8'hFF; // @[Misc.scala:222:10] wire [7:0] mask_lo_hi_1 = 8'hFF; // @[Misc.scala:222:10] wire [7:0] mask_hi_lo_1 = 8'hFF; // @[Misc.scala:222:10] wire [7:0] mask_hi_hi_1 = 8'hFF; // @[Misc.scala:222:10] wire [3:0] mask_lo_lo_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_lo_lo_hi_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_lo_hi_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_lo_hi_hi_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_lo_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_lo_hi_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_hi_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_hi_hi_1 = 4'hF; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_hi_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_hi_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_hi_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_hi_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_hi_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_hi_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_hi_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_hi_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [4:0] mask_sizeOH_1 = 5'h1; // @[Misc.scala:202:81] wire [4:0] _mask_sizeOH_T_3 = 5'h6; // @[Misc.scala:202:34] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [7:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_12 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_13 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_14 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_15 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_16 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_17 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_78 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_79 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_80 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_81 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_82 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_83 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_84 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_85 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_86 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_87 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_88 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_89 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_90 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_91 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_92 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_93 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_94 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_95 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_96 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_97 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_98 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_99 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_100 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_101 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_102 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_103 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_104 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_105 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_106 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_107 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 8'h90; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] _source_ok_T_1 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_7 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_13 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_19 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 6'h20; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 6'h21; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 6'h22; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 6'h23; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 8'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[4:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_26 = io_in_a_bits_source_0[7:5]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_32 = io_in_a_bits_source_0[7:5]; // @[Monitor.scala:36:7] wire _source_ok_T_27 = _source_ok_T_26 == 3'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_29 = _source_ok_T_27; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_31 = _source_ok_T_29; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_6 = _source_ok_T_31; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_33 = _source_ok_T_32 == 3'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_35 = _source_ok_T_33; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_37 = _source_ok_T_35; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_7 = _source_ok_T_37; // @[Parameters.scala:1138:31] wire _source_ok_T_38 = io_in_a_bits_source_0 == 8'h42; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_38; // @[Parameters.scala:1138:31] wire _source_ok_T_39 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_40 = _source_ok_T_39 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_41 = _source_ok_T_40 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_42 = _source_ok_T_41 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_43 = _source_ok_T_42 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_44 = _source_ok_T_43 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_45 = _source_ok_T_44 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_45 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [4:0] _mask_sizeOH_T = {2'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [2:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[2:0]; // @[OneHot.scala:64:49] wire [7:0] _mask_sizeOH_T_1 = 8'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [4:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[4:0]; // @[OneHot.scala:65:{12,27}] wire [4:0] mask_sizeOH = {_mask_sizeOH_T_2[4:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h4; // @[Misc.scala:206:21] wire mask_sub_sub_sub_sub_size = mask_sizeOH[4]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_sub_bit = io_in_a_bits_address_0[4]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_sub_1_2 = mask_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_sub_nbit = ~mask_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_sub_0_2 = mask_sub_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_sub_acc_T = mask_sub_sub_sub_sub_size & mask_sub_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_sub_size & mask_sub_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_sub_sub_size = mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_sub_0_2 & mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T = mask_sub_sub_sub_size & mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_sub_0_2 & mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_size & mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_2_2 = mask_sub_sub_sub_sub_1_2 & mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T_2 = mask_sub_sub_sub_size & mask_sub_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_2_1 = mask_sub_sub_sub_sub_1_1 | _mask_sub_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_3_2 = mask_sub_sub_sub_sub_1_2 & mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_sub_acc_T_3 = mask_sub_sub_sub_size & mask_sub_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_3_1 = mask_sub_sub_sub_sub_1_1 | _mask_sub_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size & mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_2_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size & mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_3_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_4_2 = mask_sub_sub_sub_2_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_4 = mask_sub_sub_size & mask_sub_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_4_1 = mask_sub_sub_sub_2_1 | _mask_sub_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_5_2 = mask_sub_sub_sub_2_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_5 = mask_sub_sub_size & mask_sub_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_5_1 = mask_sub_sub_sub_2_1 | _mask_sub_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_6_2 = mask_sub_sub_sub_3_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_6 = mask_sub_sub_size & mask_sub_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_6_1 = mask_sub_sub_sub_3_1 | _mask_sub_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_7_2 = mask_sub_sub_sub_3_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_7 = mask_sub_sub_size & mask_sub_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_7_1 = mask_sub_sub_sub_3_1 | _mask_sub_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size & mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_4_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size & mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_5_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size & mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_6_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size & mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_7_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_sub_8_2 = mask_sub_sub_4_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_8 = mask_sub_size & mask_sub_8_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_8_1 = mask_sub_sub_4_1 | _mask_sub_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_sub_9_2 = mask_sub_sub_4_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_9 = mask_sub_size & mask_sub_9_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_9_1 = mask_sub_sub_4_1 | _mask_sub_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_sub_10_2 = mask_sub_sub_5_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_10 = mask_sub_size & mask_sub_10_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_10_1 = mask_sub_sub_5_1 | _mask_sub_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_sub_11_2 = mask_sub_sub_5_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_11 = mask_sub_size & mask_sub_11_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_11_1 = mask_sub_sub_5_1 | _mask_sub_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_sub_12_2 = mask_sub_sub_6_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_12 = mask_sub_size & mask_sub_12_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_12_1 = mask_sub_sub_6_1 | _mask_sub_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_sub_13_2 = mask_sub_sub_6_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_13 = mask_sub_size & mask_sub_13_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_13_1 = mask_sub_sub_6_1 | _mask_sub_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_sub_14_2 = mask_sub_sub_7_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_14 = mask_sub_size & mask_sub_14_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_14_1 = mask_sub_sub_7_1 | _mask_sub_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_sub_15_2 = mask_sub_sub_7_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_15 = mask_sub_size & mask_sub_15_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_15_1 = mask_sub_sub_7_1 | _mask_sub_acc_T_15; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_4_1 | _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_4_1 | _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_5_1 | _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_5_1 | _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_6_1 | _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_6_1 | _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_7_1 | _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_7_1 | _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire mask_eq_16 = mask_sub_8_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_16 = mask_size & mask_eq_16; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_16 = mask_sub_8_1 | _mask_acc_T_16; // @[Misc.scala:215:{29,38}] wire mask_eq_17 = mask_sub_8_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_17 = mask_size & mask_eq_17; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_17 = mask_sub_8_1 | _mask_acc_T_17; // @[Misc.scala:215:{29,38}] wire mask_eq_18 = mask_sub_9_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_18 = mask_size & mask_eq_18; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_18 = mask_sub_9_1 | _mask_acc_T_18; // @[Misc.scala:215:{29,38}] wire mask_eq_19 = mask_sub_9_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_19 = mask_size & mask_eq_19; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_19 = mask_sub_9_1 | _mask_acc_T_19; // @[Misc.scala:215:{29,38}] wire mask_eq_20 = mask_sub_10_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_20 = mask_size & mask_eq_20; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_20 = mask_sub_10_1 | _mask_acc_T_20; // @[Misc.scala:215:{29,38}] wire mask_eq_21 = mask_sub_10_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_21 = mask_size & mask_eq_21; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_21 = mask_sub_10_1 | _mask_acc_T_21; // @[Misc.scala:215:{29,38}] wire mask_eq_22 = mask_sub_11_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_22 = mask_size & mask_eq_22; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_22 = mask_sub_11_1 | _mask_acc_T_22; // @[Misc.scala:215:{29,38}] wire mask_eq_23 = mask_sub_11_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_23 = mask_size & mask_eq_23; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_23 = mask_sub_11_1 | _mask_acc_T_23; // @[Misc.scala:215:{29,38}] wire mask_eq_24 = mask_sub_12_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_24 = mask_size & mask_eq_24; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_24 = mask_sub_12_1 | _mask_acc_T_24; // @[Misc.scala:215:{29,38}] wire mask_eq_25 = mask_sub_12_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_25 = mask_size & mask_eq_25; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_25 = mask_sub_12_1 | _mask_acc_T_25; // @[Misc.scala:215:{29,38}] wire mask_eq_26 = mask_sub_13_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_26 = mask_size & mask_eq_26; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_26 = mask_sub_13_1 | _mask_acc_T_26; // @[Misc.scala:215:{29,38}] wire mask_eq_27 = mask_sub_13_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_27 = mask_size & mask_eq_27; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_27 = mask_sub_13_1 | _mask_acc_T_27; // @[Misc.scala:215:{29,38}] wire mask_eq_28 = mask_sub_14_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_28 = mask_size & mask_eq_28; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_28 = mask_sub_14_1 | _mask_acc_T_28; // @[Misc.scala:215:{29,38}] wire mask_eq_29 = mask_sub_14_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_29 = mask_size & mask_eq_29; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_29 = mask_sub_14_1 | _mask_acc_T_29; // @[Misc.scala:215:{29,38}] wire mask_eq_30 = mask_sub_15_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_30 = mask_size & mask_eq_30; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_30 = mask_sub_15_1 | _mask_acc_T_30; // @[Misc.scala:215:{29,38}] wire mask_eq_31 = mask_sub_15_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_31 = mask_size & mask_eq_31; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_31 = mask_sub_15_1 | _mask_acc_T_31; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo_lo = {mask_lo_lo_lo_hi, mask_lo_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo_hi = {mask_lo_lo_hi_hi, mask_lo_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_lo_lo = {mask_lo_lo_hi, mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo_lo = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_lo_hi = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi_lo = {mask_lo_hi_lo_hi, mask_lo_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_hi_lo = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_hi_hi = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi_hi = {mask_lo_hi_hi_hi, mask_lo_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_lo_hi = {mask_lo_hi_hi, mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [15:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo_lo = {mask_acc_17, mask_acc_16}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_lo_hi = {mask_acc_19, mask_acc_18}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo_lo = {mask_hi_lo_lo_hi, mask_hi_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_hi_lo = {mask_acc_21, mask_acc_20}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_hi_hi = {mask_acc_23, mask_acc_22}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo_hi = {mask_hi_lo_hi_hi, mask_hi_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_hi_lo = {mask_hi_lo_hi, mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo_lo = {mask_acc_25, mask_acc_24}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_lo_hi = {mask_acc_27, mask_acc_26}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi_lo = {mask_hi_hi_lo_hi, mask_hi_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_hi_lo = {mask_acc_29, mask_acc_28}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_hi_hi = {mask_acc_31, mask_acc_30}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi_hi = {mask_hi_hi_hi_hi, mask_hi_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_hi_hi = {mask_hi_hi_hi, mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [15:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [31:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_4 = _uncommonBits_T_4[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_5 = _uncommonBits_T_5[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_10 = _uncommonBits_T_10[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_11 = _uncommonBits_T_11[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_16 = _uncommonBits_T_16[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_17 = _uncommonBits_T_17[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_22 = _uncommonBits_T_22[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_23 = _uncommonBits_T_23[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_28 = _uncommonBits_T_28[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_29 = _uncommonBits_T_29[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_34 = _uncommonBits_T_34[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_35 = _uncommonBits_T_35[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_40 = _uncommonBits_T_40[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_41 = _uncommonBits_T_41[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_46 = _uncommonBits_T_46[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_47 = _uncommonBits_T_47[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_52 = _uncommonBits_T_52[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_53 = _uncommonBits_T_53[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_55 = _uncommonBits_T_55[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_58 = _uncommonBits_T_58[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_59 = _uncommonBits_T_59[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_60 = _uncommonBits_T_60[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_61 = _uncommonBits_T_61[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_62 = _uncommonBits_T_62[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_64 = _uncommonBits_T_64[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_65 = _uncommonBits_T_65[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_46 = io_in_d_bits_source_0 == 8'h90; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_46; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] _source_ok_T_47 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_53 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_59 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_65 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire _source_ok_T_48 = _source_ok_T_47 == 6'h20; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_50 = _source_ok_T_48; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_52; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_54 = _source_ok_T_53 == 6'h21; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_58; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_60 = _source_ok_T_59 == 6'h22; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_62 = _source_ok_T_60; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_64 = _source_ok_T_62; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_64; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_66 = _source_ok_T_65 == 6'h23; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_68 = _source_ok_T_66; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_70 = _source_ok_T_68; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_70; // @[Parameters.scala:1138:31] wire _source_ok_T_71 = io_in_d_bits_source_0 == 8'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_71; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[4:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_72 = io_in_d_bits_source_0[7:5]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_78 = io_in_d_bits_source_0[7:5]; // @[Monitor.scala:36:7] wire _source_ok_T_73 = _source_ok_T_72 == 3'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_75 = _source_ok_T_73; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_77 = _source_ok_T_75; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_6 = _source_ok_T_77; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_79 = _source_ok_T_78 == 3'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_81 = _source_ok_T_79; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_83 = _source_ok_T_81; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_7 = _source_ok_T_83; // @[Parameters.scala:1138:31] wire _source_ok_T_84 = io_in_d_bits_source_0 == 8'h42; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_84; // @[Parameters.scala:1138:31] wire _source_ok_T_85 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_86 = _source_ok_T_85 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_87 = _source_ok_T_86 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_88 = _source_ok_T_87 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_89 = _source_ok_T_88 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_90 = _source_ok_T_89 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_91 = _source_ok_T_90 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_91 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire sink_ok = io_in_d_bits_sink_0 < 5'h16; // @[Monitor.scala:36:7, :309:31] wire [27:0] _GEN_0 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T = {io_in_b_bits_address_0[31:28], _GEN_0}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46] wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_5 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46] wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40] wire address_ok = _address_ok_WIRE_0 | _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64] wire [31:0] _is_aligned_T_1 = {26'h0, io_in_b_bits_address_0[5:0]}; // @[Monitor.scala:36:7] wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_sub_sub_sub_bit_1 = io_in_b_bits_address_0[4]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_sub_1_2_1 = mask_sub_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_sub_nbit_1 = ~mask_sub_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_sub_0_2_1 = mask_sub_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_sub_sub_bit_1 = io_in_b_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_nbit_1 = ~mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2_1 = mask_sub_sub_sub_sub_0_2_1 & mask_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_sub_sub_1_2_1 = mask_sub_sub_sub_sub_0_2_1 & mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_2_2_1 = mask_sub_sub_sub_sub_1_2_1 & mask_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_sub_sub_3_2_1 = mask_sub_sub_sub_sub_1_2_1 & mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2_1 = mask_sub_sub_sub_0_2_1 & mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_sub_1_2_1 = mask_sub_sub_sub_0_2_1 & mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_2_2_1 = mask_sub_sub_sub_1_2_1 & mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_sub_3_2_1 = mask_sub_sub_sub_1_2_1 & mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_4_2_1 = mask_sub_sub_sub_2_2_1 & mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_sub_5_2_1 = mask_sub_sub_sub_2_2_1 & mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_6_2_1 = mask_sub_sub_sub_3_2_1 & mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_sub_7_2_1 = mask_sub_sub_sub_3_2_1 & mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_4_2_1 = mask_sub_sub_2_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_5_2_1 = mask_sub_sub_2_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_6_2_1 = mask_sub_sub_3_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_7_2_1 = mask_sub_sub_3_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_8_2_1 = mask_sub_sub_4_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_9_2_1 = mask_sub_sub_4_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_10_2_1 = mask_sub_sub_5_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_11_2_1 = mask_sub_sub_5_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_12_2_1 = mask_sub_sub_6_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_13_2_1 = mask_sub_sub_6_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_14_2_1 = mask_sub_sub_7_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_15_2_1 = mask_sub_sub_7_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_eq_32 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_32 = mask_eq_32; // @[Misc.scala:214:27, :215:38] wire mask_eq_33 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_33 = mask_eq_33; // @[Misc.scala:214:27, :215:38] wire mask_eq_34 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_34 = mask_eq_34; // @[Misc.scala:214:27, :215:38] wire mask_eq_35 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_35 = mask_eq_35; // @[Misc.scala:214:27, :215:38] wire mask_eq_36 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_36 = mask_eq_36; // @[Misc.scala:214:27, :215:38] wire mask_eq_37 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_37 = mask_eq_37; // @[Misc.scala:214:27, :215:38] wire mask_eq_38 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_38 = mask_eq_38; // @[Misc.scala:214:27, :215:38] wire mask_eq_39 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_39 = mask_eq_39; // @[Misc.scala:214:27, :215:38] wire mask_eq_40 = mask_sub_4_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_40 = mask_eq_40; // @[Misc.scala:214:27, :215:38] wire mask_eq_41 = mask_sub_4_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_41 = mask_eq_41; // @[Misc.scala:214:27, :215:38] wire mask_eq_42 = mask_sub_5_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_42 = mask_eq_42; // @[Misc.scala:214:27, :215:38] wire mask_eq_43 = mask_sub_5_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_43 = mask_eq_43; // @[Misc.scala:214:27, :215:38] wire mask_eq_44 = mask_sub_6_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_44 = mask_eq_44; // @[Misc.scala:214:27, :215:38] wire mask_eq_45 = mask_sub_6_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_45 = mask_eq_45; // @[Misc.scala:214:27, :215:38] wire mask_eq_46 = mask_sub_7_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_46 = mask_eq_46; // @[Misc.scala:214:27, :215:38] wire mask_eq_47 = mask_sub_7_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_47 = mask_eq_47; // @[Misc.scala:214:27, :215:38] wire mask_eq_48 = mask_sub_8_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_48 = mask_eq_48; // @[Misc.scala:214:27, :215:38] wire mask_eq_49 = mask_sub_8_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_49 = mask_eq_49; // @[Misc.scala:214:27, :215:38] wire mask_eq_50 = mask_sub_9_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_50 = mask_eq_50; // @[Misc.scala:214:27, :215:38] wire mask_eq_51 = mask_sub_9_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_51 = mask_eq_51; // @[Misc.scala:214:27, :215:38] wire mask_eq_52 = mask_sub_10_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_52 = mask_eq_52; // @[Misc.scala:214:27, :215:38] wire mask_eq_53 = mask_sub_10_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_53 = mask_eq_53; // @[Misc.scala:214:27, :215:38] wire mask_eq_54 = mask_sub_11_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_54 = mask_eq_54; // @[Misc.scala:214:27, :215:38] wire mask_eq_55 = mask_sub_11_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_55 = mask_eq_55; // @[Misc.scala:214:27, :215:38] wire mask_eq_56 = mask_sub_12_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_56 = mask_eq_56; // @[Misc.scala:214:27, :215:38] wire mask_eq_57 = mask_sub_12_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_57 = mask_eq_57; // @[Misc.scala:214:27, :215:38] wire mask_eq_58 = mask_sub_13_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_58 = mask_eq_58; // @[Misc.scala:214:27, :215:38] wire mask_eq_59 = mask_sub_13_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_59 = mask_eq_59; // @[Misc.scala:214:27, :215:38] wire mask_eq_60 = mask_sub_14_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_60 = mask_eq_60; // @[Misc.scala:214:27, :215:38] wire mask_eq_61 = mask_sub_14_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_61 = mask_eq_61; // @[Misc.scala:214:27, :215:38] wire mask_eq_62 = mask_sub_15_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_62 = mask_eq_62; // @[Misc.scala:214:27, :215:38] wire mask_eq_63 = mask_sub_15_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_63 = mask_eq_63; // @[Misc.scala:214:27, :215:38] wire _source_ok_T_92 = io_in_c_bits_source_0 == 8'h90; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_0 = _source_ok_T_92; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_12 = _source_ok_uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] _source_ok_T_93 = io_in_c_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_99 = io_in_c_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_105 = io_in_c_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_111 = io_in_c_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire _source_ok_T_94 = _source_ok_T_93 == 6'h20; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_96 = _source_ok_T_94; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_98 = _source_ok_T_96; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_1 = _source_ok_T_98; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_13 = _source_ok_uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_100 = _source_ok_T_99 == 6'h21; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_102 = _source_ok_T_100; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_104 = _source_ok_T_102; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_2 = _source_ok_T_104; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_14 = _source_ok_uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_106 = _source_ok_T_105 == 6'h22; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_108 = _source_ok_T_106; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_110 = _source_ok_T_108; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_3 = _source_ok_T_110; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_15 = _source_ok_uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_112 = _source_ok_T_111 == 6'h23; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_114 = _source_ok_T_112; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_116 = _source_ok_T_114; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_4 = _source_ok_T_116; // @[Parameters.scala:1138:31] wire _source_ok_T_117 = io_in_c_bits_source_0 == 8'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_5 = _source_ok_T_117; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_16 = _source_ok_uncommonBits_T_16[4:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_118 = io_in_c_bits_source_0[7:5]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_124 = io_in_c_bits_source_0[7:5]; // @[Monitor.scala:36:7] wire _source_ok_T_119 = _source_ok_T_118 == 3'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_121 = _source_ok_T_119; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_123 = _source_ok_T_121; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_6 = _source_ok_T_123; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_17 = _source_ok_uncommonBits_T_17[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_125 = _source_ok_T_124 == 3'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_127 = _source_ok_T_125; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_129 = _source_ok_T_127; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_7 = _source_ok_T_129; // @[Parameters.scala:1138:31] wire _source_ok_T_130 = io_in_c_bits_source_0 == 8'h42; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_8 = _source_ok_T_130; // @[Parameters.scala:1138:31] wire _source_ok_T_131 = _source_ok_WIRE_2_0 | _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_132 = _source_ok_T_131 | _source_ok_WIRE_2_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_133 = _source_ok_T_132 | _source_ok_WIRE_2_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_134 = _source_ok_T_133 | _source_ok_WIRE_2_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_135 = _source_ok_T_134 | _source_ok_WIRE_2_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_136 = _source_ok_T_135 | _source_ok_WIRE_2_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_137 = _source_ok_T_136 | _source_ok_WIRE_2_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_2 = _source_ok_T_137 | _source_ok_WIRE_2_8; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN_1 = 13'h3F << io_in_c_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_1; // @[package.scala:243:71] wire [12:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_1; // @[package.scala:243:71] wire [12:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_1; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {26'h0, io_in_c_bits_address_0[5:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [27:0] _GEN_2 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_10 = {io_in_c_bits_address_0[31:28], _GEN_2}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_15 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_19; // @[Parameters.scala:612:40] wire address_ok_1 = _address_ok_WIRE_1_0 | _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire [1:0] uncommonBits_78 = _uncommonBits_T_78[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_79 = _uncommonBits_T_79[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_80 = _uncommonBits_T_80[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_81 = _uncommonBits_T_81[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_82 = _uncommonBits_T_82[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_83 = _uncommonBits_T_83[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_84 = _uncommonBits_T_84[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_85 = _uncommonBits_T_85[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_86 = _uncommonBits_T_86[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_87 = _uncommonBits_T_87[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_88 = _uncommonBits_T_88[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_89 = _uncommonBits_T_89[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_90 = _uncommonBits_T_90[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_91 = _uncommonBits_T_91[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_92 = _uncommonBits_T_92[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_93 = _uncommonBits_T_93[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_94 = _uncommonBits_T_94[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_95 = _uncommonBits_T_95[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_96 = _uncommonBits_T_96[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_97 = _uncommonBits_T_97[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_98 = _uncommonBits_T_98[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_99 = _uncommonBits_T_99[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_100 = _uncommonBits_T_100[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_101 = _uncommonBits_T_101[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_102 = _uncommonBits_T_102[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_103 = _uncommonBits_T_103[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_104 = _uncommonBits_T_104[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_105 = _uncommonBits_T_105[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_106 = _uncommonBits_T_106[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_107 = _uncommonBits_T_107[4:0]; // @[Parameters.scala:52:{29,56}] wire sink_ok_1 = io_in_e_bits_sink_0 < 5'h16; // @[Monitor.scala:36:7, :367:31] wire _T_2317 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_2317; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_2317; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire a_first_beats1_decode = _a_first_beats1_decode_T_2[5]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire a_first_beats1 = a_first_beats1_opdata & a_first_beats1_decode; // @[Edges.scala:92:28, :220:59, :221:14] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_1 = ~a_first_beats1; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [7:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_2391 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_2391; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_2391; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_2391; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_2391; // @[Decoupled.scala:51:35] wire [12:0] _GEN_3 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_3; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_3; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_3; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_3; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_decode = _d_first_beats1_decode_T_2[5]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1 = d_first_beats1_opdata & d_first_beats1_decode; // @[Edges.scala:106:36, :220:59, :221:14] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_1 = ~d_first_beats1; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [7:0] source_1; // @[Monitor.scala:541:22] reg [4:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35] wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35] reg b_first_counter; // @[Edges.scala:229:27] wire _b_first_last_T = b_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _b_first_counter1_T = {1'h0, b_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire b_first_counter1 = _b_first_counter1_T[0]; // @[Edges.scala:230:28] wire b_first = ~b_first_counter; // @[Edges.scala:229:27, :231:25] wire _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27] wire _b_first_counter_T = ~b_first & b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _T_2388 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_2388; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_2388; // @[Decoupled.scala:51:35] wire [5:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire c_first_beats1_decode = _c_first_beats1_decode_T_2[5]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1 = c_first_beats1_opdata & c_first_beats1_decode; // @[Edges.scala:102:36, :220:59, :221:14] reg c_first_counter; // @[Edges.scala:229:27] wire _c_first_last_T = c_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _c_first_counter1_T = {1'h0, c_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire c_first_counter1 = _c_first_counter1_T[0]; // @[Edges.scala:230:28] wire c_first = ~c_first_counter; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_1 = ~c_first_beats1; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T | _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [2:0] size_3; // @[Monitor.scala:517:22] reg [7:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [144:0] inflight; // @[Monitor.scala:614:27] reg [579:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [579:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire a_first_beats1_1 = a_first_beats1_opdata_1 & a_first_beats1_decode_1; // @[Edges.scala:92:28, :220:59, :221:14] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_3 = ~a_first_beats1_1; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5]; // @[package.scala:243:46] wire d_first_beats1_1 = d_first_beats1_opdata_1 & d_first_beats1_decode_1; // @[Edges.scala:106:36, :220:59, :221:14] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_3 = ~d_first_beats1_1; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [144:0] a_set; // @[Monitor.scala:626:34] wire [144:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [579:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [579:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [10:0] _GEN_4 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [10:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_4; // @[Monitor.scala:637:69] wire [10:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_4; // @[Monitor.scala:637:69, :641:65] wire [10:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_4; // @[Monitor.scala:637:69, :680:101] wire [10:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_4; // @[Monitor.scala:637:69, :681:99] wire [10:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_4; // @[Monitor.scala:637:69, :749:69] wire [10:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_4; // @[Monitor.scala:637:69, :750:67] wire [10:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_4; // @[Monitor.scala:637:69, :790:101] wire [10:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_4; // @[Monitor.scala:637:69, :791:99] wire [579:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [579:0] _a_opcode_lookup_T_6 = {576'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [579:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[579:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [579:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [579:0] _a_size_lookup_T_6 = {576'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [579:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[579:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [255:0] _GEN_5 = 256'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_5; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[144:0] : 145'h0; // @[OneHot.scala:58:35] wire _T_2243 = _T_2317 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_2243 ? _a_set_T[144:0] : 145'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_2243 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_2243 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [10:0] _GEN_6 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [10:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_6; // @[Monitor.scala:659:79] wire [10:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_6; // @[Monitor.scala:659:79, :660:77] wire [2050:0] _a_opcodes_set_T_1 = {2047'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_2243 ? _a_opcodes_set_T_1[579:0] : 580'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [2050:0] _a_sizes_set_T_1 = {2047'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_2243 ? _a_sizes_set_T_1[579:0] : 580'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [144:0] d_clr; // @[Monitor.scala:664:34] wire [144:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [579:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [579:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_7 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_7; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_7; // @[Monitor.scala:673:46, :783:46] wire _T_2289 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [255:0] _GEN_8 = 256'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_8; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_8; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_8; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_8; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_2289 & ~d_release_ack ? _d_clr_wo_ready_T[144:0] : 145'h0; // @[OneHot.scala:58:35] wire _T_2258 = _T_2391 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_2258 ? _d_clr_T[144:0] : 145'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_5 = 2063'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_2258 ? _d_opcodes_clr_T_5[579:0] : 580'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [2062:0] _d_sizes_clr_T_5 = 2063'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_2258 ? _d_sizes_clr_T_5[579:0] : 580'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [144:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [144:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [144:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [579:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [579:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [579:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [579:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [579:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [579:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [144:0] inflight_1; // @[Monitor.scala:726:35] reg [579:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [579:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [5:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[5]; // @[package.scala:243:46] wire c_first_beats1_1 = c_first_beats1_opdata_1 & c_first_beats1_decode_1; // @[Edges.scala:102:36, :220:59, :221:14] reg c_first_counter_1; // @[Edges.scala:229:27] wire _c_first_last_T_2 = c_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire c_first_counter1_1 = _c_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire c_first_1 = ~c_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_3 = ~c_first_beats1_1; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 | _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5]; // @[package.scala:243:46] wire d_first_beats1_2 = d_first_beats1_opdata_2 & d_first_beats1_decode_2; // @[Edges.scala:106:36, :220:59, :221:14] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_5 = ~d_first_beats1_2; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [144:0] c_set; // @[Monitor.scala:738:34] wire [144:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [579:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [579:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [579:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [579:0] _c_opcode_lookup_T_6 = {576'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [579:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[579:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [579:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [579:0] _c_size_lookup_T_6 = {576'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [579:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[579:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [255:0] _GEN_9 = 256'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_9; // @[OneHot.scala:58:35] wire [255:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_9; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[144:0] : 145'h0; // @[OneHot.scala:58:35] wire _T_2330 = _T_2388 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_2330 ? _c_set_T[144:0] : 145'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_2330 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [3:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [3:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_2330 ? _c_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [10:0] _GEN_10 = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [10:0] _c_opcodes_set_T; // @[Monitor.scala:767:79] assign _c_opcodes_set_T = _GEN_10; // @[Monitor.scala:767:79] wire [10:0] _c_sizes_set_T; // @[Monitor.scala:768:77] assign _c_sizes_set_T = _GEN_10; // @[Monitor.scala:767:79, :768:77] wire [2050:0] _c_opcodes_set_T_1 = {2047'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}] assign c_opcodes_set = _T_2330 ? _c_opcodes_set_T_1[579:0] : 580'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [2050:0] _c_sizes_set_T_1 = {2047'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}] assign c_sizes_set = _T_2330 ? _c_sizes_set_T_1[579:0] : 580'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T | _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [144:0] d_clr_1; // @[Monitor.scala:774:34] wire [144:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [579:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [579:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_2361 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_2361 & d_release_ack_1 ? _d_clr_wo_ready_T_1[144:0] : 145'h0; // @[OneHot.scala:58:35] wire _T_2343 = _T_2391 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_2343 ? _d_clr_T_1[144:0] : 145'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_11 = 2063'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_2343 ? _d_opcodes_clr_T_11[579:0] : 580'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [2062:0] _d_sizes_clr_T_11 = 2063'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_2343 ? _d_sizes_clr_T_11[579:0] : 580'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [144:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [144:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [144:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [579:0] _inflight_opcodes_T_3 = inflight_opcodes_1 | c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [579:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [579:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [579:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [579:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [579:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [21:0] inflight_2; // @[Monitor.scala:828:27] wire [5:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[5]; // @[package.scala:243:46] wire d_first_beats1_3 = d_first_beats1_opdata_3 & d_first_beats1_decode_3; // @[Edges.scala:106:36, :220:59, :221:14] reg d_first_counter_3; // @[Edges.scala:229:27] wire _d_first_last_T_6 = d_first_counter_3; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_3 = _d_first_counter1_T_3[0]; // @[Edges.scala:230:28] wire d_first_3 = ~d_first_counter_3; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_7 = ~d_first_beats1_3; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 | _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [21:0] d_set; // @[Monitor.scala:833:25] wire _T_2397 = _T_2391 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [31:0] _d_set_T = 32'h1 << io_in_d_bits_sink_0; // @[OneHot.scala:58:35] assign d_set = _T_2397 ? _d_set_T[21:0] : 22'h0; // @[OneHot.scala:58:35] wire [21:0] e_clr; // @[Monitor.scala:839:25] wire [31:0] _e_clr_T = 32'h1 << io_in_e_bits_sink_0; // @[OneHot.scala:58:35] assign e_clr = io_in_e_valid_0 ? _e_clr_T[21:0] : 22'h0; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to the following Chisel files. File ShiftRegisterPriorityQueue.scala: package compressacc import chisel3._ import chisel3.util._ import chisel3.util._ // TODO : support enq & deq at the same cycle class PriorityQueueStageIO(keyWidth: Int, value: ValueInfo) extends Bundle { val output_prev = KeyValue(keyWidth, value) val output_nxt = KeyValue(keyWidth, value) val input_prev = Flipped(KeyValue(keyWidth, value)) val input_nxt = Flipped(KeyValue(keyWidth, value)) val cmd = Flipped(Valid(UInt(1.W))) val insert_here = Input(Bool()) val cur_input_keyval = Flipped(KeyValue(keyWidth, value)) val cur_output_keyval = KeyValue(keyWidth, value) } class PriorityQueueStage(keyWidth: Int, value: ValueInfo) extends Module { val io = IO(new PriorityQueueStageIO(keyWidth, value)) dontTouch(io) val CMD_DEQ = 0.U val CMD_ENQ = 1.U val MAX_VALUE = (1 << keyWidth) - 1 val key_reg = RegInit(MAX_VALUE.U(keyWidth.W)) val value_reg = Reg(value) io.output_prev.key := key_reg io.output_prev.value := value_reg io.output_nxt.key := key_reg io.output_nxt.value := value_reg io.cur_output_keyval.key := key_reg io.cur_output_keyval.value := value_reg when (io.cmd.valid) { switch (io.cmd.bits) { is (CMD_DEQ) { key_reg := io.input_nxt.key value_reg := io.input_nxt.value } is (CMD_ENQ) { when (io.insert_here) { key_reg := io.cur_input_keyval.key value_reg := io.cur_input_keyval.value } .elsewhen (key_reg >= io.cur_input_keyval.key) { key_reg := io.input_prev.key value_reg := io.input_prev.value } .otherwise { // do nothing } } } } } object PriorityQueueStage { def apply(keyWidth: Int, v: ValueInfo): PriorityQueueStage = new PriorityQueueStage(keyWidth, v) } // TODO // - This design is not scalable as the enqued_keyval is broadcasted to all the stages // - Add pipeline registers later class PriorityQueueIO(queSize: Int, keyWidth: Int, value: ValueInfo) extends Bundle { val cnt_bits = log2Ceil(queSize+1) val counter = Output(UInt(cnt_bits.W)) val enq = Flipped(Decoupled(KeyValue(keyWidth, value))) val deq = Decoupled(KeyValue(keyWidth, value)) } class PriorityQueue(queSize: Int, keyWidth: Int, value: ValueInfo) extends Module { val keyWidthInternal = keyWidth + 1 val CMD_DEQ = 0.U val CMD_ENQ = 1.U val io = IO(new PriorityQueueIO(queSize, keyWidthInternal, value)) dontTouch(io) val MAX_VALUE = ((1 << keyWidthInternal) - 1).U val cnt_bits = log2Ceil(queSize+1) // do not consider cases where we are inserting more entries then the queSize val counter = RegInit(0.U(cnt_bits.W)) io.counter := counter val full = (counter === queSize.U) val empty = (counter === 0.U) io.deq.valid := !empty io.enq.ready := !full when (io.enq.fire) { counter := counter + 1.U } when (io.deq.fire) { counter := counter - 1.U } val cmd_valid = io.enq.valid || io.deq.ready val cmd = Mux(io.enq.valid, CMD_ENQ, CMD_DEQ) assert(!(io.enq.valid && io.deq.ready)) val stages = Seq.fill(queSize)(Module(new PriorityQueueStage(keyWidthInternal, value))) for (i <- 0 until (queSize - 1)) { stages(i+1).io.input_prev <> stages(i).io.output_nxt stages(i).io.input_nxt <> stages(i+1).io.output_prev } stages(queSize-1).io.input_nxt.key := MAX_VALUE // stages(queSize-1).io.input_nxt.value := stages(queSize-1).io.input_nxt.value.symbol := 0.U // stages(queSize-1).io.input_nxt.value.child(0) := 0.U // stages(queSize-1).io.input_nxt.value.child(1) := 0.U stages(0).io.input_prev.key := io.enq.bits.key stages(0).io.input_prev.value <> io.enq.bits.value for (i <- 0 until queSize) { stages(i).io.cmd.valid := cmd_valid stages(i).io.cmd.bits := cmd stages(i).io.cur_input_keyval <> io.enq.bits } val is_large_or_equal = WireInit(VecInit(Seq.fill(queSize)(false.B))) for (i <- 0 until queSize) { is_large_or_equal(i) := (stages(i).io.cur_output_keyval.key >= io.enq.bits.key) } val is_large_or_equal_cat = Wire(UInt(queSize.W)) is_large_or_equal_cat := Cat(is_large_or_equal.reverse) val insert_here_idx = PriorityEncoder(is_large_or_equal_cat) for (i <- 0 until queSize) { when (i.U === insert_here_idx) { stages(i).io.insert_here := true.B } .otherwise { stages(i).io.insert_here := false.B } } io.deq.bits <> stages(0).io.output_prev }
module PriorityQueueStage_68( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands */ class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def *(t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def *(t: UInt) = self * t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros | ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def *(t: SInt) = self * t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros | ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid || output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def *(t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def *(t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }
module PE_330( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_74 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ :*=* _) .getOrElse(TLNameNode("no_buffer")) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File BaseTile.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tile import chisel3._ import chisel3.util.{log2Ceil, log2Up} import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.bundlebridge._ import freechips.rocketchip.resources.{PropertyMap, PropertyOption, ResourceReference, DTSTimebase} import freechips.rocketchip.interrupts.{IntInwardNode, IntOutwardNode} import freechips.rocketchip.rocket.{ICacheParams, DCacheParams, BTBParams, ASIdBits, VMIdBits, TraceAux, BPWatch} import freechips.rocketchip.subsystem.{ HierarchicalElementParams, InstantiableHierarchicalElementParams, HierarchicalElementCrossingParamsLike, CacheBlockBytes, SystemBusKey, BaseHierarchicalElement, InsertTimingClosureRegistersOnHartIds, BaseHierarchicalElementModuleImp } import freechips.rocketchip.tilelink.{TLEphemeralNode, TLOutwardNode, TLNode, TLFragmenter, EarlyAck, TLWidthWidget, TLManagerParameters, ManagerUnification} import freechips.rocketchip.prci.{ClockCrossingType, ClockSinkParameters} import freechips.rocketchip.util.{TraceCoreParams, TraceCoreInterface} import freechips.rocketchip.resources.{BigIntToProperty, IntToProperty, StringToProperty} import freechips.rocketchip.util.BooleanToAugmentedBoolean case object TileVisibilityNodeKey extends Field[TLEphemeralNode] case object TileKey extends Field[TileParams] case object LookupByHartId extends Field[LookupByHartIdImpl] trait TileParams extends HierarchicalElementParams { val core: CoreParams val icache: Option[ICacheParams] val dcache: Option[DCacheParams] val btb: Option[BTBParams] val tileId: Int // may not be hartid val blockerCtrlAddr: Option[BigInt] } abstract class InstantiableTileParams[TileType <: BaseTile] extends InstantiableHierarchicalElementParams[TileType] with TileParams { def instantiate(crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl) (implicit p: Parameters): TileType } /** These parameters values are not computed based on diplomacy negotiation * and so are safe to use while diplomacy itself is running. */ trait HasNonDiplomaticTileParameters { implicit val p: Parameters def tileParams: TileParams = p(TileKey) def usingVM: Boolean = tileParams.core.useVM def usingUser: Boolean = tileParams.core.useUser || usingSupervisor def usingSupervisor: Boolean = tileParams.core.hasSupervisorMode def usingHypervisor: Boolean = usingVM && tileParams.core.useHypervisor def usingDebug: Boolean = tileParams.core.useDebug def usingRoCC: Boolean = !p(BuildRoCC).isEmpty def usingBTB: Boolean = tileParams.btb.isDefined && tileParams.btb.get.nEntries > 0 def usingPTW: Boolean = usingVM def usingDataScratchpad: Boolean = tileParams.dcache.flatMap(_.scratch).isDefined def xLen: Int = tileParams.core.xLen def xBytes: Int = xLen / 8 def iLen: Int = 32 def pgIdxBits: Int = 12 def pgLevelBits: Int = 10 - log2Ceil(xLen / 32) def pgLevels: Int = tileParams.core.pgLevels def maxSVAddrBits: Int = pgIdxBits + pgLevels * pgLevelBits def maxHypervisorExtraAddrBits: Int = 2 def hypervisorExtraAddrBits: Int = { if (usingHypervisor) maxHypervisorExtraAddrBits else 0 } def maxHVAddrBits: Int = maxSVAddrBits + hypervisorExtraAddrBits def minPgLevels: Int = { val res = xLen match { case 32 => 2; case 64 => 3 } require(pgLevels >= res) res } def asIdBits: Int = p(ASIdBits) def vmIdBits: Int = p(VMIdBits) lazy val maxPAddrBits: Int = { require(xLen == 32 || xLen == 64, s"Only XLENs of 32 or 64 are supported, but got $xLen") xLen match { case 32 => 34; case 64 => 56 } } def tileId: Int = tileParams.tileId def cacheBlockBytes = p(CacheBlockBytes) def lgCacheBlockBytes = log2Up(cacheBlockBytes) def masterPortBeatBytes = p(SystemBusKey).beatBytes // TODO make HellaCacheIO diplomatic and remove this brittle collection of hacks // Core PTW DTIM coprocessors def dcacheArbPorts = 1 + usingVM.toInt + usingDataScratchpad.toInt + p(BuildRoCC).size + (tileParams.core.useVector && tileParams.core.vectorUseDCache).toInt // TODO merge with isaString in CSR.scala def isaDTS: String = { val ie = if (tileParams.core.useRVE) "e" else "i" val m = if (tileParams.core.mulDiv.nonEmpty) "m" else "" val a = if (tileParams.core.useAtomics) "a" else "" val f = if (tileParams.core.fpu.nonEmpty) "f" else "" val d = if (tileParams.core.fpu.nonEmpty && tileParams.core.fpu.get.fLen > 32) "d" else "" val c = if (tileParams.core.useCompressed) "c" else "" val b = if (tileParams.core.useBitmanip) "b" else "" val v = if (tileParams.core.useVector && tileParams.core.vLen >= 128 && tileParams.core.eLen == 64 && tileParams.core.vfLen == 64) "v" else "" val h = if (usingHypervisor) "h" else "" val ext_strs = Seq( (tileParams.core.useVector) -> s"zvl${tileParams.core.vLen}b", (tileParams.core.useVector) -> { val c = tileParams.core.vfLen match { case 64 => "d" case 32 => "f" case 0 => "x" } s"zve${tileParams.core.eLen}$c" }, (tileParams.core.useVector && tileParams.core.vfh) -> "zvfh", (tileParams.core.fpu.map(_.fLen >= 16).getOrElse(false) && tileParams.core.minFLen <= 16) -> "zfh", (tileParams.core.useZba) -> "zba", (tileParams.core.useZbb) -> "zbb", (tileParams.core.useZbs) -> "zbs", (tileParams.core.useConditionalZero) -> "zicond" ).filter(_._1).map(_._2) val multiLetterExt = ( // rdcycle[h], rdinstret[h] is implemented // rdtime[h] is not implemented, and could be provided by software emulation // see https://github.com/chipsalliance/rocket-chip/issues/3207 //Some(Seq("zicntr")) ++ Some(Seq("zicsr", "zifencei", "zihpm")) ++ Some(ext_strs) ++ Some(tileParams.core.vExts) ++ tileParams.core.customIsaExt.map(Seq(_)) ).flatten val multiLetterString = multiLetterExt.mkString("_") s"rv$xLen$ie$m$a$f$d$c$b$v$h$multiLetterString" } def tileProperties: PropertyMap = { val dcache = tileParams.dcache.filter(!_.scratch.isDefined).map(d => Map( "d-cache-block-size" -> cacheBlockBytes.asProperty, "d-cache-sets" -> d.nSets.asProperty, "d-cache-size" -> (d.nSets * d.nWays * cacheBlockBytes).asProperty) ).getOrElse(Nil) val incoherent = if (!tileParams.core.useAtomicsOnlyForIO) Nil else Map( "sifive,d-cache-incoherent" -> Nil) val icache = tileParams.icache.map(i => Map( "i-cache-block-size" -> cacheBlockBytes.asProperty, "i-cache-sets" -> i.nSets.asProperty, "i-cache-size" -> (i.nSets * i.nWays * cacheBlockBytes).asProperty) ).getOrElse(Nil) val dtlb = tileParams.dcache.filter(_ => tileParams.core.useVM).map(d => Map( "d-tlb-size" -> (d.nTLBWays * d.nTLBSets).asProperty, "d-tlb-sets" -> d.nTLBSets.asProperty)).getOrElse(Nil) val itlb = tileParams.icache.filter(_ => tileParams.core.useVM).map(i => Map( "i-tlb-size" -> (i.nTLBWays * i.nTLBSets).asProperty, "i-tlb-sets" -> i.nTLBSets.asProperty)).getOrElse(Nil) val mmu = if (tileParams.core.useVM) { if (tileParams.core.useHypervisor) { Map("tlb-split" -> Nil, "mmu-type" -> s"riscv,sv${maxSVAddrBits},sv${maxSVAddrBits}x4".asProperty) } else { Map("tlb-split" -> Nil, "mmu-type" -> s"riscv,sv$maxSVAddrBits".asProperty) } } else { Nil } val pmp = if (tileParams.core.nPMPs > 0) Map( "riscv,pmpregions" -> tileParams.core.nPMPs.asProperty, "riscv,pmpgranularity" -> tileParams.core.pmpGranularity.asProperty) else Nil dcache ++ icache ++ dtlb ++ itlb ++ mmu ++ pmp ++ incoherent } } /** These parameters values are computed based on diplomacy negotiations * and so are NOT safe to use while diplomacy itself is running. * Only mix this trait into LazyModuleImps, Modules, Bundles, Data, etc. */ trait HasTileParameters extends HasNonDiplomaticTileParameters { protected def tlBundleParams = p(TileVisibilityNodeKey).edges.out.head.bundle lazy val paddrBits: Int = { val bits = tlBundleParams.addressBits require(bits <= maxPAddrBits, s"Requested $bits paddr bits, but since xLen is $xLen only $maxPAddrBits will fit") bits } def vaddrBits: Int = if (usingVM) { val v = maxHVAddrBits require(v == xLen || xLen > v && v > paddrBits) v } else { // since virtual addresses sign-extend but physical addresses // zero-extend, make room for a zero sign bit for physical addresses (paddrBits + 1) min xLen } def vpnBits: Int = vaddrBits - pgIdxBits def ppnBits: Int = paddrBits - pgIdxBits def vpnBitsExtended: Int = vpnBits + (if (vaddrBits < xLen) 1 + usingHypervisor.toInt else 0) def vaddrBitsExtended: Int = vpnBitsExtended + pgIdxBits } /** Base class for all Tiles that use TileLink */ abstract class BaseTile private (crossing: ClockCrossingType, q: Parameters) extends BaseHierarchicalElement(crossing)(q) with HasNonDiplomaticTileParameters { // Public constructor alters Parameters to supply some legacy compatibility keys def this(tileParams: TileParams, crossing: ClockCrossingType, lookup: LookupByHartIdImpl, p: Parameters) = { this(crossing, p.alterMap(Map( TileKey -> tileParams, TileVisibilityNodeKey -> TLEphemeralNode()(ValName("tile_master")), LookupByHartId -> lookup ))) } def intInwardNode: IntInwardNode // Interrupts to the core from external devices def intOutwardNode: Option[IntOutwardNode] // Interrupts from tile-internal devices (e.g. BEU) def haltNode: IntOutwardNode // Unrecoverable error has occurred; suggest reset def ceaseNode: IntOutwardNode // Tile has ceased to retire instructions def wfiNode: IntOutwardNode // Tile is waiting for an interrupt def module: BaseTileModuleImp[BaseTile] /** Node for broadcasting a hart id to diplomatic consumers within the tile. */ val hartIdNexusNode: BundleBridgeNode[UInt] = BundleBroadcast[UInt](registered = p(InsertTimingClosureRegistersOnHartIds)) /** Node for consuming the hart id input in tile-layer Chisel logic. */ val hartIdSinkNode = BundleBridgeSink[UInt]() /** Node for driving a hart id input, which is to be broadcast to units within the tile. * * Making this id value an IO and then using it to do lookups of information * that would make otherwise-homogeneous tiles heterogeneous is a useful trick * to enable deduplication of tiles for hierarchical P&R flows. */ val hartIdNode: BundleBridgeInwardNode[UInt] = hartIdSinkNode := hartIdNexusNode := BundleBridgeNameNode("hartid") /** Node for broadcasting a reset vector to diplomatic consumers within the tile. */ val resetVectorNexusNode: BundleBridgeNode[UInt] = BundleBroadcast[UInt]() /** Node for consuming the reset vector input in tile-layer Chisel logic. * * Its width is sized by looking at the size of the address space visible * on the tile's master ports, but this lookup is not evaluated until * diplomacy has completed and Chisel elaboration has begun. */ val resetVectorSinkNode = BundleBridgeSink[UInt](Some(() => UInt(visiblePhysAddrBits.W))) /** Node for supplying a reset vector that processors in this tile might begin fetching instructions from as they come out of reset. */ val resetVectorNode: BundleBridgeInwardNode[UInt] = resetVectorSinkNode := resetVectorNexusNode := BundleBridgeNameNode("reset_vector") /** Nodes for connecting NMI interrupt sources and vectors into the tile */ val nmiSinkNode = Option.when(tileParams.core.useNMI) { BundleBridgeSink[NMI](Some(() => new NMI(visiblePhysAddrBits))) } val nmiNode: Option[BundleBridgeInwardNode[NMI]] = nmiSinkNode.map(_ := BundleBridgeNameNode("nmi")) /** Node for broadcasting an address prefix to diplomatic consumers within the tile. * * The prefix should be applied by consumers by or-ing ouputs of this node * with a static base address (which is looked up based on the driven hartid value). */ val mmioAddressPrefixNexusNode = BundleBridgeNexus[UInt]( inputFn = BundleBridgeNexus.orReduction[UInt](registered = false) _, outputFn = BundleBridgeNexus.fillN[UInt](registered = false) _, default = Some(() => 0.U(1.W)) ) /** Node for external drivers to prefix base addresses of MMIO devices to which the core has a direct access path. */ val mmioAddressPrefixNode: BundleBridgeInwardNode[UInt] = mmioAddressPrefixNexusNode :=* BundleBridgeNameNode("mmio_address_prefix") // TODO: Any node marked "consumed by the core" or "driven by the core" // should be moved to either be: a member of a specific BaseTile subclass, // or actually just a member of the core's LazyModule itself, // assuming the core itself is diplomatic. // Then these nodes should just become IdentityNodes of their respective type protected def traceRetireWidth = tileParams.core.retireWidth /** Node for the core to drive legacy "raw" instruction trace. */ val traceSourceNode = BundleBridgeSource(() => new TraceBundle) /** Node for external consumers to source a legacy instruction trace from the core. */ val traceNode = traceSourceNode def traceCoreParams = new TraceCoreParams() /** Node for core to drive instruction trace conforming to RISC-V Processor Trace spec V1.0 */ val traceCoreSourceNode = BundleBridgeSource(() => new TraceCoreInterface(traceCoreParams)) /** Node for external consumers to source a V1.0 instruction trace from the core. */ val traceCoreNode = traceCoreSourceNode /** Node to broadcast collected trace sideband signals into the tile. */ val traceAuxNexusNode = BundleBridgeNexus[TraceAux](default = Some(() => { val aux = Wire(new TraceAux) aux.stall := false.B aux.enable := false.B aux })) /** Trace sideband signals to be consumed by the core. */ val traceAuxSinkNode = BundleBridgeSink[TraceAux]() /** Trace sideband signals collected here to be driven into the tile. */ val traceAuxNode: BundleBridgeInwardNode[TraceAux] = traceAuxSinkNode := traceAuxNexusNode :=* BundleBridgeNameNode("trace_aux") /** Node for watchpoints to control trace driven by core. */ val bpwatchSourceNode = BundleBridgeSource(() => Vec(tileParams.core.nBreakpoints, new BPWatch(traceRetireWidth))) /** Node to broadcast watchpoints to control trace. */ val bpwatchNexusNode = BundleBroadcast[Vec[BPWatch]]() /** Node for external consumers to source watchpoints to control trace. */ val bpwatchNode: BundleBridgeOutwardNode[Vec[BPWatch]] = BundleBridgeNameNode("bpwatch") :*= bpwatchNexusNode := bpwatchSourceNode /** Helper function for connecting MMIO devices inside the tile to an xbar that will make them visible to external masters. */ def connectTLSlave(xbarNode: TLOutwardNode, node: TLNode, bytes: Int): Unit = { DisableMonitors { implicit p => (Seq(node, TLFragmenter(bytes, cacheBlockBytes, earlyAck=EarlyAck.PutFulls)) ++ (xBytes != bytes).option(TLWidthWidget(xBytes))) .foldRight(xbarNode)(_ :*= _) } } def connectTLSlave(node: TLNode, bytes: Int): Unit = { connectTLSlave(tlSlaveXbar.node, node, bytes) } /** TileLink node which represents the view that the intra-tile masters have of the rest of the system. */ val visibilityNode = p(TileVisibilityNodeKey) protected def visibleManagers = visibilityNode.edges.out.flatMap(_.manager.managers) protected def visiblePhysAddrBits = visibilityNode.edges.out.head.bundle.addressBits def unifyManagers: List[TLManagerParameters] = ManagerUnification(visibleManagers) /** Finds resource labels for all the outward caches. */ def nextLevelCacheProperty: PropertyOption = { val outer = visibleManagers .filter(_.supportsAcquireB) .flatMap(_.resources.headOption) .map(_.owner.label) .distinct if (outer.isEmpty) None else Some("next-level-cache" -> outer.map(l => ResourceReference(l)).toList) } /** Create a DTS representation of this "cpu". */ def cpuProperties: PropertyMap = Map( "device_type" -> "cpu".asProperty, "status" -> "okay".asProperty, "clock-frequency" -> tileParams.core.bootFreqHz.asProperty, "riscv,isa" -> isaDTS.asProperty, "timebase-frequency" -> p(DTSTimebase).asProperty, "hardware-exec-breakpoint-count" -> tileParams.core.nBreakpoints.asProperty ) /** Can be used to access derived params calculated by HasCoreParameters * * However, callers must ensure they do not access a diplomatically-determined parameter * before the graph in question has been fully connected. */ protected lazy val lazyCoreParamsView: HasCoreParameters = { class C(implicit val p: Parameters) extends HasCoreParameters new C } this.suggestName(tileParams.baseName) } abstract class BaseTileModuleImp[+L <: BaseTile](outer: L) extends BaseHierarchicalElementModuleImp[L](outer) File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File HierarchicalElement.scala: package freechips.rocketchip.subsystem import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.devices.debug.TLDebugModule import freechips.rocketchip.diplomacy.{BufferParams} import freechips.rocketchip.interrupts.IntXbar import freechips.rocketchip.prci.{ClockSinkParameters, ResetCrossingType, ClockCrossingType} import freechips.rocketchip.tile.{LookupByHartIdImpl, TraceBundle} import freechips.rocketchip.tilelink.{TLNode, TLIdentityNode, TLXbar, TLBuffer, TLInwardNode, TLOutwardNode} trait HierarchicalElementParams { val baseName: String // duplicated instances shouuld share a base name val uniqueName: String val clockSinkParams: ClockSinkParameters } abstract class InstantiableHierarchicalElementParams[ElementType <: BaseHierarchicalElement] extends HierarchicalElementParams /** An interface for describing the parameteization of how HierarchicalElements are connected to interconnects */ trait HierarchicalElementCrossingParamsLike { /** The type of clock crossing that should be inserted at the element boundary. */ def crossingType: ClockCrossingType /** Parameters describing the contents and behavior of the point where the element is attached as an interconnect master. */ def master: HierarchicalElementPortParamsLike /** Parameters describing the contents and behavior of the point where the element is attached as an interconnect slave. */ def slave: HierarchicalElementPortParamsLike /** The subnetwork location of the device selecting the apparent base address of MMIO devices inside the element */ def mmioBaseAddressPrefixWhere: TLBusWrapperLocation /** Inject a reset management subgraph that effects the element child reset only */ def resetCrossingType: ResetCrossingType /** Keep the element clock separate from the interconnect clock (e.g. even if they are synchronous to one another) */ def forceSeparateClockReset: Boolean } /** An interface for describing the parameterization of how a particular element port is connected to an interconnect */ trait HierarchicalElementPortParamsLike { /** The subnetwork location of the interconnect to which this element port should be connected. */ def where: TLBusWrapperLocation /** Allows port-specific adapters to be injected into the interconnect side of the attachment point. */ def injectNode(context: Attachable)(implicit p: Parameters): TLNode } abstract class BaseHierarchicalElement (val crossing: ClockCrossingType)(implicit p: Parameters) extends LazyModule()(p) with CrossesToOnlyOneClockDomain { def module: BaseHierarchicalElementModuleImp[BaseHierarchicalElement] protected val tlOtherMastersNode = TLIdentityNode() protected val tlMasterXbar = LazyModule(new TLXbar(nameSuffix = Some(s"MasterXbar_$desiredName"))) protected val tlSlaveXbar = LazyModule(new TLXbar(nameSuffix = Some(s"SlaveXbar_$desiredName"))) protected val intXbar = LazyModule(new IntXbar) def masterNode: TLOutwardNode def slaveNode: TLInwardNode /** Helper function to insert additional buffers on master ports at the boundary of the tile. * * The boundary buffering needed to cut feed-through paths is * microarchitecture specific, so this may need to be overridden * in subclasses of this class. */ def makeMasterBoundaryBuffers(crossing: ClockCrossingType)(implicit p: Parameters) = TLBuffer(BufferParams.none) /** Helper function to insert additional buffers on slave ports at the boundary of the tile. * * The boundary buffering needed to cut feed-through paths is * microarchitecture specific, so this may need to be overridden * in subclasses of this class. */ def makeSlaveBoundaryBuffers(crossing: ClockCrossingType)(implicit p: Parameters) = TLBuffer(BufferParams.none) } abstract class BaseHierarchicalElementModuleImp[+L <: BaseHierarchicalElement](val outer: L) extends LazyModuleImp(outer) File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } } File IbexTile.scala: //****************************************************************************** // Copyright (c) 2021 - 2021, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Ibex Tile Wrapper //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package ibex import chisel3._ import chisel3.util._ import chisel3.experimental.{IntParam, StringParam, RawParam} import scala.collection.mutable.{ListBuffer} import org.chipsalliance.cde.config._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.rocket._ import freechips.rocketchip.subsystem.{RocketCrossingParams} import freechips.rocketchip.tilelink._ import freechips.rocketchip.interrupts._ import freechips.rocketchip.util._ import freechips.rocketchip.tile._ import freechips.rocketchip.prci._ case class IbexCoreParams( //Defaults based on Ibex "small" configuration //See https://github.com/lowRISC/ibex for more information val bootFreqHz: BigInt = BigInt(1700000000), val pmpEnable: Int = 0, val pmpGranularity: Int = 0, val pmpNumRegions: Int = 4, val mhpmCounterNum: Int = 0, val mhpmCounterWidth: Int = 0, val rv32e: Int = 0, val rv32m: String = "RV32MFast", val rv32b: String = "RV32BNone", val regFile: String = "RegFileFF", val branchTargetALU: Int = 0, val wbStage: Int = 0, val branchPredictor: Int = 0, val dbgHwBreakNum: Int = 1, val dmHaltAddr: Int = 0x1A110800, val dmExceptionAddr: Int = 0x1A110808 ) extends CoreParams { val xLen = 32 val pgLevels = 2 val useVM: Boolean = false val useHypervisor: Boolean = false val useUser: Boolean = true val useSupervisor: Boolean = false val useDebug: Boolean = true val useAtomics: Boolean = false val useAtomicsOnlyForIO: Boolean = false val useCompressed: Boolean = false override val useVector: Boolean = false val useSCIE: Boolean = false val useRVE: Boolean = true val mulDiv: Option[MulDivParams] = Some(MulDivParams()) // copied from Rocket val fpu: Option[FPUParams] = None //floating point not supported val fetchWidth: Int = 1 val decodeWidth: Int = 1 val retireWidth: Int = 2 val instBits: Int = if (useCompressed) 16 else 32 val nLocalInterrupts: Int = 15 val nPMPs: Int = 0 val nBreakpoints: Int = 0 val useBPWatch: Boolean = false val nPerfCounters: Int = 29 val haveBasicCounters: Boolean = true val haveFSDirty: Boolean = false val misaWritable: Boolean = false val haveCFlush: Boolean = false val nL2TLBEntries: Int = 0 val mtvecInit: Option[BigInt] = Some(BigInt(0)) val mtvecWritable: Boolean = true val nL2TLBWays: Int = 1 val lrscCycles: Int = 80 val mcontextWidth: Int = 0 val scontextWidth: Int = 0 val useNMI: Boolean = true val nPTECacheEntries: Int = 0 val traceHasWdata: Boolean = false val useConditionalZero: Boolean = false val useZba: Boolean = false val useZbb: Boolean = false val useZbs: Boolean = false } case class IbexTileAttachParams( tileParams: IbexTileParams, crossingParams: RocketCrossingParams ) extends CanAttachTile { type TileType = IbexTile val lookup = PriorityMuxHartIdFromSeq(Seq(tileParams)) } case class IbexTileParams( name: Option[String] = Some("ibex_tile"), tileId: Int = 0, val core: IbexCoreParams = IbexCoreParams() ) extends InstantiableTileParams[IbexTile] { val beuAddr: Option[BigInt] = None val blockerCtrlAddr: Option[BigInt] = None val btb: Option[BTBParams] = None val boundaryBuffers: Boolean = false val dcache: Option[DCacheParams] = None //no dcache val icache: Option[ICacheParams] = None //optional icache, currently in draft so turning option off val clockSinkParams: ClockSinkParameters = ClockSinkParameters() def instantiate(crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters): IbexTile = { new IbexTile(this, crossing, lookup) } val baseName = name.getOrElse("ibex_tile") val uniqueName = s"${baseName}_$tileId" } class IbexTile private( val ibexParams: IbexTileParams, crossing: ClockCrossingType, lookup: LookupByHartIdImpl, q: Parameters) extends BaseTile(ibexParams, crossing, lookup, q) with SinksExternalInterrupts with SourcesExternalNotifications { def this(params: IbexTileParams, crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters) = this(params, crossing.crossingType, lookup, p) //TileLink nodes val intOutwardNode = None val masterNode = visibilityNode val slaveNode = TLIdentityNode() tlOtherMastersNode := tlMasterXbar.node masterNode :=* tlOtherMastersNode DisableMonitors { implicit p => tlSlaveXbar.node :*= slaveNode } override lazy val module = new IbexTileModuleImp(this) val portName = "ibex-mem-port" val node = TLIdentityNode() val dmemNode = TLClientNode( Seq(TLMasterPortParameters.v1( clients = Seq(TLMasterParameters.v1( name = portName, sourceId = IdRange(0, 1)))))) val imemNode = TLClientNode( Seq(TLMasterPortParameters.v1( clients = Seq(TLMasterParameters.v1( name = portName, sourceId = IdRange(0, 1)))))) tlMasterXbar.node := node := TLBuffer() := dmemNode tlMasterXbar.node := node := TLBuffer() := imemNode // Required entry of CPU device in the device tree for interrupt purpose val cpuDevice: SimpleDevice = new SimpleDevice("cpu", Seq("lowRISC,ibex", "riscv")) { override def parent = Some(ResourceAnchors.cpus) override def describe(resources: ResourceBindings): Description = { val Description(name, mapping) = super.describe(resources) Description(name, mapping ++ cpuProperties ++ nextLevelCacheProperty ++ tileProperties) } } ResourceBinding { Resource(cpuDevice, "reg").bind(ResourceAddress(tileId)) } def connectIbexInterrupts(debug: Bool, msip: Bool, mtip: Bool, meip: Bool) { val (interrupts, _) = intSinkNode.in(0) debug := interrupts(0) msip := interrupts(1) mtip := interrupts(2) meip := interrupts(3) } } class IbexTileModuleImp(outer: IbexTile) extends BaseTileModuleImp(outer){ // annotate the parameters Annotated.params(this, outer.ibexParams) // convert string params into int params (since chisel rawparams are converted to strings // which prevents casting from string to enum in SV) // following matches ibex_pkg val rv32mInt: Option[Int] = outer.ibexParams.core.rv32m match { case "RV32MNone" => Some(0) case "RV32MSlow" => Some(1) case "RV32MFast" => Some(2) case "RV32MSingleCycle" => Some(3) case _ => None } require(rv32mInt.isDefined, "Invalid RV32M argument") val rv32bInt: Option[Int] = outer.ibexParams.core.rv32b match { case "RV32BNone" => Some(0) case "RV32BBalanced" => Some(1) case "RV32BFull" => Some(2) case _ => None } require(rv32bInt.isDefined, "Invalid RV32B argument") val regFileInt: Option[Int] = outer.ibexParams.core.regFile match { case "RegFileFF" => Some(0) case "RegFileFPGA" => Some(1) case "RegFileLatch" => Some(2) case _ => None } require(regFileInt.isDefined, "Invalid RegFile argument") val core = Module(new IbexCoreBlackbox( pmpEnable = outer.ibexParams.core.pmpEnable, pmpGranularity = outer.ibexParams.core.pmpGranularity, pmpNumRegions = outer.ibexParams.core.pmpNumRegions, mhpmCounterNum = outer.ibexParams.core.mhpmCounterNum, mhpmCounterWidth = outer.ibexParams.core.mhpmCounterWidth, rv32e = outer.ibexParams.core.rv32e, rv32m = rv32mInt.get, rv32b = rv32bInt.get, regfile = regFileInt.get, branchTargetALU = outer.ibexParams.core.branchTargetALU, wbStage = outer.ibexParams.core.wbStage, branchPredictor = outer.ibexParams.core.branchPredictor, dbgHwBreakNum = outer.ibexParams.core.dbgHwBreakNum, dmHaltAddr = outer.ibexParams.core.dmHaltAddr, dmExceptionAddr = outer.ibexParams.core.dmExceptionAddr )) //connect signals core.io.clk_i := clock core.io.rst_ni := ~reset.asBool core.io.test_en_i := false.B core.io.boot_addr_i := outer.resetVectorSinkNode.bundle core.io.hart_id_i := outer.hartIdSinkNode.bundle outer.connectIbexInterrupts(core.io.debug_req_i, core.io.irq_software_i, core.io.irq_timer_i, core.io.irq_external_i) core.io.irq_nm_i := 0.U //recoverable nmi, tying off core.io.irq_fast_i := 0.U //local interrupts, tying off // MEMORY // DMEM val (dmem, dmem_edge) = outer.dmemNode.out(0) val s_ready :: s_active :: s_inflight :: Nil = Enum(3) val dmem_state = RegInit(s_ready) val dmem_addr = Reg(UInt(32.W)) val dmem_data = Reg(UInt(32.W)) val dmem_mask = Reg(UInt(8.W)) val byte_en = Reg(UInt(4.W)) val num_bytes = Reg(UInt(3.W)) val r_size = Reg(UInt(2.W)) val w_size = Reg(UInt(2.W)) r_size := 2.U when (dmem_state === s_ready && core.io.data_req_o) { dmem_state := s_active dmem_addr := core.io.data_addr_o + (PriorityEncoder(core.io.data_be_o) * core.io.data_we_o) //if write, shift address based on mask dmem_data := core.io.data_wdata_o byte_en := core.io.data_be_o dmem_mask := core.io.data_be_o w_size := PriorityEncoder(PopCount(core.io.data_be_o)) //log2Ceil } when (dmem_state === s_active && dmem.a.fire) { dmem_state := s_inflight } when (dmem_state === s_inflight && dmem.d.fire) { dmem_state := s_ready } dmem.a.valid := dmem_state === s_active core.io.data_gnt_i := dmem_state === s_ready && core.io.data_req_o dmem.d.ready := true.B core.io.data_rvalid_i := dmem.d.valid val dmem_get = dmem_edge.Get(0.U, dmem_addr, r_size)._2 val dmem_put = dmem_edge.Put(0.U, dmem_addr, w_size, dmem_data, dmem_mask)._2 dmem.a.bits := Mux(core.io.data_we_o, dmem_put, dmem_get) //write or read depending on write enable core.io.data_rdata_i := dmem.d.bits.data //read data core.io.data_err_i := dmem.d.bits.corrupt | dmem.d.bits.denied //set error //unused dmem.b.valid := false.B dmem.c.ready := true.B dmem.e.ready := true.B //IMEM val (imem, imem_edge) = outer.imemNode.out(0) val imem_state = RegInit(s_ready) val imem_addr = Reg(UInt(32.W)) when (imem_state === s_ready && core.io.instr_req_o) { imem_state := s_active imem_addr := core.io.instr_addr_o } when (imem_state === s_active && imem.a.fire) { imem_state := s_inflight } when (imem_state === s_inflight && imem.d.fire) { imem_state := s_ready } imem.a.valid := imem_state === s_active core.io.instr_gnt_i := imem_state === s_ready imem.d.ready := true.B core.io.instr_rvalid_i := imem.d.valid val imem_get = imem_edge.Get(0.U, imem_addr, r_size)._2 imem.a.bits := imem_get core.io.instr_rdata_i := imem.d.bits.data core.io.instr_err_i := imem.d.bits.corrupt | imem.d.bits.denied //unused imem.b.valid := false.B imem.c.ready := true.B imem.e.ready := true.B //used for icache, tie off core.io.ram_cfg_i_ram_cfg_en := 0.U core.io.ram_cfg_i_ram_cfg := 0.U core.io.ram_cfg_i_rf_cfg_en := 0.U core.io.ram_cfg_i_rf_cfg := 0.U //continuously fetch instructions core.io.fetch_enable_i := 1.U //DFT not used core.io.scan_rst_ni := 1.U } File BundleBridgeNexus.scala: package org.chipsalliance.diplomacy.bundlebridge import chisel3.{chiselTypeOf, ActualDirection, Data, Reg} import chisel3.reflect.DataMirror import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyRawModuleImp} class BundleBridgeNexus[T <: Data]( inputFn: Seq[T] => T, outputFn: (T, Int) => Seq[T], default: Option[() => T] = None, inputRequiresOutput: Boolean = false, override val shouldBeInlined: Boolean = true )( implicit p: Parameters) extends LazyModule { val node = BundleBridgeNexusNode[T](default, inputRequiresOutput) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val defaultWireOpt = default.map(_()) val inputs: Seq[T] = node.in.map(_._1) inputs.foreach { i => require( DataMirror.checkTypeEquivalence(i, inputs.head), s"${node.context} requires all inputs have equivalent Chisel Data types, but got\n$i\nvs\n${inputs.head}" ) } inputs.flatMap(getElements).foreach { elt => DataMirror.directionOf(elt) match { case ActualDirection.Output => () case ActualDirection.Unspecified => () case _ => require(false, s"${node.context} can only be used with Output-directed Bundles") } } val outputs: Seq[T] = if (node.out.size > 0) { val broadcast: T = if (inputs.size >= 1) inputFn(inputs) else defaultWireOpt.get outputFn(broadcast, node.out.size) } else { Nil } val typeName = outputs.headOption.map(_.typeName).getOrElse("NoOutput") override def desiredName = s"BundleBridgeNexus_$typeName" node.out.map(_._1).foreach { o => require( DataMirror.checkTypeEquivalence(o, outputs.head), s"${node.context} requires all outputs have equivalent Chisel Data types, but got\n$o\nvs\n${outputs.head}" ) } require( outputs.size == node.out.size, s"${node.context} outputFn must generate one output wire per edgeOut, but got ${outputs.size} vs ${node.out.size}" ) node.out.zip(outputs).foreach { case ((out, _), bcast) => out := bcast } } } object BundleBridgeNexus { def safeRegNext[T <: Data](x: T): T = { val reg = Reg(chiselTypeOf(x)) reg := x reg } def requireOne[T <: Data](registered: Boolean)(seq: Seq[T]): T = { require(seq.size == 1, "BundleBroadcast default requires one input") if (registered) safeRegNext(seq.head) else seq.head } def orReduction[T <: Data](registered: Boolean)(seq: Seq[T]): T = { val x = seq.reduce((a, b) => (a.asUInt | b.asUInt).asTypeOf(seq.head)) if (registered) safeRegNext(x) else x } def fillN[T <: Data](registered: Boolean)(x: T, n: Int): Seq[T] = Seq.fill(n) { if (registered) safeRegNext(x) else x } def apply[T <: Data]( inputFn: Seq[T] => T = orReduction[T](false) _, outputFn: (T, Int) => Seq[T] = fillN[T](false) _, default: Option[() => T] = None, inputRequiresOutput: Boolean = false, shouldBeInlined: Boolean = true )( implicit p: Parameters ): BundleBridgeNexusNode[T] = { val nexus = LazyModule(new BundleBridgeNexus[T](inputFn, outputFn, default, inputRequiresOutput, shouldBeInlined)) nexus.node } }
module IbexTile( // @[IbexTile.scala:190:7] input clock, // @[IbexTile.scala:190:7] input reset, // @[IbexTile.scala:190:7] input auto_buffer_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [31:0] auto_buffer_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_int_local_in_2_0, // @[LazyModuleImp.scala:107:25] input auto_int_local_in_1_0, // @[LazyModuleImp.scala:107:25] input auto_int_local_in_1_1, // @[LazyModuleImp.scala:107:25] input auto_int_local_in_0_0, // @[LazyModuleImp.scala:107:25] input auto_hartid_in // @[LazyModuleImp.scala:107:25] ); wire x1_nodeOut_d_valid; // @[MixedNode.scala:542:17] wire x1_nodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17] wire [31:0] x1_nodeOut_d_bits_data; // @[MixedNode.scala:542:17] wire x1_nodeOut_d_bits_denied; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_d_bits_sink; // @[MixedNode.scala:542:17] wire [3:0] x1_nodeOut_d_bits_size; // @[MixedNode.scala:542:17] wire [1:0] x1_nodeOut_d_bits_param; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17] wire x1_nodeOut_a_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid; // @[MixedNode.scala:542:17] wire nodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_d_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_d_bits_denied; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_d_bits_sink; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_d_bits_size; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_d_bits_param; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17] wire nodeOut_a_ready; // @[MixedNode.scala:542:17] wire buffer_2_auto_in_d_valid; // @[Buffer.scala:40:9] wire buffer_2_auto_in_d_ready; // @[Buffer.scala:40:9] wire buffer_2_auto_in_d_bits_corrupt; // @[Buffer.scala:40:9] wire [31:0] buffer_2_auto_in_d_bits_data; // @[Buffer.scala:40:9] wire buffer_2_auto_in_d_bits_denied; // @[Buffer.scala:40:9] wire [2:0] buffer_2_auto_in_d_bits_sink; // @[Buffer.scala:40:9] wire buffer_2_auto_in_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_2_auto_in_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_2_auto_in_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_2_auto_in_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_2_auto_in_a_valid; // @[Buffer.scala:40:9] wire buffer_2_auto_in_a_ready; // @[Buffer.scala:40:9] wire buffer_2_auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire [31:0] buffer_2_auto_in_a_bits_data; // @[Buffer.scala:40:9] wire [3:0] buffer_2_auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [31:0] buffer_2_auto_in_a_bits_address; // @[Buffer.scala:40:9] wire buffer_2_auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_2_auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_2_auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_2_auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire broadcast_auto_in; // @[BundleBridgeNexus.scala:20:9] wire _core_instr_req_o; // @[IbexTile.scala:222:20] wire [31:0] _core_instr_addr_o; // @[IbexTile.scala:222:20] wire _core_data_req_o; // @[IbexTile.scala:222:20] wire _core_data_we_o; // @[IbexTile.scala:222:20] wire [3:0] _core_data_be_o; // @[IbexTile.scala:222:20] wire [31:0] _core_data_addr_o; // @[IbexTile.scala:222:20] wire [31:0] _core_data_wdata_o; // @[IbexTile.scala:222:20] wire auto_buffer_out_a_ready_0 = auto_buffer_out_a_ready; // @[IbexTile.scala:190:7] wire auto_buffer_out_d_valid_0 = auto_buffer_out_d_valid; // @[IbexTile.scala:190:7] wire [2:0] auto_buffer_out_d_bits_opcode_0 = auto_buffer_out_d_bits_opcode; // @[IbexTile.scala:190:7] wire [1:0] auto_buffer_out_d_bits_param_0 = auto_buffer_out_d_bits_param; // @[IbexTile.scala:190:7] wire [3:0] auto_buffer_out_d_bits_size_0 = auto_buffer_out_d_bits_size; // @[IbexTile.scala:190:7] wire auto_buffer_out_d_bits_source_0 = auto_buffer_out_d_bits_source; // @[IbexTile.scala:190:7] wire [2:0] auto_buffer_out_d_bits_sink_0 = auto_buffer_out_d_bits_sink; // @[IbexTile.scala:190:7] wire auto_buffer_out_d_bits_denied_0 = auto_buffer_out_d_bits_denied; // @[IbexTile.scala:190:7] wire [31:0] auto_buffer_out_d_bits_data_0 = auto_buffer_out_d_bits_data; // @[IbexTile.scala:190:7] wire auto_buffer_out_d_bits_corrupt_0 = auto_buffer_out_d_bits_corrupt; // @[IbexTile.scala:190:7] wire auto_int_local_in_2_0_0 = auto_int_local_in_2_0; // @[IbexTile.scala:190:7] wire auto_int_local_in_1_0_0 = auto_int_local_in_1_0; // @[IbexTile.scala:190:7] wire auto_int_local_in_1_1_0 = auto_int_local_in_1_1; // @[IbexTile.scala:190:7] wire auto_int_local_in_0_0_0 = auto_int_local_in_0_0; // @[IbexTile.scala:190:7] wire auto_hartid_in_0 = auto_hartid_in; // @[IbexTile.scala:190:7] wire _core_io_rst_ni_T = reset; // @[IbexTile.scala:242:28] wire auto_wfi_out_0 = 1'h0; // @[IbexTile.scala:190:7] wire auto_cease_out_0 = 1'h0; // @[IbexTile.scala:190:7] wire auto_halt_out_0 = 1'h0; // @[IbexTile.scala:190:7] wire auto_trace_core_source_out_group_0_iretire = 1'h0; // @[IbexTile.scala:190:7] wire auto_trace_core_source_out_group_0_ilastsize = 1'h0; // @[IbexTile.scala:190:7] wire auto_trace_source_out_insns_0_valid = 1'h0; // @[IbexTile.scala:190:7] wire auto_trace_source_out_insns_0_exception = 1'h0; // @[IbexTile.scala:190:7] wire auto_trace_source_out_insns_0_interrupt = 1'h0; // @[IbexTile.scala:190:7] wire auto_trace_source_out_insns_1_valid = 1'h0; // @[IbexTile.scala:190:7] wire auto_trace_source_out_insns_1_exception = 1'h0; // @[IbexTile.scala:190:7] wire auto_trace_source_out_insns_1_interrupt = 1'h0; // @[IbexTile.scala:190:7] wire auto_nmi_in_rnmi = 1'h0; // @[IbexTile.scala:190:7] wire broadcast_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire broadcast_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire broadcast__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire broadcast_1_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire broadcast_1_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire broadcast_1__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nexus_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire nexus_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire nexus__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nexus_1_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire nexus_1_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire nexus_1__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nexus_1_x1_bundleOut_x_sourceOpt_enable = 1'h0; // @[BaseTile.scala:305:19] wire nexus_1_x1_bundleOut_x_sourceOpt_stall = 1'h0; // @[BaseTile.scala:305:19] wire nexus_1_nodeOut_enable = 1'h0; // @[MixedNode.scala:542:17] wire nexus_1_nodeOut_stall = 1'h0; // @[MixedNode.scala:542:17] wire nexus_1_defaultWireOpt_enable = 1'h0; // @[BaseTile.scala:305:19] wire nexus_1_defaultWireOpt_stall = 1'h0; // @[BaseTile.scala:305:19] wire broadcast_2_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire broadcast_2_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire broadcast_2__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nmiSinkNodeIn_rnmi = 1'h0; // @[MixedNode.scala:551:17] wire nmiOut_rnmi = 1'h0; // @[MixedNode.scala:542:17] wire nmiIn_rnmi = 1'h0; // @[MixedNode.scala:551:17] wire traceSourceNodeOut_insns_0_valid = 1'h0; // @[MixedNode.scala:542:17] wire traceSourceNodeOut_insns_0_exception = 1'h0; // @[MixedNode.scala:542:17] wire traceSourceNodeOut_insns_0_interrupt = 1'h0; // @[MixedNode.scala:542:17] wire traceSourceNodeOut_insns_1_valid = 1'h0; // @[MixedNode.scala:542:17] wire traceSourceNodeOut_insns_1_exception = 1'h0; // @[MixedNode.scala:542:17] wire traceSourceNodeOut_insns_1_interrupt = 1'h0; // @[MixedNode.scala:542:17] wire traceCoreSourceNodeOut_group_0_iretire = 1'h0; // @[MixedNode.scala:542:17] wire traceCoreSourceNodeOut_group_0_ilastsize = 1'h0; // @[MixedNode.scala:542:17] wire bundleIn_x_sourceOpt_enable = 1'h0; // @[BaseTile.scala:305:19] wire bundleIn_x_sourceOpt_stall = 1'h0; // @[BaseTile.scala:305:19] wire traceAuxSinkNodeIn_enable = 1'h0; // @[MixedNode.scala:551:17] wire traceAuxSinkNodeIn_stall = 1'h0; // @[MixedNode.scala:551:17] wire haltNodeOut_0 = 1'h0; // @[MixedNode.scala:542:17] wire ceaseNodeOut_0 = 1'h0; // @[MixedNode.scala:542:17] wire wfiNodeOut_0 = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire x1_nodeOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeIn_d_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire x1_nodeIn_d_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire dmemNodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire dmemNodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire imemNodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire imemNodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire dmem_get_source = 1'h0; // @[Edges.scala:460:17] wire dmem_get_corrupt = 1'h0; // @[Edges.scala:460:17] wire dmem_get_a_mask_sizeOH_shiftAmount = 1'h0; // @[OneHot.scala:64:49] wire dmem_get_a_mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _dmem_get_a_mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _dmem_get_a_mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _dmem_put_legal_T_62 = 1'h0; // @[Parameters.scala:684:29] wire _dmem_put_legal_T_68 = 1'h0; // @[Parameters.scala:684:54] wire dmem_put_source = 1'h0; // @[Edges.scala:500:17] wire dmem_put_corrupt = 1'h0; // @[Edges.scala:500:17] wire _dmemNodeOut_a_bits_T_source = 1'h0; // @[IbexTile.scala:289:21] wire _dmemNodeOut_a_bits_T_corrupt = 1'h0; // @[IbexTile.scala:289:21] wire imem_get_source = 1'h0; // @[Edges.scala:460:17] wire imem_get_corrupt = 1'h0; // @[Edges.scala:460:17] wire imem_get_a_mask_sizeOH_shiftAmount = 1'h0; // @[OneHot.scala:64:49] wire imem_get_a_mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _imem_get_a_mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _imem_get_a_mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire [2:0] dmem_put_opcode = 3'h1; // @[Edges.scala:500:17] wire [2:0] imemNodeOut_a_bits_opcode = 3'h4; // @[MixedNode.scala:542:17] wire [2:0] dmem_get_opcode = 3'h4; // @[Edges.scala:460:17] wire [2:0] imem_get_opcode = 3'h4; // @[Edges.scala:460:17] wire [31:0] auto_reset_vector_in = 32'h10000; // @[IbexTile.scala:190:7, :222:20] wire [31:0] broadcast_1_auto_in = 32'h10000; // @[IbexTile.scala:190:7, :222:20] wire [31:0] broadcast_1_auto_out = 32'h10000; // @[IbexTile.scala:190:7, :222:20] wire [31:0] broadcast_1_nodeIn = 32'h10000; // @[IbexTile.scala:190:7, :222:20] wire [31:0] broadcast_1_nodeOut = 32'h10000; // @[IbexTile.scala:190:7, :222:20] wire [31:0] resetVectorSinkNodeIn = 32'h10000; // @[IbexTile.scala:190:7, :222:20] wire [31:0] reset_vectorOut = 32'h10000; // @[IbexTile.scala:190:7, :222:20] wire [31:0] reset_vectorIn = 32'h10000; // @[IbexTile.scala:190:7, :222:20] wire [63:0] auto_trace_source_out_time = 64'h0; // @[IbexTile.scala:190:7] wire [63:0] traceSourceNodeOut_time = 64'h0; // @[MixedNode.scala:542:17] wire [2:0] auto_trace_source_out_insns_0_priv = 3'h0; // @[IbexTile.scala:190:7] wire [2:0] auto_trace_source_out_insns_1_priv = 3'h0; // @[IbexTile.scala:190:7] wire [2:0] traceSourceNodeOut_insns_0_priv = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] traceSourceNodeOut_insns_1_priv = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] dmemNodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] imemNodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] dmem_get_param = 3'h0; // @[Edges.scala:460:17] wire [2:0] dmem_put_param = 3'h0; // @[Edges.scala:500:17] wire [2:0] _dmemNodeOut_a_bits_T_param = 3'h0; // @[IbexTile.scala:289:21] wire [2:0] imem_get_param = 3'h0; // @[Edges.scala:460:17] wire [3:0] auto_trace_core_source_out_group_0_itype = 4'h0; // @[IbexTile.scala:190:7] wire [3:0] auto_trace_core_source_out_priv = 4'h0; // @[IbexTile.scala:190:7] wire [3:0] traceCoreSourceNodeOut_group_0_itype = 4'h0; // @[MixedNode.scala:542:17] wire [3:0] traceCoreSourceNodeOut_priv = 4'h0; // @[MixedNode.scala:542:17] wire [31:0] auto_trace_core_source_out_group_0_iaddr = 32'h0; // @[IbexTile.scala:190:7] wire [31:0] auto_trace_core_source_out_tval = 32'h0; // @[IbexTile.scala:190:7] wire [31:0] auto_trace_core_source_out_cause = 32'h0; // @[IbexTile.scala:190:7] wire [31:0] auto_trace_source_out_insns_0_iaddr = 32'h0; // @[IbexTile.scala:190:7] wire [31:0] auto_trace_source_out_insns_0_insn = 32'h0; // @[IbexTile.scala:190:7] wire [31:0] auto_trace_source_out_insns_0_cause = 32'h0; // @[IbexTile.scala:190:7] wire [31:0] auto_trace_source_out_insns_0_tval = 32'h0; // @[IbexTile.scala:190:7] wire [31:0] auto_trace_source_out_insns_1_iaddr = 32'h0; // @[IbexTile.scala:190:7] wire [31:0] auto_trace_source_out_insns_1_insn = 32'h0; // @[IbexTile.scala:190:7] wire [31:0] auto_trace_source_out_insns_1_cause = 32'h0; // @[IbexTile.scala:190:7] wire [31:0] auto_trace_source_out_insns_1_tval = 32'h0; // @[IbexTile.scala:190:7] wire [31:0] auto_nmi_in_rnmi_interrupt_vector = 32'h0; // @[IbexTile.scala:190:7] wire [31:0] auto_nmi_in_rnmi_exception_vector = 32'h0; // @[IbexTile.scala:190:7] wire [31:0] nmiSinkNodeIn_rnmi_interrupt_vector = 32'h0; // @[MixedNode.scala:551:17] wire [31:0] nmiSinkNodeIn_rnmi_exception_vector = 32'h0; // @[MixedNode.scala:551:17] wire [31:0] nmiOut_rnmi_interrupt_vector = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] nmiOut_rnmi_exception_vector = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] nmiIn_rnmi_interrupt_vector = 32'h0; // @[MixedNode.scala:551:17] wire [31:0] nmiIn_rnmi_exception_vector = 32'h0; // @[MixedNode.scala:551:17] wire [31:0] traceSourceNodeOut_insns_0_iaddr = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] traceSourceNodeOut_insns_0_insn = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] traceSourceNodeOut_insns_0_cause = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] traceSourceNodeOut_insns_0_tval = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] traceSourceNodeOut_insns_1_iaddr = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] traceSourceNodeOut_insns_1_insn = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] traceSourceNodeOut_insns_1_cause = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] traceSourceNodeOut_insns_1_tval = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] traceCoreSourceNodeOut_group_0_iaddr = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] traceCoreSourceNodeOut_tval = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] traceCoreSourceNodeOut_cause = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] imemNodeOut_a_bits_data = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] dmem_get_data = 32'h0; // @[Edges.scala:460:17] wire [31:0] imem_get_data = 32'h0; // @[Edges.scala:460:17] wire [1:0] _dmem_get_a_mask_sizeOH_T = 2'h2; // @[Misc.scala:202:34] wire [1:0] _imem_get_a_mask_sizeOH_T = 2'h2; // @[Misc.scala:202:34] wire [3:0] imemNodeOut_a_bits_size = 4'h2; // @[Edges.scala:460:17, :463:15] wire [3:0] dmem_get_size = 4'h2; // @[Edges.scala:460:17, :463:15] wire [3:0] imem_get_size = 4'h2; // @[Edges.scala:460:17, :463:15] wire [1:0] _dmem_get_a_mask_sizeOH_T_1 = 2'h1; // @[OneHot.scala:65:12] wire [1:0] _dmem_get_a_mask_sizeOH_T_2 = 2'h1; // @[OneHot.scala:65:27] wire [1:0] dmem_get_a_mask_sizeOH = 2'h1; // @[Misc.scala:202:81] wire [1:0] _imem_get_a_mask_sizeOH_T_1 = 2'h1; // @[OneHot.scala:65:12] wire [1:0] _imem_get_a_mask_sizeOH_T_2 = 2'h1; // @[OneHot.scala:65:27] wire [1:0] imem_get_a_mask_sizeOH = 2'h1; // @[Misc.scala:202:81] wire dmemNodeOut_d_ready = 1'h1; // @[MixedNode.scala:542:17] wire imemNodeOut_d_ready = 1'h1; // @[MixedNode.scala:542:17] wire _dmem_get_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _dmem_get_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _dmem_get_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _dmem_get_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _dmem_get_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _dmem_get_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _dmem_get_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _dmem_get_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire dmem_get_a_mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire dmem_get_a_mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire dmem_get_a_mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire dmem_get_a_mask_size = 1'h1; // @[Misc.scala:209:26] wire dmem_get_a_mask_acc = 1'h1; // @[Misc.scala:215:29] wire dmem_get_a_mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire dmem_get_a_mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire dmem_get_a_mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire _dmem_put_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _dmem_put_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _dmem_put_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _dmem_put_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _dmem_put_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _dmem_put_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _dmem_put_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _dmem_put_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire _imem_get_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _imem_get_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _imem_get_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _imem_get_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _imem_get_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _imem_get_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _imem_get_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _imem_get_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire imem_get_a_mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire imem_get_a_mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire imem_get_a_mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire imem_get_a_mask_size = 1'h1; // @[Misc.scala:209:26] wire imem_get_a_mask_acc = 1'h1; // @[Misc.scala:215:29] wire imem_get_a_mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire imem_get_a_mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire imem_get_a_mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire [1:0] dmem_get_a_mask_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] dmem_get_a_mask_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] imem_get_a_mask_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] imem_get_a_mask_hi = 2'h3; // @[Misc.scala:222:10] wire [3:0] imemNodeOut_a_bits_mask = 4'hF; // @[Misc.scala:222:10] wire [3:0] dmem_get_mask = 4'hF; // @[Misc.scala:222:10] wire [3:0] _dmem_get_a_mask_T = 4'hF; // @[Misc.scala:222:10] wire [3:0] imem_get_mask = 4'hF; // @[Misc.scala:222:10] wire [3:0] _imem_get_a_mask_T = 4'hF; // @[Misc.scala:222:10] wire buffer_2_auto_out_a_ready = auto_buffer_out_a_ready_0; // @[Buffer.scala:40:9] wire buffer_2_auto_out_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_2_auto_out_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_2_auto_out_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_2_auto_out_a_bits_size; // @[Buffer.scala:40:9] wire buffer_2_auto_out_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_2_auto_out_a_bits_address; // @[Buffer.scala:40:9] wire [3:0] buffer_2_auto_out_a_bits_mask; // @[Buffer.scala:40:9] wire [31:0] buffer_2_auto_out_a_bits_data; // @[Buffer.scala:40:9] wire buffer_2_auto_out_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_2_auto_out_d_ready; // @[Buffer.scala:40:9] wire buffer_2_auto_out_d_valid = auto_buffer_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] buffer_2_auto_out_d_bits_opcode = auto_buffer_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] buffer_2_auto_out_d_bits_param = auto_buffer_out_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] buffer_2_auto_out_d_bits_size = auto_buffer_out_d_bits_size_0; // @[Buffer.scala:40:9] wire buffer_2_auto_out_d_bits_source = auto_buffer_out_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] buffer_2_auto_out_d_bits_sink = auto_buffer_out_d_bits_sink_0; // @[Buffer.scala:40:9] wire buffer_2_auto_out_d_bits_denied = auto_buffer_out_d_bits_denied_0; // @[Buffer.scala:40:9] wire [31:0] buffer_2_auto_out_d_bits_data = auto_buffer_out_d_bits_data_0; // @[Buffer.scala:40:9] wire buffer_2_auto_out_d_bits_corrupt = auto_buffer_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire x1_int_localIn_1_0 = auto_int_local_in_2_0_0; // @[IbexTile.scala:190:7] wire x1_int_localIn_0 = auto_int_local_in_1_0_0; // @[IbexTile.scala:190:7] wire x1_int_localIn_1 = auto_int_local_in_1_1_0; // @[IbexTile.scala:190:7] wire int_localIn_0 = auto_int_local_in_0_0_0; // @[IbexTile.scala:190:7] wire hartidIn = auto_hartid_in_0; // @[IbexTile.scala:190:7] wire [2:0] auto_buffer_out_a_bits_opcode_0; // @[IbexTile.scala:190:7] wire [2:0] auto_buffer_out_a_bits_param_0; // @[IbexTile.scala:190:7] wire [3:0] auto_buffer_out_a_bits_size_0; // @[IbexTile.scala:190:7] wire auto_buffer_out_a_bits_source_0; // @[IbexTile.scala:190:7] wire [31:0] auto_buffer_out_a_bits_address_0; // @[IbexTile.scala:190:7] wire [3:0] auto_buffer_out_a_bits_mask_0; // @[IbexTile.scala:190:7] wire [31:0] auto_buffer_out_a_bits_data_0; // @[IbexTile.scala:190:7] wire auto_buffer_out_a_bits_corrupt_0; // @[IbexTile.scala:190:7] wire auto_buffer_out_a_valid_0; // @[IbexTile.scala:190:7] wire auto_buffer_out_d_ready_0; // @[IbexTile.scala:190:7] wire hartidOut; // @[MixedNode.scala:542:17] wire broadcast_nodeIn = broadcast_auto_in; // @[MixedNode.scala:551:17] wire broadcast_nodeOut; // @[MixedNode.scala:542:17] wire broadcast_auto_out; // @[BundleBridgeNexus.scala:20:9] wire hartIdSinkNodeIn = broadcast_auto_out; // @[MixedNode.scala:551:17] assign broadcast_nodeOut = broadcast_nodeIn; // @[MixedNode.scala:542:17, :551:17] assign broadcast_auto_out = broadcast_nodeOut; // @[MixedNode.scala:542:17] wire buffer_2_nodeIn_a_ready; // @[MixedNode.scala:551:17] wire tlOtherMastersNodeOut_a_ready = buffer_2_auto_in_a_ready; // @[Buffer.scala:40:9] wire tlOtherMastersNodeOut_a_valid; // @[MixedNode.scala:542:17] wire buffer_2_nodeIn_a_valid = buffer_2_auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] tlOtherMastersNodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_2_nodeIn_a_bits_opcode = buffer_2_auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] tlOtherMastersNodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_2_nodeIn_a_bits_param = buffer_2_auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] tlOtherMastersNodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] buffer_2_nodeIn_a_bits_size = buffer_2_auto_in_a_bits_size; // @[Buffer.scala:40:9] wire tlOtherMastersNodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire buffer_2_nodeIn_a_bits_source = buffer_2_auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] tlOtherMastersNodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] buffer_2_nodeIn_a_bits_address = buffer_2_auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [3:0] tlOtherMastersNodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [3:0] buffer_2_nodeIn_a_bits_mask = buffer_2_auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [31:0] tlOtherMastersNodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire [31:0] buffer_2_nodeIn_a_bits_data = buffer_2_auto_in_a_bits_data; // @[Buffer.scala:40:9] wire tlOtherMastersNodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire buffer_2_nodeIn_a_bits_corrupt = buffer_2_auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire tlOtherMastersNodeOut_d_ready; // @[MixedNode.scala:542:17] wire buffer_2_nodeIn_d_ready = buffer_2_auto_in_d_ready; // @[Buffer.scala:40:9] wire buffer_2_nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_2_nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire tlOtherMastersNodeOut_d_valid = buffer_2_auto_in_d_valid; // @[Buffer.scala:40:9] wire [1:0] buffer_2_nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] tlOtherMastersNodeOut_d_bits_opcode = buffer_2_auto_in_d_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] buffer_2_nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] tlOtherMastersNodeOut_d_bits_param = buffer_2_auto_in_d_bits_param; // @[Buffer.scala:40:9] wire buffer_2_nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] tlOtherMastersNodeOut_d_bits_size = buffer_2_auto_in_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_2_nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire tlOtherMastersNodeOut_d_bits_source = buffer_2_auto_in_d_bits_source; // @[Buffer.scala:40:9] wire buffer_2_nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [2:0] tlOtherMastersNodeOut_d_bits_sink = buffer_2_auto_in_d_bits_sink; // @[Buffer.scala:40:9] wire [31:0] buffer_2_nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire tlOtherMastersNodeOut_d_bits_denied = buffer_2_auto_in_d_bits_denied; // @[Buffer.scala:40:9] wire buffer_2_nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [31:0] tlOtherMastersNodeOut_d_bits_data = buffer_2_auto_in_d_bits_data; // @[Buffer.scala:40:9] wire tlOtherMastersNodeOut_d_bits_corrupt = buffer_2_auto_in_d_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_2_nodeOut_a_ready = buffer_2_auto_out_a_ready; // @[Buffer.scala:40:9] wire buffer_2_nodeOut_a_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_valid_0 = buffer_2_auto_out_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_2_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_opcode_0 = buffer_2_auto_out_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_2_nodeOut_a_bits_param; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_param_0 = buffer_2_auto_out_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_2_nodeOut_a_bits_size; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_size_0 = buffer_2_auto_out_a_bits_size; // @[Buffer.scala:40:9] wire buffer_2_nodeOut_a_bits_source; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_source_0 = buffer_2_auto_out_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_2_nodeOut_a_bits_address; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_address_0 = buffer_2_auto_out_a_bits_address; // @[Buffer.scala:40:9] wire [3:0] buffer_2_nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_mask_0 = buffer_2_auto_out_a_bits_mask; // @[Buffer.scala:40:9] wire [31:0] buffer_2_nodeOut_a_bits_data; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_data_0 = buffer_2_auto_out_a_bits_data; // @[Buffer.scala:40:9] wire buffer_2_nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_corrupt_0 = buffer_2_auto_out_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_2_nodeOut_d_ready; // @[MixedNode.scala:542:17] assign auto_buffer_out_d_ready_0 = buffer_2_auto_out_d_ready; // @[Buffer.scala:40:9] wire buffer_2_nodeOut_d_valid = buffer_2_auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_2_nodeOut_d_bits_opcode = buffer_2_auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_2_nodeOut_d_bits_param = buffer_2_auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_2_nodeOut_d_bits_size = buffer_2_auto_out_d_bits_size; // @[Buffer.scala:40:9] wire buffer_2_nodeOut_d_bits_source = buffer_2_auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] buffer_2_nodeOut_d_bits_sink = buffer_2_auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire buffer_2_nodeOut_d_bits_denied = buffer_2_auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [31:0] buffer_2_nodeOut_d_bits_data = buffer_2_auto_out_d_bits_data; // @[Buffer.scala:40:9] wire buffer_2_nodeOut_d_bits_corrupt = buffer_2_auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_2_nodeIn_a_ready = buffer_2_nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_2_auto_out_a_valid = buffer_2_nodeOut_a_valid; // @[Buffer.scala:40:9] assign buffer_2_auto_out_a_bits_opcode = buffer_2_nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_2_auto_out_a_bits_param = buffer_2_nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign buffer_2_auto_out_a_bits_size = buffer_2_nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign buffer_2_auto_out_a_bits_source = buffer_2_nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign buffer_2_auto_out_a_bits_address = buffer_2_nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign buffer_2_auto_out_a_bits_mask = buffer_2_nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_2_auto_out_a_bits_data = buffer_2_nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign buffer_2_auto_out_a_bits_corrupt = buffer_2_nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_2_auto_out_d_ready = buffer_2_nodeOut_d_ready; // @[Buffer.scala:40:9] assign buffer_2_nodeIn_d_valid = buffer_2_nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_2_nodeIn_d_bits_opcode = buffer_2_nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_2_nodeIn_d_bits_param = buffer_2_nodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_2_nodeIn_d_bits_size = buffer_2_nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_2_nodeIn_d_bits_source = buffer_2_nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_2_nodeIn_d_bits_sink = buffer_2_nodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign buffer_2_nodeIn_d_bits_denied = buffer_2_nodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign buffer_2_nodeIn_d_bits_data = buffer_2_nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_2_nodeIn_d_bits_corrupt = buffer_2_nodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_2_auto_in_a_ready = buffer_2_nodeIn_a_ready; // @[Buffer.scala:40:9] assign buffer_2_nodeOut_a_valid = buffer_2_nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_2_nodeOut_a_bits_opcode = buffer_2_nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_2_nodeOut_a_bits_param = buffer_2_nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_2_nodeOut_a_bits_size = buffer_2_nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_2_nodeOut_a_bits_source = buffer_2_nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_2_nodeOut_a_bits_address = buffer_2_nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_2_nodeOut_a_bits_mask = buffer_2_nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_2_nodeOut_a_bits_data = buffer_2_nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_2_nodeOut_a_bits_corrupt = buffer_2_nodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_2_nodeOut_d_ready = buffer_2_nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_2_auto_in_d_valid = buffer_2_nodeIn_d_valid; // @[Buffer.scala:40:9] assign buffer_2_auto_in_d_bits_opcode = buffer_2_nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign buffer_2_auto_in_d_bits_param = buffer_2_nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign buffer_2_auto_in_d_bits_size = buffer_2_nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign buffer_2_auto_in_d_bits_source = buffer_2_nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign buffer_2_auto_in_d_bits_sink = buffer_2_nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign buffer_2_auto_in_d_bits_denied = buffer_2_nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign buffer_2_auto_in_d_bits_data = buffer_2_nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign buffer_2_auto_in_d_bits_corrupt = buffer_2_nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] wire tlOtherMastersNodeIn_a_ready = tlOtherMastersNodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_a_valid; // @[MixedNode.scala:551:17] assign buffer_2_auto_in_a_valid = tlOtherMastersNodeOut_a_valid; // @[Buffer.scala:40:9] wire [2:0] tlOtherMastersNodeIn_a_bits_opcode; // @[MixedNode.scala:551:17] assign buffer_2_auto_in_a_bits_opcode = tlOtherMastersNodeOut_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] tlOtherMastersNodeIn_a_bits_param; // @[MixedNode.scala:551:17] assign buffer_2_auto_in_a_bits_param = tlOtherMastersNodeOut_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] tlOtherMastersNodeIn_a_bits_size; // @[MixedNode.scala:551:17] assign buffer_2_auto_in_a_bits_size = tlOtherMastersNodeOut_a_bits_size; // @[Buffer.scala:40:9] wire tlOtherMastersNodeIn_a_bits_source; // @[MixedNode.scala:551:17] assign buffer_2_auto_in_a_bits_source = tlOtherMastersNodeOut_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] tlOtherMastersNodeIn_a_bits_address; // @[MixedNode.scala:551:17] assign buffer_2_auto_in_a_bits_address = tlOtherMastersNodeOut_a_bits_address; // @[Buffer.scala:40:9] wire [3:0] tlOtherMastersNodeIn_a_bits_mask; // @[MixedNode.scala:551:17] assign buffer_2_auto_in_a_bits_mask = tlOtherMastersNodeOut_a_bits_mask; // @[Buffer.scala:40:9] wire [31:0] tlOtherMastersNodeIn_a_bits_data; // @[MixedNode.scala:551:17] assign buffer_2_auto_in_a_bits_data = tlOtherMastersNodeOut_a_bits_data; // @[Buffer.scala:40:9] wire tlOtherMastersNodeIn_a_bits_corrupt; // @[MixedNode.scala:551:17] assign buffer_2_auto_in_a_bits_corrupt = tlOtherMastersNodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] wire tlOtherMastersNodeIn_d_ready; // @[MixedNode.scala:551:17] assign buffer_2_auto_in_d_ready = tlOtherMastersNodeOut_d_ready; // @[Buffer.scala:40:9] wire tlOtherMastersNodeIn_d_valid = tlOtherMastersNodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] tlOtherMastersNodeIn_d_bits_opcode = tlOtherMastersNodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] tlOtherMastersNodeIn_d_bits_param = tlOtherMastersNodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] tlOtherMastersNodeIn_d_bits_size = tlOtherMastersNodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_d_bits_source = tlOtherMastersNodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] tlOtherMastersNodeIn_d_bits_sink = tlOtherMastersNodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_d_bits_denied = tlOtherMastersNodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [31:0] tlOtherMastersNodeIn_d_bits_data = tlOtherMastersNodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_d_bits_corrupt = tlOtherMastersNodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_valid = tlOtherMastersNodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_opcode = tlOtherMastersNodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_param = tlOtherMastersNodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_size = tlOtherMastersNodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_source = tlOtherMastersNodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_address = tlOtherMastersNodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_mask = tlOtherMastersNodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_data = tlOtherMastersNodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_corrupt = tlOtherMastersNodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_d_ready = tlOtherMastersNodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign broadcast_auto_in = hartidOut; // @[MixedNode.scala:542:17] assign hartidOut = hartidIn; // @[MixedNode.scala:542:17, :551:17] wire int_localOut_0; // @[MixedNode.scala:542:17] wire x1_int_localOut_0; // @[MixedNode.scala:542:17] wire x1_int_localOut_1; // @[MixedNode.scala:542:17] wire x1_int_localOut_1_0; // @[MixedNode.scala:542:17] assign int_localOut_0 = int_localIn_0; // @[MixedNode.scala:542:17, :551:17] assign x1_int_localOut_0 = x1_int_localIn_0; // @[MixedNode.scala:542:17, :551:17] assign x1_int_localOut_1 = x1_int_localIn_1; // @[MixedNode.scala:542:17, :551:17] assign x1_int_localOut_1_0 = x1_int_localIn_1_0; // @[MixedNode.scala:542:17, :551:17] wire intSinkNodeIn_0; // @[MixedNode.scala:551:17] wire intSinkNodeIn_1; // @[MixedNode.scala:551:17] wire intSinkNodeIn_2; // @[MixedNode.scala:551:17] wire intSinkNodeIn_3; // @[MixedNode.scala:551:17] wire nodeIn_a_ready = nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17] wire nodeIn_a_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_a_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_a_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_a_bits_size; // @[MixedNode.scala:551:17] wire nodeIn_a_bits_source; // @[MixedNode.scala:551:17] wire [31:0] nodeIn_a_bits_address; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_a_bits_mask; // @[MixedNode.scala:551:17] wire [31:0] nodeIn_a_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_a_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_d_ready; // @[MixedNode.scala:551:17] wire nodeIn_d_valid = nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] nodeIn_d_bits_opcode = nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] nodeIn_d_bits_param = nodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] nodeIn_d_bits_size = nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [2:0] nodeIn_d_bits_sink = nodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire nodeIn_d_bits_denied = nodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [31:0] nodeIn_d_bits_data = nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeIn_d_bits_corrupt = nodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire x1_nodeIn_a_ready = x1_nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17] wire x1_nodeIn_a_valid; // @[MixedNode.scala:551:17] wire [2:0] x1_nodeIn_a_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] x1_nodeIn_a_bits_param; // @[MixedNode.scala:551:17] wire [3:0] x1_nodeIn_a_bits_size; // @[MixedNode.scala:551:17] wire x1_nodeIn_a_bits_source; // @[MixedNode.scala:551:17] wire [31:0] x1_nodeIn_a_bits_address; // @[MixedNode.scala:551:17] wire [3:0] x1_nodeIn_a_bits_mask; // @[MixedNode.scala:551:17] wire [31:0] x1_nodeIn_a_bits_data; // @[MixedNode.scala:551:17] wire x1_nodeIn_a_bits_corrupt; // @[MixedNode.scala:551:17] wire x1_nodeIn_d_ready; // @[MixedNode.scala:551:17] wire x1_nodeIn_d_valid = x1_nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_nodeIn_d_bits_opcode = x1_nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_nodeIn_d_bits_param = x1_nodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] x1_nodeIn_d_bits_size = x1_nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_nodeIn_d_bits_sink = x1_nodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire x1_nodeIn_d_bits_denied = x1_nodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [31:0] x1_nodeIn_d_bits_data = x1_nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] x1_nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire x1_nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] x1_nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [3:0] x1_nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [31:0] x1_nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire x1_nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_nodeIn_d_bits_corrupt = x1_nodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire x1_nodeOut_a_valid; // @[MixedNode.scala:542:17] wire x1_nodeOut_d_ready; // @[MixedNode.scala:542:17] assign nodeOut_a_valid = nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_opcode = nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_param = nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_size = nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_source = nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_address = nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_mask = nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_data = nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_corrupt = nodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_d_ready = nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign x1_nodeOut_a_valid = x1_nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign x1_nodeOut_a_bits_opcode = x1_nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_nodeOut_a_bits_param = x1_nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign x1_nodeOut_a_bits_size = x1_nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign x1_nodeOut_a_bits_source = x1_nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign x1_nodeOut_a_bits_address = x1_nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign x1_nodeOut_a_bits_mask = x1_nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign x1_nodeOut_a_bits_data = x1_nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_nodeOut_a_bits_corrupt = x1_nodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign x1_nodeOut_d_ready = x1_nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17] wire _dmemNodeOut_a_valid_T; // @[IbexTile.scala:281:30] wire [2:0] _dmemNodeOut_a_bits_T_opcode; // @[IbexTile.scala:289:21] wire [3:0] _dmemNodeOut_a_bits_T_size; // @[IbexTile.scala:289:21] wire [31:0] _dmemNodeOut_a_bits_T_address; // @[IbexTile.scala:289:21] wire [3:0] _dmemNodeOut_a_bits_T_mask; // @[IbexTile.scala:289:21] wire [31:0] _dmemNodeOut_a_bits_T_data; // @[IbexTile.scala:289:21] wire [2:0] dmemNodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [3:0] dmemNodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [31:0] dmemNodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [3:0] dmemNodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [31:0] dmemNodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire dmemNodeOut_a_ready; // @[MixedNode.scala:542:17] wire dmemNodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] dmemNodeOut_d_bits_opcode; // @[MixedNode.scala:542:17] wire [1:0] dmemNodeOut_d_bits_param; // @[MixedNode.scala:542:17] wire [3:0] dmemNodeOut_d_bits_size; // @[MixedNode.scala:542:17] wire dmemNodeOut_d_bits_source; // @[MixedNode.scala:542:17] wire [2:0] dmemNodeOut_d_bits_sink; // @[MixedNode.scala:542:17] wire dmemNodeOut_d_bits_denied; // @[MixedNode.scala:542:17] wire [31:0] dmemNodeOut_d_bits_data; // @[MixedNode.scala:542:17] wire dmemNodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17] wire dmemNodeOut_d_valid; // @[MixedNode.scala:542:17] wire _imemNodeOut_a_valid_T; // @[IbexTile.scala:315:30] wire [31:0] imem_get_address; // @[Edges.scala:460:17] wire [31:0] imemNodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire imemNodeOut_a_ready; // @[MixedNode.scala:542:17] wire imemNodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] imemNodeOut_d_bits_opcode; // @[MixedNode.scala:542:17] wire [1:0] imemNodeOut_d_bits_param; // @[MixedNode.scala:542:17] wire [3:0] imemNodeOut_d_bits_size; // @[MixedNode.scala:542:17] wire imemNodeOut_d_bits_source; // @[MixedNode.scala:542:17] wire [2:0] imemNodeOut_d_bits_sink; // @[MixedNode.scala:542:17] wire imemNodeOut_d_bits_denied; // @[MixedNode.scala:542:17] wire [31:0] imemNodeOut_d_bits_data; // @[MixedNode.scala:542:17] wire imemNodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17] wire imemNodeOut_d_valid; // @[MixedNode.scala:542:17] wire _core_io_rst_ni_T_1 = ~_core_io_rst_ni_T; // @[IbexTile.scala:242:{21,28}] reg [1:0] dmem_state; // @[IbexTile.scala:256:27] reg [31:0] dmem_addr; // @[IbexTile.scala:258:22] wire [31:0] _dmem_get_legal_T_14 = dmem_addr; // @[Parameters.scala:137:31] wire [31:0] dmem_get_address = dmem_addr; // @[Edges.scala:460:17] wire [31:0] _dmem_put_legal_T_14 = dmem_addr; // @[Parameters.scala:137:31] wire [31:0] dmem_put_address = dmem_addr; // @[Edges.scala:500:17] reg [31:0] dmem_data; // @[IbexTile.scala:259:22] wire [31:0] dmem_put_data = dmem_data; // @[Edges.scala:500:17] reg [7:0] dmem_mask; // @[IbexTile.scala:260:22] reg [3:0] byte_en; // @[IbexTile.scala:261:20] reg [1:0] w_size; // @[IbexTile.scala:264:19] wire _core_io_data_gnt_i_T = dmem_state == 2'h0; // @[IbexTile.scala:256:27, :267:20, :282:36] wire _dmem_addr_T = _core_data_be_o[0]; // @[OneHot.scala:48:45] wire _w_size_T = _core_data_be_o[0]; // @[OneHot.scala:48:45] wire _dmem_addr_T_1 = _core_data_be_o[1]; // @[OneHot.scala:48:45] wire _w_size_T_1 = _core_data_be_o[1]; // @[OneHot.scala:48:45] wire _dmem_addr_T_2 = _core_data_be_o[2]; // @[OneHot.scala:48:45] wire _w_size_T_2 = _core_data_be_o[2]; // @[OneHot.scala:48:45] wire _dmem_addr_T_3 = _core_data_be_o[3]; // @[OneHot.scala:48:45] wire _w_size_T_3 = _core_data_be_o[3]; // @[OneHot.scala:48:45] wire [1:0] _dmem_addr_T_4 = {1'h1, ~_dmem_addr_T_2}; // @[OneHot.scala:48:45] wire [1:0] _dmem_addr_T_5 = _dmem_addr_T_1 ? 2'h1 : _dmem_addr_T_4; // @[OneHot.scala:48:45] wire [1:0] _dmem_addr_T_6 = _dmem_addr_T ? 2'h0 : _dmem_addr_T_5; // @[OneHot.scala:48:45] wire [2:0] _dmem_addr_T_7 = {1'h0, _dmem_addr_T_6} * {2'h0, _core_data_we_o}; // @[Mux.scala:50:70] wire [32:0] _dmem_addr_T_8 = {1'h0, _core_data_addr_o} + {30'h0, _dmem_addr_T_7}; // @[IbexTile.scala:222:20, :269:{38,76}] wire [31:0] _dmem_addr_T_9 = _dmem_addr_T_8[31:0]; // @[IbexTile.scala:269:38] wire [1:0] _w_size_T_4 = {1'h0, _w_size_T} + {1'h0, _w_size_T_1}; // @[IbexTile.scala:273:39] wire [1:0] _w_size_T_5 = _w_size_T_4; // @[IbexTile.scala:273:39] wire [1:0] _w_size_T_6 = {1'h0, _w_size_T_2} + {1'h0, _w_size_T_3}; // @[IbexTile.scala:273:39] wire [1:0] _w_size_T_7 = _w_size_T_6; // @[IbexTile.scala:273:39] wire [2:0] _w_size_T_8 = {1'h0, _w_size_T_5} + {1'h0, _w_size_T_7}; // @[IbexTile.scala:273:39] wire [2:0] _w_size_T_9 = _w_size_T_8; // @[IbexTile.scala:273:39] wire _w_size_T_10 = _w_size_T_9[0]; // @[OneHot.scala:48:45] wire _w_size_T_11 = _w_size_T_9[1]; // @[OneHot.scala:48:45] wire _w_size_T_12 = _w_size_T_9[2]; // @[OneHot.scala:48:45] wire [1:0] _w_size_T_13 = _w_size_T_11 ? 2'h1 : 2'h2; // @[OneHot.scala:48:45] wire [1:0] _w_size_T_14 = _w_size_T_10 ? 2'h0 : _w_size_T_13; // @[OneHot.scala:48:45] assign _dmemNodeOut_a_valid_T = dmem_state == 2'h1; // @[IbexTile.scala:256:27, :275:20, :281:30] assign dmemNodeOut_a_valid = _dmemNodeOut_a_valid_T; // @[IbexTile.scala:281:30] wire _core_io_data_gnt_i_T_1 = _core_io_data_gnt_i_T & _core_data_req_o; // @[IbexTile.scala:222:20, :282:{36,48}] wire [31:0] _GEN = {dmem_addr[31:14], dmem_addr[13:0] ^ 14'h3000}; // @[Parameters.scala:137:31] wire [31:0] _dmem_get_legal_T_4; // @[Parameters.scala:137:31] assign _dmem_get_legal_T_4 = _GEN; // @[Parameters.scala:137:31] wire [31:0] _dmem_put_legal_T_4; // @[Parameters.scala:137:31] assign _dmem_put_legal_T_4 = _GEN; // @[Parameters.scala:137:31] wire [32:0] _dmem_get_legal_T_5 = {1'h0, _dmem_get_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [32:0] _dmem_get_legal_T_6 = _dmem_get_legal_T_5 & 33'h9A013000; // @[Parameters.scala:137:{41,46}] wire [32:0] _dmem_get_legal_T_7 = _dmem_get_legal_T_6; // @[Parameters.scala:137:46] wire _dmem_get_legal_T_8 = _dmem_get_legal_T_7 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _dmem_get_legal_T_9 = _dmem_get_legal_T_8; // @[Parameters.scala:684:54] wire _dmem_get_legal_T_62 = _dmem_get_legal_T_9; // @[Parameters.scala:684:54, :686:26] wire [32:0] _dmem_get_legal_T_15 = {1'h0, _dmem_get_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [32:0] _dmem_get_legal_T_16 = _dmem_get_legal_T_15 & 33'h9A012000; // @[Parameters.scala:137:{41,46}] wire [32:0] _dmem_get_legal_T_17 = _dmem_get_legal_T_16; // @[Parameters.scala:137:46] wire _dmem_get_legal_T_18 = _dmem_get_legal_T_17 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_0 = {dmem_addr[31:17], dmem_addr[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31] wire [31:0] _dmem_get_legal_T_19; // @[Parameters.scala:137:31] assign _dmem_get_legal_T_19 = _GEN_0; // @[Parameters.scala:137:31] wire [31:0] _dmem_get_legal_T_24; // @[Parameters.scala:137:31] assign _dmem_get_legal_T_24 = _GEN_0; // @[Parameters.scala:137:31] wire [31:0] _dmem_put_legal_T_63; // @[Parameters.scala:137:31] assign _dmem_put_legal_T_63 = _GEN_0; // @[Parameters.scala:137:31] wire [32:0] _dmem_get_legal_T_20 = {1'h0, _dmem_get_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [32:0] _dmem_get_legal_T_21 = _dmem_get_legal_T_20 & 33'h98013000; // @[Parameters.scala:137:{41,46}] wire [32:0] _dmem_get_legal_T_22 = _dmem_get_legal_T_21; // @[Parameters.scala:137:46] wire _dmem_get_legal_T_23 = _dmem_get_legal_T_22 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _dmem_get_legal_T_25 = {1'h0, _dmem_get_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [32:0] _dmem_get_legal_T_26 = _dmem_get_legal_T_25 & 33'h9A010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _dmem_get_legal_T_27 = _dmem_get_legal_T_26; // @[Parameters.scala:137:46] wire _dmem_get_legal_T_28 = _dmem_get_legal_T_27 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_1 = {dmem_addr[31:26], dmem_addr[25:0] ^ 26'h2000000}; // @[Parameters.scala:137:31] wire [31:0] _dmem_get_legal_T_29; // @[Parameters.scala:137:31] assign _dmem_get_legal_T_29 = _GEN_1; // @[Parameters.scala:137:31] wire [31:0] _dmem_put_legal_T_24; // @[Parameters.scala:137:31] assign _dmem_put_legal_T_24 = _GEN_1; // @[Parameters.scala:137:31] wire [32:0] _dmem_get_legal_T_30 = {1'h0, _dmem_get_legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [32:0] _dmem_get_legal_T_31 = _dmem_get_legal_T_30 & 33'h9A010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _dmem_get_legal_T_32 = _dmem_get_legal_T_31; // @[Parameters.scala:137:46] wire _dmem_get_legal_T_33 = _dmem_get_legal_T_32 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_2 = {dmem_addr[31:28], dmem_addr[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31] wire [31:0] _dmem_get_legal_T_34; // @[Parameters.scala:137:31] assign _dmem_get_legal_T_34 = _GEN_2; // @[Parameters.scala:137:31] wire [31:0] _dmem_get_legal_T_39; // @[Parameters.scala:137:31] assign _dmem_get_legal_T_39 = _GEN_2; // @[Parameters.scala:137:31] wire [31:0] _dmem_put_legal_T_34; // @[Parameters.scala:137:31] assign _dmem_put_legal_T_34 = _GEN_2; // @[Parameters.scala:137:31] wire [31:0] _dmem_put_legal_T_39; // @[Parameters.scala:137:31] assign _dmem_put_legal_T_39 = _GEN_2; // @[Parameters.scala:137:31] wire [32:0] _dmem_get_legal_T_35 = {1'h0, _dmem_get_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [32:0] _dmem_get_legal_T_36 = _dmem_get_legal_T_35 & 33'h98000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _dmem_get_legal_T_37 = _dmem_get_legal_T_36; // @[Parameters.scala:137:46] wire _dmem_get_legal_T_38 = _dmem_get_legal_T_37 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _dmem_get_legal_T_40 = {1'h0, _dmem_get_legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [32:0] _dmem_get_legal_T_41 = _dmem_get_legal_T_40 & 33'h9A010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _dmem_get_legal_T_42 = _dmem_get_legal_T_41; // @[Parameters.scala:137:46] wire _dmem_get_legal_T_43 = _dmem_get_legal_T_42 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_3 = {dmem_addr[31:29], dmem_addr[28:0] ^ 29'h10000000}; // @[Parameters.scala:137:31] wire [31:0] _dmem_get_legal_T_44; // @[Parameters.scala:137:31] assign _dmem_get_legal_T_44 = _GEN_3; // @[Parameters.scala:137:31] wire [31:0] _dmem_put_legal_T_44; // @[Parameters.scala:137:31] assign _dmem_put_legal_T_44 = _GEN_3; // @[Parameters.scala:137:31] wire [32:0] _dmem_get_legal_T_45 = {1'h0, _dmem_get_legal_T_44}; // @[Parameters.scala:137:{31,41}] wire [32:0] _dmem_get_legal_T_46 = _dmem_get_legal_T_45 & 33'h9A013000; // @[Parameters.scala:137:{41,46}] wire [32:0] _dmem_get_legal_T_47 = _dmem_get_legal_T_46; // @[Parameters.scala:137:46] wire _dmem_get_legal_T_48 = _dmem_get_legal_T_47 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_4 = dmem_addr ^ 32'h80000000; // @[Parameters.scala:137:31] wire [31:0] _dmem_get_legal_T_49; // @[Parameters.scala:137:31] assign _dmem_get_legal_T_49 = _GEN_4; // @[Parameters.scala:137:31] wire [31:0] _dmem_put_legal_T_49; // @[Parameters.scala:137:31] assign _dmem_put_legal_T_49 = _GEN_4; // @[Parameters.scala:137:31] wire [32:0] _dmem_get_legal_T_50 = {1'h0, _dmem_get_legal_T_49}; // @[Parameters.scala:137:{31,41}] wire [32:0] _dmem_get_legal_T_51 = _dmem_get_legal_T_50 & 33'h90000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _dmem_get_legal_T_52 = _dmem_get_legal_T_51; // @[Parameters.scala:137:46] wire _dmem_get_legal_T_53 = _dmem_get_legal_T_52 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _dmem_get_legal_T_54 = _dmem_get_legal_T_18 | _dmem_get_legal_T_23; // @[Parameters.scala:685:42] wire _dmem_get_legal_T_55 = _dmem_get_legal_T_54 | _dmem_get_legal_T_28; // @[Parameters.scala:685:42] wire _dmem_get_legal_T_56 = _dmem_get_legal_T_55 | _dmem_get_legal_T_33; // @[Parameters.scala:685:42] wire _dmem_get_legal_T_57 = _dmem_get_legal_T_56 | _dmem_get_legal_T_38; // @[Parameters.scala:685:42] wire _dmem_get_legal_T_58 = _dmem_get_legal_T_57 | _dmem_get_legal_T_43; // @[Parameters.scala:685:42] wire _dmem_get_legal_T_59 = _dmem_get_legal_T_58 | _dmem_get_legal_T_48; // @[Parameters.scala:685:42] wire _dmem_get_legal_T_60 = _dmem_get_legal_T_59 | _dmem_get_legal_T_53; // @[Parameters.scala:685:42] wire _dmem_get_legal_T_61 = _dmem_get_legal_T_60; // @[Parameters.scala:684:54, :685:42] wire dmem_get_legal = _dmem_get_legal_T_62 | _dmem_get_legal_T_61; // @[Parameters.scala:684:54, :686:26] wire dmem_get_a_mask_sub_bit = dmem_addr[1]; // @[Misc.scala:210:26] wire dmem_get_a_mask_sub_1_2 = dmem_get_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire dmem_get_a_mask_sub_nbit = ~dmem_get_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire dmem_get_a_mask_sub_0_2 = dmem_get_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire dmem_get_a_mask_bit = dmem_addr[0]; // @[Misc.scala:210:26] wire dmem_get_a_mask_nbit = ~dmem_get_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire dmem_get_a_mask_eq = dmem_get_a_mask_sub_0_2 & dmem_get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _dmem_get_a_mask_acc_T = dmem_get_a_mask_eq; // @[Misc.scala:214:27, :215:38] wire dmem_get_a_mask_eq_1 = dmem_get_a_mask_sub_0_2 & dmem_get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _dmem_get_a_mask_acc_T_1 = dmem_get_a_mask_eq_1; // @[Misc.scala:214:27, :215:38] wire dmem_get_a_mask_eq_2 = dmem_get_a_mask_sub_1_2 & dmem_get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _dmem_get_a_mask_acc_T_2 = dmem_get_a_mask_eq_2; // @[Misc.scala:214:27, :215:38] wire dmem_get_a_mask_eq_3 = dmem_get_a_mask_sub_1_2 & dmem_get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _dmem_get_a_mask_acc_T_3 = dmem_get_a_mask_eq_3; // @[Misc.scala:214:27, :215:38] wire [32:0] _dmem_put_legal_T_5 = {1'h0, _dmem_put_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [32:0] _dmem_put_legal_T_6 = _dmem_put_legal_T_5 & 33'h9A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _dmem_put_legal_T_7 = _dmem_put_legal_T_6; // @[Parameters.scala:137:46] wire _dmem_put_legal_T_8 = _dmem_put_legal_T_7 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _dmem_put_legal_T_9 = _dmem_put_legal_T_8; // @[Parameters.scala:684:54] wire _dmem_put_legal_T_69 = _dmem_put_legal_T_9; // @[Parameters.scala:684:54, :686:26] wire [32:0] _dmem_put_legal_T_15 = {1'h0, _dmem_put_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [32:0] _dmem_put_legal_T_16 = _dmem_put_legal_T_15 & 33'h9A112000; // @[Parameters.scala:137:{41,46}] wire [32:0] _dmem_put_legal_T_17 = _dmem_put_legal_T_16; // @[Parameters.scala:137:46] wire _dmem_put_legal_T_18 = _dmem_put_legal_T_17 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _dmem_put_legal_T_19 = {dmem_addr[31:21], dmem_addr[20:0] ^ 21'h100000}; // @[Parameters.scala:137:31] wire [32:0] _dmem_put_legal_T_20 = {1'h0, _dmem_put_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [32:0] _dmem_put_legal_T_21 = _dmem_put_legal_T_20 & 33'h9A103000; // @[Parameters.scala:137:{41,46}] wire [32:0] _dmem_put_legal_T_22 = _dmem_put_legal_T_21; // @[Parameters.scala:137:46] wire _dmem_put_legal_T_23 = _dmem_put_legal_T_22 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _dmem_put_legal_T_25 = {1'h0, _dmem_put_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [32:0] _dmem_put_legal_T_26 = _dmem_put_legal_T_25 & 33'h9A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _dmem_put_legal_T_27 = _dmem_put_legal_T_26; // @[Parameters.scala:137:46] wire _dmem_put_legal_T_28 = _dmem_put_legal_T_27 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _dmem_put_legal_T_29 = {dmem_addr[31:26], dmem_addr[25:0] ^ 26'h2010000}; // @[Parameters.scala:137:31] wire [32:0] _dmem_put_legal_T_30 = {1'h0, _dmem_put_legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [32:0] _dmem_put_legal_T_31 = _dmem_put_legal_T_30 & 33'h9A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _dmem_put_legal_T_32 = _dmem_put_legal_T_31; // @[Parameters.scala:137:46] wire _dmem_put_legal_T_33 = _dmem_put_legal_T_32 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _dmem_put_legal_T_35 = {1'h0, _dmem_put_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [32:0] _dmem_put_legal_T_36 = _dmem_put_legal_T_35 & 33'h98000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _dmem_put_legal_T_37 = _dmem_put_legal_T_36; // @[Parameters.scala:137:46] wire _dmem_put_legal_T_38 = _dmem_put_legal_T_37 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _dmem_put_legal_T_40 = {1'h0, _dmem_put_legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [32:0] _dmem_put_legal_T_41 = _dmem_put_legal_T_40 & 33'h9A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _dmem_put_legal_T_42 = _dmem_put_legal_T_41; // @[Parameters.scala:137:46] wire _dmem_put_legal_T_43 = _dmem_put_legal_T_42 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _dmem_put_legal_T_45 = {1'h0, _dmem_put_legal_T_44}; // @[Parameters.scala:137:{31,41}] wire [32:0] _dmem_put_legal_T_46 = _dmem_put_legal_T_45 & 33'h9A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _dmem_put_legal_T_47 = _dmem_put_legal_T_46; // @[Parameters.scala:137:46] wire _dmem_put_legal_T_48 = _dmem_put_legal_T_47 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _dmem_put_legal_T_50 = {1'h0, _dmem_put_legal_T_49}; // @[Parameters.scala:137:{31,41}] wire [32:0] _dmem_put_legal_T_51 = _dmem_put_legal_T_50 & 33'h90000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _dmem_put_legal_T_52 = _dmem_put_legal_T_51; // @[Parameters.scala:137:46] wire _dmem_put_legal_T_53 = _dmem_put_legal_T_52 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _dmem_put_legal_T_54 = _dmem_put_legal_T_18 | _dmem_put_legal_T_23; // @[Parameters.scala:685:42] wire _dmem_put_legal_T_55 = _dmem_put_legal_T_54 | _dmem_put_legal_T_28; // @[Parameters.scala:685:42] wire _dmem_put_legal_T_56 = _dmem_put_legal_T_55 | _dmem_put_legal_T_33; // @[Parameters.scala:685:42] wire _dmem_put_legal_T_57 = _dmem_put_legal_T_56 | _dmem_put_legal_T_38; // @[Parameters.scala:685:42] wire _dmem_put_legal_T_58 = _dmem_put_legal_T_57 | _dmem_put_legal_T_43; // @[Parameters.scala:685:42] wire _dmem_put_legal_T_59 = _dmem_put_legal_T_58 | _dmem_put_legal_T_48; // @[Parameters.scala:685:42] wire _dmem_put_legal_T_60 = _dmem_put_legal_T_59 | _dmem_put_legal_T_53; // @[Parameters.scala:685:42] wire _dmem_put_legal_T_61 = _dmem_put_legal_T_60; // @[Parameters.scala:684:54, :685:42] wire [32:0] _dmem_put_legal_T_64 = {1'h0, _dmem_put_legal_T_63}; // @[Parameters.scala:137:{31,41}] wire [32:0] _dmem_put_legal_T_65 = _dmem_put_legal_T_64 & 33'h9A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _dmem_put_legal_T_66 = _dmem_put_legal_T_65; // @[Parameters.scala:137:46] wire _dmem_put_legal_T_67 = _dmem_put_legal_T_66 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _dmem_put_legal_T_70 = _dmem_put_legal_T_69 | _dmem_put_legal_T_61; // @[Parameters.scala:684:54, :686:26] wire dmem_put_legal = _dmem_put_legal_T_70; // @[Parameters.scala:686:26] wire [3:0] dmem_put_size; // @[Edges.scala:500:17] wire [3:0] dmem_put_mask; // @[Edges.scala:500:17] assign dmem_put_size = {2'h0, w_size}; // @[Edges.scala:500:17, :503:15] assign dmem_put_mask = dmem_mask[3:0]; // @[Edges.scala:500:17, :508:15] assign _dmemNodeOut_a_bits_T_opcode = _core_data_we_o ? 3'h1 : 3'h4; // @[IbexTile.scala:222:20, :289:21] assign _dmemNodeOut_a_bits_T_size = _core_data_we_o ? dmem_put_size : 4'h2; // @[Edges.scala:460:17, :463:15, :500:17] assign _dmemNodeOut_a_bits_T_address = _core_data_we_o ? dmem_put_address : dmem_get_address; // @[Edges.scala:460:17, :500:17] assign _dmemNodeOut_a_bits_T_mask = _core_data_we_o ? dmem_put_mask : 4'hF; // @[Misc.scala:222:10] assign _dmemNodeOut_a_bits_T_data = _core_data_we_o ? dmem_put_data : 32'h0; // @[Edges.scala:500:17] assign dmemNodeOut_a_bits_opcode = _dmemNodeOut_a_bits_T_opcode; // @[IbexTile.scala:289:21] assign dmemNodeOut_a_bits_size = _dmemNodeOut_a_bits_T_size; // @[IbexTile.scala:289:21] assign dmemNodeOut_a_bits_address = _dmemNodeOut_a_bits_T_address; // @[IbexTile.scala:289:21] assign dmemNodeOut_a_bits_mask = _dmemNodeOut_a_bits_T_mask; // @[IbexTile.scala:289:21] assign dmemNodeOut_a_bits_data = _dmemNodeOut_a_bits_T_data; // @[IbexTile.scala:289:21] wire _core_io_data_err_i_T = dmemNodeOut_d_bits_corrupt | dmemNodeOut_d_bits_denied; // @[IbexTile.scala:291:45] reg [1:0] imem_state; // @[IbexTile.scala:300:27] reg [31:0] imem_addr; // @[IbexTile.scala:302:22] wire [31:0] _imem_get_legal_T_14 = imem_addr; // @[Parameters.scala:137:31] assign imem_get_address = imem_addr; // @[Edges.scala:460:17] wire _core_io_instr_gnt_i_T = imem_state == 2'h0; // @[IbexTile.scala:300:27, :304:20, :316:37] assign _imemNodeOut_a_valid_T = imem_state == 2'h1; // @[IbexTile.scala:300:27, :308:20, :315:30] assign imemNodeOut_a_valid = _imemNodeOut_a_valid_T; // @[IbexTile.scala:315:30] wire [31:0] _imem_get_legal_T_4 = {imem_addr[31:14], imem_addr[13:0] ^ 14'h3000}; // @[Parameters.scala:137:31] wire [32:0] _imem_get_legal_T_5 = {1'h0, _imem_get_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [32:0] _imem_get_legal_T_6 = _imem_get_legal_T_5 & 33'h9A013000; // @[Parameters.scala:137:{41,46}] wire [32:0] _imem_get_legal_T_7 = _imem_get_legal_T_6; // @[Parameters.scala:137:46] wire _imem_get_legal_T_8 = _imem_get_legal_T_7 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _imem_get_legal_T_9 = _imem_get_legal_T_8; // @[Parameters.scala:684:54] wire _imem_get_legal_T_62 = _imem_get_legal_T_9; // @[Parameters.scala:684:54, :686:26] wire [32:0] _imem_get_legal_T_15 = {1'h0, _imem_get_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [32:0] _imem_get_legal_T_16 = _imem_get_legal_T_15 & 33'h9A012000; // @[Parameters.scala:137:{41,46}] wire [32:0] _imem_get_legal_T_17 = _imem_get_legal_T_16; // @[Parameters.scala:137:46] wire _imem_get_legal_T_18 = _imem_get_legal_T_17 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_5 = {imem_addr[31:17], imem_addr[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31] wire [31:0] _imem_get_legal_T_19; // @[Parameters.scala:137:31] assign _imem_get_legal_T_19 = _GEN_5; // @[Parameters.scala:137:31] wire [31:0] _imem_get_legal_T_24; // @[Parameters.scala:137:31] assign _imem_get_legal_T_24 = _GEN_5; // @[Parameters.scala:137:31] wire [32:0] _imem_get_legal_T_20 = {1'h0, _imem_get_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [32:0] _imem_get_legal_T_21 = _imem_get_legal_T_20 & 33'h98013000; // @[Parameters.scala:137:{41,46}] wire [32:0] _imem_get_legal_T_22 = _imem_get_legal_T_21; // @[Parameters.scala:137:46] wire _imem_get_legal_T_23 = _imem_get_legal_T_22 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _imem_get_legal_T_25 = {1'h0, _imem_get_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [32:0] _imem_get_legal_T_26 = _imem_get_legal_T_25 & 33'h9A010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _imem_get_legal_T_27 = _imem_get_legal_T_26; // @[Parameters.scala:137:46] wire _imem_get_legal_T_28 = _imem_get_legal_T_27 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _imem_get_legal_T_29 = {imem_addr[31:26], imem_addr[25:0] ^ 26'h2000000}; // @[Parameters.scala:137:31] wire [32:0] _imem_get_legal_T_30 = {1'h0, _imem_get_legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [32:0] _imem_get_legal_T_31 = _imem_get_legal_T_30 & 33'h9A010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _imem_get_legal_T_32 = _imem_get_legal_T_31; // @[Parameters.scala:137:46] wire _imem_get_legal_T_33 = _imem_get_legal_T_32 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_6 = {imem_addr[31:28], imem_addr[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31] wire [31:0] _imem_get_legal_T_34; // @[Parameters.scala:137:31] assign _imem_get_legal_T_34 = _GEN_6; // @[Parameters.scala:137:31] wire [31:0] _imem_get_legal_T_39; // @[Parameters.scala:137:31] assign _imem_get_legal_T_39 = _GEN_6; // @[Parameters.scala:137:31] wire [32:0] _imem_get_legal_T_35 = {1'h0, _imem_get_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [32:0] _imem_get_legal_T_36 = _imem_get_legal_T_35 & 33'h98000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _imem_get_legal_T_37 = _imem_get_legal_T_36; // @[Parameters.scala:137:46] wire _imem_get_legal_T_38 = _imem_get_legal_T_37 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _imem_get_legal_T_40 = {1'h0, _imem_get_legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [32:0] _imem_get_legal_T_41 = _imem_get_legal_T_40 & 33'h9A010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _imem_get_legal_T_42 = _imem_get_legal_T_41; // @[Parameters.scala:137:46] wire _imem_get_legal_T_43 = _imem_get_legal_T_42 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _imem_get_legal_T_44 = {imem_addr[31:29], imem_addr[28:0] ^ 29'h10000000}; // @[Parameters.scala:137:31] wire [32:0] _imem_get_legal_T_45 = {1'h0, _imem_get_legal_T_44}; // @[Parameters.scala:137:{31,41}] wire [32:0] _imem_get_legal_T_46 = _imem_get_legal_T_45 & 33'h9A013000; // @[Parameters.scala:137:{41,46}] wire [32:0] _imem_get_legal_T_47 = _imem_get_legal_T_46; // @[Parameters.scala:137:46] wire _imem_get_legal_T_48 = _imem_get_legal_T_47 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _imem_get_legal_T_49 = imem_addr ^ 32'h80000000; // @[Parameters.scala:137:31] wire [32:0] _imem_get_legal_T_50 = {1'h0, _imem_get_legal_T_49}; // @[Parameters.scala:137:{31,41}] wire [32:0] _imem_get_legal_T_51 = _imem_get_legal_T_50 & 33'h90000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _imem_get_legal_T_52 = _imem_get_legal_T_51; // @[Parameters.scala:137:46] wire _imem_get_legal_T_53 = _imem_get_legal_T_52 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _imem_get_legal_T_54 = _imem_get_legal_T_18 | _imem_get_legal_T_23; // @[Parameters.scala:685:42] wire _imem_get_legal_T_55 = _imem_get_legal_T_54 | _imem_get_legal_T_28; // @[Parameters.scala:685:42] wire _imem_get_legal_T_56 = _imem_get_legal_T_55 | _imem_get_legal_T_33; // @[Parameters.scala:685:42] wire _imem_get_legal_T_57 = _imem_get_legal_T_56 | _imem_get_legal_T_38; // @[Parameters.scala:685:42] wire _imem_get_legal_T_58 = _imem_get_legal_T_57 | _imem_get_legal_T_43; // @[Parameters.scala:685:42] wire _imem_get_legal_T_59 = _imem_get_legal_T_58 | _imem_get_legal_T_48; // @[Parameters.scala:685:42] wire _imem_get_legal_T_60 = _imem_get_legal_T_59 | _imem_get_legal_T_53; // @[Parameters.scala:685:42] wire _imem_get_legal_T_61 = _imem_get_legal_T_60; // @[Parameters.scala:684:54, :685:42] wire imem_get_legal = _imem_get_legal_T_62 | _imem_get_legal_T_61; // @[Parameters.scala:684:54, :686:26] assign imemNodeOut_a_bits_address = imem_get_address; // @[Edges.scala:460:17] wire imem_get_a_mask_sub_bit = imem_addr[1]; // @[Misc.scala:210:26] wire imem_get_a_mask_sub_1_2 = imem_get_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire imem_get_a_mask_sub_nbit = ~imem_get_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire imem_get_a_mask_sub_0_2 = imem_get_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire imem_get_a_mask_bit = imem_addr[0]; // @[Misc.scala:210:26] wire imem_get_a_mask_nbit = ~imem_get_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire imem_get_a_mask_eq = imem_get_a_mask_sub_0_2 & imem_get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _imem_get_a_mask_acc_T = imem_get_a_mask_eq; // @[Misc.scala:214:27, :215:38] wire imem_get_a_mask_eq_1 = imem_get_a_mask_sub_0_2 & imem_get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _imem_get_a_mask_acc_T_1 = imem_get_a_mask_eq_1; // @[Misc.scala:214:27, :215:38] wire imem_get_a_mask_eq_2 = imem_get_a_mask_sub_1_2 & imem_get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _imem_get_a_mask_acc_T_2 = imem_get_a_mask_eq_2; // @[Misc.scala:214:27, :215:38] wire imem_get_a_mask_eq_3 = imem_get_a_mask_sub_1_2 & imem_get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _imem_get_a_mask_acc_T_3 = imem_get_a_mask_eq_3; // @[Misc.scala:214:27, :215:38] wire _core_io_instr_err_i_T = imemNodeOut_d_bits_corrupt | imemNodeOut_d_bits_denied; // @[IbexTile.scala:324:46] wire _T_1 = _core_io_data_gnt_i_T & _core_data_req_o; // @[IbexTile.scala:222:20, :267:32, :282:36] wire _T_9 = _core_io_instr_gnt_i_T & _core_instr_req_o; // @[IbexTile.scala:222:20, :304:32, :316:37] always @(posedge clock) begin // @[IbexTile.scala:190:7] if (reset) begin // @[IbexTile.scala:190:7] dmem_state <= 2'h0; // @[IbexTile.scala:256:27] imem_state <= 2'h0; // @[IbexTile.scala:300:27] end else begin // @[IbexTile.scala:190:7] if (dmem_state == 2'h2 & dmemNodeOut_d_valid) // @[IbexTile.scala:256:27, :278:{20,35}] dmem_state <= 2'h0; // @[IbexTile.scala:256:27] else if (_dmemNodeOut_a_valid_T & dmemNodeOut_a_ready & dmemNodeOut_a_valid) // @[Decoupled.scala:51:35] dmem_state <= 2'h2; // @[IbexTile.scala:256:27] else if (_T_1) // @[IbexTile.scala:267:32] dmem_state <= 2'h1; // @[IbexTile.scala:256:27] if (imem_state == 2'h2 & imemNodeOut_d_valid) // @[IbexTile.scala:300:27, :311:{20,35}] imem_state <= 2'h0; // @[IbexTile.scala:300:27] else if (_imemNodeOut_a_valid_T & imemNodeOut_a_ready & imemNodeOut_a_valid) // @[Decoupled.scala:51:35] imem_state <= 2'h2; // @[IbexTile.scala:300:27] else if (_T_9) // @[IbexTile.scala:304:32] imem_state <= 2'h1; // @[IbexTile.scala:300:27] end if (_T_1) begin // @[IbexTile.scala:267:32] dmem_addr <= _dmem_addr_T_9; // @[IbexTile.scala:258:22, :269:38] dmem_data <= _core_data_wdata_o; // @[IbexTile.scala:222:20, :259:22] dmem_mask <= {4'h0, _core_data_be_o}; // @[IbexTile.scala:222:20, :260:22, :272:15] byte_en <= _core_data_be_o; // @[IbexTile.scala:222:20, :261:20] w_size <= _w_size_T_14; // @[Mux.scala:50:70] end if (_T_9) // @[IbexTile.scala:304:32] imem_addr <= _core_instr_addr_o; // @[IbexTile.scala:222:20, :302:22] always @(posedge) TLXbar_MasterXbar_IbexTile_i2_o1_a32d32s1k3z4u tlMasterXbar ( // @[HierarchicalElement.scala:55:42] .clock (clock), .reset (reset), .auto_anon_in_1_a_ready (x1_nodeOut_a_ready), .auto_anon_in_1_a_valid (x1_nodeOut_a_valid), // @[MixedNode.scala:542:17] .auto_anon_in_1_a_bits_opcode (x1_nodeOut_a_bits_opcode), // @[MixedNode.scala:542:17] .auto_anon_in_1_a_bits_param (x1_nodeOut_a_bits_param), // @[MixedNode.scala:542:17] .auto_anon_in_1_a_bits_size (x1_nodeOut_a_bits_size), // @[MixedNode.scala:542:17] .auto_anon_in_1_a_bits_source (x1_nodeOut_a_bits_source), // @[MixedNode.scala:542:17] .auto_anon_in_1_a_bits_address (x1_nodeOut_a_bits_address), // @[MixedNode.scala:542:17] .auto_anon_in_1_a_bits_mask (x1_nodeOut_a_bits_mask), // @[MixedNode.scala:542:17] .auto_anon_in_1_a_bits_data (x1_nodeOut_a_bits_data), // @[MixedNode.scala:542:17] .auto_anon_in_1_a_bits_corrupt (x1_nodeOut_a_bits_corrupt), // @[MixedNode.scala:542:17] .auto_anon_in_1_d_ready (x1_nodeOut_d_ready), // @[MixedNode.scala:542:17] .auto_anon_in_1_d_valid (x1_nodeOut_d_valid), .auto_anon_in_1_d_bits_opcode (x1_nodeOut_d_bits_opcode), .auto_anon_in_1_d_bits_param (x1_nodeOut_d_bits_param), .auto_anon_in_1_d_bits_size (x1_nodeOut_d_bits_size), .auto_anon_in_1_d_bits_sink (x1_nodeOut_d_bits_sink), .auto_anon_in_1_d_bits_denied (x1_nodeOut_d_bits_denied), .auto_anon_in_1_d_bits_data (x1_nodeOut_d_bits_data), .auto_anon_in_1_d_bits_corrupt (x1_nodeOut_d_bits_corrupt), .auto_anon_in_0_a_ready (nodeOut_a_ready), .auto_anon_in_0_a_valid (nodeOut_a_valid), // @[MixedNode.scala:542:17] .auto_anon_in_0_a_bits_opcode (nodeOut_a_bits_opcode), // @[MixedNode.scala:542:17] .auto_anon_in_0_a_bits_param (nodeOut_a_bits_param), // @[MixedNode.scala:542:17] .auto_anon_in_0_a_bits_size (nodeOut_a_bits_size), // @[MixedNode.scala:542:17] .auto_anon_in_0_a_bits_source (nodeOut_a_bits_source), // @[MixedNode.scala:542:17] .auto_anon_in_0_a_bits_address (nodeOut_a_bits_address), // @[MixedNode.scala:542:17] .auto_anon_in_0_a_bits_mask (nodeOut_a_bits_mask), // @[MixedNode.scala:542:17] .auto_anon_in_0_a_bits_data (nodeOut_a_bits_data), // @[MixedNode.scala:542:17] .auto_anon_in_0_a_bits_corrupt (nodeOut_a_bits_corrupt), // @[MixedNode.scala:542:17] .auto_anon_in_0_d_ready (nodeOut_d_ready), // @[MixedNode.scala:542:17] .auto_anon_in_0_d_valid (nodeOut_d_valid), .auto_anon_in_0_d_bits_opcode (nodeOut_d_bits_opcode), .auto_anon_in_0_d_bits_param (nodeOut_d_bits_param), .auto_anon_in_0_d_bits_size (nodeOut_d_bits_size), .auto_anon_in_0_d_bits_sink (nodeOut_d_bits_sink), .auto_anon_in_0_d_bits_denied (nodeOut_d_bits_denied), .auto_anon_in_0_d_bits_data (nodeOut_d_bits_data), .auto_anon_in_0_d_bits_corrupt (nodeOut_d_bits_corrupt), .auto_anon_out_a_ready (tlOtherMastersNodeIn_a_ready), // @[MixedNode.scala:551:17] .auto_anon_out_a_valid (tlOtherMastersNodeIn_a_valid), .auto_anon_out_a_bits_opcode (tlOtherMastersNodeIn_a_bits_opcode), .auto_anon_out_a_bits_param (tlOtherMastersNodeIn_a_bits_param), .auto_anon_out_a_bits_size (tlOtherMastersNodeIn_a_bits_size), .auto_anon_out_a_bits_source (tlOtherMastersNodeIn_a_bits_source), .auto_anon_out_a_bits_address (tlOtherMastersNodeIn_a_bits_address), .auto_anon_out_a_bits_mask (tlOtherMastersNodeIn_a_bits_mask), .auto_anon_out_a_bits_data (tlOtherMastersNodeIn_a_bits_data), .auto_anon_out_a_bits_corrupt (tlOtherMastersNodeIn_a_bits_corrupt), .auto_anon_out_d_ready (tlOtherMastersNodeIn_d_ready), .auto_anon_out_d_valid (tlOtherMastersNodeIn_d_valid), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_opcode (tlOtherMastersNodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_param (tlOtherMastersNodeIn_d_bits_param), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_size (tlOtherMastersNodeIn_d_bits_size), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_source (tlOtherMastersNodeIn_d_bits_source), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_sink (tlOtherMastersNodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_denied (tlOtherMastersNodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_data (tlOtherMastersNodeIn_d_bits_data), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_corrupt (tlOtherMastersNodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[HierarchicalElement.scala:55:42] TLXbar_SlaveXbar_IbexTile_i0_o0_a1d8s1k1z1u tlSlaveXbar ( // @[HierarchicalElement.scala:56:41] .clock (clock), .reset (reset) ); // @[HierarchicalElement.scala:56:41] IntXbar_i3_o1 intXbar ( // @[HierarchicalElement.scala:57:37] .auto_anon_in_2_0 (x1_int_localOut_1_0), // @[MixedNode.scala:542:17] .auto_anon_in_1_0 (x1_int_localOut_0), // @[MixedNode.scala:542:17] .auto_anon_in_1_1 (x1_int_localOut_1), // @[MixedNode.scala:542:17] .auto_anon_in_0_0 (int_localOut_0), // @[MixedNode.scala:542:17] .auto_anon_out_0 (intSinkNodeIn_0), .auto_anon_out_1 (intSinkNodeIn_1), .auto_anon_out_2 (intSinkNodeIn_2), .auto_anon_out_3 (intSinkNodeIn_3) ); // @[HierarchicalElement.scala:57:37] TLBuffer_a32d32s1k3z4u buffer ( // @[Buffer.scala:75:28] .clock (clock), .reset (reset), .auto_in_a_ready (dmemNodeOut_a_ready), .auto_in_a_valid (dmemNodeOut_a_valid), // @[MixedNode.scala:542:17] .auto_in_a_bits_opcode (dmemNodeOut_a_bits_opcode), // @[MixedNode.scala:542:17] .auto_in_a_bits_size (dmemNodeOut_a_bits_size), // @[MixedNode.scala:542:17] .auto_in_a_bits_address (dmemNodeOut_a_bits_address), // @[MixedNode.scala:542:17] .auto_in_a_bits_mask (dmemNodeOut_a_bits_mask), // @[MixedNode.scala:542:17] .auto_in_a_bits_data (dmemNodeOut_a_bits_data), // @[MixedNode.scala:542:17] .auto_in_d_valid (dmemNodeOut_d_valid), .auto_in_d_bits_opcode (dmemNodeOut_d_bits_opcode), .auto_in_d_bits_param (dmemNodeOut_d_bits_param), .auto_in_d_bits_size (dmemNodeOut_d_bits_size), .auto_in_d_bits_source (dmemNodeOut_d_bits_source), .auto_in_d_bits_sink (dmemNodeOut_d_bits_sink), .auto_in_d_bits_denied (dmemNodeOut_d_bits_denied), .auto_in_d_bits_data (dmemNodeOut_d_bits_data), .auto_in_d_bits_corrupt (dmemNodeOut_d_bits_corrupt), .auto_out_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .auto_out_a_valid (nodeIn_a_valid), .auto_out_a_bits_opcode (nodeIn_a_bits_opcode), .auto_out_a_bits_param (nodeIn_a_bits_param), .auto_out_a_bits_size (nodeIn_a_bits_size), .auto_out_a_bits_source (nodeIn_a_bits_source), .auto_out_a_bits_address (nodeIn_a_bits_address), .auto_out_a_bits_mask (nodeIn_a_bits_mask), .auto_out_a_bits_data (nodeIn_a_bits_data), .auto_out_a_bits_corrupt (nodeIn_a_bits_corrupt), .auto_out_d_ready (nodeIn_d_ready), .auto_out_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .auto_out_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_out_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .auto_out_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .auto_out_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .auto_out_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .auto_out_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .auto_out_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Buffer.scala:75:28] TLBuffer_a32d32s1k3z4u_1 buffer_1 ( // @[Buffer.scala:75:28] .clock (clock), .reset (reset), .auto_in_a_ready (imemNodeOut_a_ready), .auto_in_a_valid (imemNodeOut_a_valid), // @[MixedNode.scala:542:17] .auto_in_a_bits_address (imemNodeOut_a_bits_address), // @[MixedNode.scala:542:17] .auto_in_d_valid (imemNodeOut_d_valid), .auto_in_d_bits_opcode (imemNodeOut_d_bits_opcode), .auto_in_d_bits_param (imemNodeOut_d_bits_param), .auto_in_d_bits_size (imemNodeOut_d_bits_size), .auto_in_d_bits_source (imemNodeOut_d_bits_source), .auto_in_d_bits_sink (imemNodeOut_d_bits_sink), .auto_in_d_bits_denied (imemNodeOut_d_bits_denied), .auto_in_d_bits_data (imemNodeOut_d_bits_data), .auto_in_d_bits_corrupt (imemNodeOut_d_bits_corrupt), .auto_out_a_ready (x1_nodeIn_a_ready), // @[MixedNode.scala:551:17] .auto_out_a_valid (x1_nodeIn_a_valid), .auto_out_a_bits_opcode (x1_nodeIn_a_bits_opcode), .auto_out_a_bits_param (x1_nodeIn_a_bits_param), .auto_out_a_bits_size (x1_nodeIn_a_bits_size), .auto_out_a_bits_source (x1_nodeIn_a_bits_source), .auto_out_a_bits_address (x1_nodeIn_a_bits_address), .auto_out_a_bits_mask (x1_nodeIn_a_bits_mask), .auto_out_a_bits_data (x1_nodeIn_a_bits_data), .auto_out_a_bits_corrupt (x1_nodeIn_a_bits_corrupt), .auto_out_d_ready (x1_nodeIn_d_ready), .auto_out_d_valid (x1_nodeIn_d_valid), // @[MixedNode.scala:551:17] .auto_out_d_bits_opcode (x1_nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_out_d_bits_param (x1_nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .auto_out_d_bits_size (x1_nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .auto_out_d_bits_sink (x1_nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .auto_out_d_bits_denied (x1_nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .auto_out_d_bits_data (x1_nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .auto_out_d_bits_corrupt (x1_nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Buffer.scala:75:28] IbexCoreBlackbox #( .BRANCH_PREDICTOR(0), .BRANCH_TARGET_ALU(0), .DBG_HW_BREAK_NUM(1), .DM_EXCEPTION_ADDR(437323784), .DM_HALT_ADDR(437323776), .MHPM_COUNTER_NUM(0), .MHPM_COUNTER_WIDTH(0), .PMP_ENABLE(0), .PMP_GRANULARITY(0), .PMP_NUM_REGIONS(4), .REGFILE(0), .RV32B(0), .RV32E(0), .RV32M(2), .WB_STAGE(0) ) core ( // @[IbexTile.scala:222:20] .clk_i (clock), .rst_ni (_core_io_rst_ni_T_1), // @[IbexTile.scala:242:21] .test_en_i (1'h0), .ram_cfg_i_ram_cfg_en (1'h0), .ram_cfg_i_ram_cfg (4'h0), .ram_cfg_i_rf_cfg_en (1'h0), .ram_cfg_i_rf_cfg (4'h0), .hart_id_i ({31'h0, hartIdSinkNodeIn}), // @[IbexTile.scala:245:21] .boot_addr_i (32'h10000), // @[IbexTile.scala:190:7, :222:20] .instr_req_o (_core_instr_req_o), .instr_gnt_i (_core_io_instr_gnt_i_T), // @[IbexTile.scala:316:37] .instr_rvalid_i (imemNodeOut_d_valid), // @[MixedNode.scala:542:17] .instr_addr_o (_core_instr_addr_o), .instr_rdata_i (imemNodeOut_d_bits_data), // @[MixedNode.scala:542:17] .instr_err_i (_core_io_instr_err_i_T), // @[IbexTile.scala:324:46] .data_req_o (_core_data_req_o), .data_gnt_i (_core_io_data_gnt_i_T_1), // @[IbexTile.scala:282:48] .data_rvalid_i (dmemNodeOut_d_valid), // @[MixedNode.scala:542:17] .data_we_o (_core_data_we_o), .data_be_o (_core_data_be_o), .data_addr_o (_core_data_addr_o), .data_wdata_o (_core_data_wdata_o), .data_rdata_i (dmemNodeOut_d_bits_data), // @[MixedNode.scala:542:17] .data_err_i (_core_io_data_err_i_T), // @[IbexTile.scala:291:45] .irq_software_i (intSinkNodeIn_1), // @[MixedNode.scala:551:17] .irq_timer_i (intSinkNodeIn_2), // @[MixedNode.scala:551:17] .irq_external_i (intSinkNodeIn_3), // @[MixedNode.scala:551:17] .irq_fast_i (15'h0), .irq_nm_i (1'h0), .debug_req_i (intSinkNodeIn_0), // @[MixedNode.scala:551:17] .crash_dump_o_current_pc (/* unused */), .crash_dump_o_next_pc (/* unused */), .crash_dump_o_last_data_addr (/* unused */), .crash_dump_o_exception_addr (/* unused */), .fetch_enable_i (1'h1), .alert_minor_o (/* unused */), .alert_major_o (/* unused */), .core_sleep_o (/* unused */), .scan_rst_ni (1'h1) ); // @[IbexTile.scala:222:20] assign auto_buffer_out_a_valid = auto_buffer_out_a_valid_0; // @[IbexTile.scala:190:7] assign auto_buffer_out_a_bits_opcode = auto_buffer_out_a_bits_opcode_0; // @[IbexTile.scala:190:7] assign auto_buffer_out_a_bits_param = auto_buffer_out_a_bits_param_0; // @[IbexTile.scala:190:7] assign auto_buffer_out_a_bits_size = auto_buffer_out_a_bits_size_0; // @[IbexTile.scala:190:7] assign auto_buffer_out_a_bits_source = auto_buffer_out_a_bits_source_0; // @[IbexTile.scala:190:7] assign auto_buffer_out_a_bits_address = auto_buffer_out_a_bits_address_0; // @[IbexTile.scala:190:7] assign auto_buffer_out_a_bits_mask = auto_buffer_out_a_bits_mask_0; // @[IbexTile.scala:190:7] assign auto_buffer_out_a_bits_data = auto_buffer_out_a_bits_data_0; // @[IbexTile.scala:190:7] assign auto_buffer_out_a_bits_corrupt = auto_buffer_out_a_bits_corrupt_0; // @[IbexTile.scala:190:7] assign auto_buffer_out_d_ready = auto_buffer_out_d_ready_0; // @[IbexTile.scala:190:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ :*=* _) .getOrElse(TLNameNode("no_buffer")) } } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }
module TLBuffer_a32d128s3k4z4c( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [15:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [127:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_b_ready, // @[LazyModuleImp.scala:107:25] output auto_in_b_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_b_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_b_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_b_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_b_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_b_bits_address, // @[LazyModuleImp.scala:107:25] output [15:0] auto_in_b_bits_mask, // @[LazyModuleImp.scala:107:25] output [127:0] auto_in_b_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_c_ready, // @[LazyModuleImp.scala:107:25] input auto_in_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_c_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_c_bits_address, // @[LazyModuleImp.scala:107:25] input [127:0] auto_in_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [127:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_e_ready, // @[LazyModuleImp.scala:107:25] input auto_in_e_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [15:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [127:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_out_b_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_b_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_b_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_b_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input [15:0] auto_out_b_bits_mask, // @[LazyModuleImp.scala:107:25] input [127:0] auto_out_b_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [127:0] auto_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [127:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_e_ready, // @[LazyModuleImp.scala:107:25] output auto_out_e_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_e_bits_sink // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [15:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [127:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_b_ready_0 = auto_in_b_ready; // @[Buffer.scala:40:9] wire auto_in_c_valid_0 = auto_in_c_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_c_bits_opcode_0 = auto_in_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_c_bits_param_0 = auto_in_c_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_c_bits_size_0 = auto_in_c_bits_size; // @[Buffer.scala:40:9] wire [2:0] auto_in_c_bits_source_0 = auto_in_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_c_bits_address_0 = auto_in_c_bits_address; // @[Buffer.scala:40:9] wire [127:0] auto_in_c_bits_data_0 = auto_in_c_bits_data; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_in_e_valid_0 = auto_in_e_valid; // @[Buffer.scala:40:9] wire [3:0] auto_in_e_bits_sink_0 = auto_in_e_bits_sink; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_b_valid_0 = auto_out_b_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_b_bits_opcode_0 = auto_out_b_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_b_bits_param_0 = auto_out_b_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_out_b_bits_size_0 = auto_out_b_bits_size; // @[Buffer.scala:40:9] wire [2:0] auto_out_b_bits_source_0 = auto_out_b_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_out_b_bits_address_0 = auto_out_b_bits_address; // @[Buffer.scala:40:9] wire [15:0] auto_out_b_bits_mask_0 = auto_out_b_bits_mask; // @[Buffer.scala:40:9] wire [127:0] auto_out_b_bits_data_0 = auto_out_b_bits_data; // @[Buffer.scala:40:9] wire auto_out_b_bits_corrupt_0 = auto_out_b_bits_corrupt; // @[Buffer.scala:40:9] wire auto_out_c_ready_0 = auto_out_c_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [127:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire auto_out_e_ready_0 = auto_out_e_ready; // @[Buffer.scala:40:9] wire auto_in_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire auto_in_c_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_c_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [15:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [127:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_b_ready = auto_in_b_ready_0; // @[Buffer.scala:40:9] wire nodeIn_b_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_b_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_b_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_b_bits_size; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_b_bits_source; // @[MixedNode.scala:551:17] wire [31:0] nodeIn_b_bits_address; // @[MixedNode.scala:551:17] wire [15:0] nodeIn_b_bits_mask; // @[MixedNode.scala:551:17] wire [127:0] nodeIn_b_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_b_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_c_ready; // @[MixedNode.scala:551:17] wire nodeIn_c_valid = auto_in_c_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_c_bits_opcode = auto_in_c_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_c_bits_param = auto_in_c_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_c_bits_size = auto_in_c_bits_size_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_c_bits_source = auto_in_c_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_c_bits_address = auto_in_c_bits_address_0; // @[Buffer.scala:40:9] wire [127:0] nodeIn_c_bits_data = auto_in_c_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [127:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_e_ready; // @[MixedNode.scala:551:17] wire nodeIn_e_valid = auto_in_e_valid_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_e_bits_sink = auto_in_e_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [15:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [127:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_b_ready; // @[MixedNode.scala:542:17] wire nodeOut_b_valid = auto_out_b_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_b_bits_opcode = auto_out_b_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_b_bits_param = auto_out_b_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_b_bits_size = auto_out_b_bits_size_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_b_bits_source = auto_out_b_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeOut_b_bits_address = auto_out_b_bits_address_0; // @[Buffer.scala:40:9] wire [15:0] nodeOut_b_bits_mask = auto_out_b_bits_mask_0; // @[Buffer.scala:40:9] wire [127:0] nodeOut_b_bits_data = auto_out_b_bits_data_0; // @[Buffer.scala:40:9] wire nodeOut_b_bits_corrupt = auto_out_b_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeOut_c_ready = auto_out_c_ready_0; // @[Buffer.scala:40:9] wire nodeOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_c_bits_size; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_c_bits_address; // @[MixedNode.scala:542:17] wire [127:0] nodeOut_c_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_c_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9] wire [127:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeOut_e_ready = auto_out_e_ready_0; // @[Buffer.scala:40:9] wire nodeOut_e_valid; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_e_bits_sink; // @[MixedNode.scala:542:17] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_b_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_b_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_b_bits_size_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_b_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_in_b_bits_address_0; // @[Buffer.scala:40:9] wire [15:0] auto_in_b_bits_mask_0; // @[Buffer.scala:40:9] wire [127:0] auto_in_b_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_b_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_b_valid_0; // @[Buffer.scala:40:9] wire auto_in_c_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [127:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire auto_in_e_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [15:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [127:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_b_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_c_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_c_bits_size_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_c_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_c_bits_address_0; // @[Buffer.scala:40:9] wire [127:0] auto_out_c_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_c_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_e_bits_sink_0; // @[Buffer.scala:40:9] wire auto_out_e_valid_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_b_valid_0 = nodeIn_b_valid; // @[Buffer.scala:40:9] assign auto_in_b_bits_opcode_0 = nodeIn_b_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_b_bits_param_0 = nodeIn_b_bits_param; // @[Buffer.scala:40:9] assign auto_in_b_bits_size_0 = nodeIn_b_bits_size; // @[Buffer.scala:40:9] assign auto_in_b_bits_source_0 = nodeIn_b_bits_source; // @[Buffer.scala:40:9] assign auto_in_b_bits_address_0 = nodeIn_b_bits_address; // @[Buffer.scala:40:9] assign auto_in_b_bits_mask_0 = nodeIn_b_bits_mask; // @[Buffer.scala:40:9] assign auto_in_b_bits_data_0 = nodeIn_b_bits_data; // @[Buffer.scala:40:9] assign auto_in_b_bits_corrupt_0 = nodeIn_b_bits_corrupt; // @[Buffer.scala:40:9] assign auto_in_c_ready_0 = nodeIn_c_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_in_e_ready_0 = nodeIn_e_ready; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_b_ready_0 = nodeOut_b_ready; // @[Buffer.scala:40:9] assign auto_out_c_valid_0 = nodeOut_c_valid; // @[Buffer.scala:40:9] assign auto_out_c_bits_opcode_0 = nodeOut_c_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_c_bits_param_0 = nodeOut_c_bits_param; // @[Buffer.scala:40:9] assign auto_out_c_bits_size_0 = nodeOut_c_bits_size; // @[Buffer.scala:40:9] assign auto_out_c_bits_source_0 = nodeOut_c_bits_source; // @[Buffer.scala:40:9] assign auto_out_c_bits_address_0 = nodeOut_c_bits_address; // @[Buffer.scala:40:9] assign auto_out_c_bits_data_0 = nodeOut_c_bits_data; // @[Buffer.scala:40:9] assign auto_out_c_bits_corrupt_0 = nodeOut_c_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] assign auto_out_e_valid_0 = nodeOut_e_valid; // @[Buffer.scala:40:9] assign auto_out_e_bits_sink_0 = nodeOut_e_bits_sink; // @[Buffer.scala:40:9] TLMonitor_43 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_b_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17] .io_in_b_valid (nodeIn_b_valid), // @[MixedNode.scala:551:17] .io_in_b_bits_opcode (nodeIn_b_bits_opcode), // @[MixedNode.scala:551:17] .io_in_b_bits_param (nodeIn_b_bits_param), // @[MixedNode.scala:551:17] .io_in_b_bits_size (nodeIn_b_bits_size), // @[MixedNode.scala:551:17] .io_in_b_bits_source (nodeIn_b_bits_source), // @[MixedNode.scala:551:17] .io_in_b_bits_address (nodeIn_b_bits_address), // @[MixedNode.scala:551:17] .io_in_b_bits_mask (nodeIn_b_bits_mask), // @[MixedNode.scala:551:17] .io_in_b_bits_data (nodeIn_b_bits_data), // @[MixedNode.scala:551:17] .io_in_b_bits_corrupt (nodeIn_b_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_c_ready (nodeIn_c_ready), // @[MixedNode.scala:551:17] .io_in_c_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17] .io_in_c_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17] .io_in_c_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17] .io_in_c_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17] .io_in_c_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17] .io_in_c_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17] .io_in_c_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_e_ready (nodeIn_e_ready), // @[MixedNode.scala:551:17] .io_in_e_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17] .io_in_e_bits_sink (nodeIn_e_bits_sink) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a32d128s3k4z4c nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d128s3k4z4c nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleB_a32d128s3k4z4c nodeIn_b_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_b_ready), .io_enq_valid (nodeOut_b_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_b_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_b_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_b_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_b_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_address (nodeOut_b_bits_address), // @[MixedNode.scala:542:17] .io_enq_bits_mask (nodeOut_b_bits_mask), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_b_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (nodeOut_b_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_b_valid), .io_deq_bits_opcode (nodeIn_b_bits_opcode), .io_deq_bits_param (nodeIn_b_bits_param), .io_deq_bits_size (nodeIn_b_bits_size), .io_deq_bits_source (nodeIn_b_bits_source), .io_deq_bits_address (nodeIn_b_bits_address), .io_deq_bits_mask (nodeIn_b_bits_mask), .io_deq_bits_data (nodeIn_b_bits_data), .io_deq_bits_corrupt (nodeIn_b_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleC_a32d128s3k4z4c nodeOut_c_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_c_ready), .io_enq_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_c_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_c_valid), .io_deq_bits_opcode (nodeOut_c_bits_opcode), .io_deq_bits_param (nodeOut_c_bits_param), .io_deq_bits_size (nodeOut_c_bits_size), .io_deq_bits_source (nodeOut_c_bits_source), .io_deq_bits_address (nodeOut_c_bits_address), .io_deq_bits_data (nodeOut_c_bits_data), .io_deq_bits_corrupt (nodeOut_c_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleE_a32d128s3k4z4c nodeOut_e_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_e_ready), .io_enq_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17] .io_enq_bits_sink (nodeIn_e_bits_sink), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_e_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_e_valid), .io_deq_bits_sink (nodeOut_e_bits_sink) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_b_valid = auto_in_b_valid_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_opcode = auto_in_b_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_param = auto_in_b_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_size = auto_in_b_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_source = auto_in_b_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_address = auto_in_b_bits_address_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_mask = auto_in_b_bits_mask_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_data = auto_in_b_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_corrupt = auto_in_b_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_in_c_ready = auto_in_c_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_in_e_ready = auto_in_e_ready_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_b_ready = auto_out_b_ready_0; // @[Buffer.scala:40:9] assign auto_out_c_valid = auto_out_c_valid_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_opcode = auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_param = auto_out_c_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_size = auto_out_c_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_source = auto_out_c_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_address = auto_out_c_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_data = auto_out_c_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_corrupt = auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_out_e_valid = auto_out_e_valid_0; // @[Buffer.scala:40:9] assign auto_out_e_bits_sink = auto_out_e_bits_sink_0; // @[Buffer.scala:40:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Pipeline.scala: package gemmini import chisel3._ import chisel3.util._ class Pipeline[T <: Data] (gen: T, latency: Int)(comb: Seq[T => T] = Seq.fill(latency+1)((x: T) => x)) extends Module { val io = IO(new Bundle { val in = Flipped(Decoupled(gen)) val out = Decoupled(gen) val busy = Output(Bool()) }) require(comb.size == latency+1, "length of combinational is incorrect") if (latency == 0) { io.in.ready := io.out.ready io.out.valid := io.in.valid io.out.bits := comb.head(io.in.bits) io.busy := io.in.valid } else { val stages = Reg(Vec(latency, gen)) val valids = RegInit(VecInit(Seq.fill(latency)(false.B))) val stalling = VecInit(Seq.fill(latency)(false.B)) io.busy := io.in.valid || valids.reduce(_||_) // Stall signals io.in.ready := !stalling.head stalling.last := valids.last && !io.out.ready (stalling.init, stalling.tail, valids.init).zipped.foreach { case (s1, s2, v1) => s1 := v1 && s2 } // Valid signals // When the pipeline stage ahead of you isn't stalling, then make yourself invalid io.out.valid := valids.last when(io.out.ready) { valids.last := false.B } (valids.init, stalling.tail).zipped.foreach { case (v1, s2) => when(!s2) { v1 := false.B } } // When the pipeline stage behind you is valid then become true when(io.in.fire) { valids.head := true.B } (valids.tail, valids.init).zipped.foreach { case (v2, v1) => when(v1) { v2 := true.B } } // Stages when(io.in.fire) { stages.head := comb.head(io.in.bits) } io.out.bits := comb.last(stages.last) ((stages.tail zip stages.init) zip (stalling.tail zip comb.tail.init)).foreach { case ((st2, st1), (s2, c1)) => when(!s2) { st2 := c1(st1) } } } } object Pipeline { def apply[T <: Data](in: ReadyValidIO[T], latency: Int, comb: Seq[T => T]): DecoupledIO[T] = { val p = Module(new Pipeline(in.bits.cloneType, latency)(comb)) p.io.in <> in p.io.out } def apply[T <: Data](in: ReadyValidIO[T], latency: Int): DecoupledIO[T] = { val p = Module(new Pipeline(in.bits.cloneType, latency)()) p.io.in <> in p.io.out } }
module Pipeline_6( // @[Pipeline.scala:6:7] input clock, // @[Pipeline.scala:6:7] input reset, // @[Pipeline.scala:6:7] output io_in_ready, // @[Pipeline.scala:7:14] input io_in_valid, // @[Pipeline.scala:7:14] input [127:0] io_in_bits_data, // @[Pipeline.scala:7:14] input io_in_bits_fromDMA, // @[Pipeline.scala:7:14] input io_out_ready, // @[Pipeline.scala:7:14] output io_out_valid, // @[Pipeline.scala:7:14] output [127:0] io_out_bits_data // @[Pipeline.scala:7:14] ); wire io_in_valid_0 = io_in_valid; // @[Pipeline.scala:6:7] wire [127:0] io_in_bits_data_0 = io_in_bits_data; // @[Pipeline.scala:6:7] wire io_in_bits_fromDMA_0 = io_in_bits_fromDMA; // @[Pipeline.scala:6:7] wire io_out_ready_0 = io_out_ready; // @[Pipeline.scala:6:7] wire _valids_WIRE_0 = 1'h0; // @[Pipeline.scala:22:33] wire _io_in_ready_T; // @[Pipeline.scala:27:20] wire _io_busy_T; // @[Pipeline.scala:24:28] wire io_in_ready_0; // @[Pipeline.scala:6:7] wire [127:0] io_out_bits_data_0; // @[Pipeline.scala:6:7] wire io_out_bits_fromDMA; // @[Pipeline.scala:6:7] wire io_out_valid_0; // @[Pipeline.scala:6:7] wire io_busy; // @[Pipeline.scala:6:7] reg [127:0] stages_0_data; // @[Pipeline.scala:21:21] assign io_out_bits_data_0 = stages_0_data; // @[Pipeline.scala:6:7, :21:21] reg stages_0_fromDMA; // @[Pipeline.scala:21:21] assign io_out_bits_fromDMA = stages_0_fromDMA; // @[Pipeline.scala:6:7, :21:21] reg valids_0; // @[Pipeline.scala:22:25] assign io_out_valid_0 = valids_0; // @[Pipeline.scala:6:7, :22:25] wire _stalling_0_T_1; // @[Pipeline.scala:28:34] wire stalling_0; // @[Pipeline.scala:23:27] assign _io_busy_T = io_in_valid_0 | valids_0; // @[Pipeline.scala:6:7, :22:25, :24:28] assign io_busy = _io_busy_T; // @[Pipeline.scala:6:7, :24:28] assign _io_in_ready_T = ~stalling_0; // @[Pipeline.scala:23:27, :27:20] assign io_in_ready_0 = _io_in_ready_T; // @[Pipeline.scala:6:7, :27:20] wire _stalling_0_T = ~io_out_ready_0; // @[Pipeline.scala:6:7, :28:37] assign _stalling_0_T_1 = valids_0 & _stalling_0_T; // @[Pipeline.scala:22:25, :28:{34,37}] assign stalling_0 = _stalling_0_T_1; // @[Pipeline.scala:23:27, :28:34] wire _T_1 = io_in_ready_0 & io_in_valid_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Pipeline.scala:6:7] if (_T_1) begin // @[Decoupled.scala:51:35] stages_0_data <= io_in_bits_data_0; // @[Pipeline.scala:6:7, :21:21] stages_0_fromDMA <= io_in_bits_fromDMA_0; // @[Pipeline.scala:6:7, :21:21] end if (reset) // @[Pipeline.scala:6:7] valids_0 <= 1'h0; // @[Pipeline.scala:22:25] else // @[Pipeline.scala:6:7] valids_0 <= _T_1 | ~io_out_ready_0 & valids_0; // @[Decoupled.scala:51:35] always @(posedge) assign io_in_ready = io_in_ready_0; // @[Pipeline.scala:6:7] assign io_out_valid = io_out_valid_0; // @[Pipeline.scala:6:7] assign io_out_bits_data = io_out_bits_data_0; // @[Pipeline.scala:6:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }
module AsyncValidSync_129( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_150 io_out_source_valid_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }
module AsyncResetSynchronizerShiftReg_w1_d3_i0_121( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_205 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }
module AsyncValidSync_49( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_60 io_out_source_valid_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag }
module OptimizationBarrier_TLBEntryData_179( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_99( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [20:0] address; // @[Monitor.scala:391:22] reg d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] reg a_first_counter_1; // @[Edges.scala:229:27] reg d_first_counter_1; // @[Edges.scala:229:27] wire _GEN = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_0 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [1039:0] inflight_1; // @[Monitor.scala:726:35] reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg d_first_counter_2; // @[Edges.scala:229:27] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File scratchpad_adapter.scala: package sodor.common import chisel3._ import chisel3.util._ import chisel3.experimental._ import freechips.rocketchip.rocket._ import org.chipsalliance.cde.config.{Parameters, Field} import freechips.rocketchip.subsystem._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tile._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class SodorScratchpadAdapter(implicit p: Parameters, implicit val sodorConf: SodorCoreParams) extends CoreModule { val io = IO(new Bundle() { val slavePort = Flipped(new HellaCacheIO()) val memPort = new MemPortIo(data_width = coreDataBits) }) // =================== // Slave port signals val slave_req_ready = io.slavePort.req.ready val s2_slave_resp_valid = io.slavePort.resp.valid val slave_req_valid = io.slavePort.req.valid val slave_cmd = io.slavePort.req.bits.cmd val slave_req = io.slavePort.req.bits // All request are delayed for one cycle to avoid being killed val s1_slave_write_kill = io.slavePort.s1_kill val s1_slave_write_data = io.slavePort.s1_data.data val s1_slave_write_mask = io.slavePort.s1_data.mask val s1_slave_req_valid = RegNext(slave_req_valid, false.B) val s1_slave_cmd = RegNext(slave_cmd) val s1_slave_req = RegNext(slave_req) // Note that ScratchpadSlavePort requires 2-cycle delay, or it won't even send the response val s2_slave_read_data = io.slavePort.resp.bits.data_raw val s2_slave_read_mask = io.slavePort.resp.bits.mask val s2_nack = io.slavePort.s2_nack // Tie anything not defined below to DontCare io.slavePort := DontCare // =================== // HellaCacheIO to MemPortIo logic // Connect valid & ready bits slave_req_ready := io.memPort.req.ready io.memPort.req.valid := s1_slave_req_valid & (s1_slave_cmd === M_XRD || !s1_slave_write_kill) s2_slave_resp_valid := RegNext(io.memPort.resp.valid, false.B) // Connect read info s2_slave_read_mask := RegNext(new StoreGen(s1_slave_req.size, s1_slave_req.addr, 0.U, coreDataBytes).mask) s2_slave_read_data := RegNext(io.memPort.resp.bits.data) // Connect write info io.memPort.req.bits.addr := s1_slave_req.addr io.memPort.req.bits.data := s1_slave_write_data // Other connections s2_nack := false.B io.memPort.req.bits.fcn := Mux(s1_slave_cmd === M_XRD, M_XRD, M_XWR) // Since we don't have dword here (the bus only has 32 bits), s1_slave_req.size <= 2. // The expression below convert TileLink size and signedness to Sodor type. require(io.slavePort.req.bits.addr.getWidth == 32, "Slave port only support 32 bit address") assert (s1_slave_req.size <= 2.U, "Slave port received a bus request with unsupported size: %d", s1_slave_req.size) io.memPort.req.bits.setType(s1_slave_req.signed, s1_slave_req.size) } // This class simply route all memory request that doesn't belong to the scratchpad class SodorRequestRouter(cacheAddress: AddressSet)(implicit val conf: SodorCoreParams) extends Module { val io = IO(new Bundle() { val masterPort = new MemPortIo(data_width = conf.xprlen) val scratchPort = new MemPortIo(data_width = conf.xprlen) val corePort = Flipped(new MemPortIo(data_width = conf.xprlen)) val respAddress = Input(UInt(conf.xprlen.W)) }) val in_range = cacheAddress.contains(io.corePort.req.bits.addr) // Connect other signals io.masterPort.req.bits <> io.corePort.req.bits io.scratchPort.req.bits <> io.corePort.req.bits // Connect valid signal io.masterPort.req.valid := io.corePort.req.valid & !in_range io.scratchPort.req.valid := io.corePort.req.valid & in_range // Mux ready and request signal io.corePort.req.ready := Mux(in_range, io.scratchPort.req.ready, io.masterPort.req.ready) // Use respAddress to route response val resp_in_range = cacheAddress.contains(io.respAddress) io.corePort.resp.bits := Mux(resp_in_range, io.scratchPort.resp.bits, io.masterPort.resp.bits) io.corePort.resp.valid := Mux(resp_in_range, io.scratchPort.resp.valid, io.masterPort.resp.valid) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") }
module SodorRequestRouter( // @[scratchpad_adapter.scala:75:7] input clock, // @[scratchpad_adapter.scala:75:7] input reset, // @[scratchpad_adapter.scala:75:7] input io_masterPort_req_ready, // @[scratchpad_adapter.scala:76:14] output io_masterPort_req_valid, // @[scratchpad_adapter.scala:76:14] output [31:0] io_masterPort_req_bits_addr, // @[scratchpad_adapter.scala:76:14] output [31:0] io_masterPort_req_bits_data, // @[scratchpad_adapter.scala:76:14] output io_masterPort_req_bits_fcn, // @[scratchpad_adapter.scala:76:14] output [2:0] io_masterPort_req_bits_typ, // @[scratchpad_adapter.scala:76:14] input io_masterPort_resp_valid, // @[scratchpad_adapter.scala:76:14] input [31:0] io_masterPort_resp_bits_data, // @[scratchpad_adapter.scala:76:14] output io_scratchPort_req_valid, // @[scratchpad_adapter.scala:76:14] output [31:0] io_scratchPort_req_bits_addr, // @[scratchpad_adapter.scala:76:14] output [31:0] io_scratchPort_req_bits_data, // @[scratchpad_adapter.scala:76:14] output io_scratchPort_req_bits_fcn, // @[scratchpad_adapter.scala:76:14] output [2:0] io_scratchPort_req_bits_typ, // @[scratchpad_adapter.scala:76:14] input io_scratchPort_resp_valid, // @[scratchpad_adapter.scala:76:14] input [31:0] io_scratchPort_resp_bits_data, // @[scratchpad_adapter.scala:76:14] output io_corePort_req_ready, // @[scratchpad_adapter.scala:76:14] input io_corePort_req_valid, // @[scratchpad_adapter.scala:76:14] input [31:0] io_corePort_req_bits_addr, // @[scratchpad_adapter.scala:76:14] input [31:0] io_corePort_req_bits_data, // @[scratchpad_adapter.scala:76:14] input io_corePort_req_bits_fcn, // @[scratchpad_adapter.scala:76:14] input [2:0] io_corePort_req_bits_typ, // @[scratchpad_adapter.scala:76:14] output io_corePort_resp_valid, // @[scratchpad_adapter.scala:76:14] output [31:0] io_corePort_resp_bits_data, // @[scratchpad_adapter.scala:76:14] input [31:0] io_respAddress // @[scratchpad_adapter.scala:76:14] ); wire io_masterPort_req_ready_0 = io_masterPort_req_ready; // @[scratchpad_adapter.scala:75:7] wire io_masterPort_resp_valid_0 = io_masterPort_resp_valid; // @[scratchpad_adapter.scala:75:7] wire [31:0] io_masterPort_resp_bits_data_0 = io_masterPort_resp_bits_data; // @[scratchpad_adapter.scala:75:7] wire io_scratchPort_resp_valid_0 = io_scratchPort_resp_valid; // @[scratchpad_adapter.scala:75:7] wire [31:0] io_scratchPort_resp_bits_data_0 = io_scratchPort_resp_bits_data; // @[scratchpad_adapter.scala:75:7] wire io_corePort_req_valid_0 = io_corePort_req_valid; // @[scratchpad_adapter.scala:75:7] wire [31:0] io_corePort_req_bits_addr_0 = io_corePort_req_bits_addr; // @[scratchpad_adapter.scala:75:7] wire [31:0] io_corePort_req_bits_data_0 = io_corePort_req_bits_data; // @[scratchpad_adapter.scala:75:7] wire io_corePort_req_bits_fcn_0 = io_corePort_req_bits_fcn; // @[scratchpad_adapter.scala:75:7] wire [2:0] io_corePort_req_bits_typ_0 = io_corePort_req_bits_typ; // @[scratchpad_adapter.scala:75:7] wire [31:0] io_respAddress_0 = io_respAddress; // @[scratchpad_adapter.scala:75:7] wire io_scratchPort_req_ready = 1'h1; // @[scratchpad_adapter.scala:75:7, :76:14] wire _io_masterPort_req_valid_T_1; // @[scratchpad_adapter.scala:90:52] wire _io_scratchPort_req_valid_T; // @[scratchpad_adapter.scala:91:53] wire _io_corePort_req_ready_T; // @[scratchpad_adapter.scala:94:31] wire [31:0] io_masterPort_req_bits_addr_0 = io_corePort_req_bits_addr_0; // @[scratchpad_adapter.scala:75:7] wire [31:0] io_scratchPort_req_bits_addr_0 = io_corePort_req_bits_addr_0; // @[scratchpad_adapter.scala:75:7] wire [31:0] io_masterPort_req_bits_data_0 = io_corePort_req_bits_data_0; // @[scratchpad_adapter.scala:75:7] wire [31:0] io_scratchPort_req_bits_data_0 = io_corePort_req_bits_data_0; // @[scratchpad_adapter.scala:75:7] wire io_masterPort_req_bits_fcn_0 = io_corePort_req_bits_fcn_0; // @[scratchpad_adapter.scala:75:7] wire io_scratchPort_req_bits_fcn_0 = io_corePort_req_bits_fcn_0; // @[scratchpad_adapter.scala:75:7] wire [2:0] io_masterPort_req_bits_typ_0 = io_corePort_req_bits_typ_0; // @[scratchpad_adapter.scala:75:7] wire [2:0] io_scratchPort_req_bits_typ_0 = io_corePort_req_bits_typ_0; // @[scratchpad_adapter.scala:75:7] wire _io_corePort_resp_valid_T; // @[scratchpad_adapter.scala:98:32] wire [31:0] _io_corePort_resp_bits_T_data; // @[scratchpad_adapter.scala:97:31] wire io_masterPort_req_valid_0; // @[scratchpad_adapter.scala:75:7] wire io_scratchPort_req_valid_0; // @[scratchpad_adapter.scala:75:7] wire io_corePort_req_ready_0; // @[scratchpad_adapter.scala:75:7] wire [31:0] io_corePort_resp_bits_data_0; // @[scratchpad_adapter.scala:75:7] wire io_corePort_resp_valid_0; // @[scratchpad_adapter.scala:75:7] wire [31:0] _in_range_T = io_corePort_req_bits_addr_0 ^ 32'h80000000; // @[Parameters.scala:137:31] wire [32:0] _in_range_T_1 = {1'h0, _in_range_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _in_range_T_2 = _in_range_T_1 & 33'h1FFFC0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _in_range_T_3 = _in_range_T_2; // @[Parameters.scala:137:46] wire in_range = _in_range_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _io_masterPort_req_valid_T = ~in_range; // @[Parameters.scala:137:59] assign _io_masterPort_req_valid_T_1 = io_corePort_req_valid_0 & _io_masterPort_req_valid_T; // @[scratchpad_adapter.scala:75:7, :90:{52,54}] assign io_masterPort_req_valid_0 = _io_masterPort_req_valid_T_1; // @[scratchpad_adapter.scala:75:7, :90:52] assign _io_scratchPort_req_valid_T = io_corePort_req_valid_0 & in_range; // @[Parameters.scala:137:59] assign io_scratchPort_req_valid_0 = _io_scratchPort_req_valid_T; // @[scratchpad_adapter.scala:75:7, :91:53] assign _io_corePort_req_ready_T = in_range | io_masterPort_req_ready_0; // @[Parameters.scala:137:59] assign io_corePort_req_ready_0 = _io_corePort_req_ready_T; // @[scratchpad_adapter.scala:75:7, :94:31] wire [31:0] _resp_in_range_T = io_respAddress_0 ^ 32'h80000000; // @[Parameters.scala:137:31] wire [32:0] _resp_in_range_T_1 = {1'h0, _resp_in_range_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _resp_in_range_T_2 = _resp_in_range_T_1 & 33'h1FFFC0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _resp_in_range_T_3 = _resp_in_range_T_2; // @[Parameters.scala:137:46] wire resp_in_range = _resp_in_range_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] assign _io_corePort_resp_bits_T_data = resp_in_range ? io_scratchPort_resp_bits_data_0 : io_masterPort_resp_bits_data_0; // @[Parameters.scala:137:59] assign io_corePort_resp_bits_data_0 = _io_corePort_resp_bits_T_data; // @[scratchpad_adapter.scala:75:7, :97:31] assign _io_corePort_resp_valid_T = resp_in_range ? io_scratchPort_resp_valid_0 : io_masterPort_resp_valid_0; // @[Parameters.scala:137:59] assign io_corePort_resp_valid_0 = _io_corePort_resp_valid_T; // @[scratchpad_adapter.scala:75:7, :98:32] assign io_masterPort_req_valid = io_masterPort_req_valid_0; // @[scratchpad_adapter.scala:75:7] assign io_masterPort_req_bits_addr = io_masterPort_req_bits_addr_0; // @[scratchpad_adapter.scala:75:7] assign io_masterPort_req_bits_data = io_masterPort_req_bits_data_0; // @[scratchpad_adapter.scala:75:7] assign io_masterPort_req_bits_fcn = io_masterPort_req_bits_fcn_0; // @[scratchpad_adapter.scala:75:7] assign io_masterPort_req_bits_typ = io_masterPort_req_bits_typ_0; // @[scratchpad_adapter.scala:75:7] assign io_scratchPort_req_valid = io_scratchPort_req_valid_0; // @[scratchpad_adapter.scala:75:7] assign io_scratchPort_req_bits_addr = io_scratchPort_req_bits_addr_0; // @[scratchpad_adapter.scala:75:7] assign io_scratchPort_req_bits_data = io_scratchPort_req_bits_data_0; // @[scratchpad_adapter.scala:75:7] assign io_scratchPort_req_bits_fcn = io_scratchPort_req_bits_fcn_0; // @[scratchpad_adapter.scala:75:7] assign io_scratchPort_req_bits_typ = io_scratchPort_req_bits_typ_0; // @[scratchpad_adapter.scala:75:7] assign io_corePort_req_ready = io_corePort_req_ready_0; // @[scratchpad_adapter.scala:75:7] assign io_corePort_resp_valid = io_corePort_resp_valid_0; // @[scratchpad_adapter.scala:75:7] assign io_corePort_resp_bits_data = io_corePort_resp_bits_data_0; // @[scratchpad_adapter.scala:75:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File util.scala: //****************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v3.common.{MicroOp} import boom.v3.exu.{BrUpdateInfo} /** * Object to XOR fold a input register of fullLength into a compressedLength. */ object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /** * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks */ object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask) } def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) } } /** * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. */ object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /** * Object to return a BR mask given a MicroOp mask and old BR mask. */ object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask) out } } /** * Object to check if at least 1 bit matches in two masks */ object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /** * Object to clear one bit in a mask given an index */ object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /** * Object to shift a register over by one bit and concat a new one */ object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /** * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. */ object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /** * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. */ object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc | (b-1).U) } } /** * Object to rotate a signal left by one */ object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /** * Object to sext a value to a particular length. */ object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /** * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. */ object ImmGen { import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U} def apply(ip: UInt, isel: UInt): SInt = { val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt } } /** * Object to get the FP rounding mode out of a packed immediate. */ object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } } /** * Object to get the FP function fype from a packed immediate. * Note: only works if !(IS_B or IS_S) */ object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } } /** * Object to see if an instruction is a JALR. */ object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /** * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). */ object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /** * Object to return the lowest bit position after the head. */ object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /** * Object to determine whether queue * index i0 is older than index i1. */ object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } /** * Set all bits at or below the highest order '1'. */ object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_|_) } } /** * Set all bits at or above the lowest order '1'. */ object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_) } } /** * Transpose a matrix of Chisel Vecs. */ object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /** * N-wide one-hot priority encoder. */ object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /** * Connect the first k of n valid input interfaces to k output interfaces. */ class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_)) val out_valids = sels map (col => col.reduce(_||_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /** * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). */ class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v3.common.BoomModule()(p) with boom.v3.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire) val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop) uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop)) io.deq.bits := out io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop) // For flow queue behavior. if (flow) { when (io.empty) { io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop) io.deq.bits := io.enq.bits io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) do_deq := false.B when (io.deq.ready) { do_enq := false.B } } } private val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /** * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" */ def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) */ def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) */ def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) */ def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /** * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line */ def apply(strs: String*)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } File consts.scala: //****************************************************************************** // Copyright (c) 2011 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Constants //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.common.constants import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util.Str import freechips.rocketchip.rocket.RVCExpander /** * Mixin for issue queue types */ trait IQType { val IQT_SZ = 3 val IQT_INT = 1.U(IQT_SZ.W) val IQT_MEM = 2.U(IQT_SZ.W) val IQT_FP = 4.U(IQT_SZ.W) val IQT_MFP = 6.U(IQT_SZ.W) } /** * Mixin for scalar operation constants */ trait ScalarOpConstants { val X = BitPat("b?") val Y = BitPat("b1") val N = BitPat("b0") //************************************ // Extra Constants // Which branch predictor predicted us val BSRC_SZ = 2 val BSRC_1 = 0.U(BSRC_SZ.W) // 1-cycle branch pred val BSRC_2 = 1.U(BSRC_SZ.W) // 2-cycle branch pred val BSRC_3 = 2.U(BSRC_SZ.W) // 3-cycle branch pred val BSRC_C = 3.U(BSRC_SZ.W) // core branch resolution //************************************ // Control Signals // CFI types val CFI_SZ = 3 val CFI_X = 0.U(CFI_SZ.W) // Not a CFI instruction val CFI_BR = 1.U(CFI_SZ.W) // Branch val CFI_JAL = 2.U(CFI_SZ.W) // JAL val CFI_JALR = 3.U(CFI_SZ.W) // JALR // PC Select Signal val PC_PLUS4 = 0.U(2.W) // PC + 4 val PC_BRJMP = 1.U(2.W) // brjmp_target val PC_JALR = 2.U(2.W) // jump_reg_target // Branch Type val BR_N = 0.U(4.W) // Next val BR_NE = 1.U(4.W) // Branch on NotEqual val BR_EQ = 2.U(4.W) // Branch on Equal val BR_GE = 3.U(4.W) // Branch on Greater/Equal val BR_GEU = 4.U(4.W) // Branch on Greater/Equal Unsigned val BR_LT = 5.U(4.W) // Branch on Less Than val BR_LTU = 6.U(4.W) // Branch on Less Than Unsigned val BR_J = 7.U(4.W) // Jump val BR_JR = 8.U(4.W) // Jump Register // RS1 Operand Select Signal val OP1_RS1 = 0.U(2.W) // Register Source #1 val OP1_ZERO= 1.U(2.W) val OP1_PC = 2.U(2.W) val OP1_X = BitPat("b??") // RS2 Operand Select Signal val OP2_RS2 = 0.U(3.W) // Register Source #2 val OP2_IMM = 1.U(3.W) // immediate val OP2_ZERO= 2.U(3.W) // constant 0 val OP2_NEXT= 3.U(3.W) // constant 2/4 (for PC+2/4) val OP2_IMMC= 4.U(3.W) // for CSR imm found in RS1 val OP2_X = BitPat("b???") // Register File Write Enable Signal val REN_0 = false.B val REN_1 = true.B // Is 32b Word or 64b Doubldword? val SZ_DW = 1 val DW_X = true.B // Bool(xLen==64) val DW_32 = false.B val DW_64 = true.B val DW_XPR = true.B // Bool(xLen==64) // Memory Enable Signal val MEN_0 = false.B val MEN_1 = true.B val MEN_X = false.B // Immediate Extend Select val IS_I = 0.U(3.W) // I-Type (LD,ALU) val IS_S = 1.U(3.W) // S-Type (ST) val IS_B = 2.U(3.W) // SB-Type (BR) val IS_U = 3.U(3.W) // U-Type (LUI/AUIPC) val IS_J = 4.U(3.W) // UJ-Type (J/JAL) val IS_X = BitPat("b???") // Decode Stage Control Signals val RT_FIX = 0.U(2.W) val RT_FLT = 1.U(2.W) val RT_PAS = 3.U(2.W) // pass-through (prs1 := lrs1, etc) val RT_X = 2.U(2.W) // not-a-register (but shouldn't get a busy-bit, etc.) // TODO rename RT_NAR // Micro-op opcodes // TODO change micro-op opcodes into using enum val UOPC_SZ = 7 val uopX = BitPat.dontCare(UOPC_SZ) val uopNOP = 0.U(UOPC_SZ.W) val uopLD = 1.U(UOPC_SZ.W) val uopSTA = 2.U(UOPC_SZ.W) // store address generation val uopSTD = 3.U(UOPC_SZ.W) // store data generation val uopLUI = 4.U(UOPC_SZ.W) val uopADDI = 5.U(UOPC_SZ.W) val uopANDI = 6.U(UOPC_SZ.W) val uopORI = 7.U(UOPC_SZ.W) val uopXORI = 8.U(UOPC_SZ.W) val uopSLTI = 9.U(UOPC_SZ.W) val uopSLTIU= 10.U(UOPC_SZ.W) val uopSLLI = 11.U(UOPC_SZ.W) val uopSRAI = 12.U(UOPC_SZ.W) val uopSRLI = 13.U(UOPC_SZ.W) val uopSLL = 14.U(UOPC_SZ.W) val uopADD = 15.U(UOPC_SZ.W) val uopSUB = 16.U(UOPC_SZ.W) val uopSLT = 17.U(UOPC_SZ.W) val uopSLTU = 18.U(UOPC_SZ.W) val uopAND = 19.U(UOPC_SZ.W) val uopOR = 20.U(UOPC_SZ.W) val uopXOR = 21.U(UOPC_SZ.W) val uopSRA = 22.U(UOPC_SZ.W) val uopSRL = 23.U(UOPC_SZ.W) val uopBEQ = 24.U(UOPC_SZ.W) val uopBNE = 25.U(UOPC_SZ.W) val uopBGE = 26.U(UOPC_SZ.W) val uopBGEU = 27.U(UOPC_SZ.W) val uopBLT = 28.U(UOPC_SZ.W) val uopBLTU = 29.U(UOPC_SZ.W) val uopCSRRW= 30.U(UOPC_SZ.W) val uopCSRRS= 31.U(UOPC_SZ.W) val uopCSRRC= 32.U(UOPC_SZ.W) val uopCSRRWI=33.U(UOPC_SZ.W) val uopCSRRSI=34.U(UOPC_SZ.W) val uopCSRRCI=35.U(UOPC_SZ.W) val uopJ = 36.U(UOPC_SZ.W) val uopJAL = 37.U(UOPC_SZ.W) val uopJALR = 38.U(UOPC_SZ.W) val uopAUIPC= 39.U(UOPC_SZ.W) //val uopSRET = 40.U(UOPC_SZ.W) val uopCFLSH= 41.U(UOPC_SZ.W) val uopFENCE= 42.U(UOPC_SZ.W) val uopADDIW= 43.U(UOPC_SZ.W) val uopADDW = 44.U(UOPC_SZ.W) val uopSUBW = 45.U(UOPC_SZ.W) val uopSLLIW= 46.U(UOPC_SZ.W) val uopSLLW = 47.U(UOPC_SZ.W) val uopSRAIW= 48.U(UOPC_SZ.W) val uopSRAW = 49.U(UOPC_SZ.W) val uopSRLIW= 50.U(UOPC_SZ.W) val uopSRLW = 51.U(UOPC_SZ.W) val uopMUL = 52.U(UOPC_SZ.W) val uopMULH = 53.U(UOPC_SZ.W) val uopMULHU= 54.U(UOPC_SZ.W) val uopMULHSU=55.U(UOPC_SZ.W) val uopMULW = 56.U(UOPC_SZ.W) val uopDIV = 57.U(UOPC_SZ.W) val uopDIVU = 58.U(UOPC_SZ.W) val uopREM = 59.U(UOPC_SZ.W) val uopREMU = 60.U(UOPC_SZ.W) val uopDIVW = 61.U(UOPC_SZ.W) val uopDIVUW= 62.U(UOPC_SZ.W) val uopREMW = 63.U(UOPC_SZ.W) val uopREMUW= 64.U(UOPC_SZ.W) val uopFENCEI = 65.U(UOPC_SZ.W) // = 66.U(UOPC_SZ.W) val uopAMO_AG = 67.U(UOPC_SZ.W) // AMO-address gen (use normal STD for datagen) val uopFMV_W_X = 68.U(UOPC_SZ.W) val uopFMV_D_X = 69.U(UOPC_SZ.W) val uopFMV_X_W = 70.U(UOPC_SZ.W) val uopFMV_X_D = 71.U(UOPC_SZ.W) val uopFSGNJ_S = 72.U(UOPC_SZ.W) val uopFSGNJ_D = 73.U(UOPC_SZ.W) val uopFCVT_S_D = 74.U(UOPC_SZ.W) val uopFCVT_D_S = 75.U(UOPC_SZ.W) val uopFCVT_S_X = 76.U(UOPC_SZ.W) val uopFCVT_D_X = 77.U(UOPC_SZ.W) val uopFCVT_X_S = 78.U(UOPC_SZ.W) val uopFCVT_X_D = 79.U(UOPC_SZ.W) val uopCMPR_S = 80.U(UOPC_SZ.W) val uopCMPR_D = 81.U(UOPC_SZ.W) val uopFCLASS_S = 82.U(UOPC_SZ.W) val uopFCLASS_D = 83.U(UOPC_SZ.W) val uopFMINMAX_S = 84.U(UOPC_SZ.W) val uopFMINMAX_D = 85.U(UOPC_SZ.W) // = 86.U(UOPC_SZ.W) val uopFADD_S = 87.U(UOPC_SZ.W) val uopFSUB_S = 88.U(UOPC_SZ.W) val uopFMUL_S = 89.U(UOPC_SZ.W) val uopFADD_D = 90.U(UOPC_SZ.W) val uopFSUB_D = 91.U(UOPC_SZ.W) val uopFMUL_D = 92.U(UOPC_SZ.W) val uopFMADD_S = 93.U(UOPC_SZ.W) val uopFMSUB_S = 94.U(UOPC_SZ.W) val uopFNMADD_S = 95.U(UOPC_SZ.W) val uopFNMSUB_S = 96.U(UOPC_SZ.W) val uopFMADD_D = 97.U(UOPC_SZ.W) val uopFMSUB_D = 98.U(UOPC_SZ.W) val uopFNMADD_D = 99.U(UOPC_SZ.W) val uopFNMSUB_D = 100.U(UOPC_SZ.W) val uopFDIV_S = 101.U(UOPC_SZ.W) val uopFDIV_D = 102.U(UOPC_SZ.W) val uopFSQRT_S = 103.U(UOPC_SZ.W) val uopFSQRT_D = 104.U(UOPC_SZ.W) val uopWFI = 105.U(UOPC_SZ.W) // pass uop down the CSR pipeline val uopERET = 106.U(UOPC_SZ.W) // pass uop down the CSR pipeline, also is ERET val uopSFENCE = 107.U(UOPC_SZ.W) val uopROCC = 108.U(UOPC_SZ.W) val uopMOV = 109.U(UOPC_SZ.W) // conditional mov decoded from "add rd, x0, rs2" // The Bubble Instruction (Machine generated NOP) // Insert (XOR x0,x0,x0) which is different from software compiler // generated NOPs which are (ADDI x0, x0, 0). // Reasoning for this is to let visualizers and stat-trackers differentiate // between software NOPs and machine-generated Bubbles in the pipeline. val BUBBLE = (0x4033).U(32.W) def NullMicroOp()(implicit p: Parameters): boom.v3.common.MicroOp = { val uop = Wire(new boom.v3.common.MicroOp) uop := DontCare // Overridden in the following lines uop.uopc := uopNOP // maybe not required, but helps on asserts that try to catch spurious behavior uop.bypassable := false.B uop.fp_val := false.B uop.uses_stq := false.B uop.uses_ldq := false.B uop.pdst := 0.U uop.dst_rtype := RT_X val cs = Wire(new boom.v3.common.CtrlSignals()) cs := DontCare // Overridden in the following lines cs.br_type := BR_N cs.csr_cmd := freechips.rocketchip.rocket.CSR.N cs.is_load := false.B cs.is_sta := false.B cs.is_std := false.B uop.ctrl := cs uop } } /** * Mixin for RISCV constants */ trait RISCVConstants { // abstract out instruction decode magic numbers val RD_MSB = 11 val RD_LSB = 7 val RS1_MSB = 19 val RS1_LSB = 15 val RS2_MSB = 24 val RS2_LSB = 20 val RS3_MSB = 31 val RS3_LSB = 27 val CSR_ADDR_MSB = 31 val CSR_ADDR_LSB = 20 val CSR_ADDR_SZ = 12 // location of the fifth bit in the shamt (for checking for illegal ops for SRAIW,etc.) val SHAMT_5_BIT = 25 val LONGEST_IMM_SZ = 20 val X0 = 0.U val RA = 1.U // return address register // memory consistency model // The C/C++ atomics MCM requires that two loads to the same address maintain program order. // The Cortex A9 does NOT enforce load/load ordering (which leads to buggy behavior). val MCM_ORDER_DEPENDENT_LOADS = true val jal_opc = (0x6f).U val jalr_opc = (0x67).U def GetUop(inst: UInt): UInt = inst(6,0) def GetRd (inst: UInt): UInt = inst(RD_MSB,RD_LSB) def GetRs1(inst: UInt): UInt = inst(RS1_MSB,RS1_LSB) def ExpandRVC(inst: UInt)(implicit p: Parameters): UInt = { val rvc_exp = Module(new RVCExpander) rvc_exp.io.in := inst Mux(rvc_exp.io.rvc, rvc_exp.io.out.bits, inst) } // Note: Accepts only EXPANDED rvc instructions def ComputeBranchTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val b_imm32 = Cat(Fill(20,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) ((pc.asSInt + b_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def ComputeJALTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val j_imm32 = Cat(Fill(12,inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) ((pc.asSInt + j_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def GetCfiType(inst: UInt)(implicit p: Parameters): UInt = { val bdecode = Module(new boom.v3.exu.BranchDecode) bdecode.io.inst := inst bdecode.io.pc := 0.U bdecode.io.out.cfi_type } } /** * Mixin for exception cause constants */ trait ExcCauseConstants { // a memory disambigious misspeculation occurred val MINI_EXCEPTION_MEM_ORDERING = 16.U val MINI_EXCEPTION_CSR_REPLAY = 17.U require (!freechips.rocketchip.rocket.Causes.all.contains(16)) require (!freechips.rocketchip.rocket.Causes.all.contains(17)) } File issue-slot.scala: //****************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Issue Slot Logic //-------------------------------------------------------------------------- //------------------------------------------------------------------------------ // // Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot. // TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores. // TODO Disable ldspec for FP queue. package boom.v3.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import boom.v3.common._ import boom.v3.util._ import FUConstants._ /** * IO bundle to interact with Issue slot * * @param numWakeupPorts number of wakeup ports for the slot */ class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle { val valid = Output(Bool()) val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely? val request = Output(Bool()) val request_hp = Output(Bool()) val grant = Input(Bool()) val brupdate = Input(new BrUpdateInfo()) val kill = Input(Bool()) // pipeline flush val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant) val ldspec_miss = Input(Bool()) // Previous cycle's speculative load wakeup was mispredicted. val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new IqWakeup(maxPregSz)))) val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W))) val spec_ld_wakeup = Flipped(Vec(memWidth, Valid(UInt(width=maxPregSz.W)))) val in_uop = Flipped(Valid(new MicroOp())) // if valid, this WILL overwrite an entry! val out_uop = Output(new MicroOp()) // the updated slot uop; will be shifted upwards in a collasping queue. val uop = Output(new MicroOp()) // the current Slot's uop. Sent down the pipeline when issued. val debug = { val result = new Bundle { val p1 = Bool() val p2 = Bool() val p3 = Bool() val ppred = Bool() val state = UInt(width=2.W) } Output(result) } } /** * Single issue slot. Holds a uop within the issue queue * * @param numWakeupPorts number of wakeup ports */ class IssueSlot(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomModule with IssueUnitConstants { val io = IO(new IssueSlotIO(numWakeupPorts)) // slot invalid? // slot is valid, holding 1 uop // slot is valid, holds 2 uops (like a store) def is_invalid = state === s_invalid def is_valid = state =/= s_invalid val next_state = Wire(UInt()) // the next state of this slot (which might then get moved to a new slot) val next_uopc = Wire(UInt()) // the next uopc of this slot (which might then get moved to a new slot) val next_lrs1_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot) val next_lrs2_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot) val state = RegInit(s_invalid) val p1 = RegInit(false.B) val p2 = RegInit(false.B) val p3 = RegInit(false.B) val ppred = RegInit(false.B) // Poison if woken up by speculative load. // Poison lasts 1 cycle (as ldMiss will come on the next cycle). // SO if poisoned is true, set it to false! val p1_poisoned = RegInit(false.B) val p2_poisoned = RegInit(false.B) p1_poisoned := false.B p2_poisoned := false.B val next_p1_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned) val next_p2_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned) val slot_uop = RegInit(NullMicroOp) val next_uop = Mux(io.in_uop.valid, io.in_uop.bits, slot_uop) //----------------------------------------------------------------------------- // next slot state computation // compute the next state for THIS entry slot (in a collasping queue, the // current uop may get moved elsewhere, and a new uop can enter when (io.kill) { state := s_invalid } .elsewhen (io.in_uop.valid) { state := io.in_uop.bits.iw_state } .elsewhen (io.clear) { state := s_invalid } .otherwise { state := next_state } //----------------------------------------------------------------------------- // "update" state // compute the next state for the micro-op in this slot. This micro-op may // be moved elsewhere, so the "next_state" travels with it. // defaults next_state := state next_uopc := slot_uop.uopc next_lrs1_rtype := slot_uop.lrs1_rtype next_lrs2_rtype := slot_uop.lrs2_rtype when (io.kill) { next_state := s_invalid } .elsewhen ((io.grant && (state === s_valid_1)) || (io.grant && (state === s_valid_2) && p1 && p2 && ppred)) { // try to issue this uop. when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) { next_state := s_invalid } } .elsewhen (io.grant && (state === s_valid_2)) { when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) { next_state := s_valid_1 when (p1) { slot_uop.uopc := uopSTD next_uopc := uopSTD slot_uop.lrs1_rtype := RT_X next_lrs1_rtype := RT_X } .otherwise { slot_uop.lrs2_rtype := RT_X next_lrs2_rtype := RT_X } } } when (io.in_uop.valid) { slot_uop := io.in_uop.bits assert (is_invalid || io.clear || io.kill, "trying to overwrite a valid issue slot.") } // Wakeup Compare Logic // these signals are the "next_p*" for the current slot's micro-op. // they are important for shifting the current slot_uop up to an other entry. val next_p1 = WireInit(p1) val next_p2 = WireInit(p2) val next_p3 = WireInit(p3) val next_ppred = WireInit(ppred) when (io.in_uop.valid) { p1 := !(io.in_uop.bits.prs1_busy) p2 := !(io.in_uop.bits.prs2_busy) p3 := !(io.in_uop.bits.prs3_busy) ppred := !(io.in_uop.bits.ppred_busy) } when (io.ldspec_miss && next_p1_poisoned) { assert(next_uop.prs1 =/= 0.U, "Poison bit can't be set for prs1=x0!") p1 := false.B } when (io.ldspec_miss && next_p2_poisoned) { assert(next_uop.prs2 =/= 0.U, "Poison bit can't be set for prs2=x0!") p2 := false.B } for (i <- 0 until numWakeupPorts) { when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs1)) { p1 := true.B } when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs2)) { p2 := true.B } when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs3)) { p3 := true.B } } when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === next_uop.ppred) { ppred := true.B } for (w <- 0 until memWidth) { assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U), "Loads to x0 should never speculatively wakeup other instructions") } // TODO disable if FP IQ. for (w <- 0 until memWidth) { when (io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === next_uop.prs1 && next_uop.lrs1_rtype === RT_FIX) { p1 := true.B p1_poisoned := true.B assert (!next_p1_poisoned) } when (io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === next_uop.prs2 && next_uop.lrs2_rtype === RT_FIX) { p2 := true.B p2_poisoned := true.B assert (!next_p2_poisoned) } } // Handle branch misspeculations val next_br_mask = GetNewBrMask(io.brupdate, slot_uop) // was this micro-op killed by a branch? if yes, we can't let it be valid if // we compact it into an other entry when (IsKilledByBranch(io.brupdate, slot_uop)) { next_state := s_invalid } when (!io.in_uop.valid) { slot_uop.br_mask := next_br_mask } //------------------------------------------------------------- // Request Logic io.request := is_valid && p1 && p2 && p3 && ppred && !io.kill val high_priority = slot_uop.is_br || slot_uop.is_jal || slot_uop.is_jalr io.request_hp := io.request && high_priority when (state === s_valid_1) { io.request := p1 && p2 && p3 && ppred && !io.kill } .elsewhen (state === s_valid_2) { io.request := (p1 || p2) && ppred && !io.kill } .otherwise { io.request := false.B } //assign outputs io.valid := is_valid io.uop := slot_uop io.uop.iw_p1_poisoned := p1_poisoned io.uop.iw_p2_poisoned := p2_poisoned // micro-op will vacate due to grant. val may_vacate = io.grant && ((state === s_valid_1) || (state === s_valid_2) && p1 && p2 && ppred) val squash_grant = io.ldspec_miss && (p1_poisoned || p2_poisoned) io.will_be_valid := is_valid && !(may_vacate && !squash_grant) io.out_uop := slot_uop io.out_uop.iw_state := next_state io.out_uop.uopc := next_uopc io.out_uop.lrs1_rtype := next_lrs1_rtype io.out_uop.lrs2_rtype := next_lrs2_rtype io.out_uop.br_mask := next_br_mask io.out_uop.prs1_busy := !p1 io.out_uop.prs2_busy := !p2 io.out_uop.prs3_busy := !p3 io.out_uop.ppred_busy := !ppred io.out_uop.iw_p1_poisoned := p1_poisoned io.out_uop.iw_p2_poisoned := p2_poisoned when (state === s_valid_2) { when (p1 && p2 && ppred) { ; // send out the entire instruction as one uop } .elsewhen (p1 && ppred) { io.uop.uopc := slot_uop.uopc io.uop.lrs2_rtype := RT_X } .elsewhen (p2 && ppred) { io.uop.uopc := uopSTD io.uop.lrs1_rtype := RT_X } } // debug outputs io.debug.p1 := p1 io.debug.p2 := p2 io.debug.p3 := p3 io.debug.ppred := ppred io.debug.state := state }
module IssueSlot_21( // @[issue-slot.scala:69:7] input clock, // @[issue-slot.scala:69:7] input reset, // @[issue-slot.scala:69:7] output io_valid, // @[issue-slot.scala:73:14] output io_will_be_valid, // @[issue-slot.scala:73:14] output io_request, // @[issue-slot.scala:73:14] output io_request_hp, // @[issue-slot.scala:73:14] input io_grant, // @[issue-slot.scala:73:14] input [7:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14] input [7:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14] input [7:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14] input io_brupdate_b2_valid, // @[issue-slot.scala:73:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14] input io_brupdate_b2_taken, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14] input io_kill, // @[issue-slot.scala:73:14] input io_clear, // @[issue-slot.scala:73:14] input io_ldspec_miss, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14] input [5:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14] input [5:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:73:14] input [5:0] io_wakeup_ports_2_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_bits_poisoned, // @[issue-slot.scala:73:14] input io_spec_ld_wakeup_0_valid, // @[issue-slot.scala:73:14] input [5:0] io_spec_ld_wakeup_0_bits, // @[issue-slot.scala:73:14] input io_in_uop_valid, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14] input [7:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14] input io_in_uop_bits_taken, // @[issue-slot.scala:73:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14] input io_in_uop_bits_exception, // @[issue-slot.scala:73:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14] input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14] output io_out_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14] output io_out_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_is_br, // @[issue-slot.scala:73:14] output io_out_uop_is_jalr, // @[issue-slot.scala:73:14] output io_out_uop_is_jal, // @[issue-slot.scala:73:14] output io_out_uop_is_sfb, // @[issue-slot.scala:73:14] output [7:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_out_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14] output io_out_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pdst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_prs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_prs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_prs3, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ppred, // @[issue-slot.scala:73:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_out_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14] output io_out_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14] output io_out_uop_mem_signed, // @[issue-slot.scala:73:14] output io_out_uop_is_fence, // @[issue-slot.scala:73:14] output io_out_uop_is_fencei, // @[issue-slot.scala:73:14] output io_out_uop_is_amo, // @[issue-slot.scala:73:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_out_uop_uses_stq, // @[issue-slot.scala:73:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_out_uop_is_unique, // @[issue-slot.scala:73:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14] output io_out_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_out_uop_frs3_en, // @[issue-slot.scala:73:14] output io_out_uop_fp_val, // @[issue-slot.scala:73:14] output io_out_uop_fp_single, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14] output io_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14] output io_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_uop_is_br, // @[issue-slot.scala:73:14] output io_uop_is_jalr, // @[issue-slot.scala:73:14] output io_uop_is_jal, // @[issue-slot.scala:73:14] output io_uop_is_sfb, // @[issue-slot.scala:73:14] output [7:0] io_uop_br_mask, // @[issue-slot.scala:73:14] output [2:0] io_uop_br_tag, // @[issue-slot.scala:73:14] output [3:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14] output io_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14] output [4:0] io_uop_rob_idx, // @[issue-slot.scala:73:14] output [2:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14] output [2:0] io_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14] output [5:0] io_uop_pdst, // @[issue-slot.scala:73:14] output [5:0] io_uop_prs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_prs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_prs3, // @[issue-slot.scala:73:14] output [3:0] io_uop_ppred, // @[issue-slot.scala:73:14] output io_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_uop_ppred_busy, // @[issue-slot.scala:73:14] output [5:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14] output io_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14] output io_uop_mem_signed, // @[issue-slot.scala:73:14] output io_uop_is_fence, // @[issue-slot.scala:73:14] output io_uop_is_fencei, // @[issue-slot.scala:73:14] output io_uop_is_amo, // @[issue-slot.scala:73:14] output io_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_uop_uses_stq, // @[issue-slot.scala:73:14] output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_uop_is_unique, // @[issue-slot.scala:73:14] output io_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14] output io_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_uop_frs3_en, // @[issue-slot.scala:73:14] output io_uop_fp_val, // @[issue-slot.scala:73:14] output io_uop_fp_single, // @[issue-slot.scala:73:14] output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14] output io_debug_p1, // @[issue-slot.scala:73:14] output io_debug_p2, // @[issue-slot.scala:73:14] output io_debug_p3, // @[issue-slot.scala:73:14] output io_debug_ppred, // @[issue-slot.scala:73:14] output [1:0] io_debug_state // @[issue-slot.scala:73:14] ); wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7] wire [7:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7] wire [7:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7] wire [7:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7] wire io_ldspec_miss_0 = io_ldspec_miss; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7] wire [5:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_bits_poisoned_0 = io_wakeup_ports_0_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7] wire [5:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_bits_poisoned_0 = io_wakeup_ports_1_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:69:7] wire [5:0] io_wakeup_ports_2_bits_pdst_0 = io_wakeup_ports_2_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_bits_poisoned_0 = io_wakeup_ports_2_bits_poisoned; // @[issue-slot.scala:69:7] wire io_spec_ld_wakeup_0_valid_0 = io_spec_ld_wakeup_0_valid; // @[issue-slot.scala:69:7] wire [5:0] io_spec_ld_wakeup_0_bits_0 = io_spec_ld_wakeup_0_bits; // @[issue-slot.scala:69:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p1_poisoned_0 = io_in_uop_bits_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p2_poisoned_0 = io_in_uop_bits_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7] wire [7:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7] wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire [3:0] io_pred_wakeup_port_bits = 4'h0; // @[issue-slot.scala:69:7] wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_ftq_idx = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_ppred = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_br_tag = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ldq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_stq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_rob_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_prs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_prs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_prs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_stale_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [7:0] slot_uop_uop_br_mask = 8'h0; // @[consts.scala:269:19] wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire _io_valid_T; // @[issue-slot.scala:79:24] wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32] wire _io_request_hp_T; // @[issue-slot.scala:243:31] wire [6:0] next_uopc; // @[issue-slot.scala:82:29] wire [1:0] next_state; // @[issue-slot.scala:81:29] wire [7:0] next_br_mask; // @[util.scala:85:25] wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28] wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28] wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28] wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28] wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29] wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29] wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [7:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_out_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_out_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [7:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pdst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_prs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_prs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_prs3_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire io_debug_p1_0; // @[issue-slot.scala:69:7] wire io_debug_p2_0; // @[issue-slot.scala:69:7] wire io_debug_p3_0; // @[issue-slot.scala:69:7] wire io_debug_ppred_0; // @[issue-slot.scala:69:7] wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7] wire io_valid_0; // @[issue-slot.scala:69:7] wire io_will_be_valid_0; // @[issue-slot.scala:69:7] wire io_request_0; // @[issue-slot.scala:69:7] wire io_request_hp_0; // @[issue-slot.scala:69:7] assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29] assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29] assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29] assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29] reg [1:0] state; // @[issue-slot.scala:86:22] assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22] reg p1; // @[issue-slot.scala:87:22] assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22] wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25] reg p2; // @[issue-slot.scala:88:22] assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22] wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25] reg p3; // @[issue-slot.scala:89:22] assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22] wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25] reg ppred; // @[issue-slot.scala:90:22] assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22] wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28] reg p1_poisoned; // @[issue-slot.scala:95:28] assign io_out_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] assign io_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] reg p2_poisoned; // @[issue-slot.scala:96:28] assign io_out_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] assign io_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] wire next_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : p1_poisoned; // @[issue-slot.scala:69:7, :95:28, :99:29] wire next_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : p2_poisoned; // @[issue-slot.scala:69:7, :96:28, :100:29] reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25] reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25] assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25] assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_rvc; // @[issue-slot.scala:102:25] assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25] assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25] assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25] assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_is_br; // @[issue-slot.scala:102:25] assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jalr; // @[issue-slot.scala:102:25] assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jal; // @[issue-slot.scala:102:25] assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sfb; // @[issue-slot.scala:102:25] assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] reg [7:0] slot_uop_br_mask; // @[issue-slot.scala:102:25] assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_br_tag; // @[issue-slot.scala:102:25] assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_edge_inst; // @[issue-slot.scala:102:25] assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25] assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_taken; // @[issue-slot.scala:102:25] assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25] assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25] assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_prs1; // @[issue-slot.scala:102:25] assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_prs2; // @[issue-slot.scala:102:25] assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_prs3; // @[issue-slot.scala:102:25] assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ppred; // @[issue-slot.scala:102:25] assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25] assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25] assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25] assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25] assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_exception; // @[issue-slot.scala:102:25] assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25] assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bypassable; // @[issue-slot.scala:102:25] assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25] assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_mem_signed; // @[issue-slot.scala:102:25] assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fence; // @[issue-slot.scala:102:25] assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fencei; // @[issue-slot.scala:102:25] assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_amo; // @[issue-slot.scala:102:25] assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_stq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25] assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_unique; // @[issue-slot.scala:102:25] assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25] assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25] assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25] assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25] assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_val; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25] assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25] reg slot_uop_frs3_en; // @[issue-slot.scala:102:25] assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_val; // @[issue-slot.scala:102:25] assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_single; // @[issue-slot.scala:102:25] assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [7:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25] wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}] wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25] wire _T_14 = io_ldspec_miss_0 & (p1_poisoned | p2_poisoned); // @[issue-slot.scala:69:7, :95:28, :96:28, :140:{28,44}] wire _GEN = _T_12 & ~_T_14; // @[issue-slot.scala:126:14, :139:{25,51}, :140:{11,28,62}, :141:18] wire _GEN_0 = io_kill_0 | _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51] wire _GEN_1 = _GEN_0 | ~(_T_12 & ~_T_14 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:{11,28,62}, :142:17, :143:23] assign next_uopc = _GEN_1 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51] assign next_lrs1_rtype = _GEN_1 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51] wire _GEN_2 = _GEN_0 | ~_GEN | p1; // @[issue-slot.scala:87:22, :102:25, :126:14, :131:18, :134:63, :139:51, :140:62, :141:18, :142:17] assign next_lrs2_rtype = _GEN_2 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17] wire _p1_T = ~io_in_uop_bits_prs1_busy_0; // @[issue-slot.scala:69:7, :169:11] wire _p2_T = ~io_in_uop_bits_prs2_busy_0; // @[issue-slot.scala:69:7, :170:11] wire _p3_T = ~io_in_uop_bits_prs3_busy_0; // @[issue-slot.scala:69:7, :171:11] wire _ppred_T = ~io_in_uop_bits_ppred_busy_0; // @[issue-slot.scala:69:7, :172:14] wire _T_22 = io_ldspec_miss_0 & next_p1_poisoned; // @[issue-slot.scala:69:7, :99:29, :175:24] wire _T_27 = io_ldspec_miss_0 & next_p2_poisoned; // @[issue-slot.scala:69:7, :100:29, :179:24] wire _T_61 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs1 & next_uop_lrs1_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :209:38, :210:{33,51}, :211:27] wire _T_69 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs2 & next_uop_lrs2_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :216:38, :217:{33,51}, :218:27]
Generate the Verilog code corresponding to the following Chisel files. File LoopConv.scala: package gemmini import chisel3._ import chisel3.util._ import chisel3.experimental._ import freechips.rocketchip.tile.RoCCCommand import org.chipsalliance.cde.config.Parameters import GemminiISA._ import LocalAddr._ import Util._ class LoopConvOuterBounds(val large_iterator_bitwidth: Int, val small_iterator_bitwidth: Int, val tiny_iterator_bitwidth: Int) extends Bundle { val batch_size = UInt(large_iterator_bitwidth.W) val in_row_dim = UInt(small_iterator_bitwidth.W) val in_col_dim = UInt(small_iterator_bitwidth.W) val in_channels = UInt(large_iterator_bitwidth.W) val out_channels = UInt(large_iterator_bitwidth.W) val out_col_dim = UInt(large_iterator_bitwidth.W) val out_row_dim = UInt(large_iterator_bitwidth.W) val out_stride = UInt(large_iterator_bitwidth.W) //stride for output activation val in_stride = UInt(large_iterator_bitwidth.W) //stride for input activation val weight_stride = UInt(large_iterator_bitwidth.W) //stride for weight val pool_out_row_dim = UInt(small_iterator_bitwidth.W) val pool_out_col_dim = UInt(small_iterator_bitwidth.W) val stride = UInt(tiny_iterator_bitwidth.W) val padding = UInt(tiny_iterator_bitwidth.W) val kernel_dim = UInt(tiny_iterator_bitwidth.W) val kernel_dilation = UInt(tiny_iterator_bitwidth.W) val pool_size = UInt(tiny_iterator_bitwidth.W) val pool_stride = UInt(tiny_iterator_bitwidth.W) val pool_padding = UInt(tiny_iterator_bitwidth.W) } class LoopConvInnerBounds(val large_iterator_bitwidth: Int, val small_iterator_bitwidth: Int, val tiny_iterator_bitwidth: Int) extends Bundle { val batches = UInt(large_iterator_bitwidth.W) val porows = UInt(small_iterator_bitwidth.W) val pocols = UInt(small_iterator_bitwidth.W) val pochs = UInt(large_iterator_bitwidth.W) val krows = UInt(tiny_iterator_bitwidth.W) val kcols = UInt(tiny_iterator_bitwidth.W) val kchs = UInt(large_iterator_bitwidth.W) val lpad = UInt(tiny_iterator_bitwidth.W) val rpad = UInt(tiny_iterator_bitwidth.W) val upad = UInt(tiny_iterator_bitwidth.W) val dpad = UInt(tiny_iterator_bitwidth.W) val plpad = UInt(tiny_iterator_bitwidth.W) val prad = UInt(tiny_iterator_bitwidth.W) val pupad = UInt(tiny_iterator_bitwidth.W) val pdpad = UInt(tiny_iterator_bitwidth.W) val orows = UInt(small_iterator_bitwidth.W) val ocols = UInt(small_iterator_bitwidth.W) } class LoopConvDerivedParams(val large_iterator_bitwidth: Int, val small_iterator_bitwidth: Int, val tiny_iterator_bitwidth: Int) extends Bundle { val ochs = UInt(large_iterator_bitwidth.W) val irows = UInt(small_iterator_bitwidth.W) val icols = UInt(small_iterator_bitwidth.W) val irows_unpadded = UInt(small_iterator_bitwidth.W) val icols_unpadded = UInt(small_iterator_bitwidth.W) val ichs = UInt(large_iterator_bitwidth.W) val out_channels_per_bank = UInt(small_iterator_bitwidth.W) // TODO this won't work for systolic arrays above 256 in size val in_channels_per_bank = UInt(small_iterator_bitwidth.W) // TODO this won't work for systolic arrays above 256 in size val bias_spad_stride = UInt(large_iterator_bitwidth.W) val input_spad_stride = UInt(large_iterator_bitwidth.W) val weight_spad_stride = UInt(large_iterator_bitwidth.W) // val ex_overwrite = Bool() } class LoopConvLdBiasReq(val coreMaxAddrBits: Int, val large_iterator_bitwidth: Int, val small_iterator_bitwidth: Int, val tiny_iterator_bitwidth: Int, val max_acc_addr: Int, val concurrent_loops: Int) extends Bundle { val outer_bounds = new LoopConvOuterBounds(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val inner_bounds = new LoopConvInnerBounds(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val derived_params = new LoopConvDerivedParams(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val addr_start = UInt(log2Up(max_acc_addr).W) val dram_addr = UInt(coreMaxAddrBits.W) val no_bias = Bool() val loop_id = UInt(log2Up(concurrent_loops).W) } class LoopConvLdBias(block_size: Int, coreMaxAddrBits: Int, large_iterator_bitwidth: Int, small_iterator_bitwidth: Int, tiny_iterator_bitwidth: Int, max_acc_addr: Int, acc_w: Int, max_block_len_acc: Int, concurrent_loops: Int, latency: Int, config_mvin_rs1_t: ConfigMvinRs1, mvin_rs2_t: MvinRs2)(implicit p: Parameters) extends Module { val MVIN_SCALE_IDENTITY = 0x3f800000.U // TODO get this from configs somehow val io = IO(new Bundle { val req = Flipped(Decoupled(new LoopConvLdBiasReq(coreMaxAddrBits, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth: Int, max_acc_addr, concurrent_loops))) val cmd = Decoupled(Output(new RoCCCommand)) val idle = Output(Bool()) val rob_overloaded = Input(Bool()) val wait_for_prev_loop = Input(Bool()) val loop_id = Output(UInt(log2Up(concurrent_loops).W)) }) object State extends ChiselEnum { val idle, config, ld = Value } import State._ val state = RegInit(idle) val req = Reg(new LoopConvLdBiasReq(coreMaxAddrBits, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth: Int, max_acc_addr, concurrent_loops)) import req.inner_bounds._ import req.derived_params._ val acc_addr_start = req.addr_start // Derived parameters val max_ochs_per_mvin = Mux(ochs < (max_block_len_acc * block_size).U, ochs, (max_block_len_acc * block_size).U) val skip = req.dram_addr === 0.U // Iterators val b = Reg(UInt(large_iterator_bitwidth.W)) val orow = Reg(UInt(small_iterator_bitwidth.W)) val ocol = Reg(UInt(small_iterator_bitwidth.W)) val och = Reg(UInt(large_iterator_bitwidth.W)) // Addresses val dram_offset = och * (acc_w/8).U val dram_addr = Mux(req.no_bias, 0.U, req.dram_addr + LoopConv.castDramOffset(dram_offset)) val spad_addr = acc_addr_start +& (och / block_size.U(och.getWidth.W)) * batches * orows * ocols +& b * orows * ocols +& orow * ocols +& ocol // Sizes val I = Mux(ocols - ocol > block_size.U, block_size.U, ocols - ocol) val J = Mux(ochs - och > max_ochs_per_mvin, max_ochs_per_mvin, ochs - och) class RoCCCommandWithAddr extends Bundle { val cmd = new RoCCCommand val dram_addr = UInt() val spad_addr = UInt() val I = UInt() val J = UInt() } val command_p = Module(new Pipeline[RoCCCommandWithAddr](new RoCCCommandWithAddr, latency)()) // Commands val config_cmd = Wire(new RoCCCommand) config_cmd := DontCare config_cmd.inst.funct := CONFIG_CMD val config_cmd_rs1 = Wire(config_mvin_rs1_t.cloneType) config_cmd_rs1 := DontCare config_cmd_rs1.scale := MVIN_SCALE_IDENTITY config_cmd_rs1.stride := req.derived_params.bias_spad_stride config_cmd_rs1.pixel_repeats := 1.U config_cmd_rs1.state_id := 2.U config_cmd_rs1.shrink := 0.U config_cmd_rs1._unused := 1.U config_cmd.rs1 := config_cmd_rs1.asUInt config_cmd.rs2 := 0.U val mvin_cmd = Wire(new RoCCCommand) mvin_cmd := DontCare mvin_cmd.inst.funct := LOAD3_CMD mvin_cmd.rs1 := 0.U mvin_cmd.rs2 := 0.U // Inputs and outputs io.req.ready := state === idle && !command_p.io.busy io.idle := state === idle && !command_p.io.busy io.loop_id := req.loop_id command_p.io.in.valid := state =/= idle && !io.wait_for_prev_loop && !skip command_p.io.in.bits.cmd := Mux(state === config, config_cmd, mvin_cmd) command_p.io.in.bits.dram_addr := dram_addr command_p.io.in.bits.spad_addr := spad_addr command_p.io.in.bits.I := I command_p.io.in.bits.J := J command_p.io.out.ready := io.cmd.ready && !io.rob_overloaded io.cmd.valid := command_p.io.out.valid && !io.rob_overloaded io.cmd.bits := command_p.io.out.bits.cmd when (command_p.io.out.bits.cmd.inst.funct === LOAD3_CMD) { val o = command_p.io.out.bits io.cmd.bits.rs1 := o.dram_addr val mvin_cmd_rs2 = Wire(mvin_rs2_t.cloneType) mvin_cmd_rs2 := DontCare mvin_cmd_rs2.num_rows := o.I.asUInt mvin_cmd_rs2.num_cols := o.J.asUInt mvin_cmd_rs2.local_addr := cast_to_acc_addr(mvin_cmd_rs2.local_addr, o.spad_addr, accumulate = false.B, read_full = false.B) io.cmd.bits.rs2 := mvin_cmd_rs2.asUInt } // Sending outputs when (skip) { state := idle }.elsewhen(command_p.io.in.fire) { when (state === config) { state := ld }.otherwise { val next_och = floorAdd(och, max_ochs_per_mvin, ochs) val next_ocol = floorAdd(ocol, block_size.U, ocols, next_och === 0.U) val next_orow = floorAdd(orow, 1.U, orows, next_ocol === 0.U && next_och === 0.U) val next_b = floorAdd(b, 1.U, batches, next_orow === 0.U && next_ocol === 0.U && next_och === 0.U) och := next_och ocol := next_ocol orow := next_orow b := next_b state := Mux(next_b === 0.U && next_orow === 0.U && next_ocol === 0.U && next_och === 0.U, idle, ld) } } // Accepting requests when (io.req.fire) { req := io.req.bits state := config b := 0.U orow := 0.U ocol := 0.U och := 0.U } } class LoopConvLdInputReq(val coreMaxAddrBits: Int, val large_iterator_bitwidth: Int, val small_iterator_bitwidth: Int, val tiny_iterator_bitwidth: Int, val max_acc_addr: Int, val concurrent_loops: Int) extends Bundle { val outer_bounds = new LoopConvOuterBounds(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val inner_bounds = new LoopConvInnerBounds(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val derived_params = new LoopConvDerivedParams(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val addr_start = UInt(log2Up(max_acc_addr).W) val dram_addr = UInt(coreMaxAddrBits.W) val downsample = Bool() val max_pixels_per_row = UInt(small_iterator_bitwidth.W) val input_dilated = Bool() val trans_input_3120 = Bool() val loop_id = UInt(log2Up(concurrent_loops).W) } class LoopConvLdInput(block_size: Int, coreMaxAddrBits: Int, large_iterator_bitwidth: Int, small_iterator_bitwidth: Int, tiny_iterator_bitwidth: Int, max_addr: Int, input_w: Int, max_block_len: Int, concurrent_loops: Int, latency: Int, config_mvin_rs1_t: ConfigMvinRs1, mvin_rs2_t: MvinRs2) (implicit p: Parameters) extends Module { val MVIN_SCALE_IDENTITY = 0x3f800000.U // TODO get this from configs somehow val io = IO(new Bundle { val req = Flipped(Decoupled(new LoopConvLdInputReq(coreMaxAddrBits, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth, max_addr, concurrent_loops))) val cmd = Decoupled(Output(new RoCCCommand)) val idle = Output(Bool()) val rob_overloaded = Input(Bool()) val wait_for_prev_loop = Input(Bool()) val loop_id = Output(UInt(log2Up(concurrent_loops).W)) }) object State extends ChiselEnum { val idle, config, ld = Value } import State._ val state = RegInit(idle) val req = Reg(new LoopConvLdInputReq(coreMaxAddrBits, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth, max_addr, concurrent_loops)) import req.outer_bounds._ import req.inner_bounds._ import req.derived_params._ def undilated(x: UInt): UInt = (x +& req.input_dilated) >> req.input_dilated // Derived parameters val max_ichs_per_mvin = Mux(ichs < (max_block_len * block_size).U, ichs, (max_block_len * block_size).U).zext val max_batches_per_mvin = Mux(batches < (max_block_len * block_size).U, batches, (max_block_len * block_size).U).zext val max_chs_per_mvin = Mux(req.trans_input_3120, max_batches_per_mvin, max_ichs_per_mvin) // Iterators val b = Reg(SInt(large_iterator_bitwidth.W)) val irow = Reg(SInt(small_iterator_bitwidth.W)) val icol = Reg(SInt(small_iterator_bitwidth.W)) val ich = Reg(SInt(large_iterator_bitwidth.W)) // Calculated params val irow_padded = irow +& undilated(upad).zext val icol_padded = icol +& undilated(lpad).zext val is_zeros = irow < 0.S || irow >= irows_unpadded.zext || icol < 0.S || icol >= icols_unpadded.zext val dram_stride = Mux(req.trans_input_3120, batch_size * (input_w/8).U, in_stride * (input_w/8).U) // Addresses val dram_offset = Mux(req.trans_input_3120, (((ich * in_col_dim * in_row_dim +& irow*in_col_dim +& icol) * batches +& b) * (input_w/8).U).asUInt, (((b * in_row_dim * in_col_dim +& irow*in_col_dim +& icol) * in_stride +& ich) * (input_w/8).U).asUInt) val dram_addr = Mux(is_zeros, 0.U, req.dram_addr + LoopConv.castDramOffset(dram_offset)) val spad_addr = Mux(req.trans_input_3120, // To prevent Verilator errors, we replace some "/ block_size.U" calls here with ">> log2Up(block_size)" req.addr_start.zext +& (b >> log2Up(block_size)) * input_spad_stride +& ich * (irows >> req.downsample) * (icols >> req.downsample) +& (irow_padded >> req.downsample) * (icols >> req.downsample) +& (icol_padded >> req.downsample), req.addr_start.zext +& (ich >> log2Up(block_size)) * input_spad_stride +& b * (irows >> req.downsample) * (icols >> req.downsample) +& (irow_padded >> req.downsample) * (icols >> req.downsample) +& (icol_padded >> req.downsample)) // Sizes val block_size_downsampled = (block_size.U << req.downsample).asUInt.zext val I = MuxCase( Mux(icols_unpadded.zext -& icol > block_size_downsampled, block_size_downsampled, icols_unpadded.zext -& icol), Seq( (icol < 0.S) -> Mux((0.S-&icol) > block_size.S, block_size.S, 0.S-&icol), (icol >= icols_unpadded.zext) -> Mux(icols_unpadded.zext +& undilated(rpad).zext -& icol > block_size.S, block_size.S, icols_unpadded.zext +& undilated(rpad).zext -& icol) ) ) val K = Mux(req.trans_input_3120, Mux(batches.zext -& b > max_chs_per_mvin, max_chs_per_mvin, batches.zext -& b), Mux(ichs.zext -& ich > max_chs_per_mvin, max_chs_per_mvin, ichs.zext -& ich)) class RoCCCommandWithAddr extends Bundle { val cmd = new RoCCCommand val dram_addr = UInt() val spad_addr = SInt() val I = SInt() val K = SInt() } val command_p = Module(new Pipeline[RoCCCommandWithAddr](new RoCCCommandWithAddr, latency)()) // Commands val config_cmd = Wire(new RoCCCommand) config_cmd := DontCare config_cmd.inst.funct := CONFIG_CMD val config_cmd_rs1 = Wire(config_mvin_rs1_t.cloneType) config_cmd_rs1 := DontCare config_cmd_rs1.scale := MVIN_SCALE_IDENTITY config_cmd_rs1.stride := input_spad_stride config_cmd_rs1.pixel_repeats := req.max_pixels_per_row config_cmd_rs1.state_id := 0.U config_cmd_rs1.shrink := 0.U config_cmd_rs1._unused := 1.U config_cmd.rs1 := config_cmd_rs1.asUInt config_cmd.rs2 := dram_stride << req.downsample val mvin_cmd = Wire(new RoCCCommand) mvin_cmd := DontCare mvin_cmd.inst.funct := LOAD_CMD mvin_cmd.rs1 := 0.U // dram_addr mvin_cmd.rs2 := 0.U // mvin_cmd_rs2 // Inputs and outputs io.req.ready := state === idle && !command_p.io.busy io.idle := state === idle && !command_p.io.busy io.loop_id := req.loop_id command_p.io.in.valid := state =/= idle && !io.wait_for_prev_loop && (req.dram_addr =/= 0.U) command_p.io.in.bits.cmd := Mux(state === config, config_cmd, mvin_cmd) command_p.io.in.bits.dram_addr := dram_addr command_p.io.in.bits.spad_addr := spad_addr command_p.io.in.bits.I := I command_p.io.in.bits.K := K command_p.io.out.ready := io.cmd.ready && !io.rob_overloaded io.cmd.valid := command_p.io.out.valid && !io.rob_overloaded io.cmd.bits := command_p.io.out.bits.cmd when (command_p.io.out.bits.cmd.inst.funct === LOAD_CMD) { val o = command_p.io.out.bits io.cmd.bits.rs1 := o.dram_addr val mvin_cmd_rs2 = Wire(mvin_rs2_t.cloneType) mvin_cmd_rs2 := DontCare mvin_cmd_rs2.num_rows := (o.I >> req.downsample).asUInt mvin_cmd_rs2.num_cols := o.K.asUInt mvin_cmd_rs2.local_addr := cast_to_sp_addr(mvin_cmd_rs2.local_addr, o.spad_addr) io.cmd.bits.rs2 := mvin_cmd_rs2.asUInt } // Sending outputs when(req.dram_addr === 0.U){ state := idle }.elsewhen(command_p.io.in.fire) { when (state === config) { state := ld }.otherwise { val b_it = Mux(req.trans_input_3120, max_chs_per_mvin.asUInt, 1.U) val ich_it = Mux(req.trans_input_3120, 1.U, max_chs_per_mvin.asUInt) val next_ich = sFloorAdd(ich, ich_it, ichs.zext, 0.S) val next_icol = sFloorAdd(icol, I.asUInt, (icols_unpadded +& undilated(rpad)).zext, 0.S-&undilated(lpad).zext, next_ich === 0.S) val next_irow = sFloorAdd(irow, 1.U << req.downsample, (irows_unpadded +& undilated(dpad)).zext, 0.S-&undilated(upad).zext, next_icol === 0.S-&undilated(lpad).zext && next_ich === 0.S) val next_b = sFloorAdd(b, b_it, batches.zext, 0.S, next_irow === 0.S-&undilated(upad).zext && next_icol === 0.S-&undilated(lpad).zext && next_ich === 0.S) ich := next_ich icol := next_icol irow := next_irow b := next_b state := Mux(next_b === 0.S && next_irow === 0.S-&undilated(upad).zext && next_icol === 0.S-&undilated(lpad).zext && next_ich === 0.S, idle, ld) } } // Accepting requests when (io.req.fire) { req := io.req.bits state := config b := 0.S irow := 0.S -& ((io.req.bits.inner_bounds.upad +& io.req.bits.input_dilated) >> io.req.bits.input_dilated).zext icol := 0.S -& ((io.req.bits.inner_bounds.lpad +& io.req.bits.input_dilated) >> io.req.bits.input_dilated).zext ich := 0.S } } class LoopConvLdWeightReq(val coreMaxAddrBits: Int, val large_iterator_bitwidth: Int, val small_iterator_bitwidth: Int, val tiny_iterator_bitwidth: Int, val max_addr: Int, val concurrent_loops: Int) extends Bundle { val outer_bounds = new LoopConvOuterBounds(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val inner_bounds = new LoopConvInnerBounds(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val derived_params = new LoopConvDerivedParams(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val addr_end = UInt(log2Up(max_addr+1).W) val dram_addr = UInt(coreMaxAddrBits.W) val trans_weight_1203 = Bool() val trans_weight_0132 = Bool() val dw = Bool() val loop_id = UInt(log2Up(concurrent_loops).W) } class LoopConvLdWeight(block_size: Int, coreMaxAddrBits: Int, large_iterator_bitwidth: Int, small_iterator_bitwidth: Int, tiny_iterator_bitwidth: Int, max_addr: Int, input_w: Int, max_block_len: Int, concurrent_loops: Int, latency: Int, config_mvin_rs1_t: ConfigMvinRs1, mvin_rs2_t: MvinRs2)(implicit p: Parameters) extends Module { val MVIN_SCALE_IDENTITY = 0x3f800000.U // TODO get this from configs somehow val io = IO(new Bundle { val req = Flipped(Decoupled(new LoopConvLdWeightReq(coreMaxAddrBits, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth, max_addr, concurrent_loops))) val cmd = Decoupled(Output(new RoCCCommand)) val idle = Output(Bool()) val rob_overloaded = Input(Bool()) val wait_for_prev_loop = Input(Bool()) val loop_id = Output(UInt(log2Up(concurrent_loops).W)) }) object State extends ChiselEnum { val idle, config, ld = Value } import State._ val state = RegInit(idle) val req = Reg(new LoopConvLdWeightReq(coreMaxAddrBits, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth, max_addr, concurrent_loops)) import req.outer_bounds._ import req.inner_bounds._ import req.derived_params._ // Derived parameters val max_chs_per_mvin = { val max_ochs_per_mvin = Mux(ochs < (max_block_len * block_size).U, ochs, (max_block_len * block_size).U) val max_kchs_per_mvin = Mux(kchs < (max_block_len * block_size).U, kchs, (max_block_len * block_size).U) Mux(req.trans_weight_0132, max_kchs_per_mvin, max_ochs_per_mvin) } val B_rows = Mux(req.trans_weight_0132, in_channels_per_bank * kcols * krows * ochs, out_channels_per_bank * kcols * krows * kchs) val addr_start = req.addr_end - B_rows val dram_stride = MuxCase(weight_stride, Seq( req.dw -> 1.U, req.trans_weight_1203 -> (kernel_dim * kernel_dim * out_channels), req.trans_weight_0132 -> in_channels )) * (input_w/8).U // Iterators val och = Reg(UInt(large_iterator_bitwidth.W)) val krow = Reg(UInt(tiny_iterator_bitwidth.W)) val kcol = Reg(UInt(tiny_iterator_bitwidth.W)) val kch = Reg(UInt(large_iterator_bitwidth.W)) // Addresses val dram_offset = MuxCase(((krow*kernel_dim*in_channels +& kcol*in_channels +& kch) * weight_stride +& och) * (input_w/8).U, Seq( req.dw -> (krow * kernel_dim +& kcol) * (input_w/8).U, req.trans_weight_1203 -> (((kch*kernel_dim*kernel_dim +& krow*kernel_dim +& kcol) * out_channels +& och) * (input_w/8).U), req.trans_weight_0132 -> (((krow*kernel_dim*out_channels +& kcol*out_channels +& och) * in_channels +& kch) * (input_w/8).U) )) val dram_addr = req.dram_addr + LoopConv.castDramOffset(dram_offset) val spad_addr = Mux(req.trans_weight_0132, // The width expansions are added here solely to prevent Verilator's "WIDTH" warnings, despite making the code uglier addr_start + (kch / block_size.U(kch.getWidth.W)) * krows * kcols * ochs + krow * kcols * ochs + kcol * ochs + och, addr_start + (och / block_size.U(och.getWidth.W)) * krows * kcols * kchs + krow * kcols * kchs + kcol * kchs + kch) // Sizes val J = Mux(req.trans_weight_0132, Mux(kchs - kch > max_chs_per_mvin, max_chs_per_mvin, kchs - kch), Mux(ochs - och > max_chs_per_mvin, max_chs_per_mvin, ochs - och)) val K = Mux(req.trans_weight_0132, Mux(ochs - och > block_size.U, block_size.U, ochs - och), Mux(kchs - kch > block_size.U, block_size.U, kchs - kch)) class RoCCCommandWithAddr extends Bundle { val cmd = new RoCCCommand val dram_addr = UInt() val spad_addr = UInt() val K = UInt() val J = UInt() } val command_p = Module(new Pipeline[RoCCCommandWithAddr](new RoCCCommandWithAddr, latency)()) // Commands val config_cmd = Wire(new RoCCCommand) config_cmd := DontCare config_cmd.inst.funct := CONFIG_CMD val config_cmd_rs1 = Wire(config_mvin_rs1_t.cloneType) config_cmd_rs1 := DontCare config_cmd_rs1.scale := MVIN_SCALE_IDENTITY config_cmd_rs1.stride := req.derived_params.weight_spad_stride config_cmd_rs1.pixel_repeats := 1.U config_cmd_rs1.state_id := 1.U config_cmd_rs1.shrink := 0.U config_cmd_rs1._unused := 1.U config_cmd.rs1 := config_cmd_rs1.asUInt config_cmd.rs2 := dram_stride val mvin_cmd = Wire(new RoCCCommand) mvin_cmd := DontCare mvin_cmd.inst.funct := LOAD2_CMD mvin_cmd.rs1 := 0.U // dram_addr mvin_cmd.rs2 := 0.U // mvin_cmd_rs2 // Inputs and outputs io.req.ready := state === idle && !command_p.io.busy io.idle := state === idle && !command_p.io.busy io.loop_id := req.loop_id command_p.io.in.valid := state =/= idle && !io.wait_for_prev_loop && (req.dram_addr =/= 0.U) command_p.io.in.bits.cmd := Mux(state === config, config_cmd, mvin_cmd) command_p.io.in.bits.dram_addr := dram_addr command_p.io.in.bits.spad_addr := spad_addr command_p.io.in.bits.K := K command_p.io.in.bits.J := J command_p.io.out.ready := io.cmd.ready && !io.rob_overloaded io.cmd.valid := command_p.io.out.valid && !io.rob_overloaded io.cmd.bits := command_p.io.out.bits.cmd when (command_p.io.out.bits.cmd.inst.funct === LOAD2_CMD) { val o = command_p.io.out.bits io.cmd.bits.rs1 := o.dram_addr val mvin_cmd_rs2 = Wire(mvin_rs2_t.cloneType) mvin_cmd_rs2 := DontCare mvin_cmd_rs2.num_rows := o.K mvin_cmd_rs2.num_cols := o.J mvin_cmd_rs2.local_addr := cast_to_sp_addr(mvin_cmd_rs2.local_addr, o.spad_addr) io.cmd.bits.rs2 := mvin_cmd_rs2.asUInt } // Sending outputs when(req.dram_addr === 0.U){ state := idle }.elsewhen(command_p.io.in.fire) { when (state === config) { state := ld }.otherwise { val och_it = Mux(req.trans_weight_0132, block_size.U, max_chs_per_mvin) val kch_it = Mux(req.trans_weight_0132, max_chs_per_mvin, block_size.U) val next_kch = floorAdd(kch, kch_it, kchs) val next_kcol = floorAdd(kcol, 1.U, kcols, next_kch === 0.U) val next_krow = floorAdd(krow, 1.U, krows, next_kcol === 0.U && next_kch === 0.U) val next_och = floorAdd(och, och_it, ochs, next_krow === 0.U && next_kcol === 0.U && next_kch === 0.U) kch := next_kch kcol := next_kcol krow := next_krow och := next_och state := Mux(next_och === 0.U && next_krow === 0.U && next_kcol === 0.U && next_kch === 0.U, idle, ld) } } // Accepting requests when (io.req.fire) { req := io.req.bits state := config kch := 0.U kcol := 0.U krow := 0.U och := 0.U } } class LoopConvExecuteReq(val large_iterator_bitwidth: Int, val small_iterator_bitwidth: Int, val tiny_iterator_bitwidth: Int, val max_addr: Int, val max_acc_addr: Int, val concurrent_loops: Int) extends Bundle { val outer_bounds = new LoopConvOuterBounds(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val inner_bounds = new LoopConvInnerBounds(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val derived_params = new LoopConvDerivedParams(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val a_addr_start = UInt(log2Up(max_addr).W) val b_addr_end = UInt(log2Up(max_addr+1).W) val c_addr_start = UInt(log2Up(max_acc_addr).W) val wrot180 = Bool() val downsample = Bool() val max_pixels_per_row = UInt(small_iterator_bitwidth.W) val input_dilated = Bool() val trans_weight_0132 = Bool() val trans_input_3120 = Bool() val loop_id = UInt(log2Up(concurrent_loops).W) } class LoopConvExecute(block_size: Int, large_iterator_bitwidth: Int, small_iterator_bitwidth: Int, tiny_iterator_bitwidth: Int, max_addr: Int, max_acc_addr: Int, concurrent_loops: Int, latency: Int, config_ex_rs1_t: ConfigExRs1, preload_rs1_t: PreloadRs, preload_rs2_t: PreloadRs, compute_rs1_t: ComputeRs, compute_rs2_t: ComputeRs)(implicit p: Parameters) extends Module { val io = IO(new Bundle { val req = Flipped(Decoupled(new LoopConvExecuteReq(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth, max_addr, max_acc_addr, concurrent_loops))) val cmd = Decoupled(Output(new RoCCCommand)) val lda_completed = Input(Bool()) val ldb_completed = Input(Bool()) val ldd_completed = Input(Bool()) val idle = Output(Bool()) val rob_overloaded = Input(Bool()) val loop_id = Output(UInt(log2Up(concurrent_loops).W)) }) object State extends ChiselEnum { val idle, config, pre, comp = Value } import State._ val state = RegInit(idle) val req = Reg(new LoopConvExecuteReq(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth, max_addr, max_acc_addr, concurrent_loops)) import req.outer_bounds._ import req.inner_bounds._ import req.derived_params._ def undilated(x: UInt): UInt = (x +& req.input_dilated) >> req.input_dilated // Derived parameters val B_rows = Mux(req.trans_weight_0132, in_channels_per_bank * kcols * krows * ochs, out_channels_per_bank * kcols * krows * kchs) val a_addr_start = req.a_addr_start val b_addr_start = req.b_addr_end - B_rows val c_addr_start = /*(BigInt(3) << 30).U |*/ req.c_addr_start // Iterators val och = Reg(UInt(large_iterator_bitwidth.W)) val krow = Reg(UInt(tiny_iterator_bitwidth.W)) val kcol = Reg(UInt(tiny_iterator_bitwidth.W)) val kch = Reg(UInt(large_iterator_bitwidth.W)) val b = Reg(UInt(large_iterator_bitwidth.W)) val orow = Reg(UInt(small_iterator_bitwidth.W)) val ocol = Reg(UInt(small_iterator_bitwidth.W)) // TODO kernel-dilation and input-dilation can never be activated at the same time, so we can optimize out some multiplications by kernel_dilation val skip_iteration = state >= pre && req.input_dilated && (((krow * kernel_dilation +& orow -& upad)(0) & req.input_dilated).asBool || ((kcol * kernel_dilation +& ocol -& lpad)(0) & req.input_dilated).asBool) val pixels = Mux(kcols - kcol > req.max_pixels_per_row, req.max_pixels_per_row, kcols - kcol) val irow = undilated(orow * stride +& krow * kernel_dilation) val icol = undilated(ocol * stride +& kcol * kernel_dilation) val I = Mux(req.trans_input_3120, Mux(batches - b > block_size.U, block_size.U, batches - b), undilated(Mux(ocols - ocol > (block_size.U << req.input_dilated).asUInt, (block_size.U << req.input_dilated).asUInt, ocols - ocol))) val J = Mux(ochs - och > block_size.U, block_size.U, ochs - och) val K = pixels * Mux(kchs - kch > block_size.U, block_size.U, kchs - kch) // Addresses val a_addr = Mux(req.trans_input_3120, a_addr_start +& (b / block_size.U) * input_spad_stride +& kch * (irows >> req.downsample) * (icols >> req.downsample) +& (irow >> req.downsample) * (icols >> req.downsample) +& (icol >> req.downsample), a_addr_start +& (kch / block_size.U(kch.getWidth.W)) * input_spad_stride +& b * (irows >> req.downsample) * (icols >> req.downsample) +& (irow >> req.downsample) * (icols >> req.downsample) +& (icol >> req.downsample)) // val c_addr = Mux(ex_overwrite && krow === 0.U && kcol === 0.U && kch === 0.U, d_addr_start, c_addr_start) +& // (och / block_size.U) * batches * orows * ocols +& b * orows * ocols +& orow * ocols +& ocol // The width expansions are added here solely to prevent Verilator's "WIDTH" warnings, despite making the code uglier val c_addr = c_addr_start +& (och / block_size.U(och.getWidth.W)) * batches * orows * ocols +& b * orows * ocols +& orow * ocols +& ocol // val new_weights = b === 0.U && orow === 0.U && ocol === 0.U val new_weights = Reg(Bool()) val krow_rot = Mux(req.wrot180, krows - krow - 1.U, krow) val kcol_rot = Mux(req.wrot180, kcols - kcol - 1.U, kcol) val b_addr = Mux(req.trans_weight_0132, b_addr_start +& (kch / block_size.U(och.getWidth.W)) * krows * kcols * ochs +& krow_rot * kcols * ochs +& kcol_rot * ochs +& och, b_addr_start +& (och / block_size.U(och.getWidth.W)) * krows * kcols * kchs +& krow_rot * kcols * kchs +& kcol_rot * kchs +& kch) class RoCCCommandWithAddr extends Bundle { val cmd = new RoCCCommand val a_addr = UInt() val b_addr = UInt() val c_addr = UInt() val I = UInt() val J = UInt() val K = UInt() val new_weights = Bool() } val command_p = Module(new Pipeline[RoCCCommandWithAddr](new RoCCCommandWithAddr, latency)()) // Commands val config_cmd = Wire(new RoCCCommand) config_cmd := DontCare config_cmd.inst.funct := CONFIG_CMD val config_cmd_rs1 = Wire(config_ex_rs1_t.cloneType) config_cmd_rs1 := DontCare config_cmd_rs1.a_stride := (irows * icols).asUInt config_cmd_rs1.set_only_strides := 1.U config_cmd_rs1.cmd_type := 0.U val config_cmd_rs2 = Wire(new ConfigExRs2) config_cmd_rs2 := DontCare config_cmd_rs2.c_stride := (orows * ocols).asUInt config_cmd.rs1 := config_cmd_rs1.asUInt config_cmd.rs2 := config_cmd_rs2.asUInt val pre_cmd = Wire(new RoCCCommand) // preload pre_cmd := DontCare pre_cmd.inst.funct := PRELOAD_CMD pre_cmd.rs1 := 0.U//(K << 48) | (J << 32) | pre_addr pre_cmd.rs2 := 0.U//(I << 48) | (J << 32) | c_addr val comp_cmd = Wire(new RoCCCommand()) // compute.preloaded comp_cmd := DontCare comp_cmd.inst.funct := Mux(new_weights, COMPUTE_AND_FLIP_CMD, COMPUTE_AND_STAY_CMD) comp_cmd.rs1 := 0.U//(I << 48) | (K << 32) | a_addr comp_cmd.rs2 := 0.U//(I << 48) | (J << 32) | GARBAGE_ADDR val ld_ahead = io.lda_completed && io.ldb_completed && io.ldd_completed // Inputs and outputs io.req.ready := state === idle && !command_p.io.busy io.idle := state === idle && !command_p.io.busy io.loop_id := req.loop_id command_p.io.in.valid := state =/= idle && !skip_iteration && ld_ahead command_p.io.in.bits.cmd := MuxCase(config_cmd, Seq((state === pre) -> pre_cmd, (state === comp) -> comp_cmd)) command_p.io.in.bits.a_addr := a_addr command_p.io.in.bits.b_addr := b_addr command_p.io.in.bits.c_addr := c_addr command_p.io.in.bits.I := I command_p.io.in.bits.J := J command_p.io.in.bits.K := K command_p.io.in.bits.new_weights := new_weights command_p.io.out.ready := io.cmd.ready && !io.rob_overloaded io.cmd.valid := command_p.io.out.valid && !io.rob_overloaded io.cmd.bits := command_p.io.out.bits.cmd when (command_p.io.out.bits.cmd.inst.funct === PRELOAD_CMD) { val o = command_p.io.out.bits val pre_cmd_rs1 = Wire(preload_rs1_t.cloneType) pre_cmd_rs1 := DontCare pre_cmd_rs1.num_rows := o.K.asUInt pre_cmd_rs1.num_cols := o.J.asUInt pre_cmd_rs1.local_addr := Mux(o.new_weights, cast_to_sp_addr(pre_cmd_rs1.local_addr, o.b_addr), garbage_addr(pre_cmd_rs1.local_addr)) val pre_cmd_rs2 = Wire(preload_rs2_t.cloneType) pre_cmd_rs2 := DontCare pre_cmd_rs2.num_rows := o.I.asUInt pre_cmd_rs2.num_cols := o.J.asUInt pre_cmd_rs2.local_addr := cast_to_acc_addr(pre_cmd_rs2.local_addr, o.c_addr, accumulate = true.B, read_full = false.B) io.cmd.bits.rs1 := pre_cmd_rs1.asUInt io.cmd.bits.rs2 := pre_cmd_rs2.asUInt }.elsewhen(command_p.io.out.bits.cmd.inst.funct =/= CONFIG_CMD) { val o = command_p.io.out.bits val comp_cmd_rs1 = Wire(compute_rs1_t.cloneType) comp_cmd_rs1 := DontCare comp_cmd_rs1.num_rows := o.I.asUInt comp_cmd_rs1.num_cols := o.K.asUInt comp_cmd_rs1.local_addr := cast_to_sp_addr(comp_cmd_rs1.local_addr, o.a_addr) val comp_cmd_rs2 = Wire(compute_rs2_t.cloneType) comp_cmd_rs2 := DontCare comp_cmd_rs2.num_rows := o.I.asUInt comp_cmd_rs2.num_cols := o.J.asUInt comp_cmd_rs2.local_addr := garbage_addr(comp_cmd_rs2.local_addr) io.cmd.bits.rs1 := comp_cmd_rs1.asUInt io.cmd.bits.rs2 := comp_cmd_rs2.asUInt } // Updating "new_weights" when (state === comp && command_p.io.in.fire) { new_weights := false.B } // Sending outputs when (command_p.io.in.fire || skip_iteration) { when (state === config) { state := pre }.elsewhen (state === pre) { state := comp }.otherwise { val b_it = Mux(req.trans_input_3120, block_size.U, 1.U) val ocol_it = Mux(skip_iteration || req.trans_input_3120, 1.U, block_size.U << req.input_dilated).asUInt val next_ocol = floorAdd(ocol, ocol_it, ocols) val next_orow = floorAdd(orow, 1.U, orows, next_ocol === 0.U) val next_b = floorAdd(b, b_it, batches, next_orow === 0.U && next_ocol === 0.U) val next_kch = floorAdd(kch, block_size.U, kchs, next_b === 0.U && next_orow === 0.U && next_ocol === 0.U) val next_kcol = floorAdd(kcol, req.max_pixels_per_row, kcols, next_kch === 0.U && next_b === 0.U && next_orow === 0.U && next_ocol === 0.U) val next_krow = floorAdd(krow, 1.U, krows, next_kcol === 0.U && next_kch === 0.U && next_b === 0.U && next_orow === 0.U && next_ocol === 0.U) val next_och = floorAdd(och, block_size.U, ochs, next_krow === 0.U && next_kcol === 0.U && next_kch === 0.U && next_b === 0.U && next_orow === 0.U && next_ocol === 0.U) ocol := next_ocol orow := next_orow b := next_b kch := next_kch kcol := next_kcol krow := next_krow och := next_och when (next_b === 0.U && next_orow === 0.U && next_ocol === 0.U) { new_weights := true.B } state := Mux(next_och === 0.U && next_krow === 0.U && next_kcol === 0.U && next_kch === 0.U && next_b === 0.U && next_orow === 0.U && next_ocol === 0.U, idle, pre) } } // Accepting requests when (io.req.fire) { req := io.req.bits state := Mux(io.req.bits.trans_input_3120, config, pre) b := 0.U orow := 0.U ocol := 0.U och := 0.U krow := 0.U kcol := 0.U kch := 0.U new_weights := true.B } } class LoopConvStReq(val coreMaxAddrBits: Int, val large_iterator_bitwidth: Int, val small_iterator_bitwidth: Int, val tiny_iterator_bitwidth: Int, val max_acc_addr: Int, val concurrent_loops: Int) extends Bundle { val outer_bounds = new LoopConvOuterBounds(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val inner_bounds = new LoopConvInnerBounds(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val derived_params = new LoopConvDerivedParams(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val addr_start = UInt(log2Up(max_acc_addr).W) val dram_addr = UInt(coreMaxAddrBits.W) val no_pool = Bool() val activation = UInt(2.W) // TODO magic number val trans_output_1203 = Bool() val loop_id = UInt(log2Up(concurrent_loops).W) } class LoopConvSt(block_size: Int, coreMaxAddrBits: Int, large_iterator_bitwidth: Int, small_iterator_bitwidth: Int, tiny_iterator_bitwidth: Int, max_acc_addr: Int, input_w: Int, concurrent_loops: Int, latency: Int, config_mvout_rs2_t: ConfigMvoutRs2, mvout_rs2_t: MvoutRs2)(implicit p: Parameters) extends Module { val ACC_SCALE_NO_CHANGE = ~(0.U(32.W)) // TODO get this from ISA description somehow val io = IO(new Bundle { val req = Flipped(Decoupled(new LoopConvStReq(coreMaxAddrBits, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth: Int, max_acc_addr, concurrent_loops))) val cmd = Decoupled(Output(new RoCCCommand)) val ex_completed = Input(Bool()) val idle = Output(Bool()) val rob_overloaded = Input(Bool()) val loop_id = Output(UInt(log2Up(concurrent_loops).W)) }) object State extends ChiselEnum { val idle, st, pre_pool_config, pool, post_pool_config = Value } import State._ val state = RegInit(idle) val req = Reg(new LoopConvStReq(coreMaxAddrBits, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth: Int, max_acc_addr, concurrent_loops)) import req.outer_bounds._ import req.inner_bounds._ import req.derived_params._ val acc_addr_start = req.addr_start // Derived parameters val skip = req.dram_addr === 0.U // Iterators val b = Reg(UInt(large_iterator_bitwidth.W)) val orow = Reg(UInt(small_iterator_bitwidth.W)) val ocol = Reg(UInt(small_iterator_bitwidth.W)) val och = Reg(UInt(large_iterator_bitwidth.W)) // Addresses val dram_offset = Mux(req.trans_output_1203, ((orow*out_col_dim*batch_size +& ocol*batch_size +& b) * out_channels +& och) * (input_w/8).U, ((b*out_row_dim*out_col_dim +& orow*out_col_dim +& ocol) * out_stride +& och) * (input_w/8).U) val dram_addr = req.dram_addr + LoopConv.castDramOffset(dram_offset) val spad_addr = acc_addr_start +& (och / block_size.U(och.getWidth.W)) * batches * orows * ocols +& b * orows * ocols +& orow * ocols +& ocol val pool_dram_addr = req.dram_addr + ((b * pool_out_col_dim * pool_out_row_dim) * out_stride + och) * (input_w/8).U val pool_spad_addr = acc_addr_start +& (och / block_size.U(och.getWidth.W)) * batches * orows * ocols +& b * orows * ocols // Sizes val I = Mux(ocols - ocol > block_size.U, block_size.U, ocols - ocol) val J = Mux(ochs - och > block_size.U, block_size.U, ochs - och) val channels = J class RoCCCommandWithAddr extends Bundle { val cmd = new RoCCCommand val dram_addr = UInt() val spad_addr = UInt() val pool_dram_addr = UInt() val pool_spad_addr = UInt() val channels = UInt() val is_pool = Bool() val I = UInt() val J = UInt() } val command_p = Module(new Pipeline[RoCCCommandWithAddr](new RoCCCommandWithAddr, latency)()) // Commands val mvout_cmd = Wire(new RoCCCommand) mvout_cmd := DontCare mvout_cmd.inst.funct := STORE_CMD mvout_cmd.rs1 := 0.U // dram_addr mvout_cmd.rs2 := 0.U // mvout_cmd_rs2 val pre_pool_config_cmd = Wire(new RoCCCommand) pre_pool_config_cmd := DontCare pre_pool_config_cmd.inst.funct := CONFIG_CMD val pre_pool_config_cmd_rs1 = Wire(new ConfigMvoutRs1) pre_pool_config_cmd_rs1 := DontCare pre_pool_config_cmd_rs1.ocols := ocols pre_pool_config_cmd_rs1.orows := orows pre_pool_config_cmd_rs1.pocols := pocols pre_pool_config_cmd_rs1.porows := porows pre_pool_config_cmd_rs1.pool_out_dim := pool_out_col_dim pre_pool_config_cmd_rs1.lpad := plpad pre_pool_config_cmd_rs1.upad := pupad pre_pool_config_cmd_rs1.pool_size := pool_size pre_pool_config_cmd_rs1.pool_stride := pool_stride pre_pool_config_cmd_rs1.activation := req.activation pre_pool_config_cmd_rs1.cmd_type := CONFIG_STORE pre_pool_config_cmd.rs1 := pre_pool_config_cmd_rs1.asUInt val pre_pool_config_cmd_rs2 = Wire(config_mvout_rs2_t.cloneType) pre_pool_config_cmd_rs2 := DontCare pre_pool_config_cmd_rs2.acc_scale := ACC_SCALE_NO_CHANGE pre_pool_config_cmd_rs2.stride := out_stride * (input_w / 8).U pre_pool_config_cmd.rs2 := pre_pool_config_cmd_rs2.asUInt val post_pool_config_cmd = Wire(new RoCCCommand) post_pool_config_cmd := DontCare post_pool_config_cmd.inst.funct := CONFIG_CMD val post_pool_config_cmd_rs1 = Wire(new ConfigMvoutRs1) post_pool_config_cmd_rs1 := DontCare post_pool_config_cmd_rs1.activation := req.activation post_pool_config_cmd_rs1.cmd_type := CONFIG_STORE post_pool_config_cmd.rs1 := post_pool_config_cmd_rs1.asUInt val post_pool_config_cmd_rs2 = Wire(config_mvout_rs2_t.cloneType) post_pool_config_cmd_rs2 := DontCare post_pool_config_cmd_rs2.acc_scale := ACC_SCALE_NO_CHANGE post_pool_config_cmd_rs2.stride := out_stride * (input_w / 8).U post_pool_config_cmd.rs2 := post_pool_config_cmd_rs2.asUInt val pool_cmd = Wire(new RoCCCommand) pool_cmd := DontCare pool_cmd.inst.funct := STORE_CMD pool_cmd.rs1 := 0.U//pool_dram_addr pool_cmd.rs2 := 0.U//(channels << 32.U) | pool_spad_addr // Inputs and outputs io.req.ready := state === idle && !command_p.io.busy io.idle := state === idle && !command_p.io.busy io.loop_id := req.loop_id command_p.io.in.valid := state =/= idle && !skip && io.ex_completed command_p.io.in.bits.cmd := MuxLookup(state.asUInt, mvout_cmd)(Seq( pre_pool_config.asUInt -> pre_pool_config_cmd, pool.asUInt -> pool_cmd, post_pool_config.asUInt -> post_pool_config_cmd) ) command_p.io.in.bits.is_pool := state === pool command_p.io.in.bits.dram_addr := dram_addr command_p.io.in.bits.spad_addr := spad_addr command_p.io.in.bits.pool_spad_addr := pool_spad_addr command_p.io.in.bits.pool_dram_addr := pool_dram_addr command_p.io.in.bits.channels := channels command_p.io.in.bits.I := I command_p.io.in.bits.J := J command_p.io.out.ready := io.cmd.ready && !io.rob_overloaded io.cmd.valid := command_p.io.out.valid && !io.rob_overloaded io.cmd.bits := command_p.io.out.bits.cmd when (command_p.io.out.bits.cmd.inst.funct === STORE_CMD) { val o = command_p.io.out.bits when (o.is_pool) { val pool_mvout_cmd_rs2 = Wire(mvout_rs2_t.cloneType) pool_mvout_cmd_rs2 := DontCare pool_mvout_cmd_rs2.num_cols := o.channels pool_mvout_cmd_rs2.local_addr := cast_to_acc_addr(pool_mvout_cmd_rs2.local_addr, o.pool_spad_addr, accumulate = false.B, read_full = false.B) io.cmd.bits.rs1 := o.pool_dram_addr io.cmd.bits.rs2 := pool_mvout_cmd_rs2.asUInt } .otherwise { val mvout_cmd_rs2 = Wire(mvout_rs2_t.cloneType) mvout_cmd_rs2 := DontCare mvout_cmd_rs2.num_rows := o.I.asUInt mvout_cmd_rs2.num_cols := o.J.asUInt mvout_cmd_rs2.local_addr := cast_to_acc_addr(mvout_cmd_rs2.local_addr, o.spad_addr, accumulate = false.B, read_full = false.B) io.cmd.bits.rs1 := o.dram_addr io.cmd.bits.rs2 := mvout_cmd_rs2.asUInt } } // Sending outputs when (skip) { state := idle }.elsewhen(command_p.io.in.fire) { when (req.no_pool) { val next_och = floorAdd(och, block_size.U, ochs) val next_ocol = floorAdd(ocol, block_size.U, ocols, next_och === 0.U) val next_orow = floorAdd(orow, 1.U, orows, next_ocol === 0.U && next_och === 0.U) val next_b = floorAdd(b, 1.U, batches, next_orow === 0.U && next_ocol === 0.U && next_och === 0.U) och := next_och ocol := next_ocol orow := next_orow b := next_b state := Mux(next_b === 0.U && next_orow === 0.U && next_ocol === 0.U && next_och === 0.U, idle, st) }.elsewhen(state === pre_pool_config) { state := pool }.elsewhen(state === post_pool_config) { state := idle }.otherwise { val next_och = floorAdd(och, block_size.U, ochs) val next_b = floorAdd(b, 1.U, batches, next_och === 0.U) och := next_och b := next_b state := Mux(next_b === 0.U && next_och === 0.U, post_pool_config, pool) } } // Accepting requests when (io.req.fire) { req := io.req.bits state := Mux(io.req.bits.no_pool, st, pre_pool_config) b := 0.U orow := 0.U ocol := 0.U och := 0.U } } class LoopConvState(val block_size: Int, val large_iterator_bitwidth: Int, val small_iterator_bitwidth: Int, val tiny_iterator_bitwidth: Int, val coreMaxAddrBits: Int, val max_addr: Int, val max_acc_addr: Int) extends Bundle { val outer_bounds = new LoopConvOuterBounds(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val inner_bounds = new LoopConvInnerBounds(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val bias_dram_addr = UInt(coreMaxAddrBits.W) val weights_dram_addr = UInt(coreMaxAddrBits.W) val input_dram_addr = UInt(coreMaxAddrBits.W) val output_dram_addr = UInt(coreMaxAddrBits.W) val no_bias = Bool() val wrot180 = Bool() val no_pool = Bool() val downsample = Bool() val input_dilated = Bool() val activation = UInt(2.W) // TODO magic number val trans_output_1203 = Bool() val trans_weight_1203 = Bool() val trans_weight_0132 = Bool() val trans_input_3120 = Bool() val dw = Bool() val max_pixels_per_row = UInt(small_iterator_bitwidth.W) val a_ex_spad_id = UInt(2.W) val b_ex_spad_id = UInt(2.W) val configured = Bool() val running = Bool() val ld_bias_started = Bool() val ld_input_started = Bool() val ld_weights_started = Bool() val ex_started = Bool() val st_started = Bool() val ld_bias_completed = Bool() val ld_input_completed = Bool() val ld_weights_completed = Bool() val ex_completed = Bool() val st_completed = Bool() def all_completed(dummy: Int=0): Bool = ld_bias_completed && ld_input_completed && ld_weights_completed && ex_completed && st_completed val a_addr_start = UInt(log2Up(max_addr).W) val b_addr_end = UInt(log2Up(max_addr+1).W) def derived_params(dummy: Int=0): LoopConvDerivedParams = { import outer_bounds.{stride, kernel_dilation} import inner_bounds.{batches, pochs, orows, ocols, krows, kcols, upad, dpad, lpad, rpad, kchs} val result = Wire(new LoopConvDerivedParams(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth)) result.ochs := pochs val dilated_krows = krows + (kernel_dilation - 1.U)*(krows - 1.U) val dilated_kcols = kcols + (kernel_dilation - 1.U)*(kcols - 1.U) val irows_without_dilation = orows * stride +& dilated_krows -& 1.U val icols_without_dilation = ocols * stride +& dilated_kcols -& 1.U val irows_unpadded_without_dilation = irows_without_dilation -& upad -& dpad val icols_unpadded_without_dilation = icols_without_dilation -& lpad -& rpad def undilated(x: UInt): UInt = (x +& input_dilated) >> input_dilated val irows_unpadded = undilated(irows_unpadded_without_dilation) val icols_unpadded = undilated(icols_unpadded_without_dilation) result.irows := Mux(input_dilated, irows_unpadded +& undilated(upad) +& undilated(dpad), irows_without_dilation) result.icols := Mux(input_dilated, icols_unpadded +& undilated(lpad) +& undilated(rpad), icols_without_dilation) result.irows_unpadded := irows_unpadded result.icols_unpadded := icols_unpadded result.ichs := kchs result.out_channels_per_bank := result.ochs / block_size.U(result.ochs.getWidth.W) +& (result.ochs % block_size.U =/= 0.U) result.in_channels_per_bank := result.ichs / block_size.U(result.ochs.getWidth.W) +& (result.ichs % block_size.U =/= 0.U) result.bias_spad_stride := batches * orows * ocols result.input_spad_stride := Mux(trans_input_3120, result.ichs * (result.irows >> downsample) * (result.icols >> downsample), batches * (result.irows >> downsample) * (result.icols >> downsample)) result.weight_spad_stride := Mux(trans_weight_0132, krows * kcols * pochs, krows * kcols * kchs) // result.ex_overwrite := bias_dram_addr =/= 0.U && no_bias result } def reset(): Unit = { configured := false.B running := false.B ld_bias_started := false.B ld_input_started := false.B ld_weights_started := false.B ex_started := false.B st_started := false.B ld_bias_completed := false.B ld_input_completed := false.B ld_weights_completed := false.B ex_completed := false.B st_completed := false.B } } class LoopConv (block_size: Int, coreMaxAddrBits: Int, reservation_station_size: Int, max_lds: Int, max_exs: Int, max_sts: Int, max_addr: Int, max_acc_addr: Int, input_w: Int, acc_w: Int, dma_max_bytes: Int, config_mvin_rs1_t: ConfigMvinRs1, mvin_rs2_t: MvinRs2, config_mvout_rs2_t: ConfigMvoutRs2, mvout_rs2_t: MvoutRs2, config_ex_rs1_t: ConfigExRs1, preload_rs1_t: PreloadRs, preload_rs2_t: PreloadRs, compute_rs1_t: ComputeRs, compute_rs2_t: ComputeRs, has_training_convs: Boolean, has_max_pool: Boolean, has_first_layer_optimizations: Boolean, has_dw_convs: Boolean) (implicit p: Parameters) extends Module { val large_iterator_bitwidth = 16 val small_iterator_bitwidth = 16 // 8 val tiny_iterator_bitwidth = 16 // 4 val max_block_len = (dma_max_bytes / (block_size * (input_w / 8))) max 1 val max_block_len_acc = (dma_max_bytes / (block_size * (acc_w / 8))) max 1 val io = IO(new Bundle { val in = Flipped(Decoupled(new GemminiCmd(reservation_station_size))) val out = Decoupled(new GemminiCmd(reservation_station_size)) val ld_completed = Input(UInt(log2Up(reservation_station_size+1).W)) val st_completed = Input(UInt(log2Up(reservation_station_size+1).W)) val ex_completed = Input(UInt(log2Up(reservation_station_size+1).W)) val busy = Output(Bool()) }) // Create states val concurrent_loops = 2 val loops = Reg(Vec(concurrent_loops, new LoopConvState(block_size, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth, coreMaxAddrBits, max_addr, max_acc_addr))) val head_loop_id = RegInit(0.U(log2Up(concurrent_loops).W)) val tail_loop_id = (~head_loop_id).asUInt // This is the loop that we always try to configure if available val head_loop = loops(head_loop_id) val tail_loop = loops(tail_loop_id) val loop_configured = loops.map(_.configured).reduce(_ || _) val loop_being_configured_id = Mux(head_loop.configured, tail_loop_id, head_loop_id) val loop_being_configured = loops(loop_being_configured_id) // Create inner modules val latency = 2 val ld_bias = Module(new LoopConvLdBias(block_size, coreMaxAddrBits, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth, max_acc_addr, acc_w, max_block_len_acc, concurrent_loops, latency, config_mvin_rs1_t, mvin_rs2_t)) val ld_input = Module(new LoopConvLdInput(block_size, coreMaxAddrBits, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth, max_addr, input_w, max_block_len, concurrent_loops, latency, config_mvin_rs1_t, mvin_rs2_t)) val ld_weights = Module(new LoopConvLdWeight(block_size, coreMaxAddrBits, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth, max_addr, input_w, max_block_len, concurrent_loops, latency, config_mvin_rs1_t, mvin_rs2_t)) val ex = Module(new LoopConvExecute(block_size, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth, max_addr, max_acc_addr, concurrent_loops, latency, config_ex_rs1_t, preload_rs1_t, preload_rs2_t, compute_rs1_t, compute_rs2_t)) val st = Module(new LoopConvSt(block_size, coreMaxAddrBits, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth, max_acc_addr, input_w, concurrent_loops, latency, config_mvout_rs2_t, mvout_rs2_t)) // Create command queue val cmd = Queue(io.in) io.busy := cmd.valid || loop_configured // Create arbiter val arb = Module(new Arbiter(new RoCCCommand, 5)) arb.io.in(0) <> st.io.cmd arb.io.in(1) <> ex.io.cmd arb.io.in(2) <> ld_bias.io.cmd arb.io.in(3) <> ld_weights.io.cmd arb.io.in(4) <> ld_input.io.cmd val unrolled_cmd = arb.io.out // Create reservation station utilization counters val ld_utilization = RegInit(0.U(log2Up(max_lds+1).W)) val st_utilization = RegInit(0.U(log2Up(max_sts+1).W)) val ex_utilization = RegInit(0.U(log2Up(max_exs+1).W)) ld_utilization := ld_utilization +& (ld_bias.io.cmd.fire || ld_weights.io.cmd.fire || ld_input.io.cmd.fire) -& io.ld_completed st_utilization := st_utilization +& st.io.cmd.fire -& io.st_completed ex_utilization := ex_utilization +& ex.io.cmd.fire -& io.ex_completed assert(ld_utilization >= io.ld_completed, "ld utilization underflow") assert(st_utilization >= io.st_completed, "st utilization underflow") assert(ex_utilization >= io.ex_completed, "ex utilization underflow") // Wire up unrolled command output val is_loop_run_cmd = cmd.bits.cmd.inst.funct === LOOP_CONV_WS val is_loop_config_cmd = cmd.bits.cmd.inst.funct >= LOOP_CONV_WS_CONFIG_1 && cmd.bits.cmd.inst.funct <= LOOP_CONV_WS_CONFIG_6 val is_loop_cmd = is_loop_run_cmd || is_loop_config_cmd io.out.bits.cmd := Mux(loop_configured, unrolled_cmd.bits, cmd.bits.cmd) io.out.bits.cmd.status := cmd.bits.cmd.status // TODO This is not guaranteed to be the correct fix! We must fix this io.out.bits.rob_id := DontCare io.out.bits.from_matmul_fsm := Mux(loop_configured, false.B, cmd.bits.from_matmul_fsm) io.out.bits.from_conv_fsm := Mux(loop_configured, true.B, cmd.bits.from_conv_fsm) io.out.valid := Mux(loop_configured, unrolled_cmd.valid, cmd.valid && !is_loop_config_cmd && !is_loop_run_cmd) cmd.ready := Mux(is_loop_cmd, !loop_being_configured.configured, !loop_configured && io.out.ready) arb.io.out.ready := io.out.ready // Wire up waiting-for-loads signals val ex_is_waiting_for_loads = loops(ex.io.loop_id).ex_started && !loops(ex.io.loop_id).ex_completed && !(loops(ex.io.loop_id).ld_input_completed && loops(ex.io.loop_id).ld_weights_completed && loops(ex.io.loop_id).ld_bias_completed) ld_bias.io.wait_for_prev_loop := ex_is_waiting_for_loads && ld_bias.io.loop_id =/= ex.io.loop_id ld_weights.io.wait_for_prev_loop := ex_is_waiting_for_loads && ld_weights.io.loop_id =/= ex.io.loop_id ld_input.io.wait_for_prev_loop := ex_is_waiting_for_loads && ld_input.io.loop_id =/= ex.io.loop_id // Wire up overloaded signals ld_bias.io.rob_overloaded := ld_utilization >= max_lds.U ld_input.io.rob_overloaded := ld_utilization >= max_lds.U ld_weights.io.rob_overloaded := ld_utilization >= max_lds.U ex.io.rob_overloaded := ex_utilization >= max_exs.U st.io.rob_overloaded := st_utilization >= max_sts.U // Wire up iterator inputs ex.io.lda_completed := (ld_input.io.loop_id =/= ex.io.loop_id) || ld_input.io.idle ex.io.ldb_completed := (ld_weights.io.loop_id =/= ex.io.loop_id) || ld_weights.io.idle ex.io.ldd_completed := (ld_bias.io.loop_id =/= ex.io.loop_id) || ld_bias.io.idle st.io.ex_completed := (ex.io.loop_id =/= st.io.loop_id) || ex.io.idle // Create config registers when(cmd.valid && is_loop_cmd && !loop_being_configured.configured) { switch (cmd.bits.cmd.inst.funct) { is (LOOP_CONV_WS_CONFIG_1) { loop_being_configured.outer_bounds.out_channels := cmd.bits.cmd.rs1(63, 48) loop_being_configured.outer_bounds.in_channels := cmd.bits.cmd.rs1(47, 32) loop_being_configured.outer_bounds.in_row_dim := cmd.bits.cmd.rs1(31, 16) loop_being_configured.outer_bounds.batch_size := cmd.bits.cmd.rs1(15, 0) loop_being_configured.outer_bounds.padding := cmd.bits.cmd.rs2(63, 56) loop_being_configured.outer_bounds.stride := cmd.bits.cmd.rs2(55, 48) loop_being_configured.outer_bounds.out_col_dim := cmd.bits.cmd.rs2(47, 32) loop_being_configured.outer_bounds.pool_out_row_dim := cmd.bits.cmd.rs2(31, 16) loop_being_configured.outer_bounds.out_row_dim := cmd.bits.cmd.rs2(15, 0) } is (LOOP_CONV_WS_CONFIG_2) { loop_being_configured.outer_bounds.kernel_dim := cmd.bits.cmd.rs1(63, 48) loop_being_configured.outer_bounds.pool_out_col_dim := cmd.bits.cmd.rs1(47, 32) loop_being_configured.outer_bounds.pool_size := (if (!has_max_pool) 1.U else cmd.bits.cmd.rs1(31, 16)) loop_being_configured.outer_bounds.pool_stride := (if (!has_max_pool) 1.U else cmd.bits.cmd.rs1(15, 8)) loop_being_configured.outer_bounds.pool_padding := (if (!has_max_pool) 0.U else cmd.bits.cmd.rs1(7, 0)) loop_being_configured.inner_bounds.batches := cmd.bits.cmd.rs2(63, 48) loop_being_configured.inner_bounds.porows := cmd.bits.cmd.rs2(47, 32) loop_being_configured.inner_bounds.pocols := cmd.bits.cmd.rs2(31, 16) loop_being_configured.inner_bounds.pochs := cmd.bits.cmd.rs2(15, 0) } is (LOOP_CONV_WS_CONFIG_3) { loop_being_configured.inner_bounds.krows := cmd.bits.cmd.rs1(63, 48) loop_being_configured.inner_bounds.kcols := cmd.bits.cmd.rs1(47, 32) loop_being_configured.inner_bounds.kchs := cmd.bits.cmd.rs1(31, 16) loop_being_configured.inner_bounds.lpad := cmd.bits.cmd.rs1(15, 0) loop_being_configured.inner_bounds.rpad := cmd.bits.cmd.rs2(63, 48) loop_being_configured.inner_bounds.upad := cmd.bits.cmd.rs2(47, 32) loop_being_configured.inner_bounds.dpad := cmd.bits.cmd.rs2(31, 24) loop_being_configured.inner_bounds.plpad := cmd.bits.cmd.rs2(23, 16) loop_being_configured.outer_bounds.in_col_dim := cmd.bits.cmd.rs2(15, 0) } is (LOOP_CONV_WS_CONFIG_4) { loop_being_configured.inner_bounds.orows := cmd.bits.cmd.rs1(63, 48) loop_being_configured.inner_bounds.prad := cmd.bits.cmd.rs1(47, 32) loop_being_configured.inner_bounds.pupad := cmd.bits.cmd.rs1(31, 21) loop_being_configured.inner_bounds.pdpad := cmd.bits.cmd.rs1(20, 10) loop_being_configured.outer_bounds.kernel_dilation := cmd.bits.cmd.rs1(9, 0) loop_being_configured.inner_bounds.ocols := cmd.bits.cmd.rs2(15, 0) loop_being_configured.outer_bounds.in_stride := cmd.bits.cmd.rs2(63, 48) loop_being_configured.outer_bounds.weight_stride := cmd.bits.cmd.rs2(47, 32) loop_being_configured.outer_bounds.out_stride := cmd.bits.cmd.rs2(31, 16) } is (LOOP_CONV_WS_CONFIG_5) { loop_being_configured.weights_dram_addr := cmd.bits.cmd.rs1 loop_being_configured.output_dram_addr := cmd.bits.cmd.rs2 } is (LOOP_CONV_WS_CONFIG_6) { loop_being_configured.bias_dram_addr := cmd.bits.cmd.rs1 loop_being_configured.input_dram_addr := cmd.bits.cmd.rs2 } is (LOOP_CONV_WS) { loop_being_configured.no_bias := cmd.bits.cmd.rs1(0) // TODO we added a default value for max_pixels_per_row just to maintain backwards compatibility. we should deprecate and remove it later val config_max_pixels_per_row = cmd.bits.cmd.rs1(15, 8) loop_being_configured.max_pixels_per_row := Mux( !has_first_layer_optimizations.B || config_max_pixels_per_row === 0.U, 1.U, config_max_pixels_per_row) loop_being_configured.a_ex_spad_id := cmd.bits.cmd.rs1(19, 18) loop_being_configured.b_ex_spad_id := cmd.bits.cmd.rs1(17, 16) loop_being_configured.wrot180 := has_training_convs.B && cmd.bits.cmd.rs1(1) loop_being_configured.input_dilated := has_training_convs.B && cmd.bits.cmd.rs2(2) loop_being_configured.trans_output_1203 := has_training_convs.B && cmd.bits.cmd.rs1(2) loop_being_configured.trans_weight_1203 := has_training_convs.B && cmd.bits.cmd.rs1(3) loop_being_configured.trans_weight_0132 := has_training_convs.B && cmd.bits.cmd.rs1(4) loop_being_configured.trans_input_3120 := has_training_convs.B && cmd.bits.cmd.rs1(5) loop_being_configured.dw := has_dw_convs.B && cmd.bits.cmd.rs1(6) loop_being_configured.no_pool := !has_max_pool.B || cmd.bits.cmd.rs2(0) loop_being_configured.activation := cmd.bits.cmd.rs2(4,3) loop_being_configured.downsample := cmd.bits.cmd.rs2(1) loop_being_configured.configured := true.B // assert(!loop_being_configured.input_dilated || loop_being_configured.outer_bounds.stride === 1.U) // assert(!loop_being_configured.downsample || (loop_being_configured.outer_bounds.kernel_dim === 1.U && loop_being_configured.outer_bounds.stride === 2.U)) // TODO add the rest of the conditions that must be true for "downsample" to be enabled } } } // Wire up request signals val ld_bias_addr_start = RegInit(0.U(log2Up(max_acc_addr).W)) val ex_c_addr_start = RegInit(0.U(log2Up(max_acc_addr).W)) val st_addr_start = RegInit(0.U(log2Up(max_acc_addr).W)) val loop_requesting_ld_bias_id = Mux(head_loop.ld_bias_started, tail_loop_id, head_loop_id) val loop_requesting_ld_bias = loops(loop_requesting_ld_bias_id) ld_bias.io.req.bits.outer_bounds := loop_requesting_ld_bias.outer_bounds ld_bias.io.req.bits.inner_bounds := loop_requesting_ld_bias.inner_bounds ld_bias.io.req.bits.derived_params := loop_requesting_ld_bias.derived_params() ld_bias.io.req.bits.addr_start := ld_bias_addr_start ld_bias.io.req.bits.dram_addr := loop_requesting_ld_bias.bias_dram_addr ld_bias.io.req.bits.no_bias := loop_requesting_ld_bias.no_bias ld_bias.io.req.bits.loop_id := loop_requesting_ld_bias_id ld_bias.io.req.valid := !loop_requesting_ld_bias.ld_bias_started && loop_requesting_ld_bias.configured when (ld_bias.io.req.fire) { loop_requesting_ld_bias.running := true.B loop_requesting_ld_bias.ld_bias_started := true.B // when (loop_requesting_ld_bias.bias_dram_addr =/= 0.U) { when (loop_requesting_ld_bias.output_dram_addr =/= 0.U) { ld_bias_addr_start := floorAdd(ld_bias_addr_start, (max_acc_addr / concurrent_loops).U, max_acc_addr.U) } } val loop_requesting_ld_input_id = Mux(head_loop.ld_input_started, tail_loop_id, head_loop_id) val loop_requesting_ld_input = loops(loop_requesting_ld_input_id) ld_input.io.req.bits.outer_bounds := loop_requesting_ld_input.outer_bounds ld_input.io.req.bits.inner_bounds := loop_requesting_ld_input.inner_bounds ld_input.io.req.bits.derived_params := loop_requesting_ld_input.derived_params() ld_input.io.req.bits.addr_start := Mux(loop_requesting_ld_input.a_ex_spad_id === 0.U, loop_requesting_ld_input.a_addr_start, (loop_requesting_ld_input.a_ex_spad_id - 1.U) * (max_addr / concurrent_loops).U) ld_input.io.req.bits.dram_addr := loop_requesting_ld_input.input_dram_addr ld_input.io.req.bits.downsample := loop_requesting_ld_input.downsample ld_input.io.req.bits.max_pixels_per_row := loop_requesting_ld_input.max_pixels_per_row ld_input.io.req.bits.input_dilated := loop_requesting_ld_input.input_dilated ld_input.io.req.bits.trans_input_3120 := loop_requesting_ld_input.trans_input_3120 ld_input.io.req.bits.loop_id := loop_requesting_ld_input_id ld_input.io.req.valid := !loop_requesting_ld_input.ld_input_started && loop_requesting_ld_input.configured when (ld_input.io.req.fire) { loop_requesting_ld_input.running := true.B loop_requesting_ld_input.ld_input_started := true.B } val loop_requesting_ld_weights_id = Mux(head_loop.ld_weights_started, tail_loop_id, head_loop_id) val loop_requesting_ld_weights = loops(loop_requesting_ld_weights_id) ld_weights.io.req.bits.outer_bounds := loop_requesting_ld_weights.outer_bounds ld_weights.io.req.bits.inner_bounds := loop_requesting_ld_weights.inner_bounds ld_weights.io.req.bits.derived_params := loop_requesting_ld_weights.derived_params() ld_weights.io.req.bits.addr_end := Mux(loop_requesting_ld_weights.b_ex_spad_id === 0.U, loop_requesting_ld_weights.b_addr_end, (loop_requesting_ld_weights.b_ex_spad_id) * (max_addr / concurrent_loops).U) ld_weights.io.req.bits.dram_addr := loop_requesting_ld_weights.weights_dram_addr ld_weights.io.req.bits.trans_weight_1203 := loop_requesting_ld_weights.trans_weight_1203 ld_weights.io.req.bits.trans_weight_0132 := loop_requesting_ld_weights.trans_weight_0132 ld_weights.io.req.bits.dw := loop_requesting_ld_weights.dw ld_weights.io.req.bits.loop_id := loop_requesting_ld_weights_id ld_weights.io.req.valid := !loop_requesting_ld_weights.ld_weights_started && loop_requesting_ld_weights.configured when (ld_weights.io.req.fire) { loop_requesting_ld_weights.running := true.B loop_requesting_ld_weights.ld_weights_started := true.B } val loop_requesting_ex_id = Mux(head_loop.ex_started, tail_loop_id, head_loop_id) val loop_requesting_ex = loops(loop_requesting_ex_id) ex.io.req.bits.outer_bounds := loop_requesting_ex.outer_bounds ex.io.req.bits.inner_bounds := loop_requesting_ex.inner_bounds ex.io.req.bits.derived_params := loop_requesting_ex.derived_params() ex.io.req.bits.a_addr_start := Mux(loop_requesting_ex.a_ex_spad_id === 0.U, loop_requesting_ex.a_addr_start, (loop_requesting_ex.a_ex_spad_id - 1.U) * (max_addr / concurrent_loops).U) ex.io.req.bits.b_addr_end := Mux(loop_requesting_ex.b_ex_spad_id === 0.U, loop_requesting_ex.b_addr_end, (loop_requesting_ex.b_ex_spad_id) * (max_addr / concurrent_loops).U) ex.io.req.bits.c_addr_start := ex_c_addr_start ex.io.req.bits.wrot180 := loop_requesting_ex.wrot180 ex.io.req.bits.downsample := loop_requesting_ex.downsample ex.io.req.bits.max_pixels_per_row := loop_requesting_ex.max_pixels_per_row ex.io.req.bits.input_dilated := loop_requesting_ex.input_dilated ex.io.req.bits.trans_weight_0132 := loop_requesting_ex.trans_weight_0132 ex.io.req.bits.trans_input_3120 := loop_requesting_ex.trans_input_3120 ex.io.req.bits.loop_id := loop_requesting_ex_id ex.io.req.valid := !loop_requesting_ex.ex_started && loop_requesting_ex.ld_bias_started && loop_requesting_ex.ld_input_started && loop_requesting_ex.ld_weights_started && loop_requesting_ex.configured when (ex.io.req.fire) { loop_requesting_ex.running := true.B loop_requesting_ex.ex_started := true.B when (loop_requesting_ex.output_dram_addr =/= 0.U) { ex_c_addr_start := floorAdd(ex_c_addr_start, (max_acc_addr / concurrent_loops).U, max_acc_addr.U) } } val loop_requesting_st_id = Mux(head_loop.st_started, tail_loop_id, head_loop_id) val loop_requesting_st = loops(loop_requesting_st_id) st.io.req.bits.outer_bounds := loop_requesting_st.outer_bounds st.io.req.bits.inner_bounds := loop_requesting_st.inner_bounds st.io.req.bits.derived_params := loop_requesting_st.derived_params() st.io.req.bits.addr_start := st_addr_start st.io.req.bits.dram_addr := loop_requesting_st.output_dram_addr st.io.req.bits.no_pool := loop_requesting_st.no_pool st.io.req.bits.activation := loop_requesting_st.activation st.io.req.bits.trans_output_1203 := loop_requesting_st.trans_output_1203 st.io.req.bits.loop_id := loop_requesting_st_id st.io.req.valid := !loop_requesting_st.st_started && loop_requesting_st.ex_started && loop_requesting_st.configured when (st.io.req.fire) { loop_requesting_st.running := true.B loop_requesting_st.st_started := true.B when (loop_requesting_st.output_dram_addr =/= 0.U) { st_addr_start := floorAdd(st_addr_start, (max_acc_addr / concurrent_loops).U, max_acc_addr.U) } } // Handle completed signals when (ld_bias.io.idle && loops(ld_bias.io.loop_id).running && loops(ld_bias.io.loop_id).ld_bias_started) { loops(ld_bias.io.loop_id).ld_bias_completed := true.B } when (ld_input.io.idle && loops(ld_input.io.loop_id).running && loops(ld_input.io.loop_id).ld_input_started) { loops(ld_input.io.loop_id).ld_input_completed := true.B } when (ld_weights.io.idle && loops(ld_weights.io.loop_id).running && loops(ld_weights.io.loop_id).ld_weights_started) { loops(ld_weights.io.loop_id).ld_weights_completed := true.B } when (ex.io.idle && loops(ex.io.loop_id).running && loops(ex.io.loop_id).ex_started) { loops(ex.io.loop_id).ex_completed := true.B } when (st.io.idle && loops(st.io.loop_id).running && loops(st.io.loop_id).st_started) { loops(st.io.loop_id).st_completed := true.B } when (head_loop.running && head_loop.all_completed()) { head_loop.reset() head_loop_id := ~head_loop_id } // Resets when (reset.asBool) { loops.zipWithIndex.foreach { case (l, i) => l.reset() l.a_addr_start := (i * (max_addr / concurrent_loops)).U l.b_addr_end := ((i+1) * (max_addr / concurrent_loops)).U } } } object LoopConv { def apply(in: DecoupledIO[GemminiCmd], ld_completed: UInt, st_completed: UInt, ex_completed: UInt, block_size: Int, coreMaxAddrBits: Int, rob_size: Int, max_lds: Int, max_exs: Int, max_sts: Int, max_addr: Int, max_acc_addr: Int, input_w: Int, acc_w: Int, dma_max_bytes: Int, config_mvin_rs1_t: ConfigMvinRs1, mvin_rs2_t: MvinRs2, config_mvout_rs2_t: ConfigMvoutRs2, mvout_rs2_t: MvoutRs2, config_ex_rs1_t: ConfigExRs1, preload_rs1_t: PreloadRs, preload_rs2_t: PreloadRs, compute_rs1_t: ComputeRs, compute_rs2_t: ComputeRs, has_training_convs: Boolean, has_max_pool: Boolean, has_first_layer_optimizations: Boolean, has_dw_convs: Boolean) (implicit p: Parameters): (DecoupledIO[GemminiCmd], Bool) = { val mod = Module(new LoopConv(block_size, coreMaxAddrBits, rob_size, max_lds, max_exs, max_sts, max_addr, max_acc_addr, input_w, acc_w, dma_max_bytes, config_mvin_rs1_t, mvin_rs2_t, config_mvout_rs2_t, mvout_rs2_t, config_ex_rs1_t, preload_rs1_t, preload_rs2_t, compute_rs1_t, compute_rs2_t, has_training_convs, has_max_pool, has_first_layer_optimizations, has_dw_convs)) mod.io.in <> in mod.io.ld_completed := ld_completed mod.io.st_completed := st_completed mod.io.ex_completed := ex_completed (mod.io.out, mod.io.busy) } def castDramOffset(dram_offset: UInt): UInt = { // Cast dram offsets to 32 bits max dram_offset & "hFFFFFFFF".U } } File LocalAddr.scala: package gemmini import chisel3._ import chisel3.util._ class LocalAddr(sp_banks: Int, sp_bank_entries: Int, acc_banks: Int, acc_bank_entries: Int) extends Bundle { private val localAddrBits = 32 // TODO magic number private val spAddrBits = log2Ceil(sp_banks * sp_bank_entries) private val accAddrBits = log2Ceil(acc_banks * acc_bank_entries) private val maxAddrBits = spAddrBits max accAddrBits private val spBankBits = log2Up(sp_banks) private val spBankRowBits = log2Up(sp_bank_entries) private val accBankBits = log2Up(acc_banks) val accBankRowBits = log2Up(acc_bank_entries) val spRows = sp_banks * sp_bank_entries val is_acc_addr = Bool() val accumulate = Bool() val read_full_acc_row = Bool() val norm_cmd = NormCmd() private val metadata_w = is_acc_addr.getWidth + accumulate.getWidth + read_full_acc_row.getWidth + norm_cmd.getWidth assert(maxAddrBits + metadata_w < 32) val garbage = UInt(((localAddrBits - maxAddrBits - metadata_w - 1) max 0).W) val garbage_bit = if (localAddrBits - maxAddrBits >= metadata_w + 1) UInt(1.W) else UInt(0.W) val data = UInt(maxAddrBits.W) def sp_bank(dummy: Int = 0) = if (spAddrBits == spBankRowBits) 0.U else data(spAddrBits - 1, spBankRowBits) def sp_row(dummy: Int = 0) = data(spBankRowBits - 1, 0) def acc_bank(dummy: Int = 0) = if (accAddrBits == accBankRowBits) 0.U else data(accAddrBits - 1, accBankRowBits) def acc_row(dummy: Int = 0) = data(accBankRowBits - 1, 0) def full_sp_addr(dummy: Int = 0) = data(spAddrBits - 1, 0) def full_acc_addr(dummy: Int = 0) = data(accAddrBits - 1, 0) def is_same_address(other: LocalAddr): Bool = is_acc_addr === other.is_acc_addr && data === other.data def is_same_address(other: UInt): Bool = is_same_address(other.asTypeOf(this)) def is_garbage(dummy: Int = 0) = is_acc_addr && accumulate && read_full_acc_row && data.andR && (if (garbage_bit.getWidth > 0) garbage_bit.asBool else true.B) def +(other: UInt) = { require(isPow2(sp_bank_entries)) // TODO remove this requirement require(isPow2(acc_bank_entries)) // TODO remove this requirement val result = WireInit(this) result.data := data + other result } def <=(other: LocalAddr) = is_acc_addr === other.is_acc_addr && Mux(is_acc_addr, full_acc_addr() <= other.full_acc_addr(), full_sp_addr() <= other.full_sp_addr()) def <(other: LocalAddr) = is_acc_addr === other.is_acc_addr && Mux(is_acc_addr, full_acc_addr() < other.full_acc_addr(), full_sp_addr() < other.full_sp_addr()) def >(other: LocalAddr) = is_acc_addr === other.is_acc_addr && Mux(is_acc_addr, full_acc_addr() > other.full_acc_addr(), full_sp_addr() > other.full_sp_addr()) def add_with_overflow(other: UInt): Tuple2[LocalAddr, Bool] = { require(isPow2(sp_bank_entries)) // TODO remove this requirement require(isPow2(acc_bank_entries)) // TODO remove this requirement val sum = data +& other val overflow = Mux(is_acc_addr, sum(accAddrBits), sum(spAddrBits)) val result = WireInit(this) result.data := sum(maxAddrBits - 1, 0) (result, overflow) } // This function can only be used with non-accumulator addresses. Returns both new address and underflow def floorSub(other: UInt, floor: UInt): (LocalAddr, Bool) = { require(isPow2(sp_bank_entries)) // TODO remove this requirement require(isPow2(acc_bank_entries)) // TODO remove this requirement val underflow = data < (floor +& other) val result = WireInit(this) result.data := Mux(underflow, floor, data - other) (result, underflow) } def make_this_garbage(dummy: Int = 0): Unit = { is_acc_addr := true.B accumulate := true.B read_full_acc_row := true.B garbage_bit := 1.U data := ~(0.U(maxAddrBits.W)) } } object LocalAddr { def cast_to_local_addr[T <: Data](local_addr_t: LocalAddr, t: T): LocalAddr = { // This convenience function is basically the same as calling "asTypeOf(local_addr_t)". However, this convenience // function will also cast unnecessary garbage bits to 0, which may help reduce multiplier/adder bitwidths val result = WireInit(t.asTypeOf(local_addr_t)) if (result.garbage_bit.getWidth > 0) result.garbage := 0.U result } def cast_to_sp_addr[T <: Data](local_addr_t: LocalAddr, t: T): LocalAddr = { // This function is a wrapper around cast_to_local_addr, but it assumes that the input will not be the garbage // address val result = WireInit(cast_to_local_addr(local_addr_t, t)) result.is_acc_addr := false.B result.accumulate := false.B result.read_full_acc_row := false.B // assert(!result.garbage_bit, "cast_to_sp_addr doesn't work on garbage addresses") result } def cast_to_acc_addr[T <: Data](local_addr_t: LocalAddr, t: T, accumulate: Bool, read_full: Bool): LocalAddr = { // This function is a wrapper around cast_to_local_addr, but it assumes that the input will not be the garbage // address val result = WireInit(cast_to_local_addr(local_addr_t, t)) result.is_acc_addr := true.B result.accumulate := accumulate result.read_full_acc_row := read_full // assert(!result.garbage_bit, "cast_to_acc_addr doesn't work on garbage addresses") result } def garbage_addr(local_addr_t: LocalAddr): LocalAddr = { val result = Wire(chiselTypeOf(local_addr_t)) result := DontCare result.make_this_garbage() result } } File Util.scala: package gemmini import chisel3._ import chisel3.util._ object Util { def wrappingAdd(u: UInt, n: UInt, max_plus_one: Int): UInt = { val max = max_plus_one - 1 if (max == 0) { 0.U } else { assert(n <= max.U, "cannot wrapAdd when n is larger than max") Mux(u >= max.U - n + 1.U && n =/= 0.U, n - (max.U - u) - 1.U, u + n) } } def wrappingAdd(u: UInt, n: UInt, max_plus_one: UInt, en: Bool = true.B): UInt = { val max = max_plus_one - 1.U assert(n <= max || max === 0.U, "cannot wrapAdd when n is larger than max, unless max is 0") /* Mux(!en, u, Mux (max === 0.U, 0.U, Mux(u >= max - n + 1.U && n =/= 0.U, n - (max - u) - 1.U, u + n))) */ MuxCase(u + n, Seq( (!en) -> u, (max === 0.U) -> 0.U, (u >= max - n + 1.U && n =/= 0.U) -> (n - (max - u) - 1.U) )) } def satAdd(u: UInt, v: UInt, max: UInt): UInt = { Mux(u +& v > max, max, u + v) } def floorAdd(u: UInt, n: UInt, max_plus_one: UInt, en: Bool = true.B): UInt = { val max = max_plus_one - 1.U MuxCase(u + n, Seq( (!en) -> u, ((u +& n) > max) -> 0.U )) } def sFloorAdd(s: SInt, n: UInt, max_plus_one: SInt, min: SInt, en: Bool = true.B): SInt = { val max = max_plus_one - 1.S MuxCase(s + n.zext, Seq( (!en) -> s, ((s +& n.zext) > max) -> min )) } def wrappingSub(u: UInt, n: UInt, max_plus_one: Int): UInt = { val max = max_plus_one - 1 assert(n <= max.U, "cannot wrapSub when n is larger than max") Mux(u < n, max.U - (n-u) + 1.U, u - n) } def ceilingDivide(numer: Int, denom: Int): Int = { if (numer % denom == 0) { numer / denom } else { numer / denom + 1} } def closestLowerPowerOf2(u: UInt): UInt = { // TODO figure out a more efficient way of doing this. Is this many muxes really necessary? val exp = u.asBools.zipWithIndex.map { case (b, i) => Mux(b, i.U, 0.U) }.reduce((acc, u) => Mux(acc > u, acc, u)) (1.U << exp).asUInt } def closestAlignedLowerPowerOf2(u: UInt, addr: UInt, stride: UInt, rowBytes: Int): UInt = { val lgRowBytes = log2Ceil(rowBytes) // TODO figure out a more efficient way of doing this. Is this many muxes really necessary? val exp = u.asBools.zipWithIndex.map { case (b, i) => Mux(b && addr(i + lgRowBytes - 1, 0) === 0.U && stride(i + lgRowBytes - 1, 0) === 0.U, i.U, 0.U) }.reduce((acc, u) => Mux(acc > u, acc, u)) (1.U << exp).asUInt } // This function will return "next" with a 0-cycle delay when the "enable" signal is high. It's like a queue with // the "pipe" and "flow" parameters set to "true" def RegEnableThru[T <: Data](next: T, enable: Bool): T = { val buf = RegEnable(next, enable) Mux(enable, next, buf) } def RegEnableThru[T <: Data](next: T, init: T, enable: Bool): T = { val buf = RegEnable(next, init, enable) Mux(enable, next, buf) } def maxOf(u1: UInt, u2: UInt): UInt = { Mux(u1 > u2, u1, u2) } def maxOf[T <: Data](x: T, y: T)(implicit ev: Arithmetic[T]): T = { import ev._ Mux(x > y, x, y) } def minOf(u1: UInt, u2: UInt): UInt = { Mux(u1 < u2, u1, u2) } def accumulateTree[T <: Data](xs: Seq[T])(implicit ev: Arithmetic[T]): T = { import ev._ assert(xs.nonEmpty, "can't accumulate 0 elements") if (xs.length == 1) { xs.head } else { val upperRowLen = 1 << log2Ceil(xs.length) val upperRow = xs.padTo(upperRowLen, xs.head.zero) val pairs = upperRow.grouped(2) val lowerRow = pairs.map { case Seq(a, b) => a + b } accumulateTree(lowerRow.toSeq) } } // An undirectioned Valid bundle class UDValid[T <: Data](t: T) extends Bundle { val valid = Bool() val bits = t.cloneType def push(b: T): Unit = { valid := true.B bits := b } def pop(dummy: Int = 0): T = { valid := false.B bits } } object UDValid { def apply[T <: Data](t: T): UDValid[T] = new UDValid(t) } // creates a Reg and the next-state Wire, and returns both def regwire(bits: Int) = { val wire = Wire(UInt(bits.W)) val reg = RegNext(wire) wire := reg // default wire to read from reg (reg, wire) } }
module LoopConvSt( // @[LoopConv.scala:853:7] input clock, // @[LoopConv.scala:853:7] input reset, // @[LoopConv.scala:853:7] output io_req_ready, // @[LoopConv.scala:856:14] input io_req_valid, // @[LoopConv.scala:856:14] input [15:0] io_req_bits_outer_bounds_batch_size, // @[LoopConv.scala:856:14] input [15:0] io_req_bits_outer_bounds_in_row_dim, // @[LoopConv.scala:856:14] input [15:0] io_req_bits_outer_bounds_in_col_dim, // @[LoopConv.scala:856:14] input [15:0] io_req_bits_outer_bounds_in_channels, // @[LoopConv.scala:856:14] input [15:0] io_req_bits_outer_bounds_out_channels, // @[LoopConv.scala:856:14] input [15:0] io_req_bits_outer_bounds_out_col_dim, // @[LoopConv.scala:856:14] input [15:0] io_req_bits_outer_bounds_out_row_dim, // @[LoopConv.scala:856:14] input [15:0] io_req_bits_outer_bounds_out_stride, // @[LoopConv.scala:856:14] input [15:0] io_req_bits_outer_bounds_in_stride, // @[LoopConv.scala:856:14] input [15:0] io_req_bits_outer_bounds_weight_stride, // @[LoopConv.scala:856:14] input [15:0] io_req_bits_outer_bounds_pool_out_row_dim, // @[LoopConv.scala:856:14] input [15:0] io_req_bits_outer_bounds_pool_out_col_dim, // @[LoopConv.scala:856:14] input [15:0] io_req_bits_outer_bounds_stride, // @[LoopConv.scala:856:14] input [15:0] io_req_bits_outer_bounds_padding, // @[LoopConv.scala:856:14] input [15:0] io_req_bits_outer_bounds_kernel_dim, // @[LoopConv.scala:856:14] input [15:0] io_req_bits_outer_bounds_kernel_dilation, // @[LoopConv.scala:856:14] input [15:0] io_req_bits_outer_bounds_pool_size, // @[LoopConv.scala:856:14] input [15:0] io_req_bits_outer_bounds_pool_stride, // @[LoopConv.scala:856:14] input [15:0] io_req_bits_outer_bounds_pool_padding, // @[LoopConv.scala:856:14] input [15:0] io_req_bits_inner_bounds_batches, // @[LoopConv.scala:856:14] input [15:0] io_req_bits_inner_bounds_porows, // @[LoopConv.scala:856:14] input [15:0] io_req_bits_inner_bounds_pocols, // @[LoopConv.scala:856:14] input [15:0] io_req_bits_inner_bounds_pochs, // @[LoopConv.scala:856:14] input [15:0] io_req_bits_inner_bounds_krows, // @[LoopConv.scala:856:14] input [15:0] io_req_bits_inner_bounds_kcols, // @[LoopConv.scala:856:14] input [15:0] io_req_bits_inner_bounds_kchs, // @[LoopConv.scala:856:14] input [15:0] io_req_bits_inner_bounds_lpad, // @[LoopConv.scala:856:14] input [15:0] io_req_bits_inner_bounds_rpad, // @[LoopConv.scala:856:14] input [15:0] io_req_bits_inner_bounds_upad, // @[LoopConv.scala:856:14] input [15:0] io_req_bits_inner_bounds_dpad, // @[LoopConv.scala:856:14] input [15:0] io_req_bits_inner_bounds_plpad, // @[LoopConv.scala:856:14] input [15:0] io_req_bits_inner_bounds_prad, // @[LoopConv.scala:856:14] input [15:0] io_req_bits_inner_bounds_pupad, // @[LoopConv.scala:856:14] input [15:0] io_req_bits_inner_bounds_pdpad, // @[LoopConv.scala:856:14] input [15:0] io_req_bits_inner_bounds_orows, // @[LoopConv.scala:856:14] input [15:0] io_req_bits_inner_bounds_ocols, // @[LoopConv.scala:856:14] input [15:0] io_req_bits_derived_params_ochs, // @[LoopConv.scala:856:14] input [15:0] io_req_bits_derived_params_irows, // @[LoopConv.scala:856:14] input [15:0] io_req_bits_derived_params_icols, // @[LoopConv.scala:856:14] input [15:0] io_req_bits_derived_params_irows_unpadded, // @[LoopConv.scala:856:14] input [15:0] io_req_bits_derived_params_icols_unpadded, // @[LoopConv.scala:856:14] input [15:0] io_req_bits_derived_params_ichs, // @[LoopConv.scala:856:14] input [15:0] io_req_bits_derived_params_out_channels_per_bank, // @[LoopConv.scala:856:14] input [15:0] io_req_bits_derived_params_in_channels_per_bank, // @[LoopConv.scala:856:14] input [15:0] io_req_bits_derived_params_bias_spad_stride, // @[LoopConv.scala:856:14] input [15:0] io_req_bits_derived_params_input_spad_stride, // @[LoopConv.scala:856:14] input [15:0] io_req_bits_derived_params_weight_spad_stride, // @[LoopConv.scala:856:14] input [11:0] io_req_bits_addr_start, // @[LoopConv.scala:856:14] input [39:0] io_req_bits_dram_addr, // @[LoopConv.scala:856:14] input io_req_bits_no_pool, // @[LoopConv.scala:856:14] input [1:0] io_req_bits_activation, // @[LoopConv.scala:856:14] input io_req_bits_trans_output_1203, // @[LoopConv.scala:856:14] input io_req_bits_loop_id, // @[LoopConv.scala:856:14] input io_cmd_ready, // @[LoopConv.scala:856:14] output io_cmd_valid, // @[LoopConv.scala:856:14] output [6:0] io_cmd_bits_inst_funct, // @[LoopConv.scala:856:14] output [4:0] io_cmd_bits_inst_rs2, // @[LoopConv.scala:856:14] output [4:0] io_cmd_bits_inst_rs1, // @[LoopConv.scala:856:14] output io_cmd_bits_inst_xd, // @[LoopConv.scala:856:14] output io_cmd_bits_inst_xs1, // @[LoopConv.scala:856:14] output io_cmd_bits_inst_xs2, // @[LoopConv.scala:856:14] output [4:0] io_cmd_bits_inst_rd, // @[LoopConv.scala:856:14] output [6:0] io_cmd_bits_inst_opcode, // @[LoopConv.scala:856:14] output [63:0] io_cmd_bits_rs1, // @[LoopConv.scala:856:14] output [63:0] io_cmd_bits_rs2, // @[LoopConv.scala:856:14] output io_cmd_bits_status_debug, // @[LoopConv.scala:856:14] output io_cmd_bits_status_cease, // @[LoopConv.scala:856:14] output io_cmd_bits_status_wfi, // @[LoopConv.scala:856:14] output [31:0] io_cmd_bits_status_isa, // @[LoopConv.scala:856:14] output [1:0] io_cmd_bits_status_dprv, // @[LoopConv.scala:856:14] output io_cmd_bits_status_dv, // @[LoopConv.scala:856:14] output [1:0] io_cmd_bits_status_prv, // @[LoopConv.scala:856:14] output io_cmd_bits_status_v, // @[LoopConv.scala:856:14] output io_cmd_bits_status_sd, // @[LoopConv.scala:856:14] output [22:0] io_cmd_bits_status_zero2, // @[LoopConv.scala:856:14] output io_cmd_bits_status_mpv, // @[LoopConv.scala:856:14] output io_cmd_bits_status_gva, // @[LoopConv.scala:856:14] output io_cmd_bits_status_mbe, // @[LoopConv.scala:856:14] output io_cmd_bits_status_sbe, // @[LoopConv.scala:856:14] output [1:0] io_cmd_bits_status_sxl, // @[LoopConv.scala:856:14] output [1:0] io_cmd_bits_status_uxl, // @[LoopConv.scala:856:14] output io_cmd_bits_status_sd_rv32, // @[LoopConv.scala:856:14] output [7:0] io_cmd_bits_status_zero1, // @[LoopConv.scala:856:14] output io_cmd_bits_status_tsr, // @[LoopConv.scala:856:14] output io_cmd_bits_status_tw, // @[LoopConv.scala:856:14] output io_cmd_bits_status_tvm, // @[LoopConv.scala:856:14] output io_cmd_bits_status_mxr, // @[LoopConv.scala:856:14] output io_cmd_bits_status_sum, // @[LoopConv.scala:856:14] output io_cmd_bits_status_mprv, // @[LoopConv.scala:856:14] output [1:0] io_cmd_bits_status_xs, // @[LoopConv.scala:856:14] output [1:0] io_cmd_bits_status_fs, // @[LoopConv.scala:856:14] output [1:0] io_cmd_bits_status_mpp, // @[LoopConv.scala:856:14] output [1:0] io_cmd_bits_status_vs, // @[LoopConv.scala:856:14] output io_cmd_bits_status_spp, // @[LoopConv.scala:856:14] output io_cmd_bits_status_mpie, // @[LoopConv.scala:856:14] output io_cmd_bits_status_ube, // @[LoopConv.scala:856:14] output io_cmd_bits_status_spie, // @[LoopConv.scala:856:14] output io_cmd_bits_status_upie, // @[LoopConv.scala:856:14] output io_cmd_bits_status_mie, // @[LoopConv.scala:856:14] output io_cmd_bits_status_hie, // @[LoopConv.scala:856:14] output io_cmd_bits_status_sie, // @[LoopConv.scala:856:14] output io_cmd_bits_status_uie, // @[LoopConv.scala:856:14] input io_ex_completed, // @[LoopConv.scala:856:14] output io_idle, // @[LoopConv.scala:856:14] input io_rob_overloaded, // @[LoopConv.scala:856:14] output io_loop_id // @[LoopConv.scala:856:14] ); wire _mvout_cmd_rs2_local_addr_result_result_WIRE_is_acc_addr; // @[LocalAddr.scala:108:37] wire _mvout_cmd_rs2_local_addr_result_result_WIRE_accumulate; // @[LocalAddr.scala:108:37] wire _mvout_cmd_rs2_local_addr_result_result_WIRE_read_full_acc_row; // @[LocalAddr.scala:108:37] wire [2:0] _mvout_cmd_rs2_local_addr_result_result_WIRE_norm_cmd; // @[LocalAddr.scala:108:37] wire _mvout_cmd_rs2_local_addr_result_result_WIRE_garbage_bit; // @[LocalAddr.scala:108:37] wire [13:0] _mvout_cmd_rs2_local_addr_result_result_WIRE_data; // @[LocalAddr.scala:108:37] wire [4:0] mvout_cmd_rs2_num_cols; // @[LoopConv.scala:1005:31] wire [2:0] mvout_cmd_rs2_local_addr_norm_cmd; // @[LoopConv.scala:1005:31] wire _pool_mvout_cmd_rs2_local_addr_result_result_WIRE_is_acc_addr; // @[LocalAddr.scala:108:37] wire _pool_mvout_cmd_rs2_local_addr_result_result_WIRE_accumulate; // @[LocalAddr.scala:108:37] wire _pool_mvout_cmd_rs2_local_addr_result_result_WIRE_read_full_acc_row; // @[LocalAddr.scala:108:37] wire [2:0] _pool_mvout_cmd_rs2_local_addr_result_result_WIRE_norm_cmd; // @[LocalAddr.scala:108:37] wire _pool_mvout_cmd_rs2_local_addr_result_result_WIRE_garbage_bit; // @[LocalAddr.scala:108:37] wire [13:0] _pool_mvout_cmd_rs2_local_addr_result_result_WIRE_data; // @[LocalAddr.scala:108:37] wire [4:0] pool_mvout_cmd_rs2_num_cols; // @[LoopConv.scala:997:36] wire [2:0] pool_mvout_cmd_rs2_local_addr_norm_cmd; // @[LoopConv.scala:997:36] wire _command_p_io_in_ready; // @[LoopConv.scala:917:25] wire _command_p_io_out_valid; // @[LoopConv.scala:917:25] wire [6:0] _command_p_io_out_bits_cmd_inst_funct; // @[LoopConv.scala:917:25] wire [63:0] _command_p_io_out_bits_cmd_rs1; // @[LoopConv.scala:917:25] wire [63:0] _command_p_io_out_bits_cmd_rs2; // @[LoopConv.scala:917:25] wire [69:0] _command_p_io_out_bits_dram_addr; // @[LoopConv.scala:917:25] wire [67:0] _command_p_io_out_bits_spad_addr; // @[LoopConv.scala:917:25] wire [66:0] _command_p_io_out_bits_pool_dram_addr; // @[LoopConv.scala:917:25] wire [65:0] _command_p_io_out_bits_pool_spad_addr; // @[LoopConv.scala:917:25] wire [15:0] _command_p_io_out_bits_channels; // @[LoopConv.scala:917:25] wire _command_p_io_out_bits_is_pool; // @[LoopConv.scala:917:25] wire [15:0] _command_p_io_out_bits_I; // @[LoopConv.scala:917:25] wire [15:0] _command_p_io_out_bits_J; // @[LoopConv.scala:917:25] wire _command_p_io_busy; // @[LoopConv.scala:917:25] wire io_req_valid_0 = io_req_valid; // @[LoopConv.scala:853:7] wire [15:0] io_req_bits_outer_bounds_batch_size_0 = io_req_bits_outer_bounds_batch_size; // @[LoopConv.scala:853:7] wire [15:0] io_req_bits_outer_bounds_in_row_dim_0 = io_req_bits_outer_bounds_in_row_dim; // @[LoopConv.scala:853:7] wire [15:0] io_req_bits_outer_bounds_in_col_dim_0 = io_req_bits_outer_bounds_in_col_dim; // @[LoopConv.scala:853:7] wire [15:0] io_req_bits_outer_bounds_in_channels_0 = io_req_bits_outer_bounds_in_channels; // @[LoopConv.scala:853:7] wire [15:0] io_req_bits_outer_bounds_out_channels_0 = io_req_bits_outer_bounds_out_channels; // @[LoopConv.scala:853:7] wire [15:0] io_req_bits_outer_bounds_out_col_dim_0 = io_req_bits_outer_bounds_out_col_dim; // @[LoopConv.scala:853:7] wire [15:0] io_req_bits_outer_bounds_out_row_dim_0 = io_req_bits_outer_bounds_out_row_dim; // @[LoopConv.scala:853:7] wire [15:0] io_req_bits_outer_bounds_out_stride_0 = io_req_bits_outer_bounds_out_stride; // @[LoopConv.scala:853:7] wire [15:0] io_req_bits_outer_bounds_in_stride_0 = io_req_bits_outer_bounds_in_stride; // @[LoopConv.scala:853:7] wire [15:0] io_req_bits_outer_bounds_weight_stride_0 = io_req_bits_outer_bounds_weight_stride; // @[LoopConv.scala:853:7] wire [15:0] io_req_bits_outer_bounds_pool_out_row_dim_0 = io_req_bits_outer_bounds_pool_out_row_dim; // @[LoopConv.scala:853:7] wire [15:0] io_req_bits_outer_bounds_pool_out_col_dim_0 = io_req_bits_outer_bounds_pool_out_col_dim; // @[LoopConv.scala:853:7] wire [15:0] io_req_bits_outer_bounds_stride_0 = io_req_bits_outer_bounds_stride; // @[LoopConv.scala:853:7] wire [15:0] io_req_bits_outer_bounds_padding_0 = io_req_bits_outer_bounds_padding; // @[LoopConv.scala:853:7] wire [15:0] io_req_bits_outer_bounds_kernel_dim_0 = io_req_bits_outer_bounds_kernel_dim; // @[LoopConv.scala:853:7] wire [15:0] io_req_bits_outer_bounds_kernel_dilation_0 = io_req_bits_outer_bounds_kernel_dilation; // @[LoopConv.scala:853:7] wire [15:0] io_req_bits_outer_bounds_pool_size_0 = io_req_bits_outer_bounds_pool_size; // @[LoopConv.scala:853:7] wire [15:0] io_req_bits_outer_bounds_pool_stride_0 = io_req_bits_outer_bounds_pool_stride; // @[LoopConv.scala:853:7] wire [15:0] io_req_bits_outer_bounds_pool_padding_0 = io_req_bits_outer_bounds_pool_padding; // @[LoopConv.scala:853:7] wire [15:0] io_req_bits_inner_bounds_batches_0 = io_req_bits_inner_bounds_batches; // @[LoopConv.scala:853:7] wire [15:0] io_req_bits_inner_bounds_porows_0 = io_req_bits_inner_bounds_porows; // @[LoopConv.scala:853:7] wire [15:0] io_req_bits_inner_bounds_pocols_0 = io_req_bits_inner_bounds_pocols; // @[LoopConv.scala:853:7] wire [15:0] io_req_bits_inner_bounds_pochs_0 = io_req_bits_inner_bounds_pochs; // @[LoopConv.scala:853:7] wire [15:0] io_req_bits_inner_bounds_krows_0 = io_req_bits_inner_bounds_krows; // @[LoopConv.scala:853:7] wire [15:0] io_req_bits_inner_bounds_kcols_0 = io_req_bits_inner_bounds_kcols; // @[LoopConv.scala:853:7] wire [15:0] io_req_bits_inner_bounds_kchs_0 = io_req_bits_inner_bounds_kchs; // @[LoopConv.scala:853:7] wire [15:0] io_req_bits_inner_bounds_lpad_0 = io_req_bits_inner_bounds_lpad; // @[LoopConv.scala:853:7] wire [15:0] io_req_bits_inner_bounds_rpad_0 = io_req_bits_inner_bounds_rpad; // @[LoopConv.scala:853:7] wire [15:0] io_req_bits_inner_bounds_upad_0 = io_req_bits_inner_bounds_upad; // @[LoopConv.scala:853:7] wire [15:0] io_req_bits_inner_bounds_dpad_0 = io_req_bits_inner_bounds_dpad; // @[LoopConv.scala:853:7] wire [15:0] io_req_bits_inner_bounds_plpad_0 = io_req_bits_inner_bounds_plpad; // @[LoopConv.scala:853:7] wire [15:0] io_req_bits_inner_bounds_prad_0 = io_req_bits_inner_bounds_prad; // @[LoopConv.scala:853:7] wire [15:0] io_req_bits_inner_bounds_pupad_0 = io_req_bits_inner_bounds_pupad; // @[LoopConv.scala:853:7] wire [15:0] io_req_bits_inner_bounds_pdpad_0 = io_req_bits_inner_bounds_pdpad; // @[LoopConv.scala:853:7] wire [15:0] io_req_bits_inner_bounds_orows_0 = io_req_bits_inner_bounds_orows; // @[LoopConv.scala:853:7] wire [15:0] io_req_bits_inner_bounds_ocols_0 = io_req_bits_inner_bounds_ocols; // @[LoopConv.scala:853:7] wire [15:0] io_req_bits_derived_params_ochs_0 = io_req_bits_derived_params_ochs; // @[LoopConv.scala:853:7] wire [15:0] io_req_bits_derived_params_irows_0 = io_req_bits_derived_params_irows; // @[LoopConv.scala:853:7] wire [15:0] io_req_bits_derived_params_icols_0 = io_req_bits_derived_params_icols; // @[LoopConv.scala:853:7] wire [15:0] io_req_bits_derived_params_irows_unpadded_0 = io_req_bits_derived_params_irows_unpadded; // @[LoopConv.scala:853:7] wire [15:0] io_req_bits_derived_params_icols_unpadded_0 = io_req_bits_derived_params_icols_unpadded; // @[LoopConv.scala:853:7] wire [15:0] io_req_bits_derived_params_ichs_0 = io_req_bits_derived_params_ichs; // @[LoopConv.scala:853:7] wire [15:0] io_req_bits_derived_params_out_channels_per_bank_0 = io_req_bits_derived_params_out_channels_per_bank; // @[LoopConv.scala:853:7] wire [15:0] io_req_bits_derived_params_in_channels_per_bank_0 = io_req_bits_derived_params_in_channels_per_bank; // @[LoopConv.scala:853:7] wire [15:0] io_req_bits_derived_params_bias_spad_stride_0 = io_req_bits_derived_params_bias_spad_stride; // @[LoopConv.scala:853:7] wire [15:0] io_req_bits_derived_params_input_spad_stride_0 = io_req_bits_derived_params_input_spad_stride; // @[LoopConv.scala:853:7] wire [15:0] io_req_bits_derived_params_weight_spad_stride_0 = io_req_bits_derived_params_weight_spad_stride; // @[LoopConv.scala:853:7] wire [11:0] io_req_bits_addr_start_0 = io_req_bits_addr_start; // @[LoopConv.scala:853:7] wire [39:0] io_req_bits_dram_addr_0 = io_req_bits_dram_addr; // @[LoopConv.scala:853:7] wire io_req_bits_no_pool_0 = io_req_bits_no_pool; // @[LoopConv.scala:853:7] wire [1:0] io_req_bits_activation_0 = io_req_bits_activation; // @[LoopConv.scala:853:7] wire io_req_bits_trans_output_1203_0 = io_req_bits_trans_output_1203; // @[LoopConv.scala:853:7] wire io_req_bits_loop_id_0 = io_req_bits_loop_id; // @[LoopConv.scala:853:7] wire io_cmd_ready_0 = io_cmd_ready; // @[LoopConv.scala:853:7] wire io_ex_completed_0 = io_ex_completed; // @[LoopConv.scala:853:7] wire io_rob_overloaded_0 = io_rob_overloaded; // @[LoopConv.scala:853:7] wire [11:0] pre_pool_config_cmd_rs1__spacer = 12'h0; // @[LoopConv.scala:928:37] wire [11:0] post_pool_config_cmd_rs1__spacer = 12'h0; // @[LoopConv.scala:953:38] wire [3:0] post_pool_config_cmd_rs1_lo_hi_hi = 4'h0; // @[LoopConv.scala:957:56] wire [5:0] post_pool_config_cmd_rs1_lo_hi = 6'h0; // @[LoopConv.scala:957:56] wire [27:0] post_pool_config_cmd_rs1_hi_lo = 28'h0; // @[LoopConv.scala:957:56] wire [23:0] post_pool_config_cmd_rs1_hi_hi = 24'h0; // @[LoopConv.scala:957:56] wire [51:0] post_pool_config_cmd_rs1_hi = 52'h0; // @[LoopConv.scala:957:56] wire [31:0] ACC_SCALE_NO_CHANGE = 32'hFFFFFFFF; // @[LoopConv.scala:854:29] wire [31:0] pre_pool_config_cmd_rs2_acc_scale = 32'hFFFFFFFF; // @[LoopConv.scala:943:37] wire [31:0] pre_pool_config_cmd_rs2_hi = 32'hFFFFFFFF; // @[LoopConv.scala:947:54] wire [31:0] post_pool_config_cmd_rs2_acc_scale = 32'hFFFFFFFF; // @[LoopConv.scala:959:38] wire [31:0] post_pool_config_cmd_rs2_hi = 32'hFFFFFFFF; // @[LoopConv.scala:963:56] wire [6:0] mvout_cmd_inst_funct = 7'h3; // @[LoopConv.scala:919:23, :994:46] wire [6:0] pool_cmd_inst_funct = 7'h3; // @[LoopConv.scala:965:22, :994:46] wire [63:0] mvout_cmd_rs1 = 64'h0; // @[LoopConv.scala:919:23] wire [63:0] mvout_cmd_rs2 = 64'h0; // @[LoopConv.scala:919:23] wire [63:0] pool_cmd_rs1 = 64'h0; // @[LoopConv.scala:965:22] wire [63:0] pool_cmd_rs2 = 64'h0; // @[LoopConv.scala:965:22] wire [1:0] _command_p_io_in_bits_cmd_T_2 = 2'h3; // @[LoopConv.scala:979:10] wire [2:0] _command_p_io_in_bits_cmd_T_3 = 3'h4; // @[LoopConv.scala:980:22] wire [4:0] mvout_cmd_inst_rs2 = 5'h0; // @[LoopConv.scala:919:23] wire [4:0] mvout_cmd_inst_rs1 = 5'h0; // @[LoopConv.scala:919:23] wire [4:0] mvout_cmd_inst_rd = 5'h0; // @[LoopConv.scala:919:23] wire [4:0] pre_pool_config_cmd_inst_rs2 = 5'h0; // @[LoopConv.scala:925:33] wire [4:0] pre_pool_config_cmd_inst_rs1 = 5'h0; // @[LoopConv.scala:925:33] wire [4:0] pre_pool_config_cmd_inst_rd = 5'h0; // @[LoopConv.scala:925:33] wire [4:0] post_pool_config_cmd_inst_rs2 = 5'h0; // @[LoopConv.scala:949:34] wire [4:0] post_pool_config_cmd_inst_rs1 = 5'h0; // @[LoopConv.scala:949:34] wire [4:0] post_pool_config_cmd_inst_rd = 5'h0; // @[LoopConv.scala:949:34] wire [4:0] pool_cmd_inst_rs2 = 5'h0; // @[LoopConv.scala:965:22] wire [4:0] pool_cmd_inst_rs1 = 5'h0; // @[LoopConv.scala:965:22] wire [4:0] pool_cmd_inst_rd = 5'h0; // @[LoopConv.scala:965:22] wire [4:0] _command_p_io_in_bits_cmd_T_5_inst_rs2 = 5'h0; // @[LoopConv.scala:977:65] wire [4:0] _command_p_io_in_bits_cmd_T_5_inst_rs1 = 5'h0; // @[LoopConv.scala:977:65] wire [4:0] _command_p_io_in_bits_cmd_T_5_inst_rd = 5'h0; // @[LoopConv.scala:977:65] wire [4:0] _command_p_io_in_bits_cmd_T_7_inst_rs2 = 5'h0; // @[LoopConv.scala:977:65] wire [4:0] _command_p_io_in_bits_cmd_T_7_inst_rs1 = 5'h0; // @[LoopConv.scala:977:65] wire [4:0] _command_p_io_in_bits_cmd_T_7_inst_rd = 5'h0; // @[LoopConv.scala:977:65] wire [4:0] _command_p_io_in_bits_cmd_T_9_inst_rs2 = 5'h0; // @[LoopConv.scala:977:65] wire [4:0] _command_p_io_in_bits_cmd_T_9_inst_rs1 = 5'h0; // @[LoopConv.scala:977:65] wire [4:0] _command_p_io_in_bits_cmd_T_9_inst_rd = 5'h0; // @[LoopConv.scala:977:65] wire [6:0] mvout_cmd_inst_opcode = 7'h0; // @[LoopConv.scala:919:23] wire [6:0] pre_pool_config_cmd_inst_funct = 7'h0; // @[LoopConv.scala:925:33] wire [6:0] pre_pool_config_cmd_inst_opcode = 7'h0; // @[LoopConv.scala:925:33] wire [6:0] post_pool_config_cmd_inst_funct = 7'h0; // @[LoopConv.scala:949:34] wire [6:0] post_pool_config_cmd_inst_opcode = 7'h0; // @[LoopConv.scala:949:34] wire [6:0] pool_cmd_inst_opcode = 7'h0; // @[LoopConv.scala:965:22] wire [6:0] _command_p_io_in_bits_cmd_T_5_inst_opcode = 7'h0; // @[LoopConv.scala:977:65] wire [6:0] _command_p_io_in_bits_cmd_T_7_inst_opcode = 7'h0; // @[LoopConv.scala:977:65] wire [6:0] _command_p_io_in_bits_cmd_T_9_inst_opcode = 7'h0; // @[LoopConv.scala:977:65] wire [31:0] mvout_cmd_status_isa = 32'h0; // @[LoopConv.scala:919:23] wire [31:0] pre_pool_config_cmd_status_isa = 32'h0; // @[LoopConv.scala:925:33] wire [31:0] post_pool_config_cmd_status_isa = 32'h0; // @[LoopConv.scala:949:34] wire [31:0] pool_cmd_status_isa = 32'h0; // @[LoopConv.scala:965:22] wire [31:0] _command_p_io_in_bits_cmd_T_5_status_isa = 32'h0; // @[LoopConv.scala:977:65] wire [31:0] _command_p_io_in_bits_cmd_T_7_status_isa = 32'h0; // @[LoopConv.scala:977:65] wire [31:0] _command_p_io_in_bits_cmd_T_9_status_isa = 32'h0; // @[LoopConv.scala:977:65] wire [22:0] mvout_cmd_status_zero2 = 23'h0; // @[LoopConv.scala:919:23] wire [22:0] pre_pool_config_cmd_status_zero2 = 23'h0; // @[LoopConv.scala:925:33] wire [22:0] post_pool_config_cmd_status_zero2 = 23'h0; // @[LoopConv.scala:949:34] wire [22:0] pool_cmd_status_zero2 = 23'h0; // @[LoopConv.scala:965:22] wire [22:0] _command_p_io_in_bits_cmd_T_5_status_zero2 = 23'h0; // @[LoopConv.scala:977:65] wire [22:0] _command_p_io_in_bits_cmd_T_7_status_zero2 = 23'h0; // @[LoopConv.scala:977:65] wire [22:0] _command_p_io_in_bits_cmd_T_9_status_zero2 = 23'h0; // @[LoopConv.scala:977:65] wire [7:0] mvout_cmd_status_zero1 = 8'h0; // @[LoopConv.scala:919:23] wire [7:0] pre_pool_config_cmd_status_zero1 = 8'h0; // @[LoopConv.scala:925:33] wire [7:0] post_pool_config_cmd_status_zero1 = 8'h0; // @[LoopConv.scala:949:34] wire [7:0] post_pool_config_cmd_rs1_ocols = 8'h0; // @[LoopConv.scala:953:38] wire [7:0] post_pool_config_cmd_rs1_orows = 8'h0; // @[LoopConv.scala:953:38] wire [7:0] post_pool_config_cmd_rs1_pocols = 8'h0; // @[LoopConv.scala:953:38] wire [7:0] post_pool_config_cmd_rs1_porows = 8'h0; // @[LoopConv.scala:953:38] wire [7:0] post_pool_config_cmd_rs1_pool_out_dim = 8'h0; // @[LoopConv.scala:953:38] wire [7:0] pool_cmd_status_zero1 = 8'h0; // @[LoopConv.scala:965:22] wire [7:0] _command_p_io_in_bits_cmd_T_5_status_zero1 = 8'h0; // @[LoopConv.scala:977:65] wire [7:0] _command_p_io_in_bits_cmd_T_7_status_zero1 = 8'h0; // @[LoopConv.scala:977:65] wire [7:0] _command_p_io_in_bits_cmd_T_9_status_zero1 = 8'h0; // @[LoopConv.scala:977:65] wire [1:0] mvout_cmd_status_dprv = 2'h0; // @[LoopConv.scala:919:23] wire [1:0] mvout_cmd_status_prv = 2'h0; // @[LoopConv.scala:919:23] wire [1:0] mvout_cmd_status_sxl = 2'h0; // @[LoopConv.scala:919:23] wire [1:0] mvout_cmd_status_uxl = 2'h0; // @[LoopConv.scala:919:23] wire [1:0] mvout_cmd_status_xs = 2'h0; // @[LoopConv.scala:919:23] wire [1:0] mvout_cmd_status_fs = 2'h0; // @[LoopConv.scala:919:23] wire [1:0] mvout_cmd_status_mpp = 2'h0; // @[LoopConv.scala:919:23] wire [1:0] mvout_cmd_status_vs = 2'h0; // @[LoopConv.scala:919:23] wire [1:0] pre_pool_config_cmd_status_dprv = 2'h0; // @[LoopConv.scala:925:33] wire [1:0] pre_pool_config_cmd_status_prv = 2'h0; // @[LoopConv.scala:925:33] wire [1:0] pre_pool_config_cmd_status_sxl = 2'h0; // @[LoopConv.scala:925:33] wire [1:0] pre_pool_config_cmd_status_uxl = 2'h0; // @[LoopConv.scala:925:33] wire [1:0] pre_pool_config_cmd_status_xs = 2'h0; // @[LoopConv.scala:925:33] wire [1:0] pre_pool_config_cmd_status_fs = 2'h0; // @[LoopConv.scala:925:33] wire [1:0] pre_pool_config_cmd_status_mpp = 2'h0; // @[LoopConv.scala:925:33] wire [1:0] pre_pool_config_cmd_status_vs = 2'h0; // @[LoopConv.scala:925:33] wire [1:0] post_pool_config_cmd_status_dprv = 2'h0; // @[LoopConv.scala:949:34] wire [1:0] post_pool_config_cmd_status_prv = 2'h0; // @[LoopConv.scala:949:34] wire [1:0] post_pool_config_cmd_status_sxl = 2'h0; // @[LoopConv.scala:949:34] wire [1:0] post_pool_config_cmd_status_uxl = 2'h0; // @[LoopConv.scala:949:34] wire [1:0] post_pool_config_cmd_status_xs = 2'h0; // @[LoopConv.scala:949:34] wire [1:0] post_pool_config_cmd_status_fs = 2'h0; // @[LoopConv.scala:949:34] wire [1:0] post_pool_config_cmd_status_mpp = 2'h0; // @[LoopConv.scala:949:34] wire [1:0] post_pool_config_cmd_status_vs = 2'h0; // @[LoopConv.scala:949:34] wire [1:0] post_pool_config_cmd_rs1_lpad = 2'h0; // @[LoopConv.scala:953:38] wire [1:0] post_pool_config_cmd_rs1_upad = 2'h0; // @[LoopConv.scala:953:38] wire [1:0] post_pool_config_cmd_rs1_pool_size = 2'h0; // @[LoopConv.scala:953:38] wire [1:0] post_pool_config_cmd_rs1_pool_stride = 2'h0; // @[LoopConv.scala:953:38] wire [1:0] pool_cmd_status_dprv = 2'h0; // @[LoopConv.scala:965:22] wire [1:0] pool_cmd_status_prv = 2'h0; // @[LoopConv.scala:965:22] wire [1:0] pool_cmd_status_sxl = 2'h0; // @[LoopConv.scala:965:22] wire [1:0] pool_cmd_status_uxl = 2'h0; // @[LoopConv.scala:965:22] wire [1:0] pool_cmd_status_xs = 2'h0; // @[LoopConv.scala:965:22] wire [1:0] pool_cmd_status_fs = 2'h0; // @[LoopConv.scala:965:22] wire [1:0] pool_cmd_status_mpp = 2'h0; // @[LoopConv.scala:965:22] wire [1:0] pool_cmd_status_vs = 2'h0; // @[LoopConv.scala:965:22] wire [1:0] _command_p_io_in_bits_cmd_T_5_status_dprv = 2'h0; // @[LoopConv.scala:977:65] wire [1:0] _command_p_io_in_bits_cmd_T_5_status_prv = 2'h0; // @[LoopConv.scala:977:65] wire [1:0] _command_p_io_in_bits_cmd_T_5_status_sxl = 2'h0; // @[LoopConv.scala:977:65] wire [1:0] _command_p_io_in_bits_cmd_T_5_status_uxl = 2'h0; // @[LoopConv.scala:977:65] wire [1:0] _command_p_io_in_bits_cmd_T_5_status_xs = 2'h0; // @[LoopConv.scala:977:65] wire [1:0] _command_p_io_in_bits_cmd_T_5_status_fs = 2'h0; // @[LoopConv.scala:977:65] wire [1:0] _command_p_io_in_bits_cmd_T_5_status_mpp = 2'h0; // @[LoopConv.scala:977:65] wire [1:0] _command_p_io_in_bits_cmd_T_5_status_vs = 2'h0; // @[LoopConv.scala:977:65] wire [1:0] _command_p_io_in_bits_cmd_T_7_status_dprv = 2'h0; // @[LoopConv.scala:977:65] wire [1:0] _command_p_io_in_bits_cmd_T_7_status_prv = 2'h0; // @[LoopConv.scala:977:65] wire [1:0] _command_p_io_in_bits_cmd_T_7_status_sxl = 2'h0; // @[LoopConv.scala:977:65] wire [1:0] _command_p_io_in_bits_cmd_T_7_status_uxl = 2'h0; // @[LoopConv.scala:977:65] wire [1:0] _command_p_io_in_bits_cmd_T_7_status_xs = 2'h0; // @[LoopConv.scala:977:65] wire [1:0] _command_p_io_in_bits_cmd_T_7_status_fs = 2'h0; // @[LoopConv.scala:977:65] wire [1:0] _command_p_io_in_bits_cmd_T_7_status_mpp = 2'h0; // @[LoopConv.scala:977:65] wire [1:0] _command_p_io_in_bits_cmd_T_7_status_vs = 2'h0; // @[LoopConv.scala:977:65] wire [1:0] _command_p_io_in_bits_cmd_T_9_status_dprv = 2'h0; // @[LoopConv.scala:977:65] wire [1:0] _command_p_io_in_bits_cmd_T_9_status_prv = 2'h0; // @[LoopConv.scala:977:65] wire [1:0] _command_p_io_in_bits_cmd_T_9_status_sxl = 2'h0; // @[LoopConv.scala:977:65] wire [1:0] _command_p_io_in_bits_cmd_T_9_status_uxl = 2'h0; // @[LoopConv.scala:977:65] wire [1:0] _command_p_io_in_bits_cmd_T_9_status_xs = 2'h0; // @[LoopConv.scala:977:65] wire [1:0] _command_p_io_in_bits_cmd_T_9_status_fs = 2'h0; // @[LoopConv.scala:977:65] wire [1:0] _command_p_io_in_bits_cmd_T_9_status_mpp = 2'h0; // @[LoopConv.scala:977:65] wire [1:0] _command_p_io_in_bits_cmd_T_9_status_vs = 2'h0; // @[LoopConv.scala:977:65] wire [2:0] pool_mvout_cmd_rs2_num_rows = 3'h0; // @[LoopConv.scala:872:22, :997:36] wire [15:0] post_pool_config_cmd_rs1_hi_lo_hi = 16'h0; // @[LoopConv.scala:957:56] wire [15:0] post_pool_config_cmd_rs1_hi_hi_hi = 16'h0; // @[LoopConv.scala:957:56] wire [15:0] io_cmd_bits_rs2_hi_hi_1 = 16'h0; // @[LoopConv.scala:1003:45] wire [26:0] io_cmd_bits_rs2_hi_1 = 27'h0; // @[LoopConv.scala:1003:45] wire [12:0] pool_mvout_cmd_rs2__spacer2 = 13'h0; // @[LoopConv.scala:997:36] wire [12:0] mvout_cmd_rs2__spacer2 = 13'h0; // @[LoopConv.scala:1005:31] wire pool_mvout_cmd_rs2_local_addr_is_acc_addr = 1'h1; // @[LoopConv.scala:997:36] wire pool_mvout_cmd_rs2_local_addr_result_is_acc_addr = 1'h1; // @[LocalAddr.scala:129:26] wire mvout_cmd_rs2_local_addr_is_acc_addr = 1'h1; // @[LoopConv.scala:1005:31] wire mvout_cmd_rs2_local_addr_result_is_acc_addr = 1'h1; // @[LocalAddr.scala:129:26] wire [10:0] pool_mvout_cmd_rs2__spacer1 = 11'h0; // @[LoopConv.scala:997:36] wire [10:0] pool_mvout_cmd_rs2_local_addr_garbage = 11'h0; // @[LoopConv.scala:997:36] wire [10:0] pool_mvout_cmd_rs2_local_addr_result_result_garbage = 11'h0; // @[LocalAddr.scala:108:26] wire [10:0] pool_mvout_cmd_rs2_local_addr_result_garbage = 11'h0; // @[LocalAddr.scala:129:26] wire [10:0] mvout_cmd_rs2__spacer1 = 11'h0; // @[LoopConv.scala:1005:31] wire [10:0] mvout_cmd_rs2_local_addr_garbage = 11'h0; // @[LoopConv.scala:1005:31] wire [10:0] mvout_cmd_rs2_local_addr_result_result_garbage = 11'h0; // @[LocalAddr.scala:108:26] wire [10:0] mvout_cmd_rs2_local_addr_result_garbage = 11'h0; // @[LocalAddr.scala:129:26] wire [1:0] pre_pool_config_cmd_rs1_cmd_type = 2'h2; // @[LoopConv.scala:928:37] wire [1:0] post_pool_config_cmd_rs1_cmd_type = 2'h2; // @[LoopConv.scala:953:38] wire [1:0] _command_p_io_in_bits_cmd_T_1 = 2'h2; // @[LoopConv.scala:978:21] wire [1:0] io_cmd_bits_rs2_hi_hi = 2'h2; // @[LoopConv.scala:1003:45] wire [1:0] io_cmd_bits_rs2_hi_hi_2 = 2'h2; // @[LoopConv.scala:1012:40] wire mvout_cmd_inst_xd = 1'h0; // @[LoopConv.scala:919:23] wire mvout_cmd_inst_xs1 = 1'h0; // @[LoopConv.scala:919:23] wire mvout_cmd_inst_xs2 = 1'h0; // @[LoopConv.scala:919:23] wire mvout_cmd_status_debug = 1'h0; // @[LoopConv.scala:919:23] wire mvout_cmd_status_cease = 1'h0; // @[LoopConv.scala:919:23] wire mvout_cmd_status_wfi = 1'h0; // @[LoopConv.scala:919:23] wire mvout_cmd_status_dv = 1'h0; // @[LoopConv.scala:919:23] wire mvout_cmd_status_v = 1'h0; // @[LoopConv.scala:919:23] wire mvout_cmd_status_sd = 1'h0; // @[LoopConv.scala:919:23] wire mvout_cmd_status_mpv = 1'h0; // @[LoopConv.scala:919:23] wire mvout_cmd_status_gva = 1'h0; // @[LoopConv.scala:919:23] wire mvout_cmd_status_mbe = 1'h0; // @[LoopConv.scala:919:23] wire mvout_cmd_status_sbe = 1'h0; // @[LoopConv.scala:919:23] wire mvout_cmd_status_sd_rv32 = 1'h0; // @[LoopConv.scala:919:23] wire mvout_cmd_status_tsr = 1'h0; // @[LoopConv.scala:919:23] wire mvout_cmd_status_tw = 1'h0; // @[LoopConv.scala:919:23] wire mvout_cmd_status_tvm = 1'h0; // @[LoopConv.scala:919:23] wire mvout_cmd_status_mxr = 1'h0; // @[LoopConv.scala:919:23] wire mvout_cmd_status_sum = 1'h0; // @[LoopConv.scala:919:23] wire mvout_cmd_status_mprv = 1'h0; // @[LoopConv.scala:919:23] wire mvout_cmd_status_spp = 1'h0; // @[LoopConv.scala:919:23] wire mvout_cmd_status_mpie = 1'h0; // @[LoopConv.scala:919:23] wire mvout_cmd_status_ube = 1'h0; // @[LoopConv.scala:919:23] wire mvout_cmd_status_spie = 1'h0; // @[LoopConv.scala:919:23] wire mvout_cmd_status_upie = 1'h0; // @[LoopConv.scala:919:23] wire mvout_cmd_status_mie = 1'h0; // @[LoopConv.scala:919:23] wire mvout_cmd_status_hie = 1'h0; // @[LoopConv.scala:919:23] wire mvout_cmd_status_sie = 1'h0; // @[LoopConv.scala:919:23] wire mvout_cmd_status_uie = 1'h0; // @[LoopConv.scala:919:23] wire pre_pool_config_cmd_inst_xd = 1'h0; // @[LoopConv.scala:925:33] wire pre_pool_config_cmd_inst_xs1 = 1'h0; // @[LoopConv.scala:925:33] wire pre_pool_config_cmd_inst_xs2 = 1'h0; // @[LoopConv.scala:925:33] wire pre_pool_config_cmd_status_debug = 1'h0; // @[LoopConv.scala:925:33] wire pre_pool_config_cmd_status_cease = 1'h0; // @[LoopConv.scala:925:33] wire pre_pool_config_cmd_status_wfi = 1'h0; // @[LoopConv.scala:925:33] wire pre_pool_config_cmd_status_dv = 1'h0; // @[LoopConv.scala:925:33] wire pre_pool_config_cmd_status_v = 1'h0; // @[LoopConv.scala:925:33] wire pre_pool_config_cmd_status_sd = 1'h0; // @[LoopConv.scala:925:33] wire pre_pool_config_cmd_status_mpv = 1'h0; // @[LoopConv.scala:925:33] wire pre_pool_config_cmd_status_gva = 1'h0; // @[LoopConv.scala:925:33] wire pre_pool_config_cmd_status_mbe = 1'h0; // @[LoopConv.scala:925:33] wire pre_pool_config_cmd_status_sbe = 1'h0; // @[LoopConv.scala:925:33] wire pre_pool_config_cmd_status_sd_rv32 = 1'h0; // @[LoopConv.scala:925:33] wire pre_pool_config_cmd_status_tsr = 1'h0; // @[LoopConv.scala:925:33] wire pre_pool_config_cmd_status_tw = 1'h0; // @[LoopConv.scala:925:33] wire pre_pool_config_cmd_status_tvm = 1'h0; // @[LoopConv.scala:925:33] wire pre_pool_config_cmd_status_mxr = 1'h0; // @[LoopConv.scala:925:33] wire pre_pool_config_cmd_status_sum = 1'h0; // @[LoopConv.scala:925:33] wire pre_pool_config_cmd_status_mprv = 1'h0; // @[LoopConv.scala:925:33] wire pre_pool_config_cmd_status_spp = 1'h0; // @[LoopConv.scala:925:33] wire pre_pool_config_cmd_status_mpie = 1'h0; // @[LoopConv.scala:925:33] wire pre_pool_config_cmd_status_ube = 1'h0; // @[LoopConv.scala:925:33] wire pre_pool_config_cmd_status_spie = 1'h0; // @[LoopConv.scala:925:33] wire pre_pool_config_cmd_status_upie = 1'h0; // @[LoopConv.scala:925:33] wire pre_pool_config_cmd_status_mie = 1'h0; // @[LoopConv.scala:925:33] wire pre_pool_config_cmd_status_hie = 1'h0; // @[LoopConv.scala:925:33] wire pre_pool_config_cmd_status_sie = 1'h0; // @[LoopConv.scala:925:33] wire pre_pool_config_cmd_status_uie = 1'h0; // @[LoopConv.scala:925:33] wire post_pool_config_cmd_inst_xd = 1'h0; // @[LoopConv.scala:949:34] wire post_pool_config_cmd_inst_xs1 = 1'h0; // @[LoopConv.scala:949:34] wire post_pool_config_cmd_inst_xs2 = 1'h0; // @[LoopConv.scala:949:34] wire post_pool_config_cmd_status_debug = 1'h0; // @[LoopConv.scala:949:34] wire post_pool_config_cmd_status_cease = 1'h0; // @[LoopConv.scala:949:34] wire post_pool_config_cmd_status_wfi = 1'h0; // @[LoopConv.scala:949:34] wire post_pool_config_cmd_status_dv = 1'h0; // @[LoopConv.scala:949:34] wire post_pool_config_cmd_status_v = 1'h0; // @[LoopConv.scala:949:34] wire post_pool_config_cmd_status_sd = 1'h0; // @[LoopConv.scala:949:34] wire post_pool_config_cmd_status_mpv = 1'h0; // @[LoopConv.scala:949:34] wire post_pool_config_cmd_status_gva = 1'h0; // @[LoopConv.scala:949:34] wire post_pool_config_cmd_status_mbe = 1'h0; // @[LoopConv.scala:949:34] wire post_pool_config_cmd_status_sbe = 1'h0; // @[LoopConv.scala:949:34] wire post_pool_config_cmd_status_sd_rv32 = 1'h0; // @[LoopConv.scala:949:34] wire post_pool_config_cmd_status_tsr = 1'h0; // @[LoopConv.scala:949:34] wire post_pool_config_cmd_status_tw = 1'h0; // @[LoopConv.scala:949:34] wire post_pool_config_cmd_status_tvm = 1'h0; // @[LoopConv.scala:949:34] wire post_pool_config_cmd_status_mxr = 1'h0; // @[LoopConv.scala:949:34] wire post_pool_config_cmd_status_sum = 1'h0; // @[LoopConv.scala:949:34] wire post_pool_config_cmd_status_mprv = 1'h0; // @[LoopConv.scala:949:34] wire post_pool_config_cmd_status_spp = 1'h0; // @[LoopConv.scala:949:34] wire post_pool_config_cmd_status_mpie = 1'h0; // @[LoopConv.scala:949:34] wire post_pool_config_cmd_status_ube = 1'h0; // @[LoopConv.scala:949:34] wire post_pool_config_cmd_status_spie = 1'h0; // @[LoopConv.scala:949:34] wire post_pool_config_cmd_status_upie = 1'h0; // @[LoopConv.scala:949:34] wire post_pool_config_cmd_status_mie = 1'h0; // @[LoopConv.scala:949:34] wire post_pool_config_cmd_status_hie = 1'h0; // @[LoopConv.scala:949:34] wire post_pool_config_cmd_status_sie = 1'h0; // @[LoopConv.scala:949:34] wire post_pool_config_cmd_status_uie = 1'h0; // @[LoopConv.scala:949:34] wire pool_cmd_inst_xd = 1'h0; // @[LoopConv.scala:965:22] wire pool_cmd_inst_xs1 = 1'h0; // @[LoopConv.scala:965:22] wire pool_cmd_inst_xs2 = 1'h0; // @[LoopConv.scala:965:22] wire pool_cmd_status_debug = 1'h0; // @[LoopConv.scala:965:22] wire pool_cmd_status_cease = 1'h0; // @[LoopConv.scala:965:22] wire pool_cmd_status_wfi = 1'h0; // @[LoopConv.scala:965:22] wire pool_cmd_status_dv = 1'h0; // @[LoopConv.scala:965:22] wire pool_cmd_status_v = 1'h0; // @[LoopConv.scala:965:22] wire pool_cmd_status_sd = 1'h0; // @[LoopConv.scala:965:22] wire pool_cmd_status_mpv = 1'h0; // @[LoopConv.scala:965:22] wire pool_cmd_status_gva = 1'h0; // @[LoopConv.scala:965:22] wire pool_cmd_status_mbe = 1'h0; // @[LoopConv.scala:965:22] wire pool_cmd_status_sbe = 1'h0; // @[LoopConv.scala:965:22] wire pool_cmd_status_sd_rv32 = 1'h0; // @[LoopConv.scala:965:22] wire pool_cmd_status_tsr = 1'h0; // @[LoopConv.scala:965:22] wire pool_cmd_status_tw = 1'h0; // @[LoopConv.scala:965:22] wire pool_cmd_status_tvm = 1'h0; // @[LoopConv.scala:965:22] wire pool_cmd_status_mxr = 1'h0; // @[LoopConv.scala:965:22] wire pool_cmd_status_sum = 1'h0; // @[LoopConv.scala:965:22] wire pool_cmd_status_mprv = 1'h0; // @[LoopConv.scala:965:22] wire pool_cmd_status_spp = 1'h0; // @[LoopConv.scala:965:22] wire pool_cmd_status_mpie = 1'h0; // @[LoopConv.scala:965:22] wire pool_cmd_status_ube = 1'h0; // @[LoopConv.scala:965:22] wire pool_cmd_status_spie = 1'h0; // @[LoopConv.scala:965:22] wire pool_cmd_status_upie = 1'h0; // @[LoopConv.scala:965:22] wire pool_cmd_status_mie = 1'h0; // @[LoopConv.scala:965:22] wire pool_cmd_status_hie = 1'h0; // @[LoopConv.scala:965:22] wire pool_cmd_status_sie = 1'h0; // @[LoopConv.scala:965:22] wire pool_cmd_status_uie = 1'h0; // @[LoopConv.scala:965:22] wire _io_req_ready_T_2; // @[LoopConv.scala:972:34] wire _command_p_io_in_bits_cmd_T_5_inst_xd = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_5_inst_xs1 = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_5_inst_xs2 = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_5_status_debug = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_5_status_cease = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_5_status_wfi = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_5_status_dv = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_5_status_v = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_5_status_sd = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_5_status_mpv = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_5_status_gva = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_5_status_mbe = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_5_status_sbe = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_5_status_sd_rv32 = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_5_status_tsr = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_5_status_tw = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_5_status_tvm = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_5_status_mxr = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_5_status_sum = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_5_status_mprv = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_5_status_spp = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_5_status_mpie = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_5_status_ube = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_5_status_spie = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_5_status_upie = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_5_status_mie = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_5_status_hie = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_5_status_sie = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_5_status_uie = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_7_inst_xd = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_7_inst_xs1 = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_7_inst_xs2 = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_7_status_debug = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_7_status_cease = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_7_status_wfi = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_7_status_dv = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_7_status_v = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_7_status_sd = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_7_status_mpv = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_7_status_gva = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_7_status_mbe = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_7_status_sbe = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_7_status_sd_rv32 = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_7_status_tsr = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_7_status_tw = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_7_status_tvm = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_7_status_mxr = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_7_status_sum = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_7_status_mprv = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_7_status_spp = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_7_status_mpie = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_7_status_ube = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_7_status_spie = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_7_status_upie = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_7_status_mie = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_7_status_hie = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_7_status_sie = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_7_status_uie = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_9_inst_xd = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_9_inst_xs1 = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_9_inst_xs2 = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_9_status_debug = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_9_status_cease = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_9_status_wfi = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_9_status_dv = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_9_status_v = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_9_status_sd = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_9_status_mpv = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_9_status_gva = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_9_status_mbe = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_9_status_sbe = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_9_status_sd_rv32 = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_9_status_tsr = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_9_status_tw = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_9_status_tvm = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_9_status_mxr = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_9_status_sum = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_9_status_mprv = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_9_status_spp = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_9_status_mpie = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_9_status_ube = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_9_status_spie = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_9_status_upie = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_9_status_mie = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_9_status_hie = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_9_status_sie = 1'h0; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_9_status_uie = 1'h0; // @[LoopConv.scala:977:65] wire pool_mvout_cmd_rs2_local_addr_accumulate = 1'h0; // @[LoopConv.scala:997:36] wire pool_mvout_cmd_rs2_local_addr_read_full_acc_row = 1'h0; // @[LoopConv.scala:997:36] wire pool_mvout_cmd_rs2_local_addr_result_accumulate = 1'h0; // @[LocalAddr.scala:129:26] wire pool_mvout_cmd_rs2_local_addr_result_read_full_acc_row = 1'h0; // @[LocalAddr.scala:129:26] wire mvout_cmd_rs2_local_addr_accumulate = 1'h0; // @[LoopConv.scala:1005:31] wire mvout_cmd_rs2_local_addr_read_full_acc_row = 1'h0; // @[LoopConv.scala:1005:31] wire mvout_cmd_rs2_local_addr_result_accumulate = 1'h0; // @[LocalAddr.scala:129:26] wire mvout_cmd_rs2_local_addr_result_read_full_acc_row = 1'h0; // @[LocalAddr.scala:129:26] wire _next_och_T_2 = 1'h0; // @[Util.scala:42:8] wire _next_och_T_8 = 1'h0; // @[Util.scala:42:8] wire _io_cmd_valid_T_1; // @[LoopConv.scala:992:42] wire _io_idle_T_2; // @[LoopConv.scala:973:29] wire io_req_ready_0; // @[LoopConv.scala:853:7] wire [6:0] io_cmd_bits_inst_funct_0; // @[LoopConv.scala:853:7] wire [4:0] io_cmd_bits_inst_rs2_0; // @[LoopConv.scala:853:7] wire [4:0] io_cmd_bits_inst_rs1_0; // @[LoopConv.scala:853:7] wire io_cmd_bits_inst_xd_0; // @[LoopConv.scala:853:7] wire io_cmd_bits_inst_xs1_0; // @[LoopConv.scala:853:7] wire io_cmd_bits_inst_xs2_0; // @[LoopConv.scala:853:7] wire [4:0] io_cmd_bits_inst_rd_0; // @[LoopConv.scala:853:7] wire [6:0] io_cmd_bits_inst_opcode_0; // @[LoopConv.scala:853:7] wire io_cmd_bits_status_debug_0; // @[LoopConv.scala:853:7] wire io_cmd_bits_status_cease_0; // @[LoopConv.scala:853:7] wire io_cmd_bits_status_wfi_0; // @[LoopConv.scala:853:7] wire [31:0] io_cmd_bits_status_isa_0; // @[LoopConv.scala:853:7] wire [1:0] io_cmd_bits_status_dprv_0; // @[LoopConv.scala:853:7] wire io_cmd_bits_status_dv_0; // @[LoopConv.scala:853:7] wire [1:0] io_cmd_bits_status_prv_0; // @[LoopConv.scala:853:7] wire io_cmd_bits_status_v_0; // @[LoopConv.scala:853:7] wire io_cmd_bits_status_sd_0; // @[LoopConv.scala:853:7] wire [22:0] io_cmd_bits_status_zero2_0; // @[LoopConv.scala:853:7] wire io_cmd_bits_status_mpv_0; // @[LoopConv.scala:853:7] wire io_cmd_bits_status_gva_0; // @[LoopConv.scala:853:7] wire io_cmd_bits_status_mbe_0; // @[LoopConv.scala:853:7] wire io_cmd_bits_status_sbe_0; // @[LoopConv.scala:853:7] wire [1:0] io_cmd_bits_status_sxl_0; // @[LoopConv.scala:853:7] wire [1:0] io_cmd_bits_status_uxl_0; // @[LoopConv.scala:853:7] wire io_cmd_bits_status_sd_rv32_0; // @[LoopConv.scala:853:7] wire [7:0] io_cmd_bits_status_zero1_0; // @[LoopConv.scala:853:7] wire io_cmd_bits_status_tsr_0; // @[LoopConv.scala:853:7] wire io_cmd_bits_status_tw_0; // @[LoopConv.scala:853:7] wire io_cmd_bits_status_tvm_0; // @[LoopConv.scala:853:7] wire io_cmd_bits_status_mxr_0; // @[LoopConv.scala:853:7] wire io_cmd_bits_status_sum_0; // @[LoopConv.scala:853:7] wire io_cmd_bits_status_mprv_0; // @[LoopConv.scala:853:7] wire [1:0] io_cmd_bits_status_xs_0; // @[LoopConv.scala:853:7] wire [1:0] io_cmd_bits_status_fs_0; // @[LoopConv.scala:853:7] wire [1:0] io_cmd_bits_status_mpp_0; // @[LoopConv.scala:853:7] wire [1:0] io_cmd_bits_status_vs_0; // @[LoopConv.scala:853:7] wire io_cmd_bits_status_spp_0; // @[LoopConv.scala:853:7] wire io_cmd_bits_status_mpie_0; // @[LoopConv.scala:853:7] wire io_cmd_bits_status_ube_0; // @[LoopConv.scala:853:7] wire io_cmd_bits_status_spie_0; // @[LoopConv.scala:853:7] wire io_cmd_bits_status_upie_0; // @[LoopConv.scala:853:7] wire io_cmd_bits_status_mie_0; // @[LoopConv.scala:853:7] wire io_cmd_bits_status_hie_0; // @[LoopConv.scala:853:7] wire io_cmd_bits_status_sie_0; // @[LoopConv.scala:853:7] wire io_cmd_bits_status_uie_0; // @[LoopConv.scala:853:7] wire [63:0] io_cmd_bits_rs1_0; // @[LoopConv.scala:853:7] wire [63:0] io_cmd_bits_rs2_0; // @[LoopConv.scala:853:7] wire io_cmd_valid_0; // @[LoopConv.scala:853:7] wire io_idle_0; // @[LoopConv.scala:853:7] wire io_loop_id_0; // @[LoopConv.scala:853:7] reg [2:0] state; // @[LoopConv.scala:872:22] wire [2:0] _command_p_io_in_bits_cmd_T = state; // @[LoopConv.scala:872:22, :977:47] reg [15:0] req_outer_bounds_batch_size; // @[LoopConv.scala:874:16] reg [15:0] req_outer_bounds_in_row_dim; // @[LoopConv.scala:874:16] reg [15:0] req_outer_bounds_in_col_dim; // @[LoopConv.scala:874:16] reg [15:0] req_outer_bounds_in_channels; // @[LoopConv.scala:874:16] reg [15:0] req_outer_bounds_out_channels; // @[LoopConv.scala:874:16] reg [15:0] req_outer_bounds_out_col_dim; // @[LoopConv.scala:874:16] reg [15:0] req_outer_bounds_out_row_dim; // @[LoopConv.scala:874:16] reg [15:0] req_outer_bounds_out_stride; // @[LoopConv.scala:874:16] reg [15:0] req_outer_bounds_in_stride; // @[LoopConv.scala:874:16] reg [15:0] req_outer_bounds_weight_stride; // @[LoopConv.scala:874:16] reg [15:0] req_outer_bounds_pool_out_row_dim; // @[LoopConv.scala:874:16] reg [15:0] req_outer_bounds_pool_out_col_dim; // @[LoopConv.scala:874:16] reg [15:0] req_outer_bounds_stride; // @[LoopConv.scala:874:16] reg [15:0] req_outer_bounds_padding; // @[LoopConv.scala:874:16] reg [15:0] req_outer_bounds_kernel_dim; // @[LoopConv.scala:874:16] reg [15:0] req_outer_bounds_kernel_dilation; // @[LoopConv.scala:874:16] reg [15:0] req_outer_bounds_pool_size; // @[LoopConv.scala:874:16] reg [15:0] req_outer_bounds_pool_stride; // @[LoopConv.scala:874:16] reg [15:0] req_outer_bounds_pool_padding; // @[LoopConv.scala:874:16] reg [15:0] req_inner_bounds_batches; // @[LoopConv.scala:874:16] reg [15:0] req_inner_bounds_porows; // @[LoopConv.scala:874:16] reg [15:0] req_inner_bounds_pocols; // @[LoopConv.scala:874:16] reg [15:0] req_inner_bounds_pochs; // @[LoopConv.scala:874:16] reg [15:0] req_inner_bounds_krows; // @[LoopConv.scala:874:16] reg [15:0] req_inner_bounds_kcols; // @[LoopConv.scala:874:16] reg [15:0] req_inner_bounds_kchs; // @[LoopConv.scala:874:16] reg [15:0] req_inner_bounds_lpad; // @[LoopConv.scala:874:16] reg [15:0] req_inner_bounds_rpad; // @[LoopConv.scala:874:16] reg [15:0] req_inner_bounds_upad; // @[LoopConv.scala:874:16] reg [15:0] req_inner_bounds_dpad; // @[LoopConv.scala:874:16] reg [15:0] req_inner_bounds_plpad; // @[LoopConv.scala:874:16] reg [15:0] req_inner_bounds_prad; // @[LoopConv.scala:874:16] reg [15:0] req_inner_bounds_pupad; // @[LoopConv.scala:874:16] reg [15:0] req_inner_bounds_pdpad; // @[LoopConv.scala:874:16] reg [15:0] req_inner_bounds_orows; // @[LoopConv.scala:874:16] reg [15:0] req_inner_bounds_ocols; // @[LoopConv.scala:874:16] reg [15:0] req_derived_params_ochs; // @[LoopConv.scala:874:16] reg [15:0] req_derived_params_irows; // @[LoopConv.scala:874:16] reg [15:0] req_derived_params_icols; // @[LoopConv.scala:874:16] reg [15:0] req_derived_params_irows_unpadded; // @[LoopConv.scala:874:16] reg [15:0] req_derived_params_icols_unpadded; // @[LoopConv.scala:874:16] reg [15:0] req_derived_params_ichs; // @[LoopConv.scala:874:16] reg [15:0] req_derived_params_out_channels_per_bank; // @[LoopConv.scala:874:16] reg [15:0] req_derived_params_in_channels_per_bank; // @[LoopConv.scala:874:16] reg [15:0] req_derived_params_bias_spad_stride; // @[LoopConv.scala:874:16] reg [15:0] req_derived_params_input_spad_stride; // @[LoopConv.scala:874:16] reg [15:0] req_derived_params_weight_spad_stride; // @[LoopConv.scala:874:16] reg [11:0] req_addr_start; // @[LoopConv.scala:874:16] reg [39:0] req_dram_addr; // @[LoopConv.scala:874:16] reg req_no_pool; // @[LoopConv.scala:874:16] reg [1:0] req_activation; // @[LoopConv.scala:874:16] wire [1:0] pre_pool_config_cmd_rs1_activation = req_activation; // @[LoopConv.scala:874:16, :928:37] wire [1:0] post_pool_config_cmd_rs1_activation = req_activation; // @[LoopConv.scala:874:16, :953:38] reg req_trans_output_1203; // @[LoopConv.scala:874:16] reg req_loop_id; // @[LoopConv.scala:874:16] assign io_loop_id_0 = req_loop_id; // @[LoopConv.scala:853:7, :874:16] wire skip = req_dram_addr == 40'h0; // @[LoopConv.scala:874:16, :882:28] reg [15:0] b; // @[LoopConv.scala:885:14] reg [15:0] orow; // @[LoopConv.scala:886:17] reg [15:0] ocol; // @[LoopConv.scala:887:17] reg [15:0] och; // @[LoopConv.scala:888:16] wire [31:0] _GEN = {16'h0, orow}; // @[LoopConv.scala:886:17, :892:11] wire [31:0] _GEN_0 = _GEN * {16'h0, req_outer_bounds_out_col_dim}; // @[LoopConv.scala:874:16, :892:11] wire [31:0] _dram_offset_T; // @[LoopConv.scala:892:11] assign _dram_offset_T = _GEN_0; // @[LoopConv.scala:892:11] wire [31:0] _dram_offset_T_10; // @[LoopConv.scala:893:40] assign _dram_offset_T_10 = _GEN_0; // @[LoopConv.scala:892:11, :893:40] wire [47:0] _dram_offset_T_1 = {16'h0, _dram_offset_T} * {32'h0, req_outer_bounds_batch_size}; // @[LoopConv.scala:874:16, :892:{11,23}] wire [31:0] _dram_offset_T_2 = {16'h0, ocol} * {16'h0, req_outer_bounds_batch_size}; // @[LoopConv.scala:874:16, :887:17, :892:42] wire [48:0] _dram_offset_T_3 = {1'h0, _dram_offset_T_1} + {17'h0, _dram_offset_T_2}; // @[LoopConv.scala:892:{23,35,42}] wire [49:0] _dram_offset_T_4 = {1'h0, _dram_offset_T_3} + {34'h0, b}; // @[LoopConv.scala:885:14, :892:{35,54}] wire [65:0] _dram_offset_T_5 = {16'h0, _dram_offset_T_4} * {50'h0, req_outer_bounds_out_channels}; // @[LoopConv.scala:874:16, :892:{54,60}] wire [66:0] _GEN_1 = {51'h0, och}; // @[LoopConv.scala:888:16, :892:75] wire [66:0] _dram_offset_T_6 = {1'h0, _dram_offset_T_5} + _GEN_1; // @[LoopConv.scala:892:{60,75}] wire [69:0] _dram_offset_T_7 = {1'h0, _dram_offset_T_6, 2'h0}; // @[LoopConv.scala:892:{75,83}] wire [31:0] _GEN_2 = {16'h0, b}; // @[LoopConv.scala:885:14, :893:8] wire [31:0] _dram_offset_T_8 = _GEN_2 * {16'h0, req_outer_bounds_out_row_dim}; // @[LoopConv.scala:874:16, :893:8] wire [47:0] _dram_offset_T_9 = {16'h0, _dram_offset_T_8} * {32'h0, req_outer_bounds_out_col_dim}; // @[LoopConv.scala:874:16, :893:{8,20}] wire [48:0] _dram_offset_T_11 = {1'h0, _dram_offset_T_9} + {17'h0, _dram_offset_T_10}; // @[LoopConv.scala:892:35, :893:{20,33,40}] wire [49:0] _dram_offset_T_12 = {1'h0, _dram_offset_T_11} + {34'h0, ocol}; // @[LoopConv.scala:887:17, :892:54, :893:{33,53}] wire [65:0] _dram_offset_T_13 = {16'h0, _dram_offset_T_12} * {50'h0, req_outer_bounds_out_stride}; // @[LoopConv.scala:874:16, :892:60, :893:{53,62}] wire [66:0] _dram_offset_T_14 = {1'h0, _dram_offset_T_13} + _GEN_1; // @[LoopConv.scala:892:75, :893:{62,75}] wire [69:0] _dram_offset_T_15 = {1'h0, _dram_offset_T_14, 2'h0}; // @[LoopConv.scala:893:{75,83}] wire [69:0] dram_offset = req_trans_output_1203 ? _dram_offset_T_7 : _dram_offset_T_15; // @[LoopConv.scala:874:16, :891:24, :892:83, :893:83] wire [69:0] _dram_addr_T = {38'h0, dram_offset[31:0]}; // @[LoopConv.scala:891:24, :1556:17] wire [70:0] _dram_addr_T_1 = {31'h0, req_dram_addr} + {1'h0, _dram_addr_T}; // @[LoopConv.scala:874:16, :894:33, :1556:17] wire [69:0] dram_addr = _dram_addr_T_1[69:0]; // @[LoopConv.scala:894:33] wire [15:0] _GEN_3 = och / 16'h4; // @[LoopConv.scala:888:16, :895:42, :901:28] wire [15:0] _spad_addr_T; // @[LoopConv.scala:895:42] assign _spad_addr_T = _GEN_3; // @[LoopConv.scala:895:42] wire [15:0] _pool_spad_addr_T; // @[LoopConv.scala:898:47] assign _pool_spad_addr_T = _GEN_3; // @[LoopConv.scala:895:42, :898:47] wire [31:0] _GEN_4 = {16'h0, req_inner_bounds_batches}; // @[LoopConv.scala:874:16, :895:74] wire [31:0] _spad_addr_T_1 = {16'h0, _spad_addr_T} * _GEN_4; // @[LoopConv.scala:895:{42,74}] wire [47:0] _GEN_5 = {32'h0, req_inner_bounds_orows}; // @[LoopConv.scala:874:16, :895:84] wire [47:0] _spad_addr_T_2 = {16'h0, _spad_addr_T_1} * _GEN_5; // @[LoopConv.scala:895:{74,84}] wire [63:0] _GEN_6 = {48'h0, req_inner_bounds_ocols}; // @[LoopConv.scala:874:16, :895:92] wire [63:0] _spad_addr_T_3 = {16'h0, _spad_addr_T_2} * _GEN_6; // @[LoopConv.scala:895:{84,92}] wire [64:0] _GEN_7 = {53'h0, req_addr_start}; // @[LoopConv.scala:874:16, :895:34] wire [64:0] _spad_addr_T_4 = _GEN_7 + {1'h0, _spad_addr_T_3}; // @[LoopConv.scala:895:{34,92}] wire [31:0] _GEN_8 = _GEN_2 * {16'h0, req_inner_bounds_orows}; // @[LoopConv.scala:874:16, :893:8, :895:105] wire [31:0] _spad_addr_T_5; // @[LoopConv.scala:895:105] assign _spad_addr_T_5 = _GEN_8; // @[LoopConv.scala:895:105] wire [31:0] _pool_spad_addr_T_5; // @[LoopConv.scala:898:110] assign _pool_spad_addr_T_5 = _GEN_8; // @[LoopConv.scala:895:105, :898:110] wire [47:0] _GEN_9 = {32'h0, req_inner_bounds_ocols}; // @[LoopConv.scala:874:16, :895:113] wire [47:0] _spad_addr_T_6 = {16'h0, _spad_addr_T_5} * _GEN_9; // @[LoopConv.scala:895:{105,113}] wire [65:0] _spad_addr_T_7 = {1'h0, _spad_addr_T_4} + {18'h0, _spad_addr_T_6}; // @[LoopConv.scala:895:{34,100,113}] wire [31:0] _spad_addr_T_8 = _GEN * {16'h0, req_inner_bounds_ocols}; // @[LoopConv.scala:874:16, :892:11, :895:129] wire [66:0] _spad_addr_T_9 = {1'h0, _spad_addr_T_7} + {35'h0, _spad_addr_T_8}; // @[LoopConv.scala:895:{100,121,129}] wire [67:0] spad_addr = {1'h0, _spad_addr_T_9} + {52'h0, ocol}; // @[LoopConv.scala:887:17, :895:{121,137}, :957:56] wire [31:0] _pool_dram_addr_T = _GEN_2 * {16'h0, req_outer_bounds_pool_out_col_dim}; // @[LoopConv.scala:874:16, :893:8, :897:44] wire [47:0] _pool_dram_addr_T_1 = {16'h0, _pool_dram_addr_T} * {32'h0, req_outer_bounds_pool_out_row_dim}; // @[LoopConv.scala:874:16, :897:{44,63}] wire [63:0] _pool_dram_addr_T_2 = {16'h0, _pool_dram_addr_T_1} * {48'h0, req_outer_bounds_out_stride}; // @[LoopConv.scala:874:16, :895:92, :897:{63,83}] wire [64:0] _pool_dram_addr_T_3 = {1'h0, _pool_dram_addr_T_2} + {49'h0, och}; // @[LoopConv.scala:888:16, :897:{83,96}] wire [63:0] _pool_dram_addr_T_4 = _pool_dram_addr_T_3[63:0]; // @[LoopConv.scala:897:96] wire [66:0] _pool_dram_addr_T_5 = {1'h0, _pool_dram_addr_T_4, 2'h0}; // @[LoopConv.scala:897:{96,103}] wire [67:0] _pool_dram_addr_T_6 = {28'h0, req_dram_addr} + {1'h0, _pool_dram_addr_T_5}; // @[LoopConv.scala:874:16, :897:{38,103}, :957:56] wire [66:0] pool_dram_addr = _pool_dram_addr_T_6[66:0]; // @[LoopConv.scala:897:38] wire [31:0] _pool_spad_addr_T_1 = {16'h0, _pool_spad_addr_T} * _GEN_4; // @[LoopConv.scala:895:74, :898:{47,79}] wire [47:0] _pool_spad_addr_T_2 = {16'h0, _pool_spad_addr_T_1} * _GEN_5; // @[LoopConv.scala:895:84, :898:{79,89}] wire [63:0] _pool_spad_addr_T_3 = {16'h0, _pool_spad_addr_T_2} * _GEN_6; // @[LoopConv.scala:895:92, :898:{89,97}] wire [64:0] _pool_spad_addr_T_4 = _GEN_7 + {1'h0, _pool_spad_addr_T_3}; // @[LoopConv.scala:895:34, :898:{39,97}] wire [47:0] _pool_spad_addr_T_6 = {16'h0, _pool_spad_addr_T_5} * _GEN_9; // @[LoopConv.scala:895:113, :898:{110,118}] wire [65:0] pool_spad_addr = {1'h0, _pool_spad_addr_T_4} + {18'h0, _pool_spad_addr_T_6}; // @[LoopConv.scala:895:100, :898:{39,105,118}] wire [16:0] _GEN_10 = {1'h0, req_inner_bounds_ocols}; // @[LoopConv.scala:874:16, :901:21] wire [16:0] _GEN_11 = {1'h0, ocol}; // @[LoopConv.scala:887:17, :901:21] wire [16:0] _GEN_12 = _GEN_10 - _GEN_11; // @[LoopConv.scala:901:21] wire [16:0] _I_T; // @[LoopConv.scala:901:21] assign _I_T = _GEN_12; // @[LoopConv.scala:901:21] wire [16:0] _I_T_3; // @[LoopConv.scala:901:64] assign _I_T_3 = _GEN_12; // @[LoopConv.scala:901:{21,64}] wire [15:0] _I_T_1 = _I_T[15:0]; // @[LoopConv.scala:901:21] wire _I_T_2 = _I_T_1 > 16'h4; // @[LoopConv.scala:901:{21,28}] wire [15:0] _I_T_4 = _I_T_3[15:0]; // @[LoopConv.scala:901:64] wire [15:0] I = _I_T_2 ? 16'h4 : _I_T_4; // @[LoopConv.scala:901:{14,28,64}] wire [16:0] _GEN_13 = {1'h0, req_derived_params_ochs}; // @[LoopConv.scala:874:16, :902:20] wire [16:0] _GEN_14 = {1'h0, och}; // @[LoopConv.scala:888:16, :902:20] wire [16:0] _GEN_15 = _GEN_13 - _GEN_14; // @[LoopConv.scala:902:20] wire [16:0] _J_T; // @[LoopConv.scala:902:20] assign _J_T = _GEN_15; // @[LoopConv.scala:902:20] wire [16:0] _J_T_3; // @[LoopConv.scala:902:61] assign _J_T_3 = _GEN_15; // @[LoopConv.scala:902:{20,61}] wire [15:0] _J_T_1 = _J_T[15:0]; // @[LoopConv.scala:902:20] wire _J_T_2 = _J_T_1 > 16'h4; // @[LoopConv.scala:901:28, :902:{20,26}] wire [15:0] _J_T_4 = _J_T_3[15:0]; // @[LoopConv.scala:902:61] wire [15:0] J = _J_T_2 ? 16'h4 : _J_T_4; // @[LoopConv.scala:901:28, :902:{14,26,61}] wire [63:0] _pre_pool_config_cmd_rs1_T; // @[LoopConv.scala:941:54] wire [63:0] _pre_pool_config_cmd_rs2_T; // @[LoopConv.scala:947:54] wire [63:0] pre_pool_config_cmd_rs1; // @[LoopConv.scala:925:33] wire [63:0] pre_pool_config_cmd_rs2; // @[LoopConv.scala:925:33] wire [7:0] pre_pool_config_cmd_rs1_ocols; // @[LoopConv.scala:928:37] wire [7:0] pre_pool_config_cmd_rs1_orows; // @[LoopConv.scala:928:37] wire [7:0] pre_pool_config_cmd_rs1_pocols; // @[LoopConv.scala:928:37] wire [7:0] pre_pool_config_cmd_rs1_porows; // @[LoopConv.scala:928:37] wire [7:0] pre_pool_config_cmd_rs1_pool_out_dim; // @[LoopConv.scala:928:37] wire [1:0] pre_pool_config_cmd_rs1_lpad; // @[LoopConv.scala:928:37] wire [1:0] pre_pool_config_cmd_rs1_upad; // @[LoopConv.scala:928:37] wire [1:0] pre_pool_config_cmd_rs1_pool_size; // @[LoopConv.scala:928:37] wire [1:0] pre_pool_config_cmd_rs1_pool_stride; // @[LoopConv.scala:928:37] assign pre_pool_config_cmd_rs1_ocols = req_inner_bounds_ocols[7:0]; // @[LoopConv.scala:874:16, :928:37, :930:33] assign pre_pool_config_cmd_rs1_orows = req_inner_bounds_orows[7:0]; // @[LoopConv.scala:874:16, :928:37, :931:33] assign pre_pool_config_cmd_rs1_pocols = req_inner_bounds_pocols[7:0]; // @[LoopConv.scala:874:16, :928:37, :932:34] assign pre_pool_config_cmd_rs1_porows = req_inner_bounds_porows[7:0]; // @[LoopConv.scala:874:16, :928:37, :933:34] assign pre_pool_config_cmd_rs1_pool_out_dim = req_outer_bounds_pool_out_col_dim[7:0]; // @[LoopConv.scala:874:16, :928:37, :934:40] assign pre_pool_config_cmd_rs1_lpad = req_inner_bounds_plpad[1:0]; // @[LoopConv.scala:874:16, :928:37, :935:32] assign pre_pool_config_cmd_rs1_upad = req_inner_bounds_pupad[1:0]; // @[LoopConv.scala:874:16, :928:37, :936:32] assign pre_pool_config_cmd_rs1_pool_size = req_outer_bounds_pool_size[1:0]; // @[LoopConv.scala:874:16, :928:37, :937:37] assign pre_pool_config_cmd_rs1_pool_stride = req_outer_bounds_pool_stride[1:0]; // @[LoopConv.scala:874:16, :928:37, :938:39] wire [3:0] pre_pool_config_cmd_rs1_lo_lo_hi = {pre_pool_config_cmd_rs1_pool_stride, pre_pool_config_cmd_rs1_activation}; // @[LoopConv.scala:928:37, :941:54] wire [5:0] pre_pool_config_cmd_rs1_lo_lo = {pre_pool_config_cmd_rs1_lo_lo_hi, 2'h2}; // @[LoopConv.scala:941:54] wire [3:0] pre_pool_config_cmd_rs1_lo_hi_hi = {pre_pool_config_cmd_rs1_lpad, pre_pool_config_cmd_rs1_upad}; // @[LoopConv.scala:928:37, :941:54] wire [5:0] pre_pool_config_cmd_rs1_lo_hi = {pre_pool_config_cmd_rs1_lo_hi_hi, pre_pool_config_cmd_rs1_pool_size}; // @[LoopConv.scala:928:37, :941:54] wire [11:0] pre_pool_config_cmd_rs1_lo = {pre_pool_config_cmd_rs1_lo_hi, pre_pool_config_cmd_rs1_lo_lo}; // @[LoopConv.scala:941:54] wire [15:0] pre_pool_config_cmd_rs1_hi_lo_hi = {pre_pool_config_cmd_rs1_porows, pre_pool_config_cmd_rs1_pool_out_dim}; // @[LoopConv.scala:928:37, :941:54] wire [27:0] pre_pool_config_cmd_rs1_hi_lo = {pre_pool_config_cmd_rs1_hi_lo_hi, 12'h0}; // @[LoopConv.scala:941:54] wire [15:0] pre_pool_config_cmd_rs1_hi_hi_hi = {pre_pool_config_cmd_rs1_ocols, pre_pool_config_cmd_rs1_orows}; // @[LoopConv.scala:928:37, :941:54] wire [23:0] pre_pool_config_cmd_rs1_hi_hi = {pre_pool_config_cmd_rs1_hi_hi_hi, pre_pool_config_cmd_rs1_pocols}; // @[LoopConv.scala:928:37, :941:54] wire [51:0] pre_pool_config_cmd_rs1_hi = {pre_pool_config_cmd_rs1_hi_hi, pre_pool_config_cmd_rs1_hi_lo}; // @[LoopConv.scala:941:54] assign _pre_pool_config_cmd_rs1_T = {pre_pool_config_cmd_rs1_hi, pre_pool_config_cmd_rs1_lo}; // @[LoopConv.scala:941:54] assign pre_pool_config_cmd_rs1 = _pre_pool_config_cmd_rs1_T; // @[LoopConv.scala:925:33, :941:54] wire [31:0] pre_pool_config_cmd_rs2_stride; // @[LoopConv.scala:943:37] wire [31:0] pre_pool_config_cmd_rs2_lo = pre_pool_config_cmd_rs2_stride; // @[LoopConv.scala:943:37, :947:54] wire [18:0] _GEN_16 = {1'h0, req_outer_bounds_out_stride, 2'h0}; // @[LoopConv.scala:874:16, :946:48] wire [18:0] _pre_pool_config_cmd_rs2_stride_T; // @[LoopConv.scala:946:48] assign _pre_pool_config_cmd_rs2_stride_T = _GEN_16; // @[LoopConv.scala:946:48] wire [18:0] _post_pool_config_cmd_rs2_stride_T; // @[LoopConv.scala:962:49] assign _post_pool_config_cmd_rs2_stride_T = _GEN_16; // @[LoopConv.scala:946:48, :962:49] assign pre_pool_config_cmd_rs2_stride = {13'h0, _pre_pool_config_cmd_rs2_stride_T}; // @[LoopConv.scala:943:37, :946:{34,48}] assign _pre_pool_config_cmd_rs2_T = {32'hFFFFFFFF, pre_pool_config_cmd_rs2_lo}; // @[LoopConv.scala:947:54] assign pre_pool_config_cmd_rs2 = _pre_pool_config_cmd_rs2_T; // @[LoopConv.scala:925:33, :947:54] wire [63:0] _post_pool_config_cmd_rs1_T; // @[LoopConv.scala:957:56] wire [63:0] _post_pool_config_cmd_rs2_T; // @[LoopConv.scala:963:56] wire [63:0] post_pool_config_cmd_rs1; // @[LoopConv.scala:949:34] wire [63:0] post_pool_config_cmd_rs2; // @[LoopConv.scala:949:34] wire [3:0] post_pool_config_cmd_rs1_lo_lo_hi = {2'h0, post_pool_config_cmd_rs1_activation}; // @[LoopConv.scala:953:38, :957:56] wire [5:0] post_pool_config_cmd_rs1_lo_lo = {post_pool_config_cmd_rs1_lo_lo_hi, 2'h2}; // @[LoopConv.scala:957:56] wire [11:0] post_pool_config_cmd_rs1_lo = {6'h0, post_pool_config_cmd_rs1_lo_lo}; // @[LoopConv.scala:957:56] assign _post_pool_config_cmd_rs1_T = {52'h0, post_pool_config_cmd_rs1_lo}; // @[LoopConv.scala:957:56] assign post_pool_config_cmd_rs1 = _post_pool_config_cmd_rs1_T; // @[LoopConv.scala:949:34, :957:56] wire [31:0] post_pool_config_cmd_rs2_stride; // @[LoopConv.scala:959:38] wire [31:0] post_pool_config_cmd_rs2_lo = post_pool_config_cmd_rs2_stride; // @[LoopConv.scala:959:38, :963:56] assign post_pool_config_cmd_rs2_stride = {13'h0, _post_pool_config_cmd_rs2_stride_T}; // @[LoopConv.scala:959:38, :962:{35,49}] assign _post_pool_config_cmd_rs2_T = {32'hFFFFFFFF, post_pool_config_cmd_rs2_lo}; // @[LoopConv.scala:963:56] assign post_pool_config_cmd_rs2 = _post_pool_config_cmd_rs2_T; // @[LoopConv.scala:949:34, :963:56] wire _io_req_ready_T = ~(|state); // @[LoopConv.scala:872:22, :972:25] wire _io_req_ready_T_1 = ~_command_p_io_busy; // @[LoopConv.scala:917:25, :972:37] assign _io_req_ready_T_2 = _io_req_ready_T & _io_req_ready_T_1; // @[LoopConv.scala:972:{25,34,37}] assign io_req_ready_0 = _io_req_ready_T_2; // @[LoopConv.scala:853:7, :972:34] wire _io_idle_T = ~(|state); // @[LoopConv.scala:872:22, :972:25, :973:20] wire _io_idle_T_1 = ~_command_p_io_busy; // @[LoopConv.scala:917:25, :972:37, :973:32] assign _io_idle_T_2 = _io_idle_T & _io_idle_T_1; // @[LoopConv.scala:973:{20,29,32}] assign io_idle_0 = _io_idle_T_2; // @[LoopConv.scala:853:7, :973:29] wire _command_p_io_in_valid_T = |state; // @[LoopConv.scala:872:22, :972:25, :976:34] wire _command_p_io_in_valid_T_1 = ~skip; // @[LoopConv.scala:882:28, :976:46] wire _command_p_io_in_valid_T_2 = _command_p_io_in_valid_T & _command_p_io_in_valid_T_1; // @[LoopConv.scala:976:{34,43,46}] wire _command_p_io_in_valid_T_3 = _command_p_io_in_valid_T_2 & io_ex_completed_0; // @[LoopConv.scala:853:7, :976:{43,52}] wire _command_p_io_in_bits_cmd_T_4 = _command_p_io_in_bits_cmd_T == 3'h2; // @[LoopConv.scala:977:{47,65}] wire [6:0] _command_p_io_in_bits_cmd_T_5_inst_funct = _command_p_io_in_bits_cmd_T_4 ? 7'h0 : 7'h3; // @[LoopConv.scala:977:65, :994:46] wire [63:0] _command_p_io_in_bits_cmd_T_5_rs1 = _command_p_io_in_bits_cmd_T_4 ? pre_pool_config_cmd_rs1 : 64'h0; // @[LoopConv.scala:925:33, :977:65] wire [63:0] _command_p_io_in_bits_cmd_T_5_rs2 = _command_p_io_in_bits_cmd_T_4 ? pre_pool_config_cmd_rs2 : 64'h0; // @[LoopConv.scala:925:33, :977:65] wire _command_p_io_in_bits_cmd_T_6 = _command_p_io_in_bits_cmd_T == 3'h3; // @[LoopConv.scala:977:{47,65}] wire [6:0] _command_p_io_in_bits_cmd_T_7_inst_funct = _command_p_io_in_bits_cmd_T_6 ? 7'h3 : _command_p_io_in_bits_cmd_T_5_inst_funct; // @[LoopConv.scala:977:65, :994:46] wire [63:0] _command_p_io_in_bits_cmd_T_7_rs1 = _command_p_io_in_bits_cmd_T_6 ? 64'h0 : _command_p_io_in_bits_cmd_T_5_rs1; // @[LoopConv.scala:977:65] wire [63:0] _command_p_io_in_bits_cmd_T_7_rs2 = _command_p_io_in_bits_cmd_T_6 ? 64'h0 : _command_p_io_in_bits_cmd_T_5_rs2; // @[LoopConv.scala:977:65] wire _command_p_io_in_bits_cmd_T_8 = _command_p_io_in_bits_cmd_T == 3'h4; // @[LoopConv.scala:977:{47,65}] wire [6:0] _command_p_io_in_bits_cmd_T_9_inst_funct = _command_p_io_in_bits_cmd_T_8 ? 7'h0 : _command_p_io_in_bits_cmd_T_7_inst_funct; // @[LoopConv.scala:977:65] wire [63:0] _command_p_io_in_bits_cmd_T_9_rs1 = _command_p_io_in_bits_cmd_T_8 ? post_pool_config_cmd_rs1 : _command_p_io_in_bits_cmd_T_7_rs1; // @[LoopConv.scala:949:34, :977:65] wire [63:0] _command_p_io_in_bits_cmd_T_9_rs2 = _command_p_io_in_bits_cmd_T_8 ? post_pool_config_cmd_rs2 : _command_p_io_in_bits_cmd_T_7_rs2; // @[LoopConv.scala:949:34, :977:65] wire _command_p_io_in_bits_is_pool_T = state == 3'h3; // @[LoopConv.scala:872:22, :977:65, :982:41] wire _command_p_io_out_ready_T = ~io_rob_overloaded_0; // @[LoopConv.scala:853:7, :991:45] wire _command_p_io_out_ready_T_1 = io_cmd_ready_0 & _command_p_io_out_ready_T; // @[LoopConv.scala:853:7, :991:{42,45}] wire _io_cmd_valid_T = ~io_rob_overloaded_0; // @[LoopConv.scala:853:7, :991:45, :992:45] assign _io_cmd_valid_T_1 = _command_p_io_out_valid & _io_cmd_valid_T; // @[LoopConv.scala:917:25, :992:{42,45}] assign io_cmd_valid_0 = _io_cmd_valid_T_1; // @[LoopConv.scala:853:7, :992:42] wire _T = _command_p_io_out_bits_cmd_inst_funct == 7'h3; // @[LoopConv.scala:917:25, :994:46] wire [4:0] io_cmd_bits_rs2_lo_hi_1 = pool_mvout_cmd_rs2_num_cols; // @[LoopConv.scala:997:36, :1003:45] wire [2:0] pool_mvout_cmd_rs2_local_addr_result_norm_cmd; // @[LocalAddr.scala:129:26] wire [2:0] _io_cmd_bits_rs2_T = pool_mvout_cmd_rs2_local_addr_norm_cmd; // @[LoopConv.scala:997:36, :1003:45] wire pool_mvout_cmd_rs2_local_addr_result_garbage_bit; // @[LocalAddr.scala:129:26] wire [13:0] pool_mvout_cmd_rs2_local_addr_result_data; // @[LocalAddr.scala:129:26] wire pool_mvout_cmd_rs2_local_addr_garbage_bit; // @[LoopConv.scala:997:36] wire [13:0] pool_mvout_cmd_rs2_local_addr_data; // @[LoopConv.scala:997:36] assign pool_mvout_cmd_rs2_num_cols = _command_p_io_out_bits_channels[4:0]; // @[LoopConv.scala:917:25, :997:36, :999:35] wire _pool_mvout_cmd_rs2_local_addr_result_result_T_6; // @[LocalAddr.scala:108:37] wire _pool_mvout_cmd_rs2_local_addr_result_result_T_5; // @[LocalAddr.scala:108:37] wire pool_mvout_cmd_rs2_local_addr_result_result_is_acc_addr = _pool_mvout_cmd_rs2_local_addr_result_result_WIRE_is_acc_addr; // @[LocalAddr.scala:108:{26,37}] wire _pool_mvout_cmd_rs2_local_addr_result_result_T_4; // @[LocalAddr.scala:108:37] wire pool_mvout_cmd_rs2_local_addr_result_result_accumulate = _pool_mvout_cmd_rs2_local_addr_result_result_WIRE_accumulate; // @[LocalAddr.scala:108:{26,37}] wire [2:0] _pool_mvout_cmd_rs2_local_addr_result_result_WIRE_3; // @[LocalAddr.scala:108:37] wire pool_mvout_cmd_rs2_local_addr_result_result_read_full_acc_row = _pool_mvout_cmd_rs2_local_addr_result_result_WIRE_read_full_acc_row; // @[LocalAddr.scala:108:{26,37}] wire [10:0] _pool_mvout_cmd_rs2_local_addr_result_result_T_2; // @[LocalAddr.scala:108:37] wire [2:0] pool_mvout_cmd_rs2_local_addr_result_result_norm_cmd = _pool_mvout_cmd_rs2_local_addr_result_result_WIRE_norm_cmd; // @[LocalAddr.scala:108:{26,37}] wire _pool_mvout_cmd_rs2_local_addr_result_result_T_1; // @[LocalAddr.scala:108:37] wire [13:0] _pool_mvout_cmd_rs2_local_addr_result_result_T; // @[LocalAddr.scala:108:37] wire pool_mvout_cmd_rs2_local_addr_result_result_garbage_bit = _pool_mvout_cmd_rs2_local_addr_result_result_WIRE_garbage_bit; // @[LocalAddr.scala:108:{26,37}] wire [13:0] pool_mvout_cmd_rs2_local_addr_result_result_data = _pool_mvout_cmd_rs2_local_addr_result_result_WIRE_data; // @[LocalAddr.scala:108:{26,37}] wire [31:0] _pool_mvout_cmd_rs2_local_addr_result_result_WIRE_1 = _command_p_io_out_bits_pool_spad_addr[31:0]; // @[LoopConv.scala:917:25] assign _pool_mvout_cmd_rs2_local_addr_result_result_T = _pool_mvout_cmd_rs2_local_addr_result_result_WIRE_1[13:0]; // @[LocalAddr.scala:108:37] assign _pool_mvout_cmd_rs2_local_addr_result_result_WIRE_data = _pool_mvout_cmd_rs2_local_addr_result_result_T; // @[LocalAddr.scala:108:37] assign _pool_mvout_cmd_rs2_local_addr_result_result_T_1 = _pool_mvout_cmd_rs2_local_addr_result_result_WIRE_1[14]; // @[LocalAddr.scala:108:37] assign _pool_mvout_cmd_rs2_local_addr_result_result_WIRE_garbage_bit = _pool_mvout_cmd_rs2_local_addr_result_result_T_1; // @[LocalAddr.scala:108:37] assign _pool_mvout_cmd_rs2_local_addr_result_result_T_2 = _pool_mvout_cmd_rs2_local_addr_result_result_WIRE_1[25:15]; // @[LocalAddr.scala:108:37] wire [10:0] _pool_mvout_cmd_rs2_local_addr_result_result_WIRE_garbage = _pool_mvout_cmd_rs2_local_addr_result_result_T_2; // @[LocalAddr.scala:108:37] wire [2:0] _pool_mvout_cmd_rs2_local_addr_result_result_T_3 = _pool_mvout_cmd_rs2_local_addr_result_result_WIRE_1[28:26]; // @[LocalAddr.scala:108:37] wire [2:0] _pool_mvout_cmd_rs2_local_addr_result_result_WIRE_2 = _pool_mvout_cmd_rs2_local_addr_result_result_T_3; // @[LocalAddr.scala:108:37] assign _pool_mvout_cmd_rs2_local_addr_result_result_WIRE_3 = _pool_mvout_cmd_rs2_local_addr_result_result_WIRE_2; // @[LocalAddr.scala:108:37] assign _pool_mvout_cmd_rs2_local_addr_result_result_WIRE_norm_cmd = _pool_mvout_cmd_rs2_local_addr_result_result_WIRE_3; // @[LocalAddr.scala:108:37] assign _pool_mvout_cmd_rs2_local_addr_result_result_T_4 = _pool_mvout_cmd_rs2_local_addr_result_result_WIRE_1[29]; // @[LocalAddr.scala:108:37] assign _pool_mvout_cmd_rs2_local_addr_result_result_WIRE_read_full_acc_row = _pool_mvout_cmd_rs2_local_addr_result_result_T_4; // @[LocalAddr.scala:108:37] assign _pool_mvout_cmd_rs2_local_addr_result_result_T_5 = _pool_mvout_cmd_rs2_local_addr_result_result_WIRE_1[30]; // @[LocalAddr.scala:108:37] assign _pool_mvout_cmd_rs2_local_addr_result_result_WIRE_accumulate = _pool_mvout_cmd_rs2_local_addr_result_result_T_5; // @[LocalAddr.scala:108:37] assign _pool_mvout_cmd_rs2_local_addr_result_result_T_6 = _pool_mvout_cmd_rs2_local_addr_result_result_WIRE_1[31]; // @[LocalAddr.scala:108:37] assign _pool_mvout_cmd_rs2_local_addr_result_result_WIRE_is_acc_addr = _pool_mvout_cmd_rs2_local_addr_result_result_T_6; // @[LocalAddr.scala:108:37] assign pool_mvout_cmd_rs2_local_addr_result_norm_cmd = pool_mvout_cmd_rs2_local_addr_result_result_norm_cmd; // @[LocalAddr.scala:108:26, :129:26] assign pool_mvout_cmd_rs2_local_addr_result_garbage_bit = pool_mvout_cmd_rs2_local_addr_result_result_garbage_bit; // @[LocalAddr.scala:108:26, :129:26] assign pool_mvout_cmd_rs2_local_addr_result_data = pool_mvout_cmd_rs2_local_addr_result_result_data; // @[LocalAddr.scala:108:26, :129:26] assign pool_mvout_cmd_rs2_local_addr_norm_cmd = pool_mvout_cmd_rs2_local_addr_result_norm_cmd; // @[LoopConv.scala:997:36] assign pool_mvout_cmd_rs2_local_addr_garbage_bit = pool_mvout_cmd_rs2_local_addr_result_garbage_bit; // @[LoopConv.scala:997:36] assign pool_mvout_cmd_rs2_local_addr_data = pool_mvout_cmd_rs2_local_addr_result_data; // @[LoopConv.scala:997:36] wire [11:0] io_cmd_bits_rs2_lo_hi = {11'h0, pool_mvout_cmd_rs2_local_addr_garbage_bit}; // @[LoopConv.scala:997:36, :1003:45] wire [25:0] io_cmd_bits_rs2_lo = {io_cmd_bits_rs2_lo_hi, pool_mvout_cmd_rs2_local_addr_data}; // @[LoopConv.scala:997:36, :1003:45] wire [3:0] io_cmd_bits_rs2_hi_lo = {1'h0, _io_cmd_bits_rs2_T}; // @[LoopConv.scala:1003:45] wire [5:0] io_cmd_bits_rs2_hi = {2'h2, io_cmd_bits_rs2_hi_lo}; // @[LoopConv.scala:1003:45] wire [31:0] _io_cmd_bits_rs2_T_1 = {io_cmd_bits_rs2_hi, io_cmd_bits_rs2_lo}; // @[LoopConv.scala:1003:45] wire [36:0] io_cmd_bits_rs2_lo_1 = {io_cmd_bits_rs2_lo_hi_1, _io_cmd_bits_rs2_T_1}; // @[LoopConv.scala:1003:45] wire [63:0] _io_cmd_bits_rs2_T_2 = {27'h0, io_cmd_bits_rs2_lo_1}; // @[LoopConv.scala:1003:45] wire [4:0] io_cmd_bits_rs2_lo_hi_3 = mvout_cmd_rs2_num_cols; // @[LoopConv.scala:1005:31, :1012:40] wire [2:0] mvout_cmd_rs2_local_addr_result_norm_cmd; // @[LocalAddr.scala:129:26] wire [2:0] _io_cmd_bits_rs2_T_3 = mvout_cmd_rs2_local_addr_norm_cmd; // @[LoopConv.scala:1005:31, :1012:40] wire mvout_cmd_rs2_local_addr_result_garbage_bit; // @[LocalAddr.scala:129:26] wire [13:0] mvout_cmd_rs2_local_addr_result_data; // @[LocalAddr.scala:129:26] wire mvout_cmd_rs2_local_addr_garbage_bit; // @[LoopConv.scala:1005:31] wire [13:0] mvout_cmd_rs2_local_addr_data; // @[LoopConv.scala:1005:31] wire [2:0] mvout_cmd_rs2_num_rows; // @[LoopConv.scala:1005:31] assign mvout_cmd_rs2_num_rows = _command_p_io_out_bits_I[2:0]; // @[LoopConv.scala:917:25, :1005:31, :1007:30] assign mvout_cmd_rs2_num_cols = _command_p_io_out_bits_J[4:0]; // @[LoopConv.scala:917:25, :1005:31, :1008:30] wire _mvout_cmd_rs2_local_addr_result_result_T_6; // @[LocalAddr.scala:108:37] wire _mvout_cmd_rs2_local_addr_result_result_T_5; // @[LocalAddr.scala:108:37] wire mvout_cmd_rs2_local_addr_result_result_is_acc_addr = _mvout_cmd_rs2_local_addr_result_result_WIRE_is_acc_addr; // @[LocalAddr.scala:108:{26,37}] wire _mvout_cmd_rs2_local_addr_result_result_T_4; // @[LocalAddr.scala:108:37] wire mvout_cmd_rs2_local_addr_result_result_accumulate = _mvout_cmd_rs2_local_addr_result_result_WIRE_accumulate; // @[LocalAddr.scala:108:{26,37}] wire [2:0] _mvout_cmd_rs2_local_addr_result_result_WIRE_3; // @[LocalAddr.scala:108:37] wire mvout_cmd_rs2_local_addr_result_result_read_full_acc_row = _mvout_cmd_rs2_local_addr_result_result_WIRE_read_full_acc_row; // @[LocalAddr.scala:108:{26,37}] wire [10:0] _mvout_cmd_rs2_local_addr_result_result_T_2; // @[LocalAddr.scala:108:37] wire [2:0] mvout_cmd_rs2_local_addr_result_result_norm_cmd = _mvout_cmd_rs2_local_addr_result_result_WIRE_norm_cmd; // @[LocalAddr.scala:108:{26,37}] wire _mvout_cmd_rs2_local_addr_result_result_T_1; // @[LocalAddr.scala:108:37] wire [13:0] _mvout_cmd_rs2_local_addr_result_result_T; // @[LocalAddr.scala:108:37] wire mvout_cmd_rs2_local_addr_result_result_garbage_bit = _mvout_cmd_rs2_local_addr_result_result_WIRE_garbage_bit; // @[LocalAddr.scala:108:{26,37}] wire [13:0] mvout_cmd_rs2_local_addr_result_result_data = _mvout_cmd_rs2_local_addr_result_result_WIRE_data; // @[LocalAddr.scala:108:{26,37}] wire [31:0] _mvout_cmd_rs2_local_addr_result_result_WIRE_1 = _command_p_io_out_bits_spad_addr[31:0]; // @[LoopConv.scala:917:25] assign _mvout_cmd_rs2_local_addr_result_result_T = _mvout_cmd_rs2_local_addr_result_result_WIRE_1[13:0]; // @[LocalAddr.scala:108:37] assign _mvout_cmd_rs2_local_addr_result_result_WIRE_data = _mvout_cmd_rs2_local_addr_result_result_T; // @[LocalAddr.scala:108:37] assign _mvout_cmd_rs2_local_addr_result_result_T_1 = _mvout_cmd_rs2_local_addr_result_result_WIRE_1[14]; // @[LocalAddr.scala:108:37] assign _mvout_cmd_rs2_local_addr_result_result_WIRE_garbage_bit = _mvout_cmd_rs2_local_addr_result_result_T_1; // @[LocalAddr.scala:108:37] assign _mvout_cmd_rs2_local_addr_result_result_T_2 = _mvout_cmd_rs2_local_addr_result_result_WIRE_1[25:15]; // @[LocalAddr.scala:108:37] wire [10:0] _mvout_cmd_rs2_local_addr_result_result_WIRE_garbage = _mvout_cmd_rs2_local_addr_result_result_T_2; // @[LocalAddr.scala:108:37] wire [2:0] _mvout_cmd_rs2_local_addr_result_result_T_3 = _mvout_cmd_rs2_local_addr_result_result_WIRE_1[28:26]; // @[LocalAddr.scala:108:37] wire [2:0] _mvout_cmd_rs2_local_addr_result_result_WIRE_2 = _mvout_cmd_rs2_local_addr_result_result_T_3; // @[LocalAddr.scala:108:37] assign _mvout_cmd_rs2_local_addr_result_result_WIRE_3 = _mvout_cmd_rs2_local_addr_result_result_WIRE_2; // @[LocalAddr.scala:108:37] assign _mvout_cmd_rs2_local_addr_result_result_WIRE_norm_cmd = _mvout_cmd_rs2_local_addr_result_result_WIRE_3; // @[LocalAddr.scala:108:37] assign _mvout_cmd_rs2_local_addr_result_result_T_4 = _mvout_cmd_rs2_local_addr_result_result_WIRE_1[29]; // @[LocalAddr.scala:108:37] assign _mvout_cmd_rs2_local_addr_result_result_WIRE_read_full_acc_row = _mvout_cmd_rs2_local_addr_result_result_T_4; // @[LocalAddr.scala:108:37] assign _mvout_cmd_rs2_local_addr_result_result_T_5 = _mvout_cmd_rs2_local_addr_result_result_WIRE_1[30]; // @[LocalAddr.scala:108:37] assign _mvout_cmd_rs2_local_addr_result_result_WIRE_accumulate = _mvout_cmd_rs2_local_addr_result_result_T_5; // @[LocalAddr.scala:108:37] assign _mvout_cmd_rs2_local_addr_result_result_T_6 = _mvout_cmd_rs2_local_addr_result_result_WIRE_1[31]; // @[LocalAddr.scala:108:37] assign _mvout_cmd_rs2_local_addr_result_result_WIRE_is_acc_addr = _mvout_cmd_rs2_local_addr_result_result_T_6; // @[LocalAddr.scala:108:37] assign mvout_cmd_rs2_local_addr_result_norm_cmd = mvout_cmd_rs2_local_addr_result_result_norm_cmd; // @[LocalAddr.scala:108:26, :129:26] assign mvout_cmd_rs2_local_addr_result_garbage_bit = mvout_cmd_rs2_local_addr_result_result_garbage_bit; // @[LocalAddr.scala:108:26, :129:26] assign mvout_cmd_rs2_local_addr_result_data = mvout_cmd_rs2_local_addr_result_result_data; // @[LocalAddr.scala:108:26, :129:26] assign mvout_cmd_rs2_local_addr_norm_cmd = mvout_cmd_rs2_local_addr_result_norm_cmd; // @[LoopConv.scala:1005:31] assign mvout_cmd_rs2_local_addr_garbage_bit = mvout_cmd_rs2_local_addr_result_garbage_bit; // @[LoopConv.scala:1005:31] assign mvout_cmd_rs2_local_addr_data = mvout_cmd_rs2_local_addr_result_data; // @[LoopConv.scala:1005:31] assign io_cmd_bits_rs1_0 = _T ? (_command_p_io_out_bits_is_pool ? _command_p_io_out_bits_pool_dram_addr[63:0] : _command_p_io_out_bits_dram_addr[63:0]) : _command_p_io_out_bits_cmd_rs1; // @[LoopConv.scala:853:7, :917:25, :993:15, :994:{46,61}, :996:22, :1002:23, :1011:23] wire [11:0] io_cmd_bits_rs2_lo_hi_2 = {11'h0, mvout_cmd_rs2_local_addr_garbage_bit}; // @[LoopConv.scala:1005:31, :1012:40] wire [25:0] io_cmd_bits_rs2_lo_2 = {io_cmd_bits_rs2_lo_hi_2, mvout_cmd_rs2_local_addr_data}; // @[LoopConv.scala:1005:31, :1012:40] wire [3:0] io_cmd_bits_rs2_hi_lo_1 = {1'h0, _io_cmd_bits_rs2_T_3}; // @[LoopConv.scala:1012:40] wire [5:0] io_cmd_bits_rs2_hi_2 = {2'h2, io_cmd_bits_rs2_hi_lo_1}; // @[LoopConv.scala:1012:40] wire [31:0] _io_cmd_bits_rs2_T_4 = {io_cmd_bits_rs2_hi_2, io_cmd_bits_rs2_lo_2}; // @[LoopConv.scala:1012:40] wire [36:0] io_cmd_bits_rs2_lo_3 = {io_cmd_bits_rs2_lo_hi_3, _io_cmd_bits_rs2_T_4}; // @[LoopConv.scala:1012:40] wire [15:0] io_cmd_bits_rs2_hi_hi_3 = {13'h0, mvout_cmd_rs2_num_rows}; // @[LoopConv.scala:1005:31, :1012:40] wire [26:0] io_cmd_bits_rs2_hi_3 = {io_cmd_bits_rs2_hi_hi_3, 11'h0}; // @[LoopConv.scala:1012:40] wire [63:0] _io_cmd_bits_rs2_T_5 = {io_cmd_bits_rs2_hi_3, io_cmd_bits_rs2_lo_3}; // @[LoopConv.scala:1012:40] assign io_cmd_bits_rs2_0 = _T ? (_command_p_io_out_bits_is_pool ? _io_cmd_bits_rs2_T_2 : _io_cmd_bits_rs2_T_5) : _command_p_io_out_bits_cmd_rs2; // @[LoopConv.scala:853:7, :917:25, :993:15, :994:{46,61}, :996:22, :1003:{23,45}, :1012:{23,40}] wire [16:0] _GEN_17 = _GEN_13 - 17'h1; // @[Util.scala:39:28] wire [16:0] _next_och_max_T; // @[Util.scala:39:28] assign _next_och_max_T = _GEN_17; // @[Util.scala:39:28] wire [16:0] _next_och_max_T_1; // @[Util.scala:39:28] assign _next_och_max_T_1 = _GEN_17; // @[Util.scala:39:28] wire [15:0] next_och_max = _next_och_max_T[15:0]; // @[Util.scala:39:28] wire [16:0] _GEN_18 = _GEN_14 + 17'h4; // @[Util.scala:41:15] wire [16:0] _next_och_T; // @[Util.scala:41:15] assign _next_och_T = _GEN_18; // @[Util.scala:41:15] wire [16:0] _next_och_T_3; // @[Util.scala:43:11] assign _next_och_T_3 = _GEN_18; // @[Util.scala:41:15, :43:11] wire [16:0] _next_och_T_6; // @[Util.scala:41:15] assign _next_och_T_6 = _GEN_18; // @[Util.scala:41:15] wire [16:0] _next_och_T_9; // @[Util.scala:43:11] assign _next_och_T_9 = _GEN_18; // @[Util.scala:41:15, :43:11] wire [15:0] _next_och_T_1 = _next_och_T[15:0]; // @[Util.scala:41:15] wire _next_och_T_4 = _next_och_T_3 > {1'h0, next_och_max}; // @[Util.scala:39:28, :43:{11,17}] wire [15:0] _next_och_T_5 = _next_och_T_4 ? 16'h0 : _next_och_T_1; // @[Mux.scala:126:16] wire [15:0] next_och = _next_och_T_5; // @[Mux.scala:126:16] wire _GEN_19 = next_och == 16'h0; // @[Mux.scala:126:16] wire _next_ocol_T; // @[LoopConv.scala:1022:68] assign _next_ocol_T = _GEN_19; // @[LoopConv.scala:1022:68] wire _next_orow_T_1; // @[LoopConv.scala:1023:80] assign _next_orow_T_1 = _GEN_19; // @[LoopConv.scala:1022:68, :1023:80] wire _next_b_T_3; // @[LoopConv.scala:1024:97] assign _next_b_T_3 = _GEN_19; // @[LoopConv.scala:1022:68, :1024:97] wire _state_T_5; // @[LoopConv.scala:1031:89] assign _state_T_5 = _GEN_19; // @[LoopConv.scala:1022:68, :1031:89] wire [16:0] _next_ocol_max_T = _GEN_10 - 17'h1; // @[Util.scala:39:28] wire [15:0] next_ocol_max = _next_ocol_max_T[15:0]; // @[Util.scala:39:28] wire [16:0] _GEN_20 = _GEN_11 + 17'h4; // @[Util.scala:41:15] wire [16:0] _next_ocol_T_1; // @[Util.scala:41:15] assign _next_ocol_T_1 = _GEN_20; // @[Util.scala:41:15] wire [16:0] _next_ocol_T_4; // @[Util.scala:43:11] assign _next_ocol_T_4 = _GEN_20; // @[Util.scala:41:15, :43:11] wire [15:0] _next_ocol_T_2 = _next_ocol_T_1[15:0]; // @[Util.scala:41:15] wire _next_ocol_T_3 = ~_next_ocol_T; // @[Util.scala:42:8] wire _next_ocol_T_5 = _next_ocol_T_4 > {1'h0, next_ocol_max}; // @[Util.scala:39:28, :43:{11,17}] wire [15:0] _next_ocol_T_6 = _next_ocol_T_5 ? 16'h0 : _next_ocol_T_2; // @[Mux.scala:126:16] wire [15:0] next_ocol = _next_ocol_T_3 ? ocol : _next_ocol_T_6; // @[Mux.scala:126:16] wire _GEN_21 = next_ocol == 16'h0; // @[Mux.scala:126:16] wire _next_orow_T; // @[LoopConv.scala:1023:60] assign _next_orow_T = _GEN_21; // @[LoopConv.scala:1023:60] wire _next_b_T_1; // @[LoopConv.scala:1024:77] assign _next_b_T_1 = _GEN_21; // @[LoopConv.scala:1023:60, :1024:77] wire _state_T_3; // @[LoopConv.scala:1031:69] assign _state_T_3 = _GEN_21; // @[LoopConv.scala:1023:60, :1031:69] wire _next_orow_T_2 = _next_orow_T & _next_orow_T_1; // @[LoopConv.scala:1023:{60,68,80}] wire [16:0] _next_orow_max_T = {1'h0, req_inner_bounds_orows} - 17'h1; // @[Util.scala:39:28] wire [15:0] next_orow_max = _next_orow_max_T[15:0]; // @[Util.scala:39:28] wire [16:0] _GEN_22 = {1'h0, orow} + 17'h1; // @[Util.scala:41:15] wire [16:0] _next_orow_T_3; // @[Util.scala:41:15] assign _next_orow_T_3 = _GEN_22; // @[Util.scala:41:15] wire [16:0] _next_orow_T_6; // @[Util.scala:43:11] assign _next_orow_T_6 = _GEN_22; // @[Util.scala:41:15, :43:11] wire [15:0] _next_orow_T_4 = _next_orow_T_3[15:0]; // @[Util.scala:41:15] wire _next_orow_T_5 = ~_next_orow_T_2; // @[Util.scala:42:8] wire _next_orow_T_7 = _next_orow_T_6 > {1'h0, next_orow_max}; // @[Util.scala:39:28, :43:{11,17}] wire [15:0] _next_orow_T_8 = _next_orow_T_7 ? 16'h0 : _next_orow_T_4; // @[Mux.scala:126:16] wire [15:0] next_orow = _next_orow_T_5 ? orow : _next_orow_T_8; // @[Mux.scala:126:16] wire _GEN_23 = next_orow == 16'h0; // @[Mux.scala:126:16] wire _next_b_T; // @[LoopConv.scala:1024:56] assign _next_b_T = _GEN_23; // @[LoopConv.scala:1024:56] wire _state_T_1; // @[LoopConv.scala:1031:48] assign _state_T_1 = _GEN_23; // @[LoopConv.scala:1024:56, :1031:48] wire _next_b_T_2 = _next_b_T & _next_b_T_1; // @[LoopConv.scala:1024:{56,64,77}] wire _next_b_T_4 = _next_b_T_2 & _next_b_T_3; // @[LoopConv.scala:1024:{64,85,97}] wire [16:0] _GEN_24 = {1'h0, req_inner_bounds_batches} - 17'h1; // @[Util.scala:39:28] wire [16:0] _next_b_max_T; // @[Util.scala:39:28] assign _next_b_max_T = _GEN_24; // @[Util.scala:39:28] wire [16:0] _next_b_max_T_1; // @[Util.scala:39:28] assign _next_b_max_T_1 = _GEN_24; // @[Util.scala:39:28] wire [15:0] next_b_max = _next_b_max_T[15:0]; // @[Util.scala:39:28] wire [16:0] _GEN_25 = {1'h0, b} + 17'h1; // @[Util.scala:41:15] wire [16:0] _next_b_T_5; // @[Util.scala:41:15] assign _next_b_T_5 = _GEN_25; // @[Util.scala:41:15] wire [16:0] _next_b_T_8; // @[Util.scala:43:11] assign _next_b_T_8 = _GEN_25; // @[Util.scala:41:15, :43:11] wire [16:0] _next_b_T_12; // @[Util.scala:41:15] assign _next_b_T_12 = _GEN_25; // @[Util.scala:41:15] wire [16:0] _next_b_T_15; // @[Util.scala:43:11] assign _next_b_T_15 = _GEN_25; // @[Util.scala:41:15, :43:11] wire [15:0] _next_b_T_6 = _next_b_T_5[15:0]; // @[Util.scala:41:15] wire _next_b_T_7 = ~_next_b_T_4; // @[Util.scala:42:8] wire _next_b_T_9 = _next_b_T_8 > {1'h0, next_b_max}; // @[Util.scala:39:28, :43:{11,17}] wire [15:0] _next_b_T_10 = _next_b_T_9 ? 16'h0 : _next_b_T_6; // @[Mux.scala:126:16] wire [15:0] next_b = _next_b_T_7 ? b : _next_b_T_10; // @[Mux.scala:126:16] wire _state_T = next_b == 16'h0; // @[Mux.scala:126:16] wire _state_T_2 = _state_T & _state_T_1; // @[LoopConv.scala:1031:{27,35,48}] wire _state_T_4 = _state_T_2 & _state_T_3; // @[LoopConv.scala:1031:{35,56,69}] wire _state_T_6 = _state_T_4 & _state_T_5; // @[LoopConv.scala:1031:{56,77,89}] wire _state_T_7 = ~_state_T_6; // @[LoopConv.scala:1031:{19,77}] wire [15:0] next_och_max_1 = _next_och_max_T_1[15:0]; // @[Util.scala:39:28] wire [15:0] _next_och_T_7 = _next_och_T_6[15:0]; // @[Util.scala:41:15] wire _next_och_T_10 = _next_och_T_9 > {1'h0, next_och_max_1}; // @[Util.scala:39:28, :43:{11,17}] wire [15:0] _next_och_T_11 = _next_och_T_10 ? 16'h0 : _next_och_T_7; // @[Mux.scala:126:16] wire [15:0] next_och_1 = _next_och_T_11; // @[Mux.scala:126:16] wire _GEN_26 = next_och_1 == 16'h0; // @[Mux.scala:126:16] wire _next_b_T_11; // @[LoopConv.scala:1039:55] assign _next_b_T_11 = _GEN_26; // @[LoopConv.scala:1039:55] wire _state_T_9; // @[LoopConv.scala:1044:47] assign _state_T_9 = _GEN_26; // @[LoopConv.scala:1039:55, :1044:47] wire [15:0] next_b_max_1 = _next_b_max_T_1[15:0]; // @[Util.scala:39:28] wire [15:0] _next_b_T_13 = _next_b_T_12[15:0]; // @[Util.scala:41:15] wire _next_b_T_14 = ~_next_b_T_11; // @[Util.scala:42:8] wire _next_b_T_16 = _next_b_T_15 > {1'h0, next_b_max_1}; // @[Util.scala:39:28, :43:{11,17}] wire [15:0] _next_b_T_17 = _next_b_T_16 ? 16'h0 : _next_b_T_13; // @[Mux.scala:126:16] wire [15:0] next_b_1 = _next_b_T_14 ? b : _next_b_T_17; // @[Mux.scala:126:16] wire _state_T_8 = next_b_1 == 16'h0; // @[Mux.scala:126:16] wire _state_T_10 = _state_T_8 & _state_T_9; // @[LoopConv.scala:1044:{27,35,47}] wire [2:0] _state_T_11 = _state_T_10 ? 3'h4 : 3'h3; // @[LoopConv.scala:977:65, :1044:{19,35}] wire [1:0] _state_T_12 = io_req_bits_no_pool_0 ? 2'h1 : 2'h2; // @[LoopConv.scala:853:7, :1052:17] wire _T_1 = _command_p_io_in_ready & _command_p_io_in_valid_T_3; // @[Decoupled.scala:51:35] wire _T_2 = state == 3'h2; // @[LoopConv.scala:872:22, :1033:22] wire _T_3 = state == 3'h4; // @[LoopConv.scala:872:22, :1035:22] wire _T_4 = io_req_ready_0 & io_req_valid_0; // @[Decoupled.scala:51:35] wire _GEN_27 = _T_2 | _T_3; // @[LoopConv.scala:888:16, :1033:{22,43}, :1035:{22,44}, :1041:11] wire _GEN_28 = skip | ~_T_1; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[LoopConv.scala:853:7] if (reset) // @[LoopConv.scala:853:7] state <= 3'h0; // @[LoopConv.scala:872:22] else if (_T_4) // @[Decoupled.scala:51:35] state <= {1'h0, _state_T_12}; // @[LoopConv.scala:872:22, :1052:{11,17}] else if (skip) // @[LoopConv.scala:882:28] state <= 3'h0; // @[LoopConv.scala:872:22] else if (_T_1) // @[Decoupled.scala:51:35] state <= req_no_pool ? {2'h0, _state_T_7} : _T_2 ? 3'h3 : _T_3 ? 3'h0 : _state_T_11; // @[LoopConv.scala:872:22, :874:16, :977:65, :1020:24, :1031:{13,19}, :1033:{22,43}, :1034:13, :1035:{22,44}, :1036:13, :1044:{13,19}] if (_T_4) begin // @[Decoupled.scala:51:35] req_outer_bounds_batch_size <= io_req_bits_outer_bounds_batch_size_0; // @[LoopConv.scala:853:7, :874:16] req_outer_bounds_in_row_dim <= io_req_bits_outer_bounds_in_row_dim_0; // @[LoopConv.scala:853:7, :874:16] req_outer_bounds_in_col_dim <= io_req_bits_outer_bounds_in_col_dim_0; // @[LoopConv.scala:853:7, :874:16] req_outer_bounds_in_channels <= io_req_bits_outer_bounds_in_channels_0; // @[LoopConv.scala:853:7, :874:16] req_outer_bounds_out_channels <= io_req_bits_outer_bounds_out_channels_0; // @[LoopConv.scala:853:7, :874:16] req_outer_bounds_out_col_dim <= io_req_bits_outer_bounds_out_col_dim_0; // @[LoopConv.scala:853:7, :874:16] req_outer_bounds_out_row_dim <= io_req_bits_outer_bounds_out_row_dim_0; // @[LoopConv.scala:853:7, :874:16] req_outer_bounds_out_stride <= io_req_bits_outer_bounds_out_stride_0; // @[LoopConv.scala:853:7, :874:16] req_outer_bounds_in_stride <= io_req_bits_outer_bounds_in_stride_0; // @[LoopConv.scala:853:7, :874:16] req_outer_bounds_weight_stride <= io_req_bits_outer_bounds_weight_stride_0; // @[LoopConv.scala:853:7, :874:16] req_outer_bounds_pool_out_row_dim <= io_req_bits_outer_bounds_pool_out_row_dim_0; // @[LoopConv.scala:853:7, :874:16] req_outer_bounds_pool_out_col_dim <= io_req_bits_outer_bounds_pool_out_col_dim_0; // @[LoopConv.scala:853:7, :874:16] req_outer_bounds_stride <= io_req_bits_outer_bounds_stride_0; // @[LoopConv.scala:853:7, :874:16] req_outer_bounds_padding <= io_req_bits_outer_bounds_padding_0; // @[LoopConv.scala:853:7, :874:16] req_outer_bounds_kernel_dim <= io_req_bits_outer_bounds_kernel_dim_0; // @[LoopConv.scala:853:7, :874:16] req_outer_bounds_kernel_dilation <= io_req_bits_outer_bounds_kernel_dilation_0; // @[LoopConv.scala:853:7, :874:16] req_outer_bounds_pool_size <= io_req_bits_outer_bounds_pool_size_0; // @[LoopConv.scala:853:7, :874:16] req_outer_bounds_pool_stride <= io_req_bits_outer_bounds_pool_stride_0; // @[LoopConv.scala:853:7, :874:16] req_outer_bounds_pool_padding <= io_req_bits_outer_bounds_pool_padding_0; // @[LoopConv.scala:853:7, :874:16] req_inner_bounds_batches <= io_req_bits_inner_bounds_batches_0; // @[LoopConv.scala:853:7, :874:16] req_inner_bounds_porows <= io_req_bits_inner_bounds_porows_0; // @[LoopConv.scala:853:7, :874:16] req_inner_bounds_pocols <= io_req_bits_inner_bounds_pocols_0; // @[LoopConv.scala:853:7, :874:16] req_inner_bounds_pochs <= io_req_bits_inner_bounds_pochs_0; // @[LoopConv.scala:853:7, :874:16] req_inner_bounds_krows <= io_req_bits_inner_bounds_krows_0; // @[LoopConv.scala:853:7, :874:16] req_inner_bounds_kcols <= io_req_bits_inner_bounds_kcols_0; // @[LoopConv.scala:853:7, :874:16] req_inner_bounds_kchs <= io_req_bits_inner_bounds_kchs_0; // @[LoopConv.scala:853:7, :874:16] req_inner_bounds_lpad <= io_req_bits_inner_bounds_lpad_0; // @[LoopConv.scala:853:7, :874:16] req_inner_bounds_rpad <= io_req_bits_inner_bounds_rpad_0; // @[LoopConv.scala:853:7, :874:16] req_inner_bounds_upad <= io_req_bits_inner_bounds_upad_0; // @[LoopConv.scala:853:7, :874:16] req_inner_bounds_dpad <= io_req_bits_inner_bounds_dpad_0; // @[LoopConv.scala:853:7, :874:16] req_inner_bounds_plpad <= io_req_bits_inner_bounds_plpad_0; // @[LoopConv.scala:853:7, :874:16] req_inner_bounds_prad <= io_req_bits_inner_bounds_prad_0; // @[LoopConv.scala:853:7, :874:16] req_inner_bounds_pupad <= io_req_bits_inner_bounds_pupad_0; // @[LoopConv.scala:853:7, :874:16] req_inner_bounds_pdpad <= io_req_bits_inner_bounds_pdpad_0; // @[LoopConv.scala:853:7, :874:16] req_inner_bounds_orows <= io_req_bits_inner_bounds_orows_0; // @[LoopConv.scala:853:7, :874:16] req_inner_bounds_ocols <= io_req_bits_inner_bounds_ocols_0; // @[LoopConv.scala:853:7, :874:16] req_derived_params_ochs <= io_req_bits_derived_params_ochs_0; // @[LoopConv.scala:853:7, :874:16] req_derived_params_irows <= io_req_bits_derived_params_irows_0; // @[LoopConv.scala:853:7, :874:16] req_derived_params_icols <= io_req_bits_derived_params_icols_0; // @[LoopConv.scala:853:7, :874:16] req_derived_params_irows_unpadded <= io_req_bits_derived_params_irows_unpadded_0; // @[LoopConv.scala:853:7, :874:16] req_derived_params_icols_unpadded <= io_req_bits_derived_params_icols_unpadded_0; // @[LoopConv.scala:853:7, :874:16] req_derived_params_ichs <= io_req_bits_derived_params_ichs_0; // @[LoopConv.scala:853:7, :874:16] req_derived_params_out_channels_per_bank <= io_req_bits_derived_params_out_channels_per_bank_0; // @[LoopConv.scala:853:7, :874:16] req_derived_params_in_channels_per_bank <= io_req_bits_derived_params_in_channels_per_bank_0; // @[LoopConv.scala:853:7, :874:16] req_derived_params_bias_spad_stride <= io_req_bits_derived_params_bias_spad_stride_0; // @[LoopConv.scala:853:7, :874:16] req_derived_params_input_spad_stride <= io_req_bits_derived_params_input_spad_stride_0; // @[LoopConv.scala:853:7, :874:16] req_derived_params_weight_spad_stride <= io_req_bits_derived_params_weight_spad_stride_0; // @[LoopConv.scala:853:7, :874:16] req_addr_start <= io_req_bits_addr_start_0; // @[LoopConv.scala:853:7, :874:16] req_dram_addr <= io_req_bits_dram_addr_0; // @[LoopConv.scala:853:7, :874:16] req_no_pool <= io_req_bits_no_pool_0; // @[LoopConv.scala:853:7, :874:16] req_activation <= io_req_bits_activation_0; // @[LoopConv.scala:853:7, :874:16] req_trans_output_1203 <= io_req_bits_trans_output_1203_0; // @[LoopConv.scala:853:7, :874:16] req_loop_id <= io_req_bits_loop_id_0; // @[LoopConv.scala:853:7, :874:16] b <= 16'h0; // @[LoopConv.scala:885:14] orow <= 16'h0; // @[LoopConv.scala:886:17] ocol <= 16'h0; // @[LoopConv.scala:887:17] och <= 16'h0; // @[LoopConv.scala:888:16] end else begin // @[Decoupled.scala:51:35] if (_GEN_28) begin // @[LoopConv.scala:885:14, :888:16, :1017:15, :1019:36] end else if (req_no_pool) // @[LoopConv.scala:874:16] b <= next_b; // @[Mux.scala:126:16] else if (~_GEN_27) // @[LoopConv.scala:888:16, :1033:43, :1035:44, :1041:11] b <= next_b_1; // @[Mux.scala:126:16] if (skip | ~(_T_1 & req_no_pool)) begin // @[Decoupled.scala:51:35] end else begin // @[LoopConv.scala:887:17, :1017:15, :1019:36] orow <= next_orow; // @[Mux.scala:126:16] ocol <= next_ocol; // @[Mux.scala:126:16] end if (_GEN_28) begin // @[LoopConv.scala:888:16, :1017:15, :1019:36] end else if (req_no_pool) // @[LoopConv.scala:874:16] och <= next_och; // @[Mux.scala:126:16] else if (~_GEN_27) // @[LoopConv.scala:888:16, :1033:43, :1035:44, :1041:11] och <= next_och_1; // @[Mux.scala:126:16] end always @(posedge) Pipeline_15 command_p ( // @[LoopConv.scala:917:25] .clock (clock), .reset (reset), .io_in_ready (_command_p_io_in_ready), .io_in_valid (_command_p_io_in_valid_T_3), // @[LoopConv.scala:976:52] .io_in_bits_cmd_inst_funct (_command_p_io_in_bits_cmd_T_9_inst_funct), // @[LoopConv.scala:977:65] .io_in_bits_cmd_rs1 (_command_p_io_in_bits_cmd_T_9_rs1), // @[LoopConv.scala:977:65] .io_in_bits_cmd_rs2 (_command_p_io_in_bits_cmd_T_9_rs2), // @[LoopConv.scala:977:65] .io_in_bits_dram_addr (dram_addr), // @[LoopConv.scala:894:33] .io_in_bits_spad_addr (spad_addr), // @[LoopConv.scala:895:137] .io_in_bits_pool_dram_addr (pool_dram_addr), // @[LoopConv.scala:897:38] .io_in_bits_pool_spad_addr (pool_spad_addr), // @[LoopConv.scala:898:105] .io_in_bits_channels (J), // @[LoopConv.scala:902:14] .io_in_bits_is_pool (_command_p_io_in_bits_is_pool_T), // @[LoopConv.scala:982:41] .io_in_bits_I (I), // @[LoopConv.scala:901:14] .io_in_bits_J (J), // @[LoopConv.scala:902:14] .io_out_ready (_command_p_io_out_ready_T_1), // @[LoopConv.scala:991:42] .io_out_valid (_command_p_io_out_valid), .io_out_bits_cmd_inst_funct (_command_p_io_out_bits_cmd_inst_funct), .io_out_bits_cmd_inst_rs2 (io_cmd_bits_inst_rs2_0), .io_out_bits_cmd_inst_rs1 (io_cmd_bits_inst_rs1_0), .io_out_bits_cmd_inst_xd (io_cmd_bits_inst_xd_0), .io_out_bits_cmd_inst_xs1 (io_cmd_bits_inst_xs1_0), .io_out_bits_cmd_inst_xs2 (io_cmd_bits_inst_xs2_0), .io_out_bits_cmd_inst_rd (io_cmd_bits_inst_rd_0), .io_out_bits_cmd_inst_opcode (io_cmd_bits_inst_opcode_0), .io_out_bits_cmd_rs1 (_command_p_io_out_bits_cmd_rs1), .io_out_bits_cmd_rs2 (_command_p_io_out_bits_cmd_rs2), .io_out_bits_cmd_status_debug (io_cmd_bits_status_debug_0), .io_out_bits_cmd_status_cease (io_cmd_bits_status_cease_0), .io_out_bits_cmd_status_wfi (io_cmd_bits_status_wfi_0), .io_out_bits_cmd_status_isa (io_cmd_bits_status_isa_0), .io_out_bits_cmd_status_dprv (io_cmd_bits_status_dprv_0), .io_out_bits_cmd_status_dv (io_cmd_bits_status_dv_0), .io_out_bits_cmd_status_prv (io_cmd_bits_status_prv_0), .io_out_bits_cmd_status_v (io_cmd_bits_status_v_0), .io_out_bits_cmd_status_sd (io_cmd_bits_status_sd_0), .io_out_bits_cmd_status_zero2 (io_cmd_bits_status_zero2_0), .io_out_bits_cmd_status_mpv (io_cmd_bits_status_mpv_0), .io_out_bits_cmd_status_gva (io_cmd_bits_status_gva_0), .io_out_bits_cmd_status_mbe (io_cmd_bits_status_mbe_0), .io_out_bits_cmd_status_sbe (io_cmd_bits_status_sbe_0), .io_out_bits_cmd_status_sxl (io_cmd_bits_status_sxl_0), .io_out_bits_cmd_status_uxl (io_cmd_bits_status_uxl_0), .io_out_bits_cmd_status_sd_rv32 (io_cmd_bits_status_sd_rv32_0), .io_out_bits_cmd_status_zero1 (io_cmd_bits_status_zero1_0), .io_out_bits_cmd_status_tsr (io_cmd_bits_status_tsr_0), .io_out_bits_cmd_status_tw (io_cmd_bits_status_tw_0), .io_out_bits_cmd_status_tvm (io_cmd_bits_status_tvm_0), .io_out_bits_cmd_status_mxr (io_cmd_bits_status_mxr_0), .io_out_bits_cmd_status_sum (io_cmd_bits_status_sum_0), .io_out_bits_cmd_status_mprv (io_cmd_bits_status_mprv_0), .io_out_bits_cmd_status_xs (io_cmd_bits_status_xs_0), .io_out_bits_cmd_status_fs (io_cmd_bits_status_fs_0), .io_out_bits_cmd_status_mpp (io_cmd_bits_status_mpp_0), .io_out_bits_cmd_status_vs (io_cmd_bits_status_vs_0), .io_out_bits_cmd_status_spp (io_cmd_bits_status_spp_0), .io_out_bits_cmd_status_mpie (io_cmd_bits_status_mpie_0), .io_out_bits_cmd_status_ube (io_cmd_bits_status_ube_0), .io_out_bits_cmd_status_spie (io_cmd_bits_status_spie_0), .io_out_bits_cmd_status_upie (io_cmd_bits_status_upie_0), .io_out_bits_cmd_status_mie (io_cmd_bits_status_mie_0), .io_out_bits_cmd_status_hie (io_cmd_bits_status_hie_0), .io_out_bits_cmd_status_sie (io_cmd_bits_status_sie_0), .io_out_bits_cmd_status_uie (io_cmd_bits_status_uie_0), .io_out_bits_dram_addr (_command_p_io_out_bits_dram_addr), .io_out_bits_spad_addr (_command_p_io_out_bits_spad_addr), .io_out_bits_pool_dram_addr (_command_p_io_out_bits_pool_dram_addr), .io_out_bits_pool_spad_addr (_command_p_io_out_bits_pool_spad_addr), .io_out_bits_channels (_command_p_io_out_bits_channels), .io_out_bits_is_pool (_command_p_io_out_bits_is_pool), .io_out_bits_I (_command_p_io_out_bits_I), .io_out_bits_J (_command_p_io_out_bits_J), .io_busy (_command_p_io_busy) ); // @[LoopConv.scala:917:25] assign io_cmd_bits_inst_funct_0 = _command_p_io_out_bits_cmd_inst_funct; // @[LoopConv.scala:853:7, :917:25] assign io_req_ready = io_req_ready_0; // @[LoopConv.scala:853:7] assign io_cmd_valid = io_cmd_valid_0; // @[LoopConv.scala:853:7] assign io_cmd_bits_inst_funct = io_cmd_bits_inst_funct_0; // @[LoopConv.scala:853:7] assign io_cmd_bits_inst_rs2 = io_cmd_bits_inst_rs2_0; // @[LoopConv.scala:853:7] assign io_cmd_bits_inst_rs1 = io_cmd_bits_inst_rs1_0; // @[LoopConv.scala:853:7] assign io_cmd_bits_inst_xd = io_cmd_bits_inst_xd_0; // @[LoopConv.scala:853:7] assign io_cmd_bits_inst_xs1 = io_cmd_bits_inst_xs1_0; // @[LoopConv.scala:853:7] assign io_cmd_bits_inst_xs2 = io_cmd_bits_inst_xs2_0; // @[LoopConv.scala:853:7] assign io_cmd_bits_inst_rd = io_cmd_bits_inst_rd_0; // @[LoopConv.scala:853:7] assign io_cmd_bits_inst_opcode = io_cmd_bits_inst_opcode_0; // @[LoopConv.scala:853:7] assign io_cmd_bits_rs1 = io_cmd_bits_rs1_0; // @[LoopConv.scala:853:7] assign io_cmd_bits_rs2 = io_cmd_bits_rs2_0; // @[LoopConv.scala:853:7] assign io_cmd_bits_status_debug = io_cmd_bits_status_debug_0; // @[LoopConv.scala:853:7] assign io_cmd_bits_status_cease = io_cmd_bits_status_cease_0; // @[LoopConv.scala:853:7] assign io_cmd_bits_status_wfi = io_cmd_bits_status_wfi_0; // @[LoopConv.scala:853:7] assign io_cmd_bits_status_isa = io_cmd_bits_status_isa_0; // @[LoopConv.scala:853:7] assign io_cmd_bits_status_dprv = io_cmd_bits_status_dprv_0; // @[LoopConv.scala:853:7] assign io_cmd_bits_status_dv = io_cmd_bits_status_dv_0; // @[LoopConv.scala:853:7] assign io_cmd_bits_status_prv = io_cmd_bits_status_prv_0; // @[LoopConv.scala:853:7] assign io_cmd_bits_status_v = io_cmd_bits_status_v_0; // @[LoopConv.scala:853:7] assign io_cmd_bits_status_sd = io_cmd_bits_status_sd_0; // @[LoopConv.scala:853:7] assign io_cmd_bits_status_zero2 = io_cmd_bits_status_zero2_0; // @[LoopConv.scala:853:7] assign io_cmd_bits_status_mpv = io_cmd_bits_status_mpv_0; // @[LoopConv.scala:853:7] assign io_cmd_bits_status_gva = io_cmd_bits_status_gva_0; // @[LoopConv.scala:853:7] assign io_cmd_bits_status_mbe = io_cmd_bits_status_mbe_0; // @[LoopConv.scala:853:7] assign io_cmd_bits_status_sbe = io_cmd_bits_status_sbe_0; // @[LoopConv.scala:853:7] assign io_cmd_bits_status_sxl = io_cmd_bits_status_sxl_0; // @[LoopConv.scala:853:7] assign io_cmd_bits_status_uxl = io_cmd_bits_status_uxl_0; // @[LoopConv.scala:853:7] assign io_cmd_bits_status_sd_rv32 = io_cmd_bits_status_sd_rv32_0; // @[LoopConv.scala:853:7] assign io_cmd_bits_status_zero1 = io_cmd_bits_status_zero1_0; // @[LoopConv.scala:853:7] assign io_cmd_bits_status_tsr = io_cmd_bits_status_tsr_0; // @[LoopConv.scala:853:7] assign io_cmd_bits_status_tw = io_cmd_bits_status_tw_0; // @[LoopConv.scala:853:7] assign io_cmd_bits_status_tvm = io_cmd_bits_status_tvm_0; // @[LoopConv.scala:853:7] assign io_cmd_bits_status_mxr = io_cmd_bits_status_mxr_0; // @[LoopConv.scala:853:7] assign io_cmd_bits_status_sum = io_cmd_bits_status_sum_0; // @[LoopConv.scala:853:7] assign io_cmd_bits_status_mprv = io_cmd_bits_status_mprv_0; // @[LoopConv.scala:853:7] assign io_cmd_bits_status_xs = io_cmd_bits_status_xs_0; // @[LoopConv.scala:853:7] assign io_cmd_bits_status_fs = io_cmd_bits_status_fs_0; // @[LoopConv.scala:853:7] assign io_cmd_bits_status_mpp = io_cmd_bits_status_mpp_0; // @[LoopConv.scala:853:7] assign io_cmd_bits_status_vs = io_cmd_bits_status_vs_0; // @[LoopConv.scala:853:7] assign io_cmd_bits_status_spp = io_cmd_bits_status_spp_0; // @[LoopConv.scala:853:7] assign io_cmd_bits_status_mpie = io_cmd_bits_status_mpie_0; // @[LoopConv.scala:853:7] assign io_cmd_bits_status_ube = io_cmd_bits_status_ube_0; // @[LoopConv.scala:853:7] assign io_cmd_bits_status_spie = io_cmd_bits_status_spie_0; // @[LoopConv.scala:853:7] assign io_cmd_bits_status_upie = io_cmd_bits_status_upie_0; // @[LoopConv.scala:853:7] assign io_cmd_bits_status_mie = io_cmd_bits_status_mie_0; // @[LoopConv.scala:853:7] assign io_cmd_bits_status_hie = io_cmd_bits_status_hie_0; // @[LoopConv.scala:853:7] assign io_cmd_bits_status_sie = io_cmd_bits_status_sie_0; // @[LoopConv.scala:853:7] assign io_cmd_bits_status_uie = io_cmd_bits_status_uie_0; // @[LoopConv.scala:853:7] assign io_idle = io_idle_0; // @[LoopConv.scala:853:7] assign io_loop_id = io_loop_id_0; // @[LoopConv.scala:853:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File InputUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{FlowRoutingBundle} import constellation.noc.{HasNoCParams} class AbstractInputUnitIO( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams], )(implicit val p: Parameters) extends Bundle with HasRouterOutputParams { val nodeId = cParam.destId val router_req = Decoupled(new RouteComputerReq) val router_resp = Input(new RouteComputerResp(outParams, egressParams)) val vcalloc_req = Decoupled(new VCAllocReq(cParam, outParams, egressParams)) val vcalloc_resp = Input(new VCAllocResp(outParams, egressParams)) val out_credit_available = Input(MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) })) val salloc_req = Vec(cParam.destSpeedup, Decoupled(new SwitchAllocReq(outParams, egressParams))) val out = Vec(cParam.destSpeedup, Valid(new SwitchBundle(outParams, egressParams))) val debug = Output(new Bundle { val va_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) val sa_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) }) val block = Input(Bool()) } abstract class AbstractInputUnit( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams] )(implicit val p: Parameters) extends Module with HasRouterOutputParams with HasNoCParams { val nodeId = cParam.destId def io: AbstractInputUnitIO } class InputBuffer(cParam: ChannelParams)(implicit p: Parameters) extends Module { val nVirtualChannels = cParam.nVirtualChannels val io = IO(new Bundle { val enq = Flipped(Vec(cParam.srcSpeedup, Valid(new Flit(cParam.payloadBits)))) val deq = Vec(cParam.nVirtualChannels, Decoupled(new BaseFlit(cParam.payloadBits))) }) val useOutputQueues = cParam.useOutputQueues val delims = if (useOutputQueues) { cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize else 0).scanLeft(0)(_+_) } else { // If no queuing, have to add an additional slot since head == tail implies empty // TODO this should be fixed, should use all slots available cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize + 1 else 0).scanLeft(0)(_+_) } val starts = delims.dropRight(1).zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val ends = delims.tail.zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val fullSize = delims.last // Ugly case. Use multiple queues if ((cParam.srcSpeedup > 1 || cParam.destSpeedup > 1 || fullSize <= 1) || !cParam.unifiedBuffer) { require(useOutputQueues) val qs = cParam.virtualChannelParams.map(v => Module(new Queue(new BaseFlit(cParam.payloadBits), v.bufferSize))) qs.zipWithIndex.foreach { case (q,i) => val sel = io.enq.map(f => f.valid && f.bits.virt_channel_id === i.U) q.io.enq.valid := sel.orR q.io.enq.bits.head := Mux1H(sel, io.enq.map(_.bits.head)) q.io.enq.bits.tail := Mux1H(sel, io.enq.map(_.bits.tail)) q.io.enq.bits.payload := Mux1H(sel, io.enq.map(_.bits.payload)) io.deq(i) <> q.io.deq } } else { val mem = Mem(fullSize, new BaseFlit(cParam.payloadBits)) val heads = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val tails = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val empty = (heads zip tails).map(t => t._1 === t._2) val qs = Seq.fill(nVirtualChannels) { Module(new Queue(new BaseFlit(cParam.payloadBits), 1, pipe=true)) } qs.foreach(_.io.enq.valid := false.B) qs.foreach(_.io.enq.bits := DontCare) val vc_sel = UIntToOH(io.enq(0).bits.virt_channel_id) val flit = Wire(new BaseFlit(cParam.payloadBits)) val direct_to_q = (Mux1H(vc_sel, qs.map(_.io.enq.ready)) && Mux1H(vc_sel, empty)) && useOutputQueues.B flit.head := io.enq(0).bits.head flit.tail := io.enq(0).bits.tail flit.payload := io.enq(0).bits.payload when (io.enq(0).valid && !direct_to_q) { val tail = tails(io.enq(0).bits.virt_channel_id) mem.write(tail, flit) tails(io.enq(0).bits.virt_channel_id) := Mux( tail === Mux1H(vc_sel, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(vc_sel, starts.map(_.U)), tail + 1.U) } .elsewhen (io.enq(0).valid && direct_to_q) { for (i <- 0 until nVirtualChannels) { when (io.enq(0).bits.virt_channel_id === i.U) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := flit } } } if (useOutputQueues) { val can_to_q = (0 until nVirtualChannels).map { i => !empty(i) && qs(i).io.enq.ready } val to_q_oh = PriorityEncoderOH(can_to_q) val to_q = OHToUInt(to_q_oh) when (can_to_q.orR) { val head = Mux1H(to_q_oh, heads) heads(to_q) := Mux( head === Mux1H(to_q_oh, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(to_q_oh, starts.map(_.U)), head + 1.U) for (i <- 0 until nVirtualChannels) { when (to_q_oh(i)) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := mem.read(head) } } } for (i <- 0 until nVirtualChannels) { io.deq(i) <> qs(i).io.deq } } else { qs.map(_.io.deq.ready := false.B) val ready_sel = io.deq.map(_.ready) val fire = io.deq.map(_.fire) assert(PopCount(fire) <= 1.U) val head = Mux1H(fire, heads) when (fire.orR) { val fire_idx = OHToUInt(fire) heads(fire_idx) := Mux( head === Mux1H(fire, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(fire, starts.map(_.U)), head + 1.U) } val read_flit = mem.read(head) for (i <- 0 until nVirtualChannels) { io.deq(i).valid := !empty(i) io.deq(i).bits := read_flit } } } } class InputUnit(cParam: ChannelParams, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams], combineRCVA: Boolean, combineSAST: Boolean ) (implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) { val nVirtualChannels = cParam.nVirtualChannels val virtualChannelParams = cParam.virtualChannelParams class InputUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) { val in = Flipped(new Channel(cParam.asInstanceOf[ChannelParams])) } val io = IO(new InputUnitIO) val g_i :: g_r :: g_v :: g_a :: g_c :: Nil = Enum(5) class InputState extends Bundle { val g = UInt(3.W) val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) val flow = new FlowRoutingBundle val fifo_deps = UInt(nVirtualChannels.W) } val input_buffer = Module(new InputBuffer(cParam)) for (i <- 0 until cParam.srcSpeedup) { input_buffer.io.enq(i) := io.in.flit(i) } input_buffer.io.deq.foreach(_.ready := false.B) val route_arbiter = Module(new Arbiter( new RouteComputerReq, nVirtualChannels )) io.router_req <> route_arbiter.io.out val states = Reg(Vec(nVirtualChannels, new InputState)) val anyFifo = cParam.possibleFlows.map(_.fifo).reduce(_||_) val allFifo = cParam.possibleFlows.map(_.fifo).reduce(_&&_) if (anyFifo) { val idle_mask = VecInit(states.map(_.g === g_i)).asUInt for (s <- states) for (i <- 0 until nVirtualChannels) s.fifo_deps := s.fifo_deps & ~idle_mask } for (i <- 0 until cParam.srcSpeedup) { when (io.in.flit(i).fire && io.in.flit(i).bits.head) { val id = io.in.flit(i).bits.virt_channel_id assert(id < nVirtualChannels.U) assert(states(id).g === g_i) val at_dest = io.in.flit(i).bits.flow.egress_node === nodeId.U states(id).g := Mux(at_dest, g_v, g_r) states(id).vc_sel.foreach(_.foreach(_ := false.B)) for (o <- 0 until nEgress) { when (o.U === io.in.flit(i).bits.flow.egress_node_id) { states(id).vc_sel(o+nOutputs)(0) := true.B } } states(id).flow := io.in.flit(i).bits.flow if (anyFifo) { val fifo = cParam.possibleFlows.filter(_.fifo).map(_.isFlow(io.in.flit(i).bits.flow)).toSeq.orR states(id).fifo_deps := VecInit(states.zipWithIndex.map { case (s, j) => s.g =/= g_i && s.flow.asUInt === io.in.flit(i).bits.flow.asUInt && j.U =/= id }).asUInt } } } (route_arbiter.io.in zip states).zipWithIndex.map { case ((i,s),idx) => if (virtualChannelParams(idx).traversable) { i.valid := s.g === g_r i.bits.flow := s.flow i.bits.src_virt_id := idx.U when (i.fire) { s.g := g_v } } else { i.valid := false.B i.bits := DontCare } } when (io.router_req.fire) { val id = io.router_req.bits.src_virt_id assert(states(id).g === g_r) states(id).g := g_v for (i <- 0 until nVirtualChannels) { when (i.U === id) { states(i).vc_sel := io.router_resp.vc_sel } } } val mask = RegInit(0.U(nVirtualChannels.W)) val vcalloc_reqs = Wire(Vec(nVirtualChannels, new VCAllocReq(cParam, outParams, egressParams))) val vcalloc_vals = Wire(Vec(nVirtualChannels, Bool())) val vcalloc_filter = PriorityEncoderOH(Cat(vcalloc_vals.asUInt, vcalloc_vals.asUInt & ~mask)) val vcalloc_sel = vcalloc_filter(nVirtualChannels-1,0) | (vcalloc_filter >> nVirtualChannels) // Prioritize incoming packetes when (io.router_req.fire) { mask := (1.U << io.router_req.bits.src_virt_id) - 1.U } .elsewhen (vcalloc_vals.orR) { mask := Mux1H(vcalloc_sel, (0 until nVirtualChannels).map { w => ~(0.U((w+1).W)) }) } io.vcalloc_req.valid := vcalloc_vals.orR io.vcalloc_req.bits := Mux1H(vcalloc_sel, vcalloc_reqs) states.zipWithIndex.map { case (s,idx) => if (virtualChannelParams(idx).traversable) { vcalloc_vals(idx) := s.g === g_v && s.fifo_deps === 0.U vcalloc_reqs(idx).in_vc := idx.U vcalloc_reqs(idx).vc_sel := s.vc_sel vcalloc_reqs(idx).flow := s.flow when (vcalloc_vals(idx) && vcalloc_sel(idx) && io.vcalloc_req.ready) { s.g := g_a } if (combineRCVA) { when (route_arbiter.io.in(idx).fire) { vcalloc_vals(idx) := true.B vcalloc_reqs(idx).vc_sel := io.router_resp.vc_sel } } } else { vcalloc_vals(idx) := false.B vcalloc_reqs(idx) := DontCare } } io.debug.va_stall := PopCount(vcalloc_vals) - io.vcalloc_req.ready when (io.vcalloc_req.fire) { for (i <- 0 until nVirtualChannels) { when (vcalloc_sel(i)) { states(i).vc_sel := io.vcalloc_resp.vc_sel states(i).g := g_a if (!combineRCVA) { assert(states(i).g === g_v) } } } } val salloc_arb = Module(new SwitchArbiter( nVirtualChannels, cParam.destSpeedup, outParams, egressParams )) (states zip salloc_arb.io.in).zipWithIndex.map { case ((s,r),i) => if (virtualChannelParams(i).traversable) { val credit_available = (s.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U r.valid := s.g === g_a && credit_available && input_buffer.io.deq(i).valid r.bits.vc_sel := s.vc_sel val deq_tail = input_buffer.io.deq(i).bits.tail r.bits.tail := deq_tail when (r.fire && deq_tail) { s.g := g_i } input_buffer.io.deq(i).ready := r.ready } else { r.valid := false.B r.bits := DontCare } } io.debug.sa_stall := PopCount(salloc_arb.io.in.map(r => r.valid && !r.ready)) io.salloc_req <> salloc_arb.io.out when (io.block) { salloc_arb.io.out.foreach(_.ready := false.B) io.salloc_req.foreach(_.valid := false.B) } class OutBundle extends Bundle { val valid = Bool() val vid = UInt(virtualChannelBits.W) val out_vid = UInt(log2Up(allOutParams.map(_.nVirtualChannels).max).W) val flit = new Flit(cParam.payloadBits) } val salloc_outs = if (combineSAST) { Wire(Vec(cParam.destSpeedup, new OutBundle)) } else { Reg(Vec(cParam.destSpeedup, new OutBundle)) } io.in.credit_return := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire, salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_|_) io.in.vc_free := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire && Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)), salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_|_) for (i <- 0 until cParam.destSpeedup) { val salloc_out = salloc_outs(i) salloc_out.valid := salloc_arb.io.out(i).fire salloc_out.vid := OHToUInt(salloc_arb.io.chosen_oh(i)) val vc_sel = Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.vc_sel)) val channel_oh = vc_sel.map(_.reduce(_||_)).toSeq val virt_channel = Mux1H(channel_oh, vc_sel.map(v => OHToUInt(v)).toSeq) when (salloc_arb.io.out(i).fire) { salloc_out.out_vid := virt_channel salloc_out.flit.payload := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.payload)) salloc_out.flit.head := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.head)) salloc_out.flit.tail := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)) salloc_out.flit.flow := Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.flow)) } .otherwise { salloc_out.out_vid := DontCare salloc_out.flit := DontCare } salloc_out.flit.virt_channel_id := DontCare // this gets set in the switch io.out(i).valid := salloc_out.valid io.out(i).bits.flit := salloc_out.flit io.out(i).bits.out_virt_channel := salloc_out.out_vid } def filterVCSel(sel: MixedVec[Vec[Bool]], srcV: Int) = { if (virtualChannelParams(srcV).traversable) { outParams.zipWithIndex.map { case (oP, oI) => (0 until oP.nVirtualChannels).map { oV => var allow = false virtualChannelParams(srcV).possibleFlows.foreach { pI => allow = allow || routingRelation( cParam.channelRoutingInfos(srcV), oP.channelRoutingInfos(oV), pI ) } if (!allow) sel(oI)(oV) := false.B } } } } (0 until nVirtualChannels).map { i => if (!virtualChannelParams(i).traversable) states(i) := DontCare filterVCSel(states(i).vc_sel, i) } when (reset.asBool) { states.foreach(_.g := g_i) } }
module InputUnit_24( // @[InputUnit.scala:158:7] input clock, // @[InputUnit.scala:158:7] input reset, // @[InputUnit.scala:158:7] output [4:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14] output [5:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14] output [2:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [5:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14] output [2:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_3, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_8, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_9, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_10, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_11, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_12, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_13, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_14, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_15, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_16, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_17, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_18, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_19, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_20, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_21, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_18, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_19, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_20, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_21, // @[InputUnit.scala:170:14] input io_vcalloc_req_ready, // @[InputUnit.scala:170:14] output io_vcalloc_req_valid, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_3, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_8, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_9, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_10, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_11, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_12, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_13, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_14, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_15, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_16, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_17, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_18, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_19, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_20, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_21, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_18, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_19, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_20, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_21, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_2, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_3, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_8, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_9, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_10, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_11, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_12, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_13, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_14, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_15, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_16, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_17, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_18, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_19, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_20, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_21, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_18, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_19, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_20, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_21, // @[InputUnit.scala:170:14] input io_out_credit_available_1_2, // @[InputUnit.scala:170:14] input io_out_credit_available_1_3, // @[InputUnit.scala:170:14] input io_out_credit_available_1_8, // @[InputUnit.scala:170:14] input io_out_credit_available_1_9, // @[InputUnit.scala:170:14] input io_out_credit_available_1_10, // @[InputUnit.scala:170:14] input io_out_credit_available_1_11, // @[InputUnit.scala:170:14] input io_out_credit_available_1_12, // @[InputUnit.scala:170:14] input io_out_credit_available_1_13, // @[InputUnit.scala:170:14] input io_out_credit_available_1_14, // @[InputUnit.scala:170:14] input io_out_credit_available_1_15, // @[InputUnit.scala:170:14] input io_out_credit_available_1_16, // @[InputUnit.scala:170:14] input io_out_credit_available_1_17, // @[InputUnit.scala:170:14] input io_out_credit_available_1_18, // @[InputUnit.scala:170:14] input io_out_credit_available_1_19, // @[InputUnit.scala:170:14] input io_out_credit_available_1_20, // @[InputUnit.scala:170:14] input io_out_credit_available_1_21, // @[InputUnit.scala:170:14] input io_out_credit_available_0_18, // @[InputUnit.scala:170:14] input io_out_credit_available_0_19, // @[InputUnit.scala:170:14] input io_out_credit_available_0_20, // @[InputUnit.scala:170:14] input io_out_credit_available_0_21, // @[InputUnit.scala:170:14] input io_salloc_req_0_ready, // @[InputUnit.scala:170:14] output io_salloc_req_0_valid, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_8, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_9, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_10, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_11, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_12, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_13, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_14, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_15, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_16, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_17, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_18, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_19, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_20, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_21, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_8, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_9, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_10, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_11, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_12, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_13, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_14, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_15, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_16, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_17, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_18, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_19, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_20, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_21, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14] output io_out_0_valid, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14] output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14] output [5:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [5:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14] output [4:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14] output [4:0] io_debug_va_stall, // @[InputUnit.scala:170:14] output [4:0] io_debug_sa_stall, // @[InputUnit.scala:170:14] input io_in_flit_0_valid, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14] input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14] input [5:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] input [5:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input [4:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14] output [21:0] io_in_credit_return, // @[InputUnit.scala:170:14] output [21:0] io_in_vc_free // @[InputUnit.scala:170:14] ); wire vcalloc_vals_21; // @[InputUnit.scala:266:32] wire vcalloc_vals_20; // @[InputUnit.scala:266:32] wire vcalloc_vals_19; // @[InputUnit.scala:266:32] wire vcalloc_vals_18; // @[InputUnit.scala:266:32] wire vcalloc_vals_17; // @[InputUnit.scala:266:32] wire vcalloc_vals_16; // @[InputUnit.scala:266:32] wire vcalloc_vals_15; // @[InputUnit.scala:266:32] wire vcalloc_vals_14; // @[InputUnit.scala:266:32] wire vcalloc_vals_13; // @[InputUnit.scala:266:32] wire vcalloc_vals_12; // @[InputUnit.scala:266:32] wire vcalloc_vals_11; // @[InputUnit.scala:266:32] wire vcalloc_vals_10; // @[InputUnit.scala:266:32] wire vcalloc_vals_9; // @[InputUnit.scala:266:32] wire vcalloc_vals_8; // @[InputUnit.scala:266:32] wire vcalloc_vals_3; // @[InputUnit.scala:266:32] wire vcalloc_vals_2; // @[InputUnit.scala:266:32] wire _salloc_arb_io_in_2_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_3_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_8_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_9_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_10_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_11_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_12_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_13_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_14_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_15_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_16_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_17_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_18_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_19_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_20_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_21_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26] wire [21:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26] wire _route_arbiter_io_in_3_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_8_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_9_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_10_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_11_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_12_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_13_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_14_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_15_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_16_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_17_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_18_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_19_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_20_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_21_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29] wire [4:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29] wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_5_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_6_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_7_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_8_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_8_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_8_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_8_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_9_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_9_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_9_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_9_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_10_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_10_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_10_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_10_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_11_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_11_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_11_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_11_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_12_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_12_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_12_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_12_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_13_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_13_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_13_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_13_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_14_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_14_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_14_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_14_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_15_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_15_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_15_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_15_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_16_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_16_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_16_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_16_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_17_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_17_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_17_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_17_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_18_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_18_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_18_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_18_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_19_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_19_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_19_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_19_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_20_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_20_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_20_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_20_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_21_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_21_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_21_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_21_bits_payload; // @[InputUnit.scala:181:28] reg [2:0] states_2_g; // @[InputUnit.scala:192:19] reg states_2_vc_sel_1_2; // @[InputUnit.scala:192:19] reg [3:0] states_2_flow_vnet_id; // @[InputUnit.scala:192:19] reg [5:0] states_2_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_2_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [5:0] states_2_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_2_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_3_g; // @[InputUnit.scala:192:19] reg states_3_vc_sel_1_2; // @[InputUnit.scala:192:19] reg states_3_vc_sel_1_3; // @[InputUnit.scala:192:19] reg [3:0] states_3_flow_vnet_id; // @[InputUnit.scala:192:19] reg [5:0] states_3_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_3_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [5:0] states_3_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_3_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_8_g; // @[InputUnit.scala:192:19] reg states_8_vc_sel_1_8; // @[InputUnit.scala:192:19] reg [3:0] states_8_flow_vnet_id; // @[InputUnit.scala:192:19] reg [5:0] states_8_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_8_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [5:0] states_8_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_8_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_9_g; // @[InputUnit.scala:192:19] reg states_9_vc_sel_1_8; // @[InputUnit.scala:192:19] reg states_9_vc_sel_1_9; // @[InputUnit.scala:192:19] reg [3:0] states_9_flow_vnet_id; // @[InputUnit.scala:192:19] reg [5:0] states_9_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_9_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [5:0] states_9_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_9_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_10_g; // @[InputUnit.scala:192:19] reg states_10_vc_sel_1_10; // @[InputUnit.scala:192:19] reg [3:0] states_10_flow_vnet_id; // @[InputUnit.scala:192:19] reg [5:0] states_10_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_10_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [5:0] states_10_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_10_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_11_g; // @[InputUnit.scala:192:19] reg states_11_vc_sel_1_10; // @[InputUnit.scala:192:19] reg states_11_vc_sel_1_11; // @[InputUnit.scala:192:19] reg [3:0] states_11_flow_vnet_id; // @[InputUnit.scala:192:19] reg [5:0] states_11_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_11_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [5:0] states_11_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_11_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_12_g; // @[InputUnit.scala:192:19] reg states_12_vc_sel_1_12; // @[InputUnit.scala:192:19] reg [3:0] states_12_flow_vnet_id; // @[InputUnit.scala:192:19] reg [5:0] states_12_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_12_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [5:0] states_12_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_12_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_13_g; // @[InputUnit.scala:192:19] reg states_13_vc_sel_1_12; // @[InputUnit.scala:192:19] reg states_13_vc_sel_1_13; // @[InputUnit.scala:192:19] reg [3:0] states_13_flow_vnet_id; // @[InputUnit.scala:192:19] reg [5:0] states_13_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_13_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [5:0] states_13_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_13_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_14_g; // @[InputUnit.scala:192:19] reg states_14_vc_sel_1_14; // @[InputUnit.scala:192:19] reg [3:0] states_14_flow_vnet_id; // @[InputUnit.scala:192:19] reg [5:0] states_14_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_14_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [5:0] states_14_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_14_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_15_g; // @[InputUnit.scala:192:19] reg states_15_vc_sel_1_14; // @[InputUnit.scala:192:19] reg states_15_vc_sel_1_15; // @[InputUnit.scala:192:19] reg [3:0] states_15_flow_vnet_id; // @[InputUnit.scala:192:19] reg [5:0] states_15_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_15_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [5:0] states_15_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_15_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_16_g; // @[InputUnit.scala:192:19] reg states_16_vc_sel_1_16; // @[InputUnit.scala:192:19] reg [3:0] states_16_flow_vnet_id; // @[InputUnit.scala:192:19] reg [5:0] states_16_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_16_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [5:0] states_16_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_16_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_17_g; // @[InputUnit.scala:192:19] reg states_17_vc_sel_1_16; // @[InputUnit.scala:192:19] reg states_17_vc_sel_1_17; // @[InputUnit.scala:192:19] reg [3:0] states_17_flow_vnet_id; // @[InputUnit.scala:192:19] reg [5:0] states_17_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_17_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [5:0] states_17_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_17_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_18_g; // @[InputUnit.scala:192:19] reg states_18_vc_sel_1_18; // @[InputUnit.scala:192:19] reg states_18_vc_sel_0_18; // @[InputUnit.scala:192:19] reg states_18_vc_sel_0_19; // @[InputUnit.scala:192:19] reg states_18_vc_sel_0_20; // @[InputUnit.scala:192:19] reg states_18_vc_sel_0_21; // @[InputUnit.scala:192:19] reg [3:0] states_18_flow_vnet_id; // @[InputUnit.scala:192:19] reg [5:0] states_18_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_18_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [5:0] states_18_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_18_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_19_g; // @[InputUnit.scala:192:19] reg states_19_vc_sel_1_18; // @[InputUnit.scala:192:19] reg states_19_vc_sel_1_19; // @[InputUnit.scala:192:19] reg states_19_vc_sel_0_18; // @[InputUnit.scala:192:19] reg states_19_vc_sel_0_19; // @[InputUnit.scala:192:19] reg states_19_vc_sel_0_20; // @[InputUnit.scala:192:19] reg states_19_vc_sel_0_21; // @[InputUnit.scala:192:19] reg [3:0] states_19_flow_vnet_id; // @[InputUnit.scala:192:19] reg [5:0] states_19_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_19_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [5:0] states_19_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_19_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_20_g; // @[InputUnit.scala:192:19] reg states_20_vc_sel_1_2; // @[InputUnit.scala:192:19] reg states_20_vc_sel_1_3; // @[InputUnit.scala:192:19] reg states_20_vc_sel_1_8; // @[InputUnit.scala:192:19] reg states_20_vc_sel_1_9; // @[InputUnit.scala:192:19] reg states_20_vc_sel_1_10; // @[InputUnit.scala:192:19] reg states_20_vc_sel_1_11; // @[InputUnit.scala:192:19] reg states_20_vc_sel_1_12; // @[InputUnit.scala:192:19] reg states_20_vc_sel_1_13; // @[InputUnit.scala:192:19] reg states_20_vc_sel_1_14; // @[InputUnit.scala:192:19] reg states_20_vc_sel_1_15; // @[InputUnit.scala:192:19] reg states_20_vc_sel_1_16; // @[InputUnit.scala:192:19] reg states_20_vc_sel_1_17; // @[InputUnit.scala:192:19] reg states_20_vc_sel_1_18; // @[InputUnit.scala:192:19] reg states_20_vc_sel_1_19; // @[InputUnit.scala:192:19] reg states_20_vc_sel_1_20; // @[InputUnit.scala:192:19] reg states_20_vc_sel_0_18; // @[InputUnit.scala:192:19] reg states_20_vc_sel_0_19; // @[InputUnit.scala:192:19] reg states_20_vc_sel_0_20; // @[InputUnit.scala:192:19] reg states_20_vc_sel_0_21; // @[InputUnit.scala:192:19] reg [3:0] states_20_flow_vnet_id; // @[InputUnit.scala:192:19] reg [5:0] states_20_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_20_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [5:0] states_20_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_20_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_21_g; // @[InputUnit.scala:192:19] reg states_21_vc_sel_1_2; // @[InputUnit.scala:192:19] reg states_21_vc_sel_1_3; // @[InputUnit.scala:192:19] reg states_21_vc_sel_1_8; // @[InputUnit.scala:192:19] reg states_21_vc_sel_1_9; // @[InputUnit.scala:192:19] reg states_21_vc_sel_1_10; // @[InputUnit.scala:192:19] reg states_21_vc_sel_1_11; // @[InputUnit.scala:192:19] reg states_21_vc_sel_1_12; // @[InputUnit.scala:192:19] reg states_21_vc_sel_1_13; // @[InputUnit.scala:192:19] reg states_21_vc_sel_1_14; // @[InputUnit.scala:192:19] reg states_21_vc_sel_1_15; // @[InputUnit.scala:192:19] reg states_21_vc_sel_1_16; // @[InputUnit.scala:192:19] reg states_21_vc_sel_1_17; // @[InputUnit.scala:192:19] reg states_21_vc_sel_1_18; // @[InputUnit.scala:192:19] reg states_21_vc_sel_1_19; // @[InputUnit.scala:192:19] reg states_21_vc_sel_1_20; // @[InputUnit.scala:192:19] reg states_21_vc_sel_1_21; // @[InputUnit.scala:192:19] reg states_21_vc_sel_0_18; // @[InputUnit.scala:192:19] reg states_21_vc_sel_0_19; // @[InputUnit.scala:192:19] reg states_21_vc_sel_0_20; // @[InputUnit.scala:192:19] reg states_21_vc_sel_0_21; // @[InputUnit.scala:192:19] reg [3:0] states_21_flow_vnet_id; // @[InputUnit.scala:192:19] reg [5:0] states_21_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_21_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [5:0] states_21_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_21_flow_egress_node_id; // @[InputUnit.scala:192:19] wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30] wire route_arbiter_io_in_2_valid = states_2_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_3_valid = states_3_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_8_valid = states_8_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_9_valid = states_9_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_10_valid = states_10_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_11_valid = states_11_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_12_valid = states_12_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_13_valid = states_13_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_14_valid = states_14_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_15_valid = states_15_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_16_valid = states_16_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_17_valid = states_17_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_18_valid = states_18_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_19_valid = states_19_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_20_valid = states_20_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_21_valid = states_21_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] reg [21:0] mask; // @[InputUnit.scala:250:21] wire [21:0] _vcalloc_filter_T_3 = {vcalloc_vals_21, vcalloc_vals_20, vcalloc_vals_19, vcalloc_vals_18, vcalloc_vals_17, vcalloc_vals_16, vcalloc_vals_15, vcalloc_vals_14, vcalloc_vals_13, vcalloc_vals_12, vcalloc_vals_11, vcalloc_vals_10, vcalloc_vals_9, vcalloc_vals_8, 4'h0, vcalloc_vals_3, vcalloc_vals_2, 2'h0} & ~mask; // @[InputUnit.scala:250:21, :253:{80,87,89}, :266:32] wire [43:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 44'h1 : _vcalloc_filter_T_3[1] ? 44'h2 : _vcalloc_filter_T_3[2] ? 44'h4 : _vcalloc_filter_T_3[3] ? 44'h8 : _vcalloc_filter_T_3[4] ? 44'h10 : _vcalloc_filter_T_3[5] ? 44'h20 : _vcalloc_filter_T_3[6] ? 44'h40 : _vcalloc_filter_T_3[7] ? 44'h80 : _vcalloc_filter_T_3[8] ? 44'h100 : _vcalloc_filter_T_3[9] ? 44'h200 : _vcalloc_filter_T_3[10] ? 44'h400 : _vcalloc_filter_T_3[11] ? 44'h800 : _vcalloc_filter_T_3[12] ? 44'h1000 : _vcalloc_filter_T_3[13] ? 44'h2000 : _vcalloc_filter_T_3[14] ? 44'h4000 : _vcalloc_filter_T_3[15] ? 44'h8000 : _vcalloc_filter_T_3[16] ? 44'h10000 : _vcalloc_filter_T_3[17] ? 44'h20000 : _vcalloc_filter_T_3[18] ? 44'h40000 : _vcalloc_filter_T_3[19] ? 44'h80000 : _vcalloc_filter_T_3[20] ? 44'h100000 : _vcalloc_filter_T_3[21] ? 44'h200000 : vcalloc_vals_2 ? 44'h1000000 : vcalloc_vals_3 ? 44'h2000000 : vcalloc_vals_8 ? 44'h40000000 : vcalloc_vals_9 ? 44'h80000000 : vcalloc_vals_10 ? 44'h100000000 : vcalloc_vals_11 ? 44'h200000000 : vcalloc_vals_12 ? 44'h400000000 : vcalloc_vals_13 ? 44'h800000000 : vcalloc_vals_14 ? 44'h1000000000 : vcalloc_vals_15 ? 44'h2000000000 : vcalloc_vals_16 ? 44'h4000000000 : vcalloc_vals_17 ? 44'h8000000000 : vcalloc_vals_18 ? 44'h10000000000 : vcalloc_vals_19 ? 44'h20000000000 : vcalloc_vals_20 ? 44'h40000000000 : {vcalloc_vals_21, 43'h0}; // @[OneHot.scala:85:71] wire [21:0] vcalloc_sel = vcalloc_filter[21:0] | vcalloc_filter[43:22]; // @[Mux.scala:50:70] wire io_vcalloc_req_valid_0 = vcalloc_vals_2 | vcalloc_vals_3 | vcalloc_vals_8 | vcalloc_vals_9 | vcalloc_vals_10 | vcalloc_vals_11 | vcalloc_vals_12 | vcalloc_vals_13 | vcalloc_vals_14 | vcalloc_vals_15 | vcalloc_vals_16 | vcalloc_vals_17 | vcalloc_vals_18 | vcalloc_vals_19 | vcalloc_vals_20 | vcalloc_vals_21; // @[package.scala:81:59] assign vcalloc_vals_2 = states_2_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_3 = states_3_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_8 = states_8_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_9 = states_9_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_10 = states_10_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_11 = states_11_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_12 = states_12_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_13 = states_13_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_14 = states_14_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_15 = states_15_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_16 = states_16_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_17 = states_17_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_18 = states_18_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_19 = states_19_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_20 = states_20_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_21 = states_21_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] wire _GEN_0 = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35] wire _GEN_1 = _GEN_0 & vcalloc_sel[2]; // @[Mux.scala:32:36] wire _GEN_2 = _GEN_0 & vcalloc_sel[3]; // @[Mux.scala:32:36] wire _GEN_3 = _GEN_0 & vcalloc_sel[8]; // @[Mux.scala:32:36] wire _GEN_4 = _GEN_0 & vcalloc_sel[9]; // @[Mux.scala:32:36] wire _GEN_5 = _GEN_0 & vcalloc_sel[10]; // @[Mux.scala:32:36] wire _GEN_6 = _GEN_0 & vcalloc_sel[11]; // @[Mux.scala:32:36] wire _GEN_7 = _GEN_0 & vcalloc_sel[12]; // @[Mux.scala:32:36] wire _GEN_8 = _GEN_0 & vcalloc_sel[13]; // @[Mux.scala:32:36] wire _GEN_9 = _GEN_0 & vcalloc_sel[14]; // @[Mux.scala:32:36] wire _GEN_10 = _GEN_0 & vcalloc_sel[15]; // @[Mux.scala:32:36] wire _GEN_11 = _GEN_0 & vcalloc_sel[16]; // @[Mux.scala:32:36] wire _GEN_12 = _GEN_0 & vcalloc_sel[17]; // @[Mux.scala:32:36] wire _GEN_13 = _GEN_0 & vcalloc_sel[18]; // @[Mux.scala:32:36] wire _GEN_14 = _GEN_0 & vcalloc_sel[19]; // @[Mux.scala:32:36] wire _GEN_15 = _GEN_0 & vcalloc_sel[20]; // @[Mux.scala:32:36] wire _GEN_16 = _GEN_0 & vcalloc_sel[21]; // @[Mux.scala:32:36]
Generate the Verilog code corresponding to the following Chisel files. File Tile.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ import Util._ /** * A Tile is a purely combinational 2D array of passThrough PEs. * a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs * @param width The data width of each PE in bits * @param rows Number of PEs on each row * @param columns Number of PEs on each column */ class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module { val io = IO(new Bundle { val in_a = Input(Vec(rows, inputType)) val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it val in_d = Input(Vec(columns, outputType)) val in_control = Input(Vec(columns, new PEControl(accType))) val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val in_last = Input(Vec(columns, Bool())) val out_a = Output(Vec(rows, inputType)) val out_c = Output(Vec(columns, outputType)) val out_b = Output(Vec(columns, outputType)) val out_control = Output(Vec(columns, new PEControl(accType))) val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val out_last = Output(Vec(columns, Bool())) val in_valid = Input(Vec(columns, Bool())) val out_valid = Output(Vec(columns, Bool())) val bad_dataflow = Output(Bool()) }) import ev._ val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls))) val tileT = tile.transpose // TODO: abstract hori/vert broadcast, all these connections look the same // Broadcast 'a' horizontally across the Tile for (r <- 0 until rows) { tile(r).foldLeft(io.in_a(r)) { case (in_a, pe) => pe.io.in_a := in_a pe.io.out_a } } // Broadcast 'b' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_b(c)) { case (in_b, pe) => pe.io.in_b := (if (tree_reduction) in_b.zero else in_b) pe.io.out_b } } // Broadcast 'd' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_d(c)) { case (in_d, pe) => pe.io.in_d := in_d pe.io.out_c } } // Broadcast 'control' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_control(c)) { case (in_ctrl, pe) => pe.io.in_control := in_ctrl pe.io.out_control } } // Broadcast 'garbage' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_valid(c)) { case (v, pe) => pe.io.in_valid := v pe.io.out_valid } } // Broadcast 'id' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_id(c)) { case (id, pe) => pe.io.in_id := id pe.io.out_id } } // Broadcast 'last' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_last(c)) { case (last, pe) => pe.io.in_last := last pe.io.out_last } } // Drive the Tile's bottom IO for (c <- 0 until columns) { io.out_c(c) := tile(rows-1)(c).io.out_c io.out_control(c) := tile(rows-1)(c).io.out_control io.out_id(c) := tile(rows-1)(c).io.out_id io.out_last(c) := tile(rows-1)(c).io.out_last io.out_valid(c) := tile(rows-1)(c).io.out_valid io.out_b(c) := { if (tree_reduction) { val prods = tileT(c).map(_.io.out_b) accumulateTree(prods :+ io.in_b(c)) } else { tile(rows - 1)(c).io.out_b } } } io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_||_)).reduce(_||_) // Drive the Tile's right IO for (r <- 0 until rows) { io.out_a(r) := tile(r)(columns-1).io.out_a } }
module Tile_207( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_463 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_498( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File ToAXI4.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.amba.{AMBACorrupt, AMBACorruptField, AMBAProt, AMBAProtField} import freechips.rocketchip.amba.axi4.{AXI4BundleARW, AXI4MasterParameters, AXI4MasterPortParameters, AXI4Parameters, AXI4Imp} import freechips.rocketchip.diplomacy.{IdMap, IdMapEntry, IdRange} import freechips.rocketchip.util.{BundleField, ControlKey, ElaborationArtefacts, UIntToOH1} import freechips.rocketchip.util.DataToAugmentedData class AXI4TLStateBundle(val sourceBits: Int) extends Bundle { val size = UInt(4.W) val source = UInt((sourceBits max 1).W) } case object AXI4TLState extends ControlKey[AXI4TLStateBundle]("tl_state") case class AXI4TLStateField(sourceBits: Int) extends BundleField[AXI4TLStateBundle](AXI4TLState, Output(new AXI4TLStateBundle(sourceBits)), x => { x.size := 0.U x.source := 0.U }) /** TLtoAXI4IdMap serves as a record for the translation performed between id spaces. * * Its member [axi4Masters] is used as the new AXI4MasterParameters in diplomacy. * Its member [mapping] is used as the template for the circuit generated in TLToAXI4Node.module. */ class TLtoAXI4IdMap(tlPort: TLMasterPortParameters) extends IdMap[TLToAXI4IdMapEntry] { val tlMasters = tlPort.masters.sortBy(_.sourceId).sortWith(TLToAXI4.sortByType) private val axi4IdSize = tlMasters.map { tl => if (tl.requestFifo) 1 else tl.sourceId.size } private val axi4IdStart = axi4IdSize.scanLeft(0)(_+_).init val axi4Masters = axi4IdStart.zip(axi4IdSize).zip(tlMasters).map { case ((start, size), tl) => AXI4MasterParameters( name = tl.name, id = IdRange(start, start+size), aligned = true, maxFlight = Some(if (tl.requestFifo) tl.sourceId.size else 1), nodePath = tl.nodePath) } private val axi4IdEnd = axi4Masters.map(_.id.end).max private val axiDigits = String.valueOf(axi4IdEnd-1).length() private val tlDigits = String.valueOf(tlPort.endSourceId-1).length() protected val fmt = s"\t[%${axiDigits}d, %${axiDigits}d) <= [%${tlDigits}d, %${tlDigits}d) %s%s%s" val mapping: Seq[TLToAXI4IdMapEntry] = tlMasters.zip(axi4Masters).map { case (tl, axi) => TLToAXI4IdMapEntry(axi.id, tl.sourceId, tl.name, tl.supports.probe, tl.requestFifo) } } case class TLToAXI4IdMapEntry(axi4Id: IdRange, tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = axi4Id val maxTransactionsInFlight = Some(tlId.size) } case class TLToAXI4Node(wcorrupt: Boolean = true)(implicit valName: ValName) extends MixedAdapterNode(TLImp, AXI4Imp)( dFn = { p => AXI4MasterPortParameters( masters = (new TLtoAXI4IdMap(p)).axi4Masters, requestFields = (if (wcorrupt) Seq(AMBACorruptField()) else Seq()) ++ p.requestFields.filter(!_.isInstanceOf[AMBAProtField]), echoFields = AXI4TLStateField(log2Ceil(p.endSourceId)) +: p.echoFields, responseKeys = p.responseKeys) }, uFn = { p => TLSlavePortParameters.v1( managers = p.slaves.map { case s => TLSlaveParameters.v1( address = s.address, resources = s.resources, regionType = s.regionType, executable = s.executable, nodePath = s.nodePath, supportsGet = s.supportsRead, supportsPutFull = s.supportsWrite, supportsPutPartial = s.supportsWrite, fifoId = Some(0), mayDenyPut = true, mayDenyGet = true)}, beatBytes = p.beatBytes, minLatency = p.minLatency, responseFields = p.responseFields, requestKeys = AMBAProt +: p.requestKeys) }) // wcorrupt alone is not enough; a slave must include AMBACorrupt in the slave port's requestKeys class TLToAXI4(val combinational: Boolean = true, val adapterName: Option[String] = None, val stripBits: Int = 0, val wcorrupt: Boolean = true)(implicit p: Parameters) extends LazyModule { require(stripBits == 0, "stripBits > 0 is no longer supported on TLToAXI4") val node = TLToAXI4Node(wcorrupt) lazy val module = new Impl class Impl extends LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => val slaves = edgeOut.slave.slaves // All pairs of slaves must promise that they will never interleave data require (slaves(0).interleavedId.isDefined) slaves.foreach { s => require (s.interleavedId == slaves(0).interleavedId) } // Construct the source=>ID mapping table val map = new TLtoAXI4IdMap(edgeIn.client) val sourceStall = WireDefault(VecInit.fill(edgeIn.client.endSourceId)(false.B)) val sourceTable = WireDefault(VecInit.fill(edgeIn.client.endSourceId)(0.U.asTypeOf(out.aw.bits.id))) val idStall = WireDefault(VecInit.fill(edgeOut.master.endId)(false.B)) var idCount = Array.fill(edgeOut.master.endId) { None:Option[Int] } map.mapping.foreach { case TLToAXI4IdMapEntry(axi4Id, tlId, _, _, fifo) => for (i <- 0 until tlId.size) { val id = axi4Id.start + (if (fifo) 0 else i) sourceStall(tlId.start + i) := idStall(id) sourceTable(tlId.start + i) := id.U } if (fifo) { idCount(axi4Id.start) = Some(tlId.size) } } adapterName.foreach { n => println(s"$n AXI4-ID <= TL-Source mapping:\n${map.pretty}\n") ElaborationArtefacts.add(s"$n.axi4.json", s"""{"mapping":[${map.mapping.mkString(",")}]}""") } // We need to keep the following state from A => D: (size, source) // All of those fields could potentially require 0 bits (argh. Chisel.) // We will pack all of that extra information into the echo bits. require (log2Ceil(edgeIn.maxLgSize+1) <= 4) val a_address = edgeIn.address(in.a.bits) val a_source = in.a.bits.source val a_size = edgeIn.size(in.a.bits) val a_isPut = edgeIn.hasData(in.a.bits) val (a_first, a_last, _) = edgeIn.firstlast(in.a) val r_state = out.r.bits.echo(AXI4TLState) val r_source = r_state.source val r_size = r_state.size val b_state = out.b.bits.echo(AXI4TLState) val b_source = b_state.source val b_size = b_state.size // We need these Queues because AXI4 queues are irrevocable val depth = if (combinational) 1 else 2 val out_arw = Wire(Decoupled(new AXI4BundleARW(out.params))) val out_w = Wire(chiselTypeOf(out.w)) out.w :<>= Queue.irrevocable(out_w, entries=depth, flow=combinational) val queue_arw = Queue.irrevocable(out_arw, entries=depth, flow=combinational) // Fan out the ARW channel to AR and AW out.ar.bits := queue_arw.bits out.aw.bits := queue_arw.bits out.ar.valid := queue_arw.valid && !queue_arw.bits.wen out.aw.valid := queue_arw.valid && queue_arw.bits.wen queue_arw.ready := Mux(queue_arw.bits.wen, out.aw.ready, out.ar.ready) val beatBytes = edgeIn.manager.beatBytes val maxSize = log2Ceil(beatBytes).U val doneAW = RegInit(false.B) when (in.a.fire) { doneAW := !a_last } val arw = out_arw.bits arw.wen := a_isPut arw.id := sourceTable(a_source) arw.addr := a_address arw.len := UIntToOH1(a_size, AXI4Parameters.lenBits + log2Ceil(beatBytes)) >> log2Ceil(beatBytes) arw.size := Mux(a_size >= maxSize, maxSize, a_size) arw.burst := AXI4Parameters.BURST_INCR arw.lock := 0.U // not exclusive (LR/SC unsupported b/c no forward progress guarantee) arw.cache := 0.U // do not allow AXI to modify our transactions arw.prot := AXI4Parameters.PROT_PRIVILEGED arw.qos := 0.U // no QoS Connectable.waiveUnmatched(arw.user, in.a.bits.user) match { case (lhs, rhs) => lhs :<= rhs } Connectable.waiveUnmatched(arw.echo, in.a.bits.echo) match { case (lhs, rhs) => lhs :<= rhs } val a_extra = arw.echo(AXI4TLState) a_extra.source := a_source a_extra.size := a_size in.a.bits.user.lift(AMBAProt).foreach { x => val prot = Wire(Vec(3, Bool())) val cache = Wire(Vec(4, Bool())) prot(0) := x.privileged prot(1) := !x.secure prot(2) := x.fetch cache(0) := x.bufferable cache(1) := x.modifiable cache(2) := x.readalloc cache(3) := x.writealloc arw.prot := Cat(prot.reverse) arw.cache := Cat(cache.reverse) } val stall = sourceStall(in.a.bits.source) && a_first in.a.ready := !stall && Mux(a_isPut, (doneAW || out_arw.ready) && out_w.ready, out_arw.ready) out_arw.valid := !stall && in.a.valid && Mux(a_isPut, !doneAW && out_w.ready, true.B) out_w.valid := !stall && in.a.valid && a_isPut && (doneAW || out_arw.ready) out_w.bits.data := in.a.bits.data out_w.bits.strb := in.a.bits.mask out_w.bits.last := a_last out_w.bits.user.lift(AMBACorrupt).foreach { _ := in.a.bits.corrupt } // R and B => D arbitration val r_holds_d = RegInit(false.B) when (out.r.fire) { r_holds_d := !out.r.bits.last } // Give R higher priority than B, unless B has been delayed for 8 cycles val b_delay = Reg(UInt(3.W)) when (out.b.valid && !out.b.ready) { b_delay := b_delay + 1.U } .otherwise { b_delay := 0.U } val r_wins = (out.r.valid && b_delay =/= 7.U) || r_holds_d out.r.ready := in.d.ready && r_wins out.b.ready := in.d.ready && !r_wins in.d.valid := Mux(r_wins, out.r.valid, out.b.valid) // If the first beat of the AXI RRESP is RESP_DECERR, treat this as a denied // request. We must pulse extend this value as AXI is allowed to change the // value of RRESP on every beat, and ChipLink may not. val r_first = RegInit(true.B) when (out.r.fire) { r_first := out.r.bits.last } val r_denied = out.r.bits.resp === AXI4Parameters.RESP_DECERR holdUnless r_first val r_corrupt = out.r.bits.resp =/= AXI4Parameters.RESP_OKAY val b_denied = out.b.bits.resp =/= AXI4Parameters.RESP_OKAY val r_d = edgeIn.AccessAck(r_source, r_size, 0.U, denied = r_denied, corrupt = r_corrupt || r_denied) val b_d = edgeIn.AccessAck(b_source, b_size, denied = b_denied) Connectable.waiveUnmatched(r_d.user, out.r.bits.user) match { case (lhs, rhs) => lhs.squeezeAll :<= rhs.squeezeAll } Connectable.waiveUnmatched(r_d.echo, out.r.bits.echo) match { case (lhs, rhs) => lhs.squeezeAll :<= rhs.squeezeAll } Connectable.waiveUnmatched(b_d.user, out.b.bits.user) match { case (lhs, rhs) => lhs.squeezeAll :<= rhs.squeezeAll } Connectable.waiveUnmatched(b_d.echo, out.b.bits.echo) match { case (lhs, rhs) => lhs.squeezeAll :<= rhs.squeezeAll } in.d.bits := Mux(r_wins, r_d, b_d) in.d.bits.data := out.r.bits.data // avoid a costly Mux // We need to track if any reads or writes are inflight for a given ID. // If the opposite type arrives, we must stall until it completes. val a_sel = UIntToOH(arw.id, edgeOut.master.endId).asBools val d_sel = UIntToOH(Mux(r_wins, out.r.bits.id, out.b.bits.id), edgeOut.master.endId).asBools val d_last = Mux(r_wins, out.r.bits.last, true.B) // If FIFO was requested, ensure that R+W ordering is preserved (a_sel zip d_sel zip idStall zip idCount) foreach { case (((as, ds), s), n) => // AXI does not guarantee read vs. write ordering. In particular, if we // are in the middle of receiving a read burst and then issue a write, // the write might affect the read burst. This violates FIFO behaviour. // To solve this, we must wait until the last beat of a burst, but this // means that a TileLink master which performs early source reuse can // have one more transaction inflight than we promised AXI; stall it too. val maxCount = n.getOrElse(1) val count = RegInit(0.U(log2Ceil(maxCount + 1).W)) val write = Reg(Bool()) val idle = count === 0.U val inc = as && out_arw.fire val dec = ds && d_last && in.d.fire count := count + inc.asUInt - dec.asUInt assert (!dec || count =/= 0.U) // underflow assert (!inc || count =/= maxCount.U) // overflow when (inc) { write := arw.wen } // If only one transaction can be inflight, it can't mismatch val mismatch = if (maxCount > 1) { write =/= arw.wen } else { false.B } s := (!idle && mismatch) || (count === maxCount.U) } // Tie off unused channels in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B } } } object TLToAXI4 { def apply(combinational: Boolean = true, adapterName: Option[String] = None, stripBits: Int = 0, wcorrupt: Boolean = true)(implicit p: Parameters) = { val tl2axi4 = LazyModule(new TLToAXI4(combinational, adapterName, stripBits, wcorrupt)) tl2axi4.node } def sortByType(a: TLMasterParameters, b: TLMasterParameters): Boolean = { if ( a.supports.probe && !b.supports.probe) return false if (!a.supports.probe && b.supports.probe) return true if ( a.requestFifo && !b.requestFifo ) return false if (!a.requestFifo && b.requestFifo ) return true return false } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLToAXI4_1( // @[ToAXI4.scala:103:9] input clock, // @[ToAXI4.scala:103:9] input reset, // @[ToAXI4.scala:103:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_aw_ready, // @[LazyModuleImp.scala:107:25] output auto_out_aw_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_aw_bits_id, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_aw_bits_addr, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_aw_bits_len, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_aw_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_aw_bits_burst, // @[LazyModuleImp.scala:107:25] output auto_out_aw_bits_lock, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_aw_bits_cache, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_aw_bits_prot, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_aw_bits_qos, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_aw_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_aw_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] input auto_out_w_ready, // @[LazyModuleImp.scala:107:25] output auto_out_w_valid, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_w_bits_data, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_w_bits_strb, // @[LazyModuleImp.scala:107:25] output auto_out_w_bits_last, // @[LazyModuleImp.scala:107:25] output auto_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_out_b_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_b_bits_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_b_bits_resp, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_b_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_b_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] input auto_out_ar_ready, // @[LazyModuleImp.scala:107:25] output auto_out_ar_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_ar_bits_id, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_ar_bits_addr, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_ar_bits_len, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_ar_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_ar_bits_burst, // @[LazyModuleImp.scala:107:25] output auto_out_ar_bits_lock, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_ar_bits_cache, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_ar_bits_prot, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_ar_bits_qos, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_ar_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_ar_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] output auto_out_r_ready, // @[LazyModuleImp.scala:107:25] input auto_out_r_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_r_bits_id, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_r_bits_data, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_r_bits_resp, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_r_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_r_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] input auto_out_r_bits_last // @[LazyModuleImp.scala:107:25] ); reg count_9; // @[ToAXI4.scala:272:28] reg count_8; // @[ToAXI4.scala:272:28] reg count_7; // @[ToAXI4.scala:272:28] reg count_6; // @[ToAXI4.scala:272:28] reg count_5; // @[ToAXI4.scala:272:28] reg count_4; // @[ToAXI4.scala:272:28] reg count_3; // @[ToAXI4.scala:272:28] reg count_2; // @[ToAXI4.scala:272:28] reg count_1; // @[ToAXI4.scala:272:28] reg count; // @[ToAXI4.scala:272:28] wire _queue_arw_deq_q_io_enq_ready; // @[Decoupled.scala:362:21] wire _queue_arw_deq_q_io_deq_valid; // @[Decoupled.scala:362:21] wire [3:0] _queue_arw_deq_q_io_deq_bits_id; // @[Decoupled.scala:362:21] wire [31:0] _queue_arw_deq_q_io_deq_bits_addr; // @[Decoupled.scala:362:21] wire [7:0] _queue_arw_deq_q_io_deq_bits_len; // @[Decoupled.scala:362:21] wire [2:0] _queue_arw_deq_q_io_deq_bits_size; // @[Decoupled.scala:362:21] wire [1:0] _queue_arw_deq_q_io_deq_bits_burst; // @[Decoupled.scala:362:21] wire _queue_arw_deq_q_io_deq_bits_lock; // @[Decoupled.scala:362:21] wire [3:0] _queue_arw_deq_q_io_deq_bits_cache; // @[Decoupled.scala:362:21] wire [2:0] _queue_arw_deq_q_io_deq_bits_prot; // @[Decoupled.scala:362:21] wire [3:0] _queue_arw_deq_q_io_deq_bits_qos; // @[Decoupled.scala:362:21] wire [3:0] _queue_arw_deq_q_io_deq_bits_echo_tl_state_size; // @[Decoupled.scala:362:21] wire [3:0] _queue_arw_deq_q_io_deq_bits_echo_tl_state_source; // @[Decoupled.scala:362:21] wire _queue_arw_deq_q_io_deq_bits_wen; // @[Decoupled.scala:362:21] wire _nodeOut_w_deq_q_io_enq_ready; // @[Decoupled.scala:362:21] wire [15:0][3:0] _GEN = '{4'h0, 4'h0, 4'h0, 4'h0, 4'h0, 4'h0, 4'h9, 4'h8, 4'h7, 4'h6, 4'h5, 4'h4, 4'h3, 4'h2, 4'h1, 4'h0}; wire [12:0] _r_beats1_decode_T = 13'h3F << auto_in_a_bits_size; // @[package.scala:243:71] wire [2:0] r_beats1 = auto_in_a_bits_opcode[2] ? 3'h0 : ~(_r_beats1_decode_T[5:3]); // @[package.scala:243:{46,71,76}] reg [2:0] r_counter; // @[Edges.scala:229:27] wire a_first = r_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire a_last = r_counter == 3'h1 | r_beats1 == 3'h0; // @[Edges.scala:221:14, :229:27, :232:{25,33,43}] reg doneAW; // @[ToAXI4.scala:167:30] wire [17:0] _out_arw_bits_len_T = 18'h7FF << auto_in_a_bits_size; // @[package.scala:243:71] wire [15:0] _GEN_0 = {{count}, {count}, {count}, {count}, {count}, {count}, {count_9}, {count_8}, {count_7}, {count_6}, {count_5}, {count_4}, {count_3}, {count_2}, {count_1}, {count}}; // @[ToAXI4.scala:205:49, :272:28] wire stall = _GEN_0[auto_in_a_bits_source] & a_first; // @[ToAXI4.scala:205:49] wire _out_w_valid_T_3 = doneAW | _queue_arw_deq_q_io_enq_ready; // @[Decoupled.scala:362:21] wire nodeIn_a_ready = ~stall & (auto_in_a_bits_opcode[2] ? _queue_arw_deq_q_io_enq_ready : _out_w_valid_T_3 & _nodeOut_w_deq_q_io_enq_ready); // @[Decoupled.scala:362:21] wire out_arw_valid = ~stall & auto_in_a_valid & (auto_in_a_bits_opcode[2] | ~doneAW & _nodeOut_w_deq_q_io_enq_ready); // @[Decoupled.scala:362:21] reg r_holds_d; // @[ToAXI4.scala:216:30] reg [2:0] b_delay; // @[ToAXI4.scala:219:24] wire r_wins = auto_out_r_valid & b_delay != 3'h7 | r_holds_d; // @[ToAXI4.scala:216:30, :219:24, :225:{33,44,53}] wire nodeOut_r_ready = auto_in_d_ready & r_wins; // @[ToAXI4.scala:225:53, :227:33] wire nodeOut_b_ready = auto_in_d_ready & ~r_wins; // @[ToAXI4.scala:225:53, :228:{33,36}] wire nodeIn_d_valid = r_wins ? auto_out_r_valid : auto_out_b_valid; // @[ToAXI4.scala:225:53, :229:24] reg r_first; // @[ToAXI4.scala:234:28] reg r_denied_r; // @[package.scala:88:63] wire r_denied = r_first ? (&auto_out_r_bits_resp) : r_denied_r; // @[package.scala:88:{42,63}] wire [2:0] nodeIn_d_bits_opcode = {2'h0, r_wins}; // @[ToAXI4.scala:225:53, :255:23] wire [2:0] nodeIn_d_bits_size = r_wins ? auto_out_r_bits_echo_tl_state_size[2:0] : auto_out_b_bits_echo_tl_state_size[2:0]; // @[ToAXI4.scala:225:53, :255:23] wire [3:0] nodeIn_d_bits_source = r_wins ? auto_out_r_bits_echo_tl_state_source : auto_out_b_bits_echo_tl_state_source; // @[ToAXI4.scala:225:53, :255:23] wire nodeIn_d_bits_denied = r_wins ? r_denied : (|auto_out_b_bits_resp); // @[package.scala:88:42] wire nodeIn_d_bits_corrupt = r_wins & ((|auto_out_r_bits_resp) | r_denied); // @[package.scala:88:42] wire [3:0] d_sel_shiftAmount = r_wins ? auto_out_r_bits_id : auto_out_b_bits_id; // @[ToAXI4.scala:225:53, :261:31] wire d_last = ~r_wins | auto_out_r_bits_last; // @[ToAXI4.scala:225:53, :262:23] wire _inc_T_9 = _queue_arw_deq_q_io_enq_ready & out_arw_valid; // @[Decoupled.scala:51:35, :362:21] wire inc = _GEN[auto_in_a_bits_source] == 4'h0 & _inc_T_9; // @[OneHot.scala:65:27] wire _dec_T_19 = auto_in_d_ready & nodeIn_d_valid; // @[Decoupled.scala:51:35] wire dec = d_sel_shiftAmount == 4'h0 & d_last & _dec_T_19; // @[OneHot.scala:65:27] wire inc_1 = _GEN[auto_in_a_bits_source] == 4'h1 & _inc_T_9; // @[OneHot.scala:65:27] wire dec_1 = d_sel_shiftAmount == 4'h1 & d_last & _dec_T_19; // @[OneHot.scala:65:27] wire inc_2 = _GEN[auto_in_a_bits_source] == 4'h2 & _inc_T_9; // @[OneHot.scala:65:27] wire dec_2 = d_sel_shiftAmount == 4'h2 & d_last & _dec_T_19; // @[OneHot.scala:65:27] wire inc_3 = _GEN[auto_in_a_bits_source] == 4'h3 & _inc_T_9; // @[OneHot.scala:65:27] wire dec_3 = d_sel_shiftAmount == 4'h3 & d_last & _dec_T_19; // @[OneHot.scala:65:27] wire inc_4 = _GEN[auto_in_a_bits_source] == 4'h4 & _inc_T_9; // @[OneHot.scala:65:27] wire dec_4 = d_sel_shiftAmount == 4'h4 & d_last & _dec_T_19; // @[OneHot.scala:65:27] wire inc_5 = _GEN[auto_in_a_bits_source] == 4'h5 & _inc_T_9; // @[OneHot.scala:65:27] wire dec_5 = d_sel_shiftAmount == 4'h5 & d_last & _dec_T_19; // @[OneHot.scala:65:27] wire inc_6 = _GEN[auto_in_a_bits_source] == 4'h6 & _inc_T_9; // @[OneHot.scala:65:27] wire dec_6 = d_sel_shiftAmount == 4'h6 & d_last & _dec_T_19; // @[OneHot.scala:65:27] wire inc_7 = _GEN[auto_in_a_bits_source] == 4'h7 & _inc_T_9; // @[OneHot.scala:65:27] wire dec_7 = d_sel_shiftAmount == 4'h7 & d_last & _dec_T_19; // @[OneHot.scala:65:27] wire inc_8 = _GEN[auto_in_a_bits_source] == 4'h8 & _inc_T_9; // @[OneHot.scala:65:27] wire dec_8 = d_sel_shiftAmount == 4'h8 & d_last & _dec_T_19; // @[OneHot.scala:65:27] wire inc_9 = _GEN[auto_in_a_bits_source] == 4'h9 & _inc_T_9; // @[OneHot.scala:65:27] wire dec_9 = d_sel_shiftAmount == 4'h9 & d_last & _dec_T_19; // @[OneHot.scala:65:27]
Generate the Verilog code corresponding to the following Chisel files. File RecFNToRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import consts._ class RecFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val in = Input(Bits((inExpWidth + inSigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawIn = rawFloatFromRecFN(inExpWidth, inSigWidth, io.in); if ((inExpWidth == outExpWidth) && (inSigWidth <= outSigWidth)) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- io.out := io.in<<(outSigWidth - inSigWidth) io.exceptionFlags := isSigNaNRawFloat(rawIn) ## 0.U(4.W) } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( inExpWidth, inSigWidth, outExpWidth, outSigWidth, flRoundOpt_sigMSBitAlwaysZero )) roundAnyRawFNToRecFN.io.invalidExc := isSigNaNRawFloat(rawIn) roundAnyRawFNToRecFN.io.infiniteExc := false.B roundAnyRawFNToRecFN.io.in := rawIn roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags } } File rawFloatFromRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ /*---------------------------------------------------------------------------- | In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be | set. *----------------------------------------------------------------------------*/ object rawFloatFromRecFN { def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat = { val exp = in(expWidth + sigWidth - 1, sigWidth - 1) val isZero = exp(expWidth, expWidth - 2) === 0.U val isSpecial = exp(expWidth, expWidth - 1) === 3.U val out = Wire(new RawFloat(expWidth, sigWidth)) out.isNaN := isSpecial && exp(expWidth - 2) out.isInf := isSpecial && ! exp(expWidth - 2) out.isZero := isZero out.sign := in(expWidth + sigWidth) out.sExp := exp.zext out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0) out } }
module RecFNToRecFN_247( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule
Generate the Verilog code corresponding to the following Chisel files. File RecFNToIN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util.log2Up import scala.math._ import consts._ class RecFNToIN(expWidth: Int, sigWidth: Int, intWidth: Int) extends chisel3.Module { override def desiredName = s"RecFNToIN_e${expWidth}_s${sigWidth}_i${intWidth}" val io = IO(new Bundle { val in = Input(Bits((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val signedOut = Input(Bool()) val out = Output(Bits(intWidth.W)) val intExceptionFlags = Output(Bits(3.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawIn = rawFloatFromRecFN(expWidth, sigWidth, io.in) val magGeOne = rawIn.sExp(expWidth) val posExp = rawIn.sExp(expWidth - 1, 0) val magJustBelowOne = !magGeOne && posExp.andR //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_near_even = (io.roundingMode === round_near_even) val roundingMode_minMag = (io.roundingMode === round_minMag) val roundingMode_min = (io.roundingMode === round_min) val roundingMode_max = (io.roundingMode === round_max) val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag) val roundingMode_odd = (io.roundingMode === round_odd) /*------------------------------------------------------------------------ | Assuming the input floating-point value is not a NaN, its magnitude is | at least 1, and it is not obviously so large as to lead to overflow, | convert its significand to fixed-point (i.e., with the binary point in a | fixed location). For a non-NaN input with a magnitude less than 1, this | expression contrives to ensure that the integer bits of 'alignedSig' | will all be zeros. *------------------------------------------------------------------------*/ val shiftedSig = (magGeOne ## rawIn.sig(sigWidth - 2, 0))<< Mux(magGeOne, rawIn.sExp(min(expWidth - 2, log2Up(intWidth) - 1), 0), 0.U ) val alignedSig = (shiftedSig>>(sigWidth - 2)) ## shiftedSig(sigWidth - 3, 0).orR val unroundedInt = 0.U(intWidth.W) | alignedSig>>2 val common_inexact = Mux(magGeOne, alignedSig(1, 0).orR, !rawIn.isZero) val roundIncr_near_even = (magGeOne && (alignedSig(2, 1).andR || alignedSig(1, 0).andR)) || (magJustBelowOne && alignedSig(1, 0).orR) val roundIncr_near_maxMag = (magGeOne && alignedSig(1)) || magJustBelowOne val roundIncr = (roundingMode_near_even && roundIncr_near_even ) || (roundingMode_near_maxMag && roundIncr_near_maxMag) || ((roundingMode_min || roundingMode_odd) && (rawIn.sign && common_inexact)) || (roundingMode_max && (!rawIn.sign && common_inexact)) val complUnroundedInt = Mux(rawIn.sign, ~unroundedInt, unroundedInt) val roundedInt = Mux(roundIncr ^ rawIn.sign, complUnroundedInt + 1.U, complUnroundedInt ) | (roundingMode_odd && common_inexact) val magGeOne_atOverflowEdge = (posExp === (intWidth - 1).U) //*** CHANGE TO TAKE BITS FROM THE ORIGINAL 'rawIn.sig' INSTEAD OF FROM //*** 'unroundedInt'?: val roundCarryBut2 = unroundedInt(intWidth - 3, 0).andR && roundIncr val common_overflow = Mux(magGeOne, (posExp >= intWidth.U) || Mux(io.signedOut, Mux(rawIn.sign, magGeOne_atOverflowEdge && (unroundedInt(intWidth - 2, 0).orR || roundIncr), magGeOne_atOverflowEdge || ((posExp === (intWidth - 2).U) && roundCarryBut2) ), rawIn.sign || (magGeOne_atOverflowEdge && unroundedInt(intWidth - 2) && roundCarryBut2) ), !io.signedOut && rawIn.sign && roundIncr ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val invalidExc = rawIn.isNaN || rawIn.isInf val overflow = !invalidExc && common_overflow val inexact = !invalidExc && !common_overflow && common_inexact val excSign = !rawIn.isNaN && rawIn.sign val excOut = Mux((io.signedOut === excSign), (BigInt(1)<<(intWidth - 1)).U, 0.U ) | Mux(!excSign, ((BigInt(1)<<(intWidth - 1)) - 1).U, 0.U) io.out := Mux(invalidExc || common_overflow, excOut, roundedInt) io.intExceptionFlags := invalidExc ## overflow ## inexact } File rawFloatFromRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ /*---------------------------------------------------------------------------- | In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be | set. *----------------------------------------------------------------------------*/ object rawFloatFromRecFN { def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat = { val exp = in(expWidth + sigWidth - 1, sigWidth - 1) val isZero = exp(expWidth, expWidth - 2) === 0.U val isSpecial = exp(expWidth, expWidth - 1) === 3.U val out = Wire(new RawFloat(expWidth, sigWidth)) out.isNaN := isSpecial && exp(expWidth - 2) out.isInf := isSpecial && ! exp(expWidth - 2) out.isZero := isZero out.sign := in(expWidth + sigWidth) out.sExp := exp.zext out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0) out } }
module RecFNToIN_e11_s53_i64( // @[RecFNToIN.scala:46:7] input clock, // @[RecFNToIN.scala:46:7] input reset, // @[RecFNToIN.scala:46:7] input [64:0] io_in, // @[RecFNToIN.scala:49:16] input [2:0] io_roundingMode, // @[RecFNToIN.scala:49:16] input io_signedOut, // @[RecFNToIN.scala:49:16] output [63:0] io_out, // @[RecFNToIN.scala:49:16] output [2:0] io_intExceptionFlags // @[RecFNToIN.scala:49:16] ); wire [64:0] io_in_0 = io_in; // @[RecFNToIN.scala:46:7] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RecFNToIN.scala:46:7] wire io_signedOut_0 = io_signedOut; // @[RecFNToIN.scala:46:7] wire [63:0] _io_out_T_1; // @[RecFNToIN.scala:145:18] wire [2:0] _io_intExceptionFlags_T_1; // @[RecFNToIN.scala:146:52] wire [63:0] io_out_0; // @[RecFNToIN.scala:46:7] wire [2:0] io_intExceptionFlags_0; // @[RecFNToIN.scala:46:7] wire [11:0] rawIn_exp = io_in_0[63:52]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [12:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[64]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [51:0] _rawIn_out_sig_T_2 = io_in_0[51:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire magGeOne = rawIn_sExp[11]; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] posExp = rawIn_sExp[10:0]; // @[rawFloatFromRecFN.scala:55:23] wire _magJustBelowOne_T = ~magGeOne; // @[RecFNToIN.scala:61:30, :63:27] wire _magJustBelowOne_T_1 = &posExp; // @[RecFNToIN.scala:62:28, :63:47] wire magJustBelowOne = _magJustBelowOne_T & _magJustBelowOne_T_1; // @[RecFNToIN.scala:63:{27,37,47}] wire roundingMode_near_even = io_roundingMode_0 == 3'h0; // @[rawFloatFromRecFN.scala:52:53] wire roundingMode_minMag = io_roundingMode_0 == 3'h1; // @[RecFNToIN.scala:46:7, :68:53] wire roundingMode_min = io_roundingMode_0 == 3'h2; // @[RecFNToIN.scala:46:7, :69:53] wire roundingMode_max = io_roundingMode_0 == 3'h3; // @[RecFNToIN.scala:46:7, :70:53] wire roundingMode_near_maxMag = io_roundingMode_0 == 3'h4; // @[RecFNToIN.scala:46:7, :71:53] wire roundingMode_odd = io_roundingMode_0 == 3'h6; // @[RecFNToIN.scala:46:7, :72:53] wire [51:0] _shiftedSig_T = rawIn_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _shiftedSig_T_1 = {magGeOne, _shiftedSig_T}; // @[RecFNToIN.scala:61:30, :83:{19,31}] wire [5:0] _shiftedSig_T_2 = rawIn_sExp[5:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _shiftedSig_T_3 = magGeOne ? _shiftedSig_T_2 : 6'h0; // @[RecFNToIN.scala:61:30, :84:16, :85:27] wire [115:0] shiftedSig = {63'h0, _shiftedSig_T_1} << _shiftedSig_T_3; // @[RecFNToIN.scala:83:{19,49}, :84:16] wire [64:0] _alignedSig_T = shiftedSig[115:51]; // @[RecFNToIN.scala:83:49, :89:20] wire [50:0] _alignedSig_T_1 = shiftedSig[50:0]; // @[RecFNToIN.scala:83:49, :89:51] wire _alignedSig_T_2 = |_alignedSig_T_1; // @[RecFNToIN.scala:89:{51,69}] wire [65:0] alignedSig = {_alignedSig_T, _alignedSig_T_2}; // @[RecFNToIN.scala:89:{20,38,69}] wire [63:0] _unroundedInt_T = alignedSig[65:2]; // @[RecFNToIN.scala:89:38, :90:52] wire [63:0] unroundedInt = _unroundedInt_T; // @[RecFNToIN.scala:90:{40,52}] wire [1:0] _common_inexact_T = alignedSig[1:0]; // @[RecFNToIN.scala:89:38, :92:50] wire [1:0] _roundIncr_near_even_T_2 = alignedSig[1:0]; // @[RecFNToIN.scala:89:38, :92:50, :94:64] wire [1:0] _roundIncr_near_even_T_6 = alignedSig[1:0]; // @[RecFNToIN.scala:89:38, :92:50, :95:39] wire _common_inexact_T_1 = |_common_inexact_T; // @[RecFNToIN.scala:92:{50,57}] wire _common_inexact_T_2 = ~rawIn_isZero_0; // @[rawFloatFromRecFN.scala:55:23] wire common_inexact = magGeOne ? _common_inexact_T_1 : _common_inexact_T_2; // @[RecFNToIN.scala:61:30, :92:{29,57,62}] wire [1:0] _roundIncr_near_even_T = alignedSig[2:1]; // @[RecFNToIN.scala:89:38, :94:39] wire _roundIncr_near_even_T_1 = &_roundIncr_near_even_T; // @[RecFNToIN.scala:94:{39,46}] wire _roundIncr_near_even_T_3 = &_roundIncr_near_even_T_2; // @[RecFNToIN.scala:94:{64,71}] wire _roundIncr_near_even_T_4 = _roundIncr_near_even_T_1 | _roundIncr_near_even_T_3; // @[RecFNToIN.scala:94:{46,51,71}] wire _roundIncr_near_even_T_5 = magGeOne & _roundIncr_near_even_T_4; // @[RecFNToIN.scala:61:30, :94:{25,51}] wire _roundIncr_near_even_T_7 = |_roundIncr_near_even_T_6; // @[RecFNToIN.scala:95:{39,46}] wire _roundIncr_near_even_T_8 = magJustBelowOne & _roundIncr_near_even_T_7; // @[RecFNToIN.scala:63:37, :95:{26,46}] wire roundIncr_near_even = _roundIncr_near_even_T_5 | _roundIncr_near_even_T_8; // @[RecFNToIN.scala:94:{25,78}, :95:26] wire _roundIncr_near_maxMag_T = alignedSig[1]; // @[RecFNToIN.scala:89:38, :96:56] wire _roundIncr_near_maxMag_T_1 = magGeOne & _roundIncr_near_maxMag_T; // @[RecFNToIN.scala:61:30, :96:{43,56}] wire roundIncr_near_maxMag = _roundIncr_near_maxMag_T_1 | magJustBelowOne; // @[RecFNToIN.scala:63:37, :96:{43,61}] wire _roundIncr_T = roundingMode_near_even & roundIncr_near_even; // @[RecFNToIN.scala:67:53, :94:78, :98:35] wire _roundIncr_T_1 = roundingMode_near_maxMag & roundIncr_near_maxMag; // @[RecFNToIN.scala:71:53, :96:61, :99:35] wire _roundIncr_T_2 = _roundIncr_T | _roundIncr_T_1; // @[RecFNToIN.scala:98:{35,61}, :99:35] wire _roundIncr_T_3 = roundingMode_min | roundingMode_odd; // @[RecFNToIN.scala:69:53, :72:53, :100:28] wire _roundIncr_T_4 = rawIn_sign & common_inexact; // @[rawFloatFromRecFN.scala:55:23] wire _roundIncr_T_5 = _roundIncr_T_3 & _roundIncr_T_4; // @[RecFNToIN.scala:100:{28,49}, :101:26] wire _roundIncr_T_6 = _roundIncr_T_2 | _roundIncr_T_5; // @[RecFNToIN.scala:98:61, :99:61, :100:49] wire _roundIncr_T_7 = ~rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire _roundIncr_T_8 = _roundIncr_T_7 & common_inexact; // @[RecFNToIN.scala:92:29, :102:{31,43}] wire _roundIncr_T_9 = roundingMode_max & _roundIncr_T_8; // @[RecFNToIN.scala:70:53, :102:{27,43}] wire roundIncr = _roundIncr_T_6 | _roundIncr_T_9; // @[RecFNToIN.scala:99:61, :101:46, :102:27] wire [63:0] _complUnroundedInt_T = ~unroundedInt; // @[RecFNToIN.scala:90:40, :103:45] wire [63:0] complUnroundedInt = rawIn_sign ? _complUnroundedInt_T : unroundedInt; // @[rawFloatFromRecFN.scala:55:23] wire _roundedInt_T = roundIncr ^ rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [64:0] _roundedInt_T_1 = {1'h0, complUnroundedInt} + 65'h1; // @[RecFNToIN.scala:103:32, :106:31] wire [63:0] _roundedInt_T_2 = _roundedInt_T_1[63:0]; // @[RecFNToIN.scala:106:31] wire [63:0] _roundedInt_T_3 = _roundedInt_T ? _roundedInt_T_2 : complUnroundedInt; // @[RecFNToIN.scala:103:32, :105:{12,23}, :106:31] wire _roundedInt_T_4 = roundingMode_odd & common_inexact; // @[RecFNToIN.scala:72:53, :92:29, :108:31] wire [63:0] roundedInt = {_roundedInt_T_3[63:1], _roundedInt_T_3[0] | _roundedInt_T_4}; // @[RecFNToIN.scala:105:12, :108:{11,31}] wire magGeOne_atOverflowEdge = posExp == 11'h3F; // @[RecFNToIN.scala:62:28, :110:43] wire [61:0] _roundCarryBut2_T = unroundedInt[61:0]; // @[RecFNToIN.scala:90:40, :113:38] wire _roundCarryBut2_T_1 = &_roundCarryBut2_T; // @[RecFNToIN.scala:113:{38,56}] wire roundCarryBut2 = _roundCarryBut2_T_1 & roundIncr; // @[RecFNToIN.scala:101:46, :113:{56,61}] wire _common_overflow_T = |(posExp[10:6]); // @[RecFNToIN.scala:62:28, :116:21] wire [62:0] _common_overflow_T_1 = unroundedInt[62:0]; // @[RecFNToIN.scala:90:40, :120:42] wire _common_overflow_T_2 = |_common_overflow_T_1; // @[RecFNToIN.scala:120:{42,60}] wire _common_overflow_T_3 = _common_overflow_T_2 | roundIncr; // @[RecFNToIN.scala:101:46, :120:{60,64}] wire _common_overflow_T_4 = magGeOne_atOverflowEdge & _common_overflow_T_3; // @[RecFNToIN.scala:110:43, :119:49, :120:64] wire _common_overflow_T_5 = posExp == 11'h3E; // @[RecFNToIN.scala:62:28, :122:38] wire _common_overflow_T_6 = _common_overflow_T_5 & roundCarryBut2; // @[RecFNToIN.scala:113:61, :122:{38,60}] wire _common_overflow_T_7 = magGeOne_atOverflowEdge | _common_overflow_T_6; // @[RecFNToIN.scala:110:43, :121:49, :122:60] wire _common_overflow_T_8 = rawIn_sign ? _common_overflow_T_4 : _common_overflow_T_7; // @[rawFloatFromRecFN.scala:55:23] wire _common_overflow_T_9 = unroundedInt[62]; // @[RecFNToIN.scala:90:40, :126:42] wire _common_overflow_T_10 = magGeOne_atOverflowEdge & _common_overflow_T_9; // @[RecFNToIN.scala:110:43, :125:50, :126:42] wire _common_overflow_T_11 = _common_overflow_T_10 & roundCarryBut2; // @[RecFNToIN.scala:113:61, :125:50, :126:57] wire _common_overflow_T_12 = rawIn_sign | _common_overflow_T_11; // @[rawFloatFromRecFN.scala:55:23] wire _common_overflow_T_13 = io_signedOut_0 ? _common_overflow_T_8 : _common_overflow_T_12; // @[RecFNToIN.scala:46:7, :117:20, :118:24, :124:32] wire _common_overflow_T_14 = _common_overflow_T | _common_overflow_T_13; // @[RecFNToIN.scala:116:{21,36}, :117:20] wire _common_overflow_T_15 = ~io_signedOut_0; // @[RecFNToIN.scala:46:7, :128:13] wire _common_overflow_T_16 = _common_overflow_T_15 & rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire _common_overflow_T_17 = _common_overflow_T_16 & roundIncr; // @[RecFNToIN.scala:101:46, :128:{27,41}] wire common_overflow = magGeOne ? _common_overflow_T_14 : _common_overflow_T_17; // @[RecFNToIN.scala:61:30, :115:12, :116:36, :128:41] wire invalidExc = rawIn_isNaN | rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire _overflow_T = ~invalidExc; // @[RecFNToIN.scala:133:34, :134:20] wire overflow = _overflow_T & common_overflow; // @[RecFNToIN.scala:115:12, :134:{20,32}] wire _inexact_T = ~invalidExc; // @[RecFNToIN.scala:133:34, :134:20, :135:20] wire _inexact_T_1 = ~common_overflow; // @[RecFNToIN.scala:115:12, :135:35] wire _inexact_T_2 = _inexact_T & _inexact_T_1; // @[RecFNToIN.scala:135:{20,32,35}] wire inexact = _inexact_T_2 & common_inexact; // @[RecFNToIN.scala:92:29, :135:{32,52}] wire _excSign_T = ~rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire excSign = _excSign_T & rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire _excOut_T = io_signedOut_0 == excSign; // @[RecFNToIN.scala:46:7, :137:32, :139:27] wire [63:0] _excOut_T_1 = {_excOut_T, 63'h0}; // @[RecFNToIN.scala:139:{12,27}] wire _excOut_T_2 = ~excSign; // @[RecFNToIN.scala:137:32, :143:13] wire [62:0] _excOut_T_3 = {63{_excOut_T_2}}; // @[RecFNToIN.scala:143:{12,13}] wire [63:0] excOut = {_excOut_T_1[63], _excOut_T_1[62:0] | _excOut_T_3}; // @[RecFNToIN.scala:139:12, :142:11, :143:12] wire _io_out_T = invalidExc | common_overflow; // @[RecFNToIN.scala:115:12, :133:34, :145:30] assign _io_out_T_1 = _io_out_T ? excOut : roundedInt; // @[RecFNToIN.scala:108:11, :142:11, :145:{18,30}] assign io_out_0 = _io_out_T_1; // @[RecFNToIN.scala:46:7, :145:18] wire [1:0] _io_intExceptionFlags_T = {invalidExc, overflow}; // @[RecFNToIN.scala:133:34, :134:32, :146:40] assign _io_intExceptionFlags_T_1 = {_io_intExceptionFlags_T, inexact}; // @[RecFNToIN.scala:135:52, :146:{40,52}] assign io_intExceptionFlags_0 = _io_intExceptionFlags_T_1; // @[RecFNToIN.scala:46:7, :146:52] assign io_out = io_out_0; // @[RecFNToIN.scala:46:7] assign io_intExceptionFlags = io_intExceptionFlags_0; // @[RecFNToIN.scala:46:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag }
module OptimizationBarrier_TLBEntryData_94( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to the following Chisel files. File RecFNToRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import consts._ class RecFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val in = Input(Bits((inExpWidth + inSigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawIn = rawFloatFromRecFN(inExpWidth, inSigWidth, io.in); if ((inExpWidth == outExpWidth) && (inSigWidth <= outSigWidth)) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- io.out := io.in<<(outSigWidth - inSigWidth) io.exceptionFlags := isSigNaNRawFloat(rawIn) ## 0.U(4.W) } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( inExpWidth, inSigWidth, outExpWidth, outSigWidth, flRoundOpt_sigMSBitAlwaysZero )) roundAnyRawFNToRecFN.io.invalidExc := isSigNaNRawFloat(rawIn) roundAnyRawFNToRecFN.io.infiniteExc := false.B roundAnyRawFNToRecFN.io.in := rawIn roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags } } File rawFloatFromRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ /*---------------------------------------------------------------------------- | In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be | set. *----------------------------------------------------------------------------*/ object rawFloatFromRecFN { def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat = { val exp = in(expWidth + sigWidth - 1, sigWidth - 1) val isZero = exp(expWidth, expWidth - 2) === 0.U val isSpecial = exp(expWidth, expWidth - 1) === 3.U val out = Wire(new RawFloat(expWidth, sigWidth)) out.isNaN := isSpecial && exp(expWidth - 2) out.isInf := isSpecial && ! exp(expWidth - 2) out.isZero := isZero out.sign := in(expWidth + sigWidth) out.sExp := exp.zext out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0) out } }
module RecFNToRecFN_141( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: package constellation.channel import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy._ import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.util._ import constellation.noc.{HasNoCParams} class NoCMonitor(val cParam: ChannelParams)(implicit val p: Parameters) extends Module with HasNoCParams { val io = IO(new Bundle { val in = Input(new Channel(cParam)) }) val in_flight = RegInit(VecInit(Seq.fill(cParam.nVirtualChannels) { false.B })) for (i <- 0 until cParam.srcSpeedup) { val flit = io.in.flit(i) when (flit.valid) { when (flit.bits.head) { in_flight(flit.bits.virt_channel_id) := true.B assert (!in_flight(flit.bits.virt_channel_id), "Flit head/tail sequencing is broken") } when (flit.bits.tail) { in_flight(flit.bits.virt_channel_id) := false.B } } val possibleFlows = cParam.possibleFlows when (flit.valid && flit.bits.head) { cParam match { case n: ChannelParams => n.virtualChannelParams.zipWithIndex.foreach { case (v,i) => assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR) } case _ => assert(cParam.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR) } } } } File Types.scala: package constellation.routing import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Parameters} import constellation.noc.{HasNoCParams} import constellation.channel.{Flit} /** A representation for 1 specific virtual channel in wormhole routing * * @param src the source node * @param vc ID for the virtual channel * @param dst the destination node * @param n_vc the number of virtual channels */ // BEGIN: ChannelRoutingInfo case class ChannelRoutingInfo( src: Int, dst: Int, vc: Int, n_vc: Int ) { // END: ChannelRoutingInfo require (src >= -1 && dst >= -1 && vc >= 0, s"Illegal $this") require (!(src == -1 && dst == -1), s"Illegal $this") require (vc < n_vc, s"Illegal $this") val isIngress = src == -1 val isEgress = dst == -1 } /** Represents the properties of a packet that are relevant for routing * ingressId and egressId uniquely identify a flow, but vnet and dst are used here * to simplify the implementation of routingrelations * * @param ingressId packet's source ingress point * @param egressId packet's destination egress point * @param vNet virtual subnetwork identifier * @param dst packet's destination node ID */ // BEGIN: FlowRoutingInfo case class FlowRoutingInfo( ingressId: Int, egressId: Int, vNetId: Int, ingressNode: Int, ingressNodeId: Int, egressNode: Int, egressNodeId: Int, fifo: Boolean ) { // END: FlowRoutingInfo def isFlow(f: FlowRoutingBundle): Bool = { (f.ingress_node === ingressNode.U && f.egress_node === egressNode.U && f.ingress_node_id === ingressNodeId.U && f.egress_node_id === egressNodeId.U) } def asLiteral(b: FlowRoutingBundle): BigInt = { Seq( (vNetId , b.vnet_id), (ingressNode , b.ingress_node), (ingressNodeId , b.ingress_node_id), (egressNode , b.egress_node), (egressNodeId , b.egress_node_id) ).foldLeft(0)((l, t) => { (l << t._2.getWidth) | t._1 }) } } class FlowRoutingBundle(implicit val p: Parameters) extends Bundle with HasNoCParams { // Instead of tracking ingress/egress ID, track the physical destination id and the offset at the destination // This simplifies the routing tables val vnet_id = UInt(log2Ceil(nVirtualNetworks).W) val ingress_node = UInt(log2Ceil(nNodes).W) val ingress_node_id = UInt(log2Ceil(maxIngressesAtNode).W) val egress_node = UInt(log2Ceil(nNodes).W) val egress_node_id = UInt(log2Ceil(maxEgressesAtNode).W) }
module NoCMonitor_55( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [5:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [2:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [5:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [2:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input [4:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26] reg in_flight_2; // @[Monitor.scala:16:26] reg in_flight_3; // @[Monitor.scala:16:26] reg in_flight_4; // @[Monitor.scala:16:26] reg in_flight_5; // @[Monitor.scala:16:26] reg in_flight_6; // @[Monitor.scala:16:26] reg in_flight_7; // @[Monitor.scala:16:26] reg in_flight_8; // @[Monitor.scala:16:26] reg in_flight_9; // @[Monitor.scala:16:26] reg in_flight_10; // @[Monitor.scala:16:26] reg in_flight_11; // @[Monitor.scala:16:26] reg in_flight_12; // @[Monitor.scala:16:26] reg in_flight_13; // @[Monitor.scala:16:26] reg in_flight_14; // @[Monitor.scala:16:26] reg in_flight_15; // @[Monitor.scala:16:26] reg in_flight_16; // @[Monitor.scala:16:26] reg in_flight_17; // @[Monitor.scala:16:26] reg in_flight_18; // @[Monitor.scala:16:26] reg in_flight_19; // @[Monitor.scala:16:26] reg in_flight_20; // @[Monitor.scala:16:26] reg in_flight_21; // @[Monitor.scala:16:26] wire _GEN = io_in_flit_0_bits_virt_channel_id == 5'h0; // @[Monitor.scala:21:46] wire _GEN_0 = io_in_flit_0_bits_virt_channel_id == 5'h1; // @[Monitor.scala:21:46] wire _GEN_1 = io_in_flit_0_bits_virt_channel_id == 5'h2; // @[Monitor.scala:21:46] wire _GEN_2 = io_in_flit_0_bits_virt_channel_id == 5'h3; // @[Monitor.scala:21:46] wire _GEN_3 = io_in_flit_0_bits_virt_channel_id == 5'h4; // @[Monitor.scala:21:46] wire _GEN_4 = io_in_flit_0_bits_virt_channel_id == 5'h5; // @[Monitor.scala:21:46] wire _GEN_5 = io_in_flit_0_bits_virt_channel_id == 5'h6; // @[Monitor.scala:21:46] wire _GEN_6 = io_in_flit_0_bits_virt_channel_id == 5'h7; // @[Monitor.scala:21:46] wire _GEN_7 = io_in_flit_0_bits_virt_channel_id == 5'h8; // @[Monitor.scala:21:46] wire _GEN_8 = io_in_flit_0_bits_virt_channel_id == 5'h9; // @[Monitor.scala:21:46] wire _GEN_9 = io_in_flit_0_bits_virt_channel_id == 5'hC; // @[Monitor.scala:21:46] wire _GEN_10 = io_in_flit_0_bits_virt_channel_id == 5'hD; // @[Monitor.scala:21:46] wire _GEN_11 = io_in_flit_0_bits_virt_channel_id == 5'h10; // @[Monitor.scala:21:46] wire _GEN_12 = io_in_flit_0_bits_virt_channel_id == 5'h11; // @[Monitor.scala:21:46]
Generate the Verilog code corresponding to the following Chisel files. File util.scala: //****************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v4.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v4.common.{MicroOp} import boom.v4.exu.{BrUpdateInfo} /** * Object to XOR fold a input register of fullLength into a compressedLength. */ object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /** * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks */ object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, flush: Bool, uop: MicroOp): Bool = { return apply(brupdate, flush, uop.br_mask) } def apply(brupdate: BrUpdateInfo, flush: Bool, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) || flush } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: T): Bool = { return apply(brupdate, flush, bundle.uop) } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Bool = { return apply(brupdate, flush, bundle.bits) } } /** * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. */ object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /** * Object to return a BR mask given a MicroOp mask and old BR mask. */ object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, flush, bundle.bits.uop.br_mask) out } } /** * Object to check if at least 1 bit matches in two masks */ object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /** * Object to clear one bit in a mask given an index */ object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /** * Object to shift a register over by one bit and concat a new one */ object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /** * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. */ object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /** * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. */ object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc | (b-1).U) } } /** * Object to rotate a signal left by one */ object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /** * Object to sext a value to a particular length. */ object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /** * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. */ object ImmGen { import boom.v4.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U, IS_N} def apply(i: UInt, isel: UInt): UInt = { val ip = Mux(isel === IS_N, 0.U(LONGEST_IMM_SZ.W), i) val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0) } } /** * Object to see if an instruction is a JALR. */ object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /** * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). */ object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /** * Object to return the lowest bit position after the head. */ object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /** * Object to determine whether queue * index i0 is older than index i1. */ object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } object IsYoungerMask { def apply(i: UInt, head: UInt, n: Integer): UInt = { val hi_mask = ~MaskLower(UIntToOH(i)(n-1,0)) val lo_mask = ~MaskUpper(UIntToOH(head)(n-1,0)) Mux(i < head, hi_mask & lo_mask, hi_mask | lo_mask)(n-1,0) } } /** * Set all bits at or below the highest order '1'. */ object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_|_) } } /** * Set all bits at or above the lowest order '1'. */ object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_) } } /** * Transpose a matrix of Chisel Vecs. */ object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /** * N-wide one-hot priority encoder. */ object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /** * Connect the first k of n valid input interfaces to k output interfaces. */ class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_)) val out_valids = sels map (col => col.reduce(_||_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /** * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). */ class BranchKillableQueue[T <: boom.v4.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v4.common.MicroOp => Bool = u => true.B, fastDeq: Boolean = false) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) if (fastDeq && entries > 1) { // Pipeline dequeue selection so the mux gets an entire cycle val main = Module(new BranchKillableQueue(gen, entries-1, flush_fn, false)) val out_reg = Reg(gen) val out_valid = RegInit(false.B) val out_uop = Reg(new MicroOp) main.io.enq <> io.enq main.io.brupdate := io.brupdate main.io.flush := io.flush io.empty := main.io.empty && !out_valid io.count := main.io.count + out_valid io.deq.valid := out_valid io.deq.bits := out_reg io.deq.bits.uop := out_uop out_uop := UpdateBrMask(io.brupdate, out_uop) out_valid := out_valid && !IsKilledByBranch(io.brupdate, false.B, out_uop) && !(io.flush && flush_fn(out_uop)) main.io.deq.ready := false.B when (io.deq.fire || !out_valid) { out_valid := main.io.deq.valid && !IsKilledByBranch(io.brupdate, false.B, main.io.deq.bits.uop) && !(io.flush && flush_fn(main.io.deq.bits.uop)) out_reg := main.io.deq.bits out_uop := UpdateBrMask(io.brupdate, main.io.deq.bits.uop) main.io.deq.ready := true.B } } else { val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire && !IsKilledByBranch(io.brupdate, false.B, io.enq.bits.uop) && !(io.flush && flush_fn(io.enq.bits.uop))) val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, false.B, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) io.deq.bits := out val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /** * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" */ def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) */ def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) */ def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) */ def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /** * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line */ def apply(strs: String*)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } class BranchKillablePipeline[T <: boom.v4.common.HasBoomUOP](gen: T, stages: Int) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val req = Input(Valid(gen)) val flush = Input(Bool()) val brupdate = Input(new BrUpdateInfo) val resp = Output(Vec(stages, Valid(gen))) }) require(stages > 0) val uops = Reg(Vec(stages, Valid(gen))) uops(0).valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.flush, io.req.bits) uops(0).bits := UpdateBrMask(io.brupdate, io.req.bits) for (i <- 1 until stages) { uops(i).valid := uops(i-1).valid && !IsKilledByBranch(io.brupdate, io.flush, uops(i-1).bits) uops(i).bits := UpdateBrMask(io.brupdate, uops(i-1).bits) } for (i <- 0 until stages) { when (reset.asBool) { uops(i).valid := false.B } } io.resp := uops } File issue-slot.scala: //****************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Issue Slot Logic //-------------------------------------------------------------------------- //------------------------------------------------------------------------------ // // Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot. // TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores. // TODO Disable ldspec for FP queue. package boom.v4.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import boom.v4.common._ import boom.v4.util._ class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle { val valid = Output(Bool()) val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely? val request = Output(Bool()) val grant = Input(Bool()) val iss_uop = Output(new MicroOp()) val in_uop = Input(Valid(new MicroOp())) // if valid, this WILL overwrite an entry! val out_uop = Output(new MicroOp()) val brupdate = Input(new BrUpdateInfo()) val kill = Input(Bool()) // pipeline flush val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant) val squash_grant = Input(Bool()) val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new Wakeup))) val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W))) val child_rebusys = Input(UInt(aluWidth.W)) } class IssueSlot(val numWakeupPorts: Int, val isMem: Boolean, val isFp: Boolean)(implicit p: Parameters) extends BoomModule { val io = IO(new IssueSlotIO(numWakeupPorts)) val slot_valid = RegInit(false.B) val slot_uop = Reg(new MicroOp()) val next_valid = WireInit(slot_valid) val next_uop = WireInit(UpdateBrMask(io.brupdate, slot_uop)) val killed = IsKilledByBranch(io.brupdate, io.kill, slot_uop) io.valid := slot_valid io.out_uop := next_uop io.will_be_valid := next_valid && !killed when (io.kill) { slot_valid := false.B } .elsewhen (io.in_uop.valid) { slot_valid := true.B } .elsewhen (io.clear) { slot_valid := false.B } .otherwise { slot_valid := next_valid && !killed } when (io.in_uop.valid) { slot_uop := io.in_uop.bits assert (!slot_valid || io.clear || io.kill) } .otherwise { slot_uop := next_uop } // Wakeups next_uop.iw_p1_bypass_hint := false.B next_uop.iw_p2_bypass_hint := false.B next_uop.iw_p3_bypass_hint := false.B next_uop.iw_p1_speculative_child := 0.U next_uop.iw_p2_speculative_child := 0.U val rebusied_prs1 = WireInit(false.B) val rebusied_prs2 = WireInit(false.B) val rebusied = rebusied_prs1 || rebusied_prs2 val prs1_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs1 } val prs2_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs2 } val prs3_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs3 } val prs1_wakeups = (io.wakeup_ports zip prs1_matches).map { case (w,m) => w.valid && m } val prs2_wakeups = (io.wakeup_ports zip prs2_matches).map { case (w,m) => w.valid && m } val prs3_wakeups = (io.wakeup_ports zip prs3_matches).map { case (w,m) => w.valid && m } val prs1_rebusys = (io.wakeup_ports zip prs1_matches).map { case (w,m) => w.bits.rebusy && m } val prs2_rebusys = (io.wakeup_ports zip prs2_matches).map { case (w,m) => w.bits.rebusy && m } val bypassables = io.wakeup_ports.map { w => w.bits.bypassable } val speculative_masks = io.wakeup_ports.map { w => w.bits.speculative_mask } when (prs1_wakeups.reduce(_||_)) { next_uop.prs1_busy := false.B next_uop.iw_p1_speculative_child := Mux1H(prs1_wakeups, speculative_masks) next_uop.iw_p1_bypass_hint := Mux1H(prs1_wakeups, bypassables) } when ((prs1_rebusys.reduce(_||_) || ((io.child_rebusys & slot_uop.iw_p1_speculative_child) =/= 0.U)) && slot_uop.lrs1_rtype === RT_FIX) { next_uop.prs1_busy := true.B rebusied_prs1 := true.B } when (prs2_wakeups.reduce(_||_)) { next_uop.prs2_busy := false.B next_uop.iw_p2_speculative_child := Mux1H(prs2_wakeups, speculative_masks) next_uop.iw_p2_bypass_hint := Mux1H(prs2_wakeups, bypassables) } when ((prs2_rebusys.reduce(_||_) || ((io.child_rebusys & slot_uop.iw_p2_speculative_child) =/= 0.U)) && slot_uop.lrs2_rtype === RT_FIX) { next_uop.prs2_busy := true.B rebusied_prs2 := true.B } when (prs3_wakeups.reduce(_||_)) { next_uop.prs3_busy := false.B next_uop.iw_p3_bypass_hint := Mux1H(prs3_wakeups, bypassables) } when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === slot_uop.ppred) { next_uop.ppred_busy := false.B } val iss_ready = !slot_uop.prs1_busy && !slot_uop.prs2_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && !(slot_uop.prs3_busy && isFp.B) val agen_ready = (slot_uop.fu_code(FC_AGEN) && !slot_uop.prs1_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && isMem.B) val dgen_ready = (slot_uop.fu_code(FC_DGEN) && !slot_uop.prs2_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && isMem.B) io.request := slot_valid && !slot_uop.iw_issued && ( iss_ready || agen_ready || dgen_ready ) io.iss_uop := slot_uop // Update state for current micro-op based on grant next_uop.iw_issued := false.B next_uop.iw_issued_partial_agen := false.B next_uop.iw_issued_partial_dgen := false.B when (io.grant && !io.squash_grant) { next_uop.iw_issued := true.B } if (isMem) { when (slot_uop.fu_code(FC_AGEN) && slot_uop.fu_code(FC_DGEN)) { when (agen_ready) { // Issue the AGEN, next slot entry is a DGEN when (io.grant && !io.squash_grant) { next_uop.iw_issued_partial_agen := true.B } io.iss_uop.fu_code(FC_AGEN) := true.B io.iss_uop.fu_code(FC_DGEN) := false.B } .otherwise { // Issue the DGEN, next slot entry is the AGEN when (io.grant && !io.squash_grant) { next_uop.iw_issued_partial_dgen := true.B } io.iss_uop.fu_code(FC_AGEN) := false.B io.iss_uop.fu_code(FC_DGEN) := true.B io.iss_uop.imm_sel := IS_N io.iss_uop.prs1 := slot_uop.prs2 io.iss_uop.lrs1_rtype := slot_uop.lrs2_rtype io.iss_uop.iw_p1_bypass_hint := slot_uop.iw_p2_bypass_hint } } .elsewhen (slot_uop.fu_code(FC_DGEN)) { io.iss_uop.imm_sel := IS_N io.iss_uop.prs1 := slot_uop.prs2 io.iss_uop.lrs1_rtype := slot_uop.lrs2_rtype io.iss_uop.iw_p1_bypass_hint := slot_uop.iw_p2_bypass_hint } io.iss_uop.lrs2_rtype := RT_X io.iss_uop.prs2 := io.iss_uop.prs1 // helps with DCE } when (slot_valid && slot_uop.iw_issued) { next_valid := rebusied if (isMem) { when (slot_uop.iw_issued_partial_agen) { next_valid := true.B when (!rebusied_prs1) { next_uop.fu_code(FC_AGEN) := false.B next_uop.fu_code(FC_DGEN) := true.B } } .elsewhen (slot_uop.iw_issued_partial_dgen) { next_valid := true.B when (!rebusied_prs2) { next_uop.fu_code(FC_AGEN) := true.B next_uop.fu_code(FC_DGEN) := false.B } } } } }
module IssueSlot_80( // @[issue-slot.scala:49:7] input clock, // @[issue-slot.scala:49:7] input reset, // @[issue-slot.scala:49:7] output io_valid, // @[issue-slot.scala:52:14] output io_will_be_valid, // @[issue-slot.scala:52:14] output io_request, // @[issue-slot.scala:52:14] input io_grant, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_debug_inst, // @[issue-slot.scala:52:14] output io_iss_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_iss_uop_debug_pc, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_iss_uop_iw_issued, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [15:0] io_iss_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_type, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfb, // @[issue-slot.scala:52:14] output io_iss_uop_is_fence, // @[issue-slot.scala:52:14] output io_iss_uop_is_fencei, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfence, // @[issue-slot.scala:52:14] output io_iss_uop_is_amo, // @[issue-slot.scala:52:14] output io_iss_uop_is_eret, // @[issue-slot.scala:52:14] output io_iss_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_iss_uop_is_rocc, // @[issue-slot.scala:52:14] output io_iss_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_iss_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_pc_lob, // @[issue-slot.scala:52:14] output io_iss_uop_taken, // @[issue-slot.scala:52:14] output io_iss_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_iss_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_op2_sel, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_rob_idx, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ldq_idx, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ppred, // @[issue-slot.scala:52:14] output io_iss_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_iss_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_iss_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_iss_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_mem_size, // @[issue-slot.scala:52:14] output io_iss_uop_mem_signed, // @[issue-slot.scala:52:14] output io_iss_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_iss_uop_uses_stq, // @[issue-slot.scala:52:14] output io_iss_uop_is_unique, // @[issue-slot.scala:52:14] output io_iss_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_iss_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_iss_uop_frs3_en, // @[issue-slot.scala:52:14] output io_iss_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_fcn_op, // @[issue-slot.scala:52:14] output io_iss_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_typ, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_in_uop_valid, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_4, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_5, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_6, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_7, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_8, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_9, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_type, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_eret, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rocc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:52:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:52:14] input io_in_uop_bits_taken, // @[issue-slot.scala:52:14] input io_in_uop_bits_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_pimm, // @[issue-slot.scala:52:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_op2_sel, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:52:14] input io_in_uop_bits_exception, // @[issue-slot.scala:52:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:52:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:52:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_csr_cmd, // @[issue-slot.scala:52:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:52:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:52:14] input io_in_uop_bits_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_fcn_op, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_typ, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:52:14] output io_out_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_out_uop_iw_issued, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_out_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_type, // @[issue-slot.scala:52:14] output io_out_uop_is_sfb, // @[issue-slot.scala:52:14] output io_out_uop_is_fence, // @[issue-slot.scala:52:14] output io_out_uop_is_fencei, // @[issue-slot.scala:52:14] output io_out_uop_is_sfence, // @[issue-slot.scala:52:14] output io_out_uop_is_amo, // @[issue-slot.scala:52:14] output io_out_uop_is_eret, // @[issue-slot.scala:52:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_out_uop_is_rocc, // @[issue-slot.scala:52:14] output io_out_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_out_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:52:14] output io_out_uop_taken, // @[issue-slot.scala:52:14] output io_out_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_op2_sel, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:52:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_out_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:52:14] output io_out_uop_mem_signed, // @[issue-slot.scala:52:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_out_uop_uses_stq, // @[issue-slot.scala:52:14] output io_out_uop_is_unique, // @[issue-slot.scala:52:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_out_uop_frs3_en, // @[issue-slot.scala:52:14] output io_out_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_fcn_op, // @[issue-slot.scala:52:14] output io_out_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_typ, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_type, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_eret, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rocc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:52:14] input io_brupdate_b2_taken, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:52:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:52:14] input io_kill, // @[issue-slot.scala:52:14] input io_clear, // @[issue-slot.scala:52:14] input io_squash_grant, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_bypassable, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_speculative_mask, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_rebusy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_2_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_2_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_2_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_2_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_2_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_2_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_3_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_3_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_3_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_3_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_3_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_3_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_4_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_4_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_4_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_4_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_4_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_4_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_4_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_4_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_pred_wakeup_port_valid, // @[issue-slot.scala:52:14] input [4:0] io_pred_wakeup_port_bits, // @[issue-slot.scala:52:14] input [2:0] io_child_rebusys // @[issue-slot.scala:52:14] ); wire [15:0] next_uop_out_br_mask; // @[util.scala:104:23] wire io_grant_0 = io_grant; // @[issue-slot.scala:49:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_0_0 = io_in_uop_bits_iq_type_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_1_0 = io_in_uop_bits_iq_type_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_2_0 = io_in_uop_bits_iq_type_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_3_0 = io_in_uop_bits_iq_type_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_0_0 = io_in_uop_bits_fu_code_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_1_0 = io_in_uop_bits_fu_code_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_2_0 = io_in_uop_bits_fu_code_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_3_0 = io_in_uop_bits_fu_code_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_4_0 = io_in_uop_bits_fu_code_4; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_5_0 = io_in_uop_bits_fu_code_5; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_6_0 = io_in_uop_bits_fu_code_6; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_7_0 = io_in_uop_bits_fu_code_7; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_8_0 = io_in_uop_bits_fu_code_8; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_9_0 = io_in_uop_bits_fu_code_9; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_0 = io_in_uop_bits_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_iw_p1_speculative_child_0 = io_in_uop_bits_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_iw_p2_speculative_child_0 = io_in_uop_bits_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p1_bypass_hint_0 = io_in_uop_bits_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p2_bypass_hint_0 = io_in_uop_bits_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p3_bypass_hint_0 = io_in_uop_bits_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_dis_col_sel_0 = io_in_uop_bits_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_type_0 = io_in_uop_bits_br_type; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfence_0 = io_in_uop_bits_is_sfence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_eret_0 = io_in_uop_bits_is_eret; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rocc_0 = io_in_uop_bits_is_rocc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_mov_0 = io_in_uop_bits_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:49:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:49:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:49:7] wire io_in_uop_bits_imm_rename_0 = io_in_uop_bits_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_imm_sel_0 = io_in_uop_bits_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_pimm_0 = io_in_uop_bits_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_op1_sel_0 = io_in_uop_bits_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_op2_sel_0 = io_in_uop_bits_op2_sel; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ldst_0 = io_in_uop_bits_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wen_0 = io_in_uop_bits_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren1_0 = io_in_uop_bits_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren2_0 = io_in_uop_bits_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren3_0 = io_in_uop_bits_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap12_0 = io_in_uop_bits_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap23_0 = io_in_uop_bits_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagIn_0 = io_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagOut_0 = io_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fromint_0 = io_in_uop_bits_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_toint_0 = io_in_uop_bits_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fastpipe_0 = io_in_uop_bits_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fma_0 = io_in_uop_bits_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_div_0 = io_in_uop_bits_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_sqrt_0 = io_in_uop_bits_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wflags_0 = io_in_uop_bits_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_vec_0 = io_in_uop_bits_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:49:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:49:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:49:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_csr_cmd_0 = io_in_uop_bits_csr_cmd; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fcn_dw_0 = io_in_uop_bits_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_fcn_op_0 = io_in_uop_bits_fcn_op; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_fp_rm_0 = io_in_uop_bits_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_typ_0 = io_in_uop_bits_fp_typ; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:49:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:49:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:49:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:49:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:49:7] wire io_squash_grant_0 = io_squash_grant; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_bypassable_0 = io_wakeup_ports_0_bits_bypassable; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_speculative_mask_0 = io_wakeup_ports_0_bits_speculative_mask; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_rebusy_0 = io_wakeup_ports_0_bits_rebusy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_2_bits_uop_inst_0 = io_wakeup_ports_2_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_2_bits_uop_debug_inst_0 = io_wakeup_ports_2_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_rvc_0 = io_wakeup_ports_2_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_2_bits_uop_debug_pc_0 = io_wakeup_ports_2_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_0_0 = io_wakeup_ports_2_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_1_0 = io_wakeup_ports_2_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_2_0 = io_wakeup_ports_2_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_3_0 = io_wakeup_ports_2_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_0_0 = io_wakeup_ports_2_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_1_0 = io_wakeup_ports_2_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_2_0 = io_wakeup_ports_2_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_3_0 = io_wakeup_ports_2_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_4_0 = io_wakeup_ports_2_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_5_0 = io_wakeup_ports_2_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_6_0 = io_wakeup_ports_2_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_7_0 = io_wakeup_ports_2_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_8_0 = io_wakeup_ports_2_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_9_0 = io_wakeup_ports_2_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_0 = io_wakeup_ports_2_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel_0 = io_wakeup_ports_2_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_2_bits_uop_br_mask_0 = io_wakeup_ports_2_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_tag_0 = io_wakeup_ports_2_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_type_0 = io_wakeup_ports_2_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sfb_0 = io_wakeup_ports_2_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_fence_0 = io_wakeup_ports_2_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_fencei_0 = io_wakeup_ports_2_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sfence_0 = io_wakeup_ports_2_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_amo_0 = io_wakeup_ports_2_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_eret_0 = io_wakeup_ports_2_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_2_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_rocc_0 = io_wakeup_ports_2_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_mov_0 = io_wakeup_ports_2_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ftq_idx_0 = io_wakeup_ports_2_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_edge_inst_0 = io_wakeup_ports_2_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_pc_lob_0 = io_wakeup_ports_2_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_taken_0 = io_wakeup_ports_2_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_imm_rename_0 = io_wakeup_ports_2_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_imm_sel_0 = io_wakeup_ports_2_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_pimm_0 = io_wakeup_ports_2_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_2_bits_uop_imm_packed_0 = io_wakeup_ports_2_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_op1_sel_0 = io_wakeup_ports_2_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_op2_sel_0 = io_wakeup_ports_2_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_rob_idx_0 = io_wakeup_ports_2_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ldq_idx_0 = io_wakeup_ports_2_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_stq_idx_0 = io_wakeup_ports_2_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_rxq_idx_0 = io_wakeup_ports_2_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_pdst_0 = io_wakeup_ports_2_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs1_0 = io_wakeup_ports_2_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs2_0 = io_wakeup_ports_2_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs3_0 = io_wakeup_ports_2_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ppred_0 = io_wakeup_ports_2_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs1_busy_0 = io_wakeup_ports_2_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs2_busy_0 = io_wakeup_ports_2_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs3_busy_0 = io_wakeup_ports_2_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_ppred_busy_0 = io_wakeup_ports_2_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_stale_pdst_0 = io_wakeup_ports_2_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_exception_0 = io_wakeup_ports_2_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_2_bits_uop_exc_cause_0 = io_wakeup_ports_2_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_mem_cmd_0 = io_wakeup_ports_2_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_mem_size_0 = io_wakeup_ports_2_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_mem_signed_0 = io_wakeup_ports_2_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_uses_ldq_0 = io_wakeup_ports_2_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_uses_stq_0 = io_wakeup_ports_2_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_unique_0 = io_wakeup_ports_2_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_flush_on_commit_0 = io_wakeup_ports_2_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_csr_cmd_0 = io_wakeup_ports_2_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_2_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_ldst_0 = io_wakeup_ports_2_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs1_0 = io_wakeup_ports_2_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs2_0 = io_wakeup_ports_2_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs3_0 = io_wakeup_ports_2_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_dst_rtype_0 = io_wakeup_ports_2_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype_0 = io_wakeup_ports_2_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype_0 = io_wakeup_ports_2_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_frs3_en_0 = io_wakeup_ports_2_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fcn_dw_0 = io_wakeup_ports_2_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_fcn_op_0 = io_wakeup_ports_2_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_val_0 = io_wakeup_ports_2_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_fp_rm_0 = io_wakeup_ports_2_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_typ_0 = io_wakeup_ports_2_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_2_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_bp_debug_if_0 = io_wakeup_ports_2_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_2_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc_0 = io_wakeup_ports_2_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc_0 = io_wakeup_ports_2_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_3_bits_uop_inst_0 = io_wakeup_ports_3_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_3_bits_uop_debug_inst_0 = io_wakeup_ports_3_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_rvc_0 = io_wakeup_ports_3_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_3_bits_uop_debug_pc_0 = io_wakeup_ports_3_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_0_0 = io_wakeup_ports_3_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_1_0 = io_wakeup_ports_3_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_2_0 = io_wakeup_ports_3_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_3_0 = io_wakeup_ports_3_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_0_0 = io_wakeup_ports_3_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_1_0 = io_wakeup_ports_3_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_2_0 = io_wakeup_ports_3_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_3_0 = io_wakeup_ports_3_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_4_0 = io_wakeup_ports_3_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_5_0 = io_wakeup_ports_3_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_6_0 = io_wakeup_ports_3_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_7_0 = io_wakeup_ports_3_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_8_0 = io_wakeup_ports_3_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_9_0 = io_wakeup_ports_3_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_0 = io_wakeup_ports_3_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel_0 = io_wakeup_ports_3_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_3_bits_uop_br_mask_0 = io_wakeup_ports_3_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_tag_0 = io_wakeup_ports_3_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_type_0 = io_wakeup_ports_3_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sfb_0 = io_wakeup_ports_3_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_fence_0 = io_wakeup_ports_3_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_fencei_0 = io_wakeup_ports_3_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sfence_0 = io_wakeup_ports_3_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_amo_0 = io_wakeup_ports_3_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_eret_0 = io_wakeup_ports_3_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_3_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_rocc_0 = io_wakeup_ports_3_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_mov_0 = io_wakeup_ports_3_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ftq_idx_0 = io_wakeup_ports_3_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_edge_inst_0 = io_wakeup_ports_3_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_pc_lob_0 = io_wakeup_ports_3_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_taken_0 = io_wakeup_ports_3_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_imm_rename_0 = io_wakeup_ports_3_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_imm_sel_0 = io_wakeup_ports_3_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_pimm_0 = io_wakeup_ports_3_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_3_bits_uop_imm_packed_0 = io_wakeup_ports_3_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_op1_sel_0 = io_wakeup_ports_3_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_op2_sel_0 = io_wakeup_ports_3_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_rob_idx_0 = io_wakeup_ports_3_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ldq_idx_0 = io_wakeup_ports_3_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_stq_idx_0 = io_wakeup_ports_3_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_rxq_idx_0 = io_wakeup_ports_3_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_pdst_0 = io_wakeup_ports_3_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs1_0 = io_wakeup_ports_3_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs2_0 = io_wakeup_ports_3_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs3_0 = io_wakeup_ports_3_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ppred_0 = io_wakeup_ports_3_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs1_busy_0 = io_wakeup_ports_3_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs2_busy_0 = io_wakeup_ports_3_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs3_busy_0 = io_wakeup_ports_3_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_ppred_busy_0 = io_wakeup_ports_3_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_stale_pdst_0 = io_wakeup_ports_3_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_exception_0 = io_wakeup_ports_3_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_3_bits_uop_exc_cause_0 = io_wakeup_ports_3_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_mem_cmd_0 = io_wakeup_ports_3_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_mem_size_0 = io_wakeup_ports_3_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_mem_signed_0 = io_wakeup_ports_3_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_uses_ldq_0 = io_wakeup_ports_3_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_uses_stq_0 = io_wakeup_ports_3_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_unique_0 = io_wakeup_ports_3_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_flush_on_commit_0 = io_wakeup_ports_3_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_csr_cmd_0 = io_wakeup_ports_3_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_3_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_ldst_0 = io_wakeup_ports_3_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs1_0 = io_wakeup_ports_3_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs2_0 = io_wakeup_ports_3_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs3_0 = io_wakeup_ports_3_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_dst_rtype_0 = io_wakeup_ports_3_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype_0 = io_wakeup_ports_3_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype_0 = io_wakeup_ports_3_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_frs3_en_0 = io_wakeup_ports_3_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fcn_dw_0 = io_wakeup_ports_3_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_fcn_op_0 = io_wakeup_ports_3_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_val_0 = io_wakeup_ports_3_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_fp_rm_0 = io_wakeup_ports_3_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_typ_0 = io_wakeup_ports_3_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_3_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_bp_debug_if_0 = io_wakeup_ports_3_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_3_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc_0 = io_wakeup_ports_3_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc_0 = io_wakeup_ports_3_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_4_bits_uop_inst_0 = io_wakeup_ports_4_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_4_bits_uop_debug_inst_0 = io_wakeup_ports_4_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_rvc_0 = io_wakeup_ports_4_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_4_bits_uop_debug_pc_0 = io_wakeup_ports_4_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_0_0 = io_wakeup_ports_4_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_1_0 = io_wakeup_ports_4_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_2_0 = io_wakeup_ports_4_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_3_0 = io_wakeup_ports_4_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_0_0 = io_wakeup_ports_4_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_1_0 = io_wakeup_ports_4_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_2_0 = io_wakeup_ports_4_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_3_0 = io_wakeup_ports_4_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_4_0 = io_wakeup_ports_4_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_5_0 = io_wakeup_ports_4_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_6_0 = io_wakeup_ports_4_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_7_0 = io_wakeup_ports_4_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_8_0 = io_wakeup_ports_4_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_9_0 = io_wakeup_ports_4_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_issued_0 = io_wakeup_ports_4_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel_0 = io_wakeup_ports_4_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_4_bits_uop_br_mask_0 = io_wakeup_ports_4_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_4_bits_uop_br_tag_0 = io_wakeup_ports_4_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_4_bits_uop_br_type_0 = io_wakeup_ports_4_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_sfb_0 = io_wakeup_ports_4_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_fence_0 = io_wakeup_ports_4_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_fencei_0 = io_wakeup_ports_4_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_sfence_0 = io_wakeup_ports_4_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_amo_0 = io_wakeup_ports_4_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_eret_0 = io_wakeup_ports_4_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_4_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_rocc_0 = io_wakeup_ports_4_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_mov_0 = io_wakeup_ports_4_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_ftq_idx_0 = io_wakeup_ports_4_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_edge_inst_0 = io_wakeup_ports_4_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_pc_lob_0 = io_wakeup_ports_4_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_taken_0 = io_wakeup_ports_4_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_imm_rename_0 = io_wakeup_ports_4_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_imm_sel_0 = io_wakeup_ports_4_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_pimm_0 = io_wakeup_ports_4_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_4_bits_uop_imm_packed_0 = io_wakeup_ports_4_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_op1_sel_0 = io_wakeup_ports_4_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_op2_sel_0 = io_wakeup_ports_4_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_rob_idx_0 = io_wakeup_ports_4_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_ldq_idx_0 = io_wakeup_ports_4_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_stq_idx_0 = io_wakeup_ports_4_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_rxq_idx_0 = io_wakeup_ports_4_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_pdst_0 = io_wakeup_ports_4_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_prs1_0 = io_wakeup_ports_4_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_prs2_0 = io_wakeup_ports_4_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_prs3_0 = io_wakeup_ports_4_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_ppred_0 = io_wakeup_ports_4_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_prs1_busy_0 = io_wakeup_ports_4_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_prs2_busy_0 = io_wakeup_ports_4_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_prs3_busy_0 = io_wakeup_ports_4_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_ppred_busy_0 = io_wakeup_ports_4_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_stale_pdst_0 = io_wakeup_ports_4_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_exception_0 = io_wakeup_ports_4_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_4_bits_uop_exc_cause_0 = io_wakeup_ports_4_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_mem_cmd_0 = io_wakeup_ports_4_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_mem_size_0 = io_wakeup_ports_4_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_mem_signed_0 = io_wakeup_ports_4_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_uses_ldq_0 = io_wakeup_ports_4_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_uses_stq_0 = io_wakeup_ports_4_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_unique_0 = io_wakeup_ports_4_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_flush_on_commit_0 = io_wakeup_ports_4_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_csr_cmd_0 = io_wakeup_ports_4_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_4_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_ldst_0 = io_wakeup_ports_4_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_lrs1_0 = io_wakeup_ports_4_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_lrs2_0 = io_wakeup_ports_4_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_lrs3_0 = io_wakeup_ports_4_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_dst_rtype_0 = io_wakeup_ports_4_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype_0 = io_wakeup_ports_4_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype_0 = io_wakeup_ports_4_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_frs3_en_0 = io_wakeup_ports_4_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fcn_dw_0 = io_wakeup_ports_4_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_fcn_op_0 = io_wakeup_ports_4_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_val_0 = io_wakeup_ports_4_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_fp_rm_0 = io_wakeup_ports_4_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_fp_typ_0 = io_wakeup_ports_4_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_4_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_bp_debug_if_0 = io_wakeup_ports_4_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_4_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc_0 = io_wakeup_ports_4_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc_0 = io_wakeup_ports_4_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_pred_wakeup_port_valid_0 = io_pred_wakeup_port_valid; // @[issue-slot.scala:49:7] wire [4:0] io_pred_wakeup_port_bits_0 = io_pred_wakeup_port_bits; // @[issue-slot.scala:49:7] wire [2:0] io_child_rebusys_0 = io_child_rebusys; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire next_uop_out_iw_issued_partial_agen = 1'h0; // @[util.scala:104:23] wire next_uop_out_iw_issued_partial_dgen = 1'h0; // @[util.scala:104:23] wire next_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:59:28] wire next_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:59:28] wire prs1_rebusys_1 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_2 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_3 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_4 = 1'h0; // @[issue-slot.scala:102:91] wire prs2_rebusys_1 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_2 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_3 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_4 = 1'h0; // @[issue-slot.scala:103:91] wire _next_uop_iw_p1_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p2_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p3_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _iss_ready_T_6 = 1'h0; // @[issue-slot.scala:136:131] wire agen_ready = 1'h0; // @[issue-slot.scala:137:114] wire dgen_ready = 1'h0; // @[issue-slot.scala:138:114] wire [2:0] io_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] _next_uop_iw_p1_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p2_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73] wire io_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire _iss_ready_T_7 = 1'h1; // @[issue-slot.scala:136:110] wire [2:0] io_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-slot.scala:49:7] wire _io_will_be_valid_T_1; // @[issue-slot.scala:65:34] wire _io_request_T_4; // @[issue-slot.scala:140:51] wire [31:0] next_uop_inst; // @[issue-slot.scala:59:28] wire [31:0] next_uop_debug_inst; // @[issue-slot.scala:59:28] wire next_uop_is_rvc; // @[issue-slot.scala:59:28] wire [39:0] next_uop_debug_pc; // @[issue-slot.scala:59:28] wire next_uop_iq_type_0; // @[issue-slot.scala:59:28] wire next_uop_iq_type_1; // @[issue-slot.scala:59:28] wire next_uop_iq_type_2; // @[issue-slot.scala:59:28] wire next_uop_iq_type_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_0; // @[issue-slot.scala:59:28] wire next_uop_fu_code_1; // @[issue-slot.scala:59:28] wire next_uop_fu_code_2; // @[issue-slot.scala:59:28] wire next_uop_fu_code_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_4; // @[issue-slot.scala:59:28] wire next_uop_fu_code_5; // @[issue-slot.scala:59:28] wire next_uop_fu_code_6; // @[issue-slot.scala:59:28] wire next_uop_fu_code_7; // @[issue-slot.scala:59:28] wire next_uop_fu_code_8; // @[issue-slot.scala:59:28] wire next_uop_fu_code_9; // @[issue-slot.scala:59:28] wire next_uop_iw_issued; // @[issue-slot.scala:59:28] wire [2:0] next_uop_iw_p1_speculative_child; // @[issue-slot.scala:59:28] wire [2:0] next_uop_iw_p2_speculative_child; // @[issue-slot.scala:59:28] wire next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:59:28] wire [2:0] next_uop_dis_col_sel; // @[issue-slot.scala:59:28] wire [15:0] next_uop_br_mask; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_tag; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_type; // @[issue-slot.scala:59:28] wire next_uop_is_sfb; // @[issue-slot.scala:59:28] wire next_uop_is_fence; // @[issue-slot.scala:59:28] wire next_uop_is_fencei; // @[issue-slot.scala:59:28] wire next_uop_is_sfence; // @[issue-slot.scala:59:28] wire next_uop_is_amo; // @[issue-slot.scala:59:28] wire next_uop_is_eret; // @[issue-slot.scala:59:28] wire next_uop_is_sys_pc2epc; // @[issue-slot.scala:59:28] wire next_uop_is_rocc; // @[issue-slot.scala:59:28] wire next_uop_is_mov; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ftq_idx; // @[issue-slot.scala:59:28] wire next_uop_edge_inst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_pc_lob; // @[issue-slot.scala:59:28] wire next_uop_taken; // @[issue-slot.scala:59:28] wire next_uop_imm_rename; // @[issue-slot.scala:59:28] wire [2:0] next_uop_imm_sel; // @[issue-slot.scala:59:28] wire [4:0] next_uop_pimm; // @[issue-slot.scala:59:28] wire [19:0] next_uop_imm_packed; // @[issue-slot.scala:59:28] wire [1:0] next_uop_op1_sel; // @[issue-slot.scala:59:28] wire [2:0] next_uop_op2_sel; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ldst; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wen; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren1; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren2; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren3; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap12; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap23; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fromint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_toint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fma; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_div; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wflags; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_vec; // @[issue-slot.scala:59:28] wire [6:0] next_uop_rob_idx; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ldq_idx; // @[issue-slot.scala:59:28] wire [4:0] next_uop_stq_idx; // @[issue-slot.scala:59:28] wire [1:0] next_uop_rxq_idx; // @[issue-slot.scala:59:28] wire [6:0] next_uop_pdst; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs1; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs2; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs3; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ppred; // @[issue-slot.scala:59:28] wire next_uop_prs1_busy; // @[issue-slot.scala:59:28] wire next_uop_prs2_busy; // @[issue-slot.scala:59:28] wire next_uop_prs3_busy; // @[issue-slot.scala:59:28] wire next_uop_ppred_busy; // @[issue-slot.scala:59:28] wire [6:0] next_uop_stale_pdst; // @[issue-slot.scala:59:28] wire next_uop_exception; // @[issue-slot.scala:59:28] wire [63:0] next_uop_exc_cause; // @[issue-slot.scala:59:28] wire [4:0] next_uop_mem_cmd; // @[issue-slot.scala:59:28] wire [1:0] next_uop_mem_size; // @[issue-slot.scala:59:28] wire next_uop_mem_signed; // @[issue-slot.scala:59:28] wire next_uop_uses_ldq; // @[issue-slot.scala:59:28] wire next_uop_uses_stq; // @[issue-slot.scala:59:28] wire next_uop_is_unique; // @[issue-slot.scala:59:28] wire next_uop_flush_on_commit; // @[issue-slot.scala:59:28] wire [2:0] next_uop_csr_cmd; // @[issue-slot.scala:59:28] wire next_uop_ldst_is_rs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_ldst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs2; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs3; // @[issue-slot.scala:59:28] wire [1:0] next_uop_dst_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs1_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs2_rtype; // @[issue-slot.scala:59:28] wire next_uop_frs3_en; // @[issue-slot.scala:59:28] wire next_uop_fcn_dw; // @[issue-slot.scala:59:28] wire [4:0] next_uop_fcn_op; // @[issue-slot.scala:59:28] wire next_uop_fp_val; // @[issue-slot.scala:59:28] wire [2:0] next_uop_fp_rm; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_typ; // @[issue-slot.scala:59:28] wire next_uop_xcpt_pf_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ae_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ma_if; // @[issue-slot.scala:59:28] wire next_uop_bp_debug_if; // @[issue-slot.scala:59:28] wire next_uop_bp_xcpt_if; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_fsrc; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_tsrc; // @[issue-slot.scala:59:28] wire io_iss_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_iss_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [15:0] io_iss_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_iss_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_iss_uop_taken_0; // @[issue-slot.scala:49:7] wire io_iss_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_iss_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_iss_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_iss_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_iss_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_iss_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_out_uop_taken_0; // @[issue-slot.scala:49:7] wire io_out_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_out_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_out_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_valid_0; // @[issue-slot.scala:49:7] wire io_will_be_valid_0; // @[issue-slot.scala:49:7] wire io_request_0; // @[issue-slot.scala:49:7] reg slot_valid; // @[issue-slot.scala:55:27] assign io_valid_0 = slot_valid; // @[issue-slot.scala:49:7, :55:27] reg [31:0] slot_uop_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_inst = slot_uop_inst; // @[util.scala:104:23] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_debug_inst = slot_uop_debug_inst; // @[util.scala:104:23] reg slot_uop_is_rvc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rvc = slot_uop_is_rvc; // @[util.scala:104:23] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:49:7, :56:21] wire [39:0] next_uop_out_debug_pc = slot_uop_debug_pc; // @[util.scala:104:23] reg slot_uop_iq_type_0; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_0_0 = slot_uop_iq_type_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_0 = slot_uop_iq_type_0; // @[util.scala:104:23] reg slot_uop_iq_type_1; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_1_0 = slot_uop_iq_type_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_1 = slot_uop_iq_type_1; // @[util.scala:104:23] reg slot_uop_iq_type_2; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_2_0 = slot_uop_iq_type_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_2 = slot_uop_iq_type_2; // @[util.scala:104:23] reg slot_uop_iq_type_3; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_3_0 = slot_uop_iq_type_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_3 = slot_uop_iq_type_3; // @[util.scala:104:23] reg slot_uop_fu_code_0; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_0_0 = slot_uop_fu_code_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_0 = slot_uop_fu_code_0; // @[util.scala:104:23] reg slot_uop_fu_code_1; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_1_0 = slot_uop_fu_code_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_1 = slot_uop_fu_code_1; // @[util.scala:104:23] reg slot_uop_fu_code_2; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_2_0 = slot_uop_fu_code_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_2 = slot_uop_fu_code_2; // @[util.scala:104:23] reg slot_uop_fu_code_3; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_3_0 = slot_uop_fu_code_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_3 = slot_uop_fu_code_3; // @[util.scala:104:23] reg slot_uop_fu_code_4; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_4_0 = slot_uop_fu_code_4; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_4 = slot_uop_fu_code_4; // @[util.scala:104:23] reg slot_uop_fu_code_5; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_5_0 = slot_uop_fu_code_5; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_5 = slot_uop_fu_code_5; // @[util.scala:104:23] reg slot_uop_fu_code_6; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_6_0 = slot_uop_fu_code_6; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_6 = slot_uop_fu_code_6; // @[util.scala:104:23] reg slot_uop_fu_code_7; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_7_0 = slot_uop_fu_code_7; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_7 = slot_uop_fu_code_7; // @[util.scala:104:23] reg slot_uop_fu_code_8; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_8_0 = slot_uop_fu_code_8; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_8 = slot_uop_fu_code_8; // @[util.scala:104:23] reg slot_uop_fu_code_9; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_9_0 = slot_uop_fu_code_9; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_9 = slot_uop_fu_code_9; // @[util.scala:104:23] reg slot_uop_iw_issued; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_issued_0 = slot_uop_iw_issued; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_issued = slot_uop_iw_issued; // @[util.scala:104:23] reg [2:0] slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_speculative_child_0 = slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_iw_p1_speculative_child = slot_uop_iw_p1_speculative_child; // @[util.scala:104:23] reg [2:0] slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_speculative_child_0 = slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_iw_p2_speculative_child = slot_uop_iw_p2_speculative_child; // @[util.scala:104:23] reg slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_bypass_hint_0 = slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p1_bypass_hint = slot_uop_iw_p1_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_bypass_hint_0 = slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p2_bypass_hint = slot_uop_iw_p2_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p3_bypass_hint_0 = slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p3_bypass_hint = slot_uop_iw_p3_bypass_hint; // @[util.scala:104:23] reg [2:0] slot_uop_dis_col_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_dis_col_sel_0 = slot_uop_dis_col_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_dis_col_sel = slot_uop_dis_col_sel; // @[util.scala:104:23] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:56:21] assign io_iss_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:49:7, :56:21] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:56:21] assign io_iss_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_tag = slot_uop_br_tag; // @[util.scala:104:23] reg [3:0] slot_uop_br_type; // @[issue-slot.scala:56:21] assign io_iss_uop_br_type_0 = slot_uop_br_type; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_type = slot_uop_br_type; // @[util.scala:104:23] reg slot_uop_is_sfb; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfb = slot_uop_is_sfb; // @[util.scala:104:23] reg slot_uop_is_fence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fence = slot_uop_is_fence; // @[util.scala:104:23] reg slot_uop_is_fencei; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fencei = slot_uop_is_fencei; // @[util.scala:104:23] reg slot_uop_is_sfence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfence_0 = slot_uop_is_sfence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfence = slot_uop_is_sfence; // @[util.scala:104:23] reg slot_uop_is_amo; // @[issue-slot.scala:56:21] assign io_iss_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_amo = slot_uop_is_amo; // @[util.scala:104:23] reg slot_uop_is_eret; // @[issue-slot.scala:56:21] assign io_iss_uop_is_eret_0 = slot_uop_is_eret; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_eret = slot_uop_is_eret; // @[util.scala:104:23] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sys_pc2epc = slot_uop_is_sys_pc2epc; // @[util.scala:104:23] reg slot_uop_is_rocc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rocc_0 = slot_uop_is_rocc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rocc = slot_uop_is_rocc; // @[util.scala:104:23] reg slot_uop_is_mov; // @[issue-slot.scala:56:21] assign io_iss_uop_is_mov_0 = slot_uop_is_mov; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_mov = slot_uop_is_mov; // @[util.scala:104:23] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ftq_idx = slot_uop_ftq_idx; // @[util.scala:104:23] reg slot_uop_edge_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_edge_inst = slot_uop_edge_inst; // @[util.scala:104:23] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:56:21] assign io_iss_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_pc_lob = slot_uop_pc_lob; // @[util.scala:104:23] reg slot_uop_taken; // @[issue-slot.scala:56:21] assign io_iss_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_taken = slot_uop_taken; // @[util.scala:104:23] reg slot_uop_imm_rename; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_rename_0 = slot_uop_imm_rename; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_imm_rename = slot_uop_imm_rename; // @[util.scala:104:23] reg [2:0] slot_uop_imm_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_sel_0 = slot_uop_imm_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_imm_sel = slot_uop_imm_sel; // @[util.scala:104:23] reg [4:0] slot_uop_pimm; // @[issue-slot.scala:56:21] assign io_iss_uop_pimm_0 = slot_uop_pimm; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_pimm = slot_uop_pimm; // @[util.scala:104:23] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:49:7, :56:21] wire [19:0] next_uop_out_imm_packed = slot_uop_imm_packed; // @[util.scala:104:23] reg [1:0] slot_uop_op1_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op1_sel_0 = slot_uop_op1_sel; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_op1_sel = slot_uop_op1_sel; // @[util.scala:104:23] reg [2:0] slot_uop_op2_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op2_sel_0 = slot_uop_op2_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_op2_sel = slot_uop_op2_sel; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ldst_0 = slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ldst = slot_uop_fp_ctrl_ldst; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wen; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wen_0 = slot_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wen = slot_uop_fp_ctrl_wen; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren1_0 = slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren1 = slot_uop_fp_ctrl_ren1; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren2_0 = slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren2 = slot_uop_fp_ctrl_ren2; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren3_0 = slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren3 = slot_uop_fp_ctrl_ren3; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap12_0 = slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap12 = slot_uop_fp_ctrl_swap12; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap23_0 = slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap23 = slot_uop_fp_ctrl_swap23; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagIn_0 = slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagIn = slot_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagOut_0 = slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagOut = slot_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fromint_0 = slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fromint = slot_uop_fp_ctrl_fromint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_toint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_toint_0 = slot_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_toint = slot_uop_fp_ctrl_toint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fastpipe_0 = slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fastpipe = slot_uop_fp_ctrl_fastpipe; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fma; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fma_0 = slot_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fma = slot_uop_fp_ctrl_fma; // @[util.scala:104:23] reg slot_uop_fp_ctrl_div; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_div_0 = slot_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_div = slot_uop_fp_ctrl_div; // @[util.scala:104:23] reg slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_sqrt_0 = slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_sqrt = slot_uop_fp_ctrl_sqrt; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wflags_0 = slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wflags = slot_uop_fp_ctrl_wflags; // @[util.scala:104:23] reg slot_uop_fp_ctrl_vec; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_vec_0 = slot_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_vec = slot_uop_fp_ctrl_vec; // @[util.scala:104:23] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_rob_idx = slot_uop_rob_idx; // @[util.scala:104:23] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ldq_idx = slot_uop_ldq_idx; // @[util.scala:104:23] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_stq_idx = slot_uop_stq_idx; // @[util.scala:104:23] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_rxq_idx = slot_uop_rxq_idx; // @[util.scala:104:23] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_pdst = slot_uop_pdst; // @[util.scala:104:23] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs1 = slot_uop_prs1; // @[util.scala:104:23] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs2 = slot_uop_prs2; // @[util.scala:104:23] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs3 = slot_uop_prs3; // @[util.scala:104:23] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ppred = slot_uop_ppred; // @[util.scala:104:23] reg slot_uop_prs1_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs1_busy = slot_uop_prs1_busy; // @[util.scala:104:23] reg slot_uop_prs2_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs2_busy = slot_uop_prs2_busy; // @[util.scala:104:23] reg slot_uop_prs3_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs3_busy = slot_uop_prs3_busy; // @[util.scala:104:23] reg slot_uop_ppred_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ppred_busy = slot_uop_ppred_busy; // @[util.scala:104:23] wire _iss_ready_T_3 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :136:88] wire _agen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :137:95] wire _dgen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :138:95] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_stale_pdst = slot_uop_stale_pdst; // @[util.scala:104:23] reg slot_uop_exception; // @[issue-slot.scala:56:21] assign io_iss_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_exception = slot_uop_exception; // @[util.scala:104:23] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:56:21] assign io_iss_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:49:7, :56:21] wire [63:0] next_uop_out_exc_cause = slot_uop_exc_cause; // @[util.scala:104:23] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_mem_cmd = slot_uop_mem_cmd; // @[util.scala:104:23] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_mem_size = slot_uop_mem_size; // @[util.scala:104:23] reg slot_uop_mem_signed; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_mem_signed = slot_uop_mem_signed; // @[util.scala:104:23] reg slot_uop_uses_ldq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_ldq = slot_uop_uses_ldq; // @[util.scala:104:23] reg slot_uop_uses_stq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_stq = slot_uop_uses_stq; // @[util.scala:104:23] reg slot_uop_is_unique; // @[issue-slot.scala:56:21] assign io_iss_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_unique = slot_uop_is_unique; // @[util.scala:104:23] reg slot_uop_flush_on_commit; // @[issue-slot.scala:56:21] assign io_iss_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_flush_on_commit = slot_uop_flush_on_commit; // @[util.scala:104:23] reg [2:0] slot_uop_csr_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_csr_cmd_0 = slot_uop_csr_cmd; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_csr_cmd = slot_uop_csr_cmd; // @[util.scala:104:23] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ldst_is_rs1 = slot_uop_ldst_is_rs1; // @[util.scala:104:23] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_ldst = slot_uop_ldst; // @[util.scala:104:23] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs1 = slot_uop_lrs1; // @[util.scala:104:23] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs2 = slot_uop_lrs2; // @[util.scala:104:23] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs3 = slot_uop_lrs3; // @[util.scala:104:23] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_dst_rtype = slot_uop_dst_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_rtype_0 = slot_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_lrs1_rtype = slot_uop_lrs1_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_rtype_0 = slot_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_lrs2_rtype = slot_uop_lrs2_rtype; // @[util.scala:104:23] reg slot_uop_frs3_en; // @[issue-slot.scala:56:21] assign io_iss_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_frs3_en = slot_uop_frs3_en; // @[util.scala:104:23] reg slot_uop_fcn_dw; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_dw_0 = slot_uop_fcn_dw; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fcn_dw = slot_uop_fcn_dw; // @[util.scala:104:23] reg [4:0] slot_uop_fcn_op; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_op_0 = slot_uop_fcn_op; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_fcn_op = slot_uop_fcn_op; // @[util.scala:104:23] reg slot_uop_fp_val; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_val = slot_uop_fp_val; // @[util.scala:104:23] reg [2:0] slot_uop_fp_rm; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_rm_0 = slot_uop_fp_rm; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_fp_rm = slot_uop_fp_rm; // @[util.scala:104:23] reg [1:0] slot_uop_fp_typ; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_typ_0 = slot_uop_fp_typ; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_typ = slot_uop_fp_typ; // @[util.scala:104:23] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_pf_if = slot_uop_xcpt_pf_if; // @[util.scala:104:23] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ae_if = slot_uop_xcpt_ae_if; // @[util.scala:104:23] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ma_if = slot_uop_xcpt_ma_if; // @[util.scala:104:23] reg slot_uop_bp_debug_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_debug_if = slot_uop_bp_debug_if; // @[util.scala:104:23] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_xcpt_if = slot_uop_bp_xcpt_if; // @[util.scala:104:23] reg [2:0] slot_uop_debug_fsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_fsrc = slot_uop_debug_fsrc; // @[util.scala:104:23] reg [2:0] slot_uop_debug_tsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_tsrc = slot_uop_debug_tsrc; // @[util.scala:104:23] wire next_valid; // @[issue-slot.scala:58:28] assign next_uop_inst = next_uop_out_inst; // @[util.scala:104:23] assign next_uop_debug_inst = next_uop_out_debug_inst; // @[util.scala:104:23] assign next_uop_is_rvc = next_uop_out_is_rvc; // @[util.scala:104:23] assign next_uop_debug_pc = next_uop_out_debug_pc; // @[util.scala:104:23] assign next_uop_iq_type_0 = next_uop_out_iq_type_0; // @[util.scala:104:23] assign next_uop_iq_type_1 = next_uop_out_iq_type_1; // @[util.scala:104:23] assign next_uop_iq_type_2 = next_uop_out_iq_type_2; // @[util.scala:104:23] assign next_uop_iq_type_3 = next_uop_out_iq_type_3; // @[util.scala:104:23] assign next_uop_fu_code_0 = next_uop_out_fu_code_0; // @[util.scala:104:23] assign next_uop_fu_code_1 = next_uop_out_fu_code_1; // @[util.scala:104:23] assign next_uop_fu_code_2 = next_uop_out_fu_code_2; // @[util.scala:104:23] assign next_uop_fu_code_3 = next_uop_out_fu_code_3; // @[util.scala:104:23] assign next_uop_fu_code_4 = next_uop_out_fu_code_4; // @[util.scala:104:23] assign next_uop_fu_code_5 = next_uop_out_fu_code_5; // @[util.scala:104:23] assign next_uop_fu_code_6 = next_uop_out_fu_code_6; // @[util.scala:104:23] assign next_uop_fu_code_7 = next_uop_out_fu_code_7; // @[util.scala:104:23] assign next_uop_fu_code_8 = next_uop_out_fu_code_8; // @[util.scala:104:23] assign next_uop_fu_code_9 = next_uop_out_fu_code_9; // @[util.scala:104:23] wire [15:0] _next_uop_out_br_mask_T_1; // @[util.scala:93:25] assign next_uop_dis_col_sel = next_uop_out_dis_col_sel; // @[util.scala:104:23] assign next_uop_br_mask = next_uop_out_br_mask; // @[util.scala:104:23] assign next_uop_br_tag = next_uop_out_br_tag; // @[util.scala:104:23] assign next_uop_br_type = next_uop_out_br_type; // @[util.scala:104:23] assign next_uop_is_sfb = next_uop_out_is_sfb; // @[util.scala:104:23] assign next_uop_is_fence = next_uop_out_is_fence; // @[util.scala:104:23] assign next_uop_is_fencei = next_uop_out_is_fencei; // @[util.scala:104:23] assign next_uop_is_sfence = next_uop_out_is_sfence; // @[util.scala:104:23] assign next_uop_is_amo = next_uop_out_is_amo; // @[util.scala:104:23] assign next_uop_is_eret = next_uop_out_is_eret; // @[util.scala:104:23] assign next_uop_is_sys_pc2epc = next_uop_out_is_sys_pc2epc; // @[util.scala:104:23] assign next_uop_is_rocc = next_uop_out_is_rocc; // @[util.scala:104:23] assign next_uop_is_mov = next_uop_out_is_mov; // @[util.scala:104:23] assign next_uop_ftq_idx = next_uop_out_ftq_idx; // @[util.scala:104:23] assign next_uop_edge_inst = next_uop_out_edge_inst; // @[util.scala:104:23] assign next_uop_pc_lob = next_uop_out_pc_lob; // @[util.scala:104:23] assign next_uop_taken = next_uop_out_taken; // @[util.scala:104:23] assign next_uop_imm_rename = next_uop_out_imm_rename; // @[util.scala:104:23] assign next_uop_imm_sel = next_uop_out_imm_sel; // @[util.scala:104:23] assign next_uop_pimm = next_uop_out_pimm; // @[util.scala:104:23] assign next_uop_imm_packed = next_uop_out_imm_packed; // @[util.scala:104:23] assign next_uop_op1_sel = next_uop_out_op1_sel; // @[util.scala:104:23] assign next_uop_op2_sel = next_uop_out_op2_sel; // @[util.scala:104:23] assign next_uop_fp_ctrl_ldst = next_uop_out_fp_ctrl_ldst; // @[util.scala:104:23] assign next_uop_fp_ctrl_wen = next_uop_out_fp_ctrl_wen; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren1 = next_uop_out_fp_ctrl_ren1; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren2 = next_uop_out_fp_ctrl_ren2; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren3 = next_uop_out_fp_ctrl_ren3; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap12 = next_uop_out_fp_ctrl_swap12; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap23 = next_uop_out_fp_ctrl_swap23; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagIn = next_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagOut = next_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23] assign next_uop_fp_ctrl_fromint = next_uop_out_fp_ctrl_fromint; // @[util.scala:104:23] assign next_uop_fp_ctrl_toint = next_uop_out_fp_ctrl_toint; // @[util.scala:104:23] assign next_uop_fp_ctrl_fastpipe = next_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23] assign next_uop_fp_ctrl_fma = next_uop_out_fp_ctrl_fma; // @[util.scala:104:23] assign next_uop_fp_ctrl_div = next_uop_out_fp_ctrl_div; // @[util.scala:104:23] assign next_uop_fp_ctrl_sqrt = next_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23] assign next_uop_fp_ctrl_wflags = next_uop_out_fp_ctrl_wflags; // @[util.scala:104:23] assign next_uop_fp_ctrl_vec = next_uop_out_fp_ctrl_vec; // @[util.scala:104:23] assign next_uop_rob_idx = next_uop_out_rob_idx; // @[util.scala:104:23] assign next_uop_ldq_idx = next_uop_out_ldq_idx; // @[util.scala:104:23] assign next_uop_stq_idx = next_uop_out_stq_idx; // @[util.scala:104:23] assign next_uop_rxq_idx = next_uop_out_rxq_idx; // @[util.scala:104:23] assign next_uop_pdst = next_uop_out_pdst; // @[util.scala:104:23] assign next_uop_prs1 = next_uop_out_prs1; // @[util.scala:104:23] assign next_uop_prs2 = next_uop_out_prs2; // @[util.scala:104:23] assign next_uop_prs3 = next_uop_out_prs3; // @[util.scala:104:23] assign next_uop_ppred = next_uop_out_ppred; // @[util.scala:104:23] assign next_uop_stale_pdst = next_uop_out_stale_pdst; // @[util.scala:104:23] assign next_uop_exception = next_uop_out_exception; // @[util.scala:104:23] assign next_uop_exc_cause = next_uop_out_exc_cause; // @[util.scala:104:23] assign next_uop_mem_cmd = next_uop_out_mem_cmd; // @[util.scala:104:23] assign next_uop_mem_size = next_uop_out_mem_size; // @[util.scala:104:23] assign next_uop_mem_signed = next_uop_out_mem_signed; // @[util.scala:104:23] assign next_uop_uses_ldq = next_uop_out_uses_ldq; // @[util.scala:104:23] assign next_uop_uses_stq = next_uop_out_uses_stq; // @[util.scala:104:23] assign next_uop_is_unique = next_uop_out_is_unique; // @[util.scala:104:23] assign next_uop_flush_on_commit = next_uop_out_flush_on_commit; // @[util.scala:104:23] assign next_uop_csr_cmd = next_uop_out_csr_cmd; // @[util.scala:104:23] assign next_uop_ldst_is_rs1 = next_uop_out_ldst_is_rs1; // @[util.scala:104:23] assign next_uop_ldst = next_uop_out_ldst; // @[util.scala:104:23] assign next_uop_lrs1 = next_uop_out_lrs1; // @[util.scala:104:23] assign next_uop_lrs2 = next_uop_out_lrs2; // @[util.scala:104:23] assign next_uop_lrs3 = next_uop_out_lrs3; // @[util.scala:104:23] assign next_uop_dst_rtype = next_uop_out_dst_rtype; // @[util.scala:104:23] assign next_uop_lrs1_rtype = next_uop_out_lrs1_rtype; // @[util.scala:104:23] assign next_uop_lrs2_rtype = next_uop_out_lrs2_rtype; // @[util.scala:104:23] assign next_uop_frs3_en = next_uop_out_frs3_en; // @[util.scala:104:23] assign next_uop_fcn_dw = next_uop_out_fcn_dw; // @[util.scala:104:23] assign next_uop_fcn_op = next_uop_out_fcn_op; // @[util.scala:104:23] assign next_uop_fp_val = next_uop_out_fp_val; // @[util.scala:104:23] assign next_uop_fp_rm = next_uop_out_fp_rm; // @[util.scala:104:23] assign next_uop_fp_typ = next_uop_out_fp_typ; // @[util.scala:104:23] assign next_uop_xcpt_pf_if = next_uop_out_xcpt_pf_if; // @[util.scala:104:23] assign next_uop_xcpt_ae_if = next_uop_out_xcpt_ae_if; // @[util.scala:104:23] assign next_uop_xcpt_ma_if = next_uop_out_xcpt_ma_if; // @[util.scala:104:23] assign next_uop_bp_debug_if = next_uop_out_bp_debug_if; // @[util.scala:104:23] assign next_uop_bp_xcpt_if = next_uop_out_bp_xcpt_if; // @[util.scala:104:23] assign next_uop_debug_fsrc = next_uop_out_debug_fsrc; // @[util.scala:104:23] assign next_uop_debug_tsrc = next_uop_out_debug_tsrc; // @[util.scala:104:23] wire [15:0] _next_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _next_uop_out_br_mask_T_1 = slot_uop_br_mask & _next_uop_out_br_mask_T; // @[util.scala:93:{25,27}] assign next_uop_out_br_mask = _next_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23] assign io_out_uop_inst_0 = next_uop_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_inst_0 = next_uop_debug_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rvc_0 = next_uop_is_rvc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_pc_0 = next_uop_debug_pc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_0_0 = next_uop_iq_type_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_1_0 = next_uop_iq_type_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_2_0 = next_uop_iq_type_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_3_0 = next_uop_iq_type_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_0_0 = next_uop_fu_code_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_1_0 = next_uop_fu_code_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_2_0 = next_uop_fu_code_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_3_0 = next_uop_fu_code_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_4_0 = next_uop_fu_code_4; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_5_0 = next_uop_fu_code_5; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_6_0 = next_uop_fu_code_6; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_7_0 = next_uop_fu_code_7; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_8_0 = next_uop_fu_code_8; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_9_0 = next_uop_fu_code_9; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_issued_0 = next_uop_iw_issued; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_speculative_child_0 = next_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_speculative_child_0 = next_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_bypass_hint_0 = next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_bypass_hint_0 = next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p3_bypass_hint_0 = next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dis_col_sel_0 = next_uop_dis_col_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_mask_0 = next_uop_br_mask; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_tag_0 = next_uop_br_tag; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_type_0 = next_uop_br_type; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfb_0 = next_uop_is_sfb; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fence_0 = next_uop_is_fence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fencei_0 = next_uop_is_fencei; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfence_0 = next_uop_is_sfence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_amo_0 = next_uop_is_amo; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_eret_0 = next_uop_is_eret; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sys_pc2epc_0 = next_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rocc_0 = next_uop_is_rocc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_mov_0 = next_uop_is_mov; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ftq_idx_0 = next_uop_ftq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_edge_inst_0 = next_uop_edge_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pc_lob_0 = next_uop_pc_lob; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_taken_0 = next_uop_taken; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_rename_0 = next_uop_imm_rename; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_sel_0 = next_uop_imm_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pimm_0 = next_uop_pimm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_packed_0 = next_uop_imm_packed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op1_sel_0 = next_uop_op1_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op2_sel_0 = next_uop_op2_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ldst_0 = next_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wen_0 = next_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren1_0 = next_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren2_0 = next_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren3_0 = next_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap12_0 = next_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap23_0 = next_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagIn_0 = next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagOut_0 = next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fromint_0 = next_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_toint_0 = next_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fastpipe_0 = next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fma_0 = next_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_div_0 = next_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_sqrt_0 = next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wflags_0 = next_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_vec_0 = next_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rob_idx_0 = next_uop_rob_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldq_idx_0 = next_uop_ldq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stq_idx_0 = next_uop_stq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rxq_idx_0 = next_uop_rxq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pdst_0 = next_uop_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_0 = next_uop_prs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_0 = next_uop_prs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_0 = next_uop_prs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_0 = next_uop_ppred; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_busy_0 = next_uop_prs1_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_busy_0 = next_uop_prs2_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_busy_0 = next_uop_prs3_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_busy_0 = next_uop_ppred_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stale_pdst_0 = next_uop_stale_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exception_0 = next_uop_exception; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exc_cause_0 = next_uop_exc_cause; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_cmd_0 = next_uop_mem_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_size_0 = next_uop_mem_size; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_signed_0 = next_uop_mem_signed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_ldq_0 = next_uop_uses_ldq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_stq_0 = next_uop_uses_stq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_unique_0 = next_uop_is_unique; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_flush_on_commit_0 = next_uop_flush_on_commit; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_csr_cmd_0 = next_uop_csr_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_is_rs1_0 = next_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_0 = next_uop_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_0 = next_uop_lrs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_0 = next_uop_lrs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs3_0 = next_uop_lrs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dst_rtype_0 = next_uop_dst_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_rtype_0 = next_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_rtype_0 = next_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_frs3_en_0 = next_uop_frs3_en; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_dw_0 = next_uop_fcn_dw; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_op_0 = next_uop_fcn_op; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_val_0 = next_uop_fp_val; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_rm_0 = next_uop_fp_rm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_typ_0 = next_uop_fp_typ; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_pf_if_0 = next_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ae_if_0 = next_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ma_if_0 = next_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_debug_if_0 = next_uop_bp_debug_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_xcpt_if_0 = next_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_fsrc_0 = next_uop_debug_fsrc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_tsrc_0 = next_uop_debug_tsrc; // @[issue-slot.scala:49:7, :59:28] wire [15:0] _killed_T = io_brupdate_b1_mispredict_mask_0 & slot_uop_br_mask; // @[util.scala:126:51] wire _killed_T_1 = |_killed_T; // @[util.scala:126:{51,59}] wire killed = _killed_T_1 | io_kill_0; // @[util.scala:61:61, :126:59] wire _io_will_be_valid_T = ~killed; // @[util.scala:61:61] assign _io_will_be_valid_T_1 = next_valid & _io_will_be_valid_T; // @[issue-slot.scala:58:28, :65:{34,37}] assign io_will_be_valid_0 = _io_will_be_valid_T_1; // @[issue-slot.scala:49:7, :65:34] wire _slot_valid_T = ~killed; // @[util.scala:61:61] wire _slot_valid_T_1 = next_valid & _slot_valid_T; // @[issue-slot.scala:58:28, :74:{30,33}]
Generate the Verilog code corresponding to the following Chisel files. File issue-unit-age-ordered.scala: //****************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Issue Logic //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v4.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util.Str import boom.v4.common._ class IssueUnitCollapsing( params: IssueParams, numWakeupPorts: Int) (implicit p: Parameters) extends IssueUnit(params, numWakeupPorts) { //------------------------------------------------------------- // Set up the dispatch uops // special case "storing" 2 uops within one issue slot. val dis_uops = Array.fill(dispatchWidth) {Wire(new MicroOp())} for (w <- 0 until dispatchWidth) { dis_uops(w) := io.dis_uops(w).bits dis_uops(w).iw_issued := false.B dis_uops(w).iw_issued_partial_agen := false.B dis_uops(w).iw_issued_partial_dgen := false.B dis_uops(w).iw_p1_bypass_hint := false.B dis_uops(w).iw_p2_bypass_hint := false.B dis_uops(w).iw_p3_bypass_hint := false.B // Handle wakeups on dispatch val prs1_matches = io.wakeup_ports.map { wu => wu.bits.uop.pdst === io.dis_uops(w).bits.prs1 } val prs2_matches = io.wakeup_ports.map { wu => wu.bits.uop.pdst === io.dis_uops(w).bits.prs2 } val prs3_matches = io.wakeup_ports.map { wu => wu.bits.uop.pdst === io.dis_uops(w).bits.prs3 } val prs1_wakeups = (io.wakeup_ports zip prs1_matches).map { case (wu,m) => wu.valid && m } val prs2_wakeups = (io.wakeup_ports zip prs2_matches).map { case (wu,m) => wu.valid && m } val prs3_wakeups = (io.wakeup_ports zip prs3_matches).map { case (wu,m) => wu.valid && m } val prs1_rebusys = (io.wakeup_ports zip prs1_matches).map { case (wu,m) => wu.bits.rebusy && m } val prs2_rebusys = (io.wakeup_ports zip prs2_matches).map { case (wu,m) => wu.bits.rebusy && m } val bypassables = io.wakeup_ports.map { wu => wu.bits.bypassable } val speculative_masks = io.wakeup_ports.map { wu => wu.bits.speculative_mask } when (prs1_wakeups.reduce(_||_)) { dis_uops(w).prs1_busy := false.B dis_uops(w).iw_p1_speculative_child := Mux1H(prs1_wakeups, speculative_masks) dis_uops(w).iw_p1_bypass_hint := Mux1H(prs1_wakeups, bypassables) } when (prs1_rebusys.reduce(_||_) || ((io.child_rebusys & io.dis_uops(w).bits.iw_p1_speculative_child) =/= 0.U)) { dis_uops(w).prs1_busy := io.dis_uops(w).bits.lrs1_rtype === RT_FIX } when (prs2_wakeups.reduce(_||_)) { dis_uops(w).prs2_busy := false.B dis_uops(w).iw_p2_speculative_child := Mux1H(prs2_wakeups, speculative_masks) dis_uops(w).iw_p2_bypass_hint := Mux1H(prs2_wakeups, bypassables) } when (prs2_rebusys.reduce(_||_) || ((io.child_rebusys & io.dis_uops(w).bits.iw_p2_speculative_child) =/= 0.U)) { dis_uops(w).prs2_busy := io.dis_uops(w).bits.lrs2_rtype === RT_FIX } when (prs3_wakeups.reduce(_||_)) { dis_uops(w).prs3_busy := false.B dis_uops(w).iw_p3_bypass_hint := Mux1H(prs3_wakeups, bypassables) } when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === io.dis_uops(w).bits.ppred) { dis_uops(w).ppred_busy := false.B } if (iqType == IQ_UNQ) { when (io.dis_uops(w).bits.fu_code(FC_I2F)) { dis_uops(w).prs2 := Cat(io.dis_uops(w).bits.fp_rm, io.dis_uops(w).bits.fp_typ) } when (io.dis_uops(w).bits.is_sfence) { dis_uops(w).pimm := io.dis_uops(w).bits.mem_size } } if (iqType == IQ_MEM) { // For store addr gen for FP, rs2 is the FP register, and we don't wait for that here when (io.dis_uops(w).bits.uses_stq && io.dis_uops(w).bits.lrs2_rtype === RT_FLT) { dis_uops(w).lrs2_rtype := RT_X dis_uops(w).prs2_busy := false.B } dis_uops(w).prs3_busy := false.B } else if (iqType == IQ_FP) { // FP "StoreAddrGen" is really storeDataGen, and rs1 is the integer address register when (io.dis_uops(w).bits.uses_stq) { dis_uops(w).lrs1_rtype := RT_X dis_uops(w).prs1_busy := false.B } } if (iqType != IQ_ALU) { assert(!(io.dis_uops(w).bits.ppred_busy && io.dis_uops(w).valid)) dis_uops(w).ppred_busy := false.B } } //------------------------------------------------------------- // Issue Table val slots = (0 until numIssueSlots) map { w => Module(new IssueSlot(numWakeupPorts, iqType == IQ_MEM, iqType == IQ_FP)) } val issue_slots = VecInit(slots.map(_.io)) for (i <- 0 until numIssueSlots) { issue_slots(i).wakeup_ports := io.wakeup_ports issue_slots(i).pred_wakeup_port := io.pred_wakeup_port issue_slots(i).child_rebusys := io.child_rebusys issue_slots(i).squash_grant := io.squash_grant issue_slots(i).brupdate := io.brupdate issue_slots(i).kill := io.flush_pipeline } for (w <- 0 until issueWidth) { io.iss_uops(w).valid := false.B } //------------------------------------------------------------- assert (PopCount(issue_slots.map(s => s.grant)) <= issueWidth.U, "[issue] window giving out too many grants.") //------------------------------------------------------------- // Figure out how much to shift entries by // Slow slots only shift 1 per cycle, these reduce critical path val nSlowSlots = params.numSlowEntries // Fast slots can shift up to dispatchWidth per cycle, so they can handle full dispatch throughput val nFastSlots = numIssueSlots - nSlowSlots require (nFastSlots >= dispatchWidth) require (nFastSlots <= numIssueSlots) val vacants = issue_slots.map(s => !(s.valid)) ++ io.dis_uops.map(_.valid).map(!_.asBool) val shamts_oh = Wire(Vec(numIssueSlots+dispatchWidth, UInt(width=dispatchWidth.W))) // track how many to shift up this entry by by counting previous vacant spots def SaturatingCounterOH(count_oh:UInt, inc: Bool, max: Int): UInt = { val next = Wire(UInt(width=max.W)) next := count_oh when (count_oh === 0.U && inc) { next := 1.U } .elsewhen (!count_oh(max-1) && inc) { next := (count_oh << 1.U) } next } shamts_oh(0) := 0.U for (i <- 1 until numIssueSlots + dispatchWidth) { val shift = if (i < nSlowSlots) (dispatchWidth min 1 + (i * (dispatchWidth-1)/nSlowSlots).toInt) else dispatchWidth if (dispatchWidth == 1 || shift == 1) { shamts_oh(i) := vacants.take(i).reduce(_||_) } else { shamts_oh(i) := SaturatingCounterOH(shamts_oh(i-1), vacants(i-1), shift) } } //------------------------------------------------------------- // which entries' uops will still be next cycle? (not being issued and vacated) val will_be_valid = (0 until numIssueSlots).map(i => issue_slots(i).will_be_valid) ++ (0 until dispatchWidth).map(i => io.dis_uops(i).valid && !dis_uops(i).exception && !dis_uops(i).is_fence && !dis_uops(i).is_fencei) val uops = issue_slots.map(s=>s.out_uop) ++ dis_uops.map(s=>s) for (i <- 0 until numIssueSlots) { issue_slots(i).in_uop.valid := false.B issue_slots(i).in_uop.bits := uops(i+1) for (j <- 1 to dispatchWidth by 1) { when (shamts_oh(i+j) === (1 << (j-1)).U) { issue_slots(i).in_uop.valid := will_be_valid(i+j) issue_slots(i).in_uop.bits := uops(i+j) } } issue_slots(i).clear := shamts_oh(i) =/= 0.U } //------------------------------------------------------------- // Dispatch/Entry Logic // did we find a spot to slide the new dispatched uops into? // Only look at the fast slots to determine readiness to dispatch. // Slow slot do not compact fast enough to make this calculation valid val is_available = Reg(Vec(nFastSlots, Bool())) is_available := VecInit((nSlowSlots until numIssueSlots).map(i => (!issue_slots(i).will_be_valid || issue_slots(i).clear) && !(issue_slots(i).in_uop.valid))) for (w <- 0 until dispatchWidth) { io.dis_uops(w).ready := RegNext(PopCount(is_available) > w.U(log2Ceil(nFastSlots).W) + PopCount(io.dis_uops.map(_.fire))) // io.dis_uops(w).ready := RegNext(PopCount(will_be_available) > w.U) assert (!io.dis_uops(w).ready || (shamts_oh(w+numIssueSlots) >> w) =/= 0.U) } //------------------------------------------------------------- // Issue Select Logic val requests = issue_slots.map(s => s.request) val port_issued = Array.fill(issueWidth){Bool()} for (w <- 0 until issueWidth) { port_issued(w) = false.B } val iss_select_mask = Array.ofDim[Boolean](issueWidth, numIssueSlots) if (params.useFullIssueSel) { for (w <- 0 until issueWidth) { for (i <- 0 until numIssueSlots) { iss_select_mask(w)(i) = true } } } else { for (w <- 0 until issueWidth) { for (i <- 0 until numIssueSlots) { iss_select_mask(w)(i) = (w % 2) == (i % 2) } iss_select_mask(w)(0) = true } } val iss_uops = Wire(Vec(issueWidth, Valid(new MicroOp))) for (w <- 0 until issueWidth) { iss_uops(w).valid := false.B iss_uops(w).bits := DontCare } for (i <- 0 until numIssueSlots) { issue_slots(i).grant := false.B var uop_issued = false.B for (w <- 0 until issueWidth) { val fu_code_match = (issue_slots(i).iss_uop.fu_code zip io.fu_types(w)).map { case (r,c) => r && c } .reduce(_||_) val can_allocate = fu_code_match && iss_select_mask(w)(i).B when (requests(i) && !uop_issued && can_allocate && !port_issued(w)) { issue_slots(i).grant := true.B iss_uops(w).valid := true.B iss_uops(w).bits := issue_slots(i).iss_uop } val was_port_issued_yet = port_issued(w) port_issued(w) = (requests(i) && !uop_issued && can_allocate) | port_issued(w) uop_issued = (requests(i) && can_allocate && !was_port_issued_yet) | uop_issued } } io.iss_uops := iss_uops when (io.squash_grant) { io.iss_uops.map { u => u.valid := false.B } } } File issue-unit.scala: //****************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Issue Logic //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v4.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util.{Str} import boom.v4.common._ import boom.v4.util.{BoolToChar} case class IssueParams( dispatchWidth: Int = 1, issueWidth: Int = 1, numEntries: Int = 8, useFullIssueSel: Boolean = true, numSlowEntries: Int = 0, iqType: Int ) abstract class IssueUnit( val params: IssueParams, val numWakeupPorts: Int )(implicit p: Parameters) extends BoomModule { val numIssueSlots = params.numEntries val issueWidth = params.issueWidth val iqType = params.iqType val dispatchWidth = params.dispatchWidth val io = IO(new Bundle { val dis_uops = Vec(dispatchWidth, Flipped(Decoupled(new MicroOp))) val iss_uops = Output(Vec(issueWidth, Valid(new MicroOp()))) val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new Wakeup))) val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W))) val child_rebusys = Input(UInt(aluWidth.W)) // tell the issue unit what each execution pipeline has in terms of functional units val fu_types = Input(Vec(issueWidth, Vec(FC_SZ, Bool()))) val brupdate = Input(new BrUpdateInfo()) val flush_pipeline = Input(Bool()) val squash_grant = Input(Bool()) val tsc_reg = Input(UInt(xLen.W)) }) //------------------------------------------------------------- def getType: String = if (iqType == IQ_ALU) "alu" else if (iqType == IQ_MEM) "mem" else if (iqType == IQ_FP) " fp" else if (iqType == IQ_UNQ) "unique" else "unknown" } object IssueUnit { def apply(params: IssueParams, numWakeupPorts: Int, useColumnIssueUnit: Boolean, useSingleWideDispatch: Boolean)(implicit p: Parameters): IssueUnit = { if (useColumnIssueUnit) Module(new IssueUnitBanked(params, numWakeupPorts, useSingleWideDispatch)) else Module(new IssueUnitCollapsing(params, numWakeupPorts)) } }
module IssueUnitCollapsing_1( // @[issue-unit-age-ordered.scala:22:7] input clock, // @[issue-unit-age-ordered.scala:22:7] input reset, // @[issue-unit-age-ordered.scala:22:7] output io_dis_uops_0_ready, // @[issue-unit.scala:44:14] input io_dis_uops_0_valid, // @[issue-unit.scala:44:14] input [31:0] io_dis_uops_0_bits_inst, // @[issue-unit.scala:44:14] input [31:0] io_dis_uops_0_bits_debug_inst, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_rvc, // @[issue-unit.scala:44:14] input [39:0] io_dis_uops_0_bits_debug_pc, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iq_type_0, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iq_type_1, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iq_type_2, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iq_type_3, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_0, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_1, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_2, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_3, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_4, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_5, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_6, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_7, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_8, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_9, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iw_issued, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iw_issued_partial_agen, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iw_issued_partial_dgen, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_0_bits_iw_p1_speculative_child, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_0_bits_iw_p2_speculative_child, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iw_p1_bypass_hint, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iw_p2_bypass_hint, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iw_p3_bypass_hint, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_0_bits_dis_col_sel, // @[issue-unit.scala:44:14] input [15:0] io_dis_uops_0_bits_br_mask, // @[issue-unit.scala:44:14] input [3:0] io_dis_uops_0_bits_br_tag, // @[issue-unit.scala:44:14] input [3:0] io_dis_uops_0_bits_br_type, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_sfb, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_fence, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_fencei, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_sfence, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_amo, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_eret, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_sys_pc2epc, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_rocc, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_mov, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_0_bits_ftq_idx, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_edge_inst, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_0_bits_pc_lob, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_taken, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_imm_rename, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_0_bits_imm_sel, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_0_bits_pimm, // @[issue-unit.scala:44:14] input [19:0] io_dis_uops_0_bits_imm_packed, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_op1_sel, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_0_bits_op2_sel, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_ldst, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_wen, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_ren1, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_ren2, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_ren3, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_swap12, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_swap23, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_fromint, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_toint, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_fma, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_div, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_sqrt, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_wflags, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_vec, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_0_bits_rob_idx, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_0_bits_ldq_idx, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_0_bits_stq_idx, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_rxq_idx, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_0_bits_pdst, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_0_bits_prs1, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_0_bits_prs2, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_0_bits_prs3, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_0_bits_ppred, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_prs1_busy, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_prs2_busy, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_prs3_busy, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_ppred_busy, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_0_bits_stale_pdst, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_exception, // @[issue-unit.scala:44:14] input [63:0] io_dis_uops_0_bits_exc_cause, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_0_bits_mem_cmd, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_mem_size, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_mem_signed, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_uses_ldq, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_uses_stq, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_unique, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_flush_on_commit, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_0_bits_csr_cmd, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_ldst_is_rs1, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_0_bits_ldst, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_0_bits_lrs1, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_0_bits_lrs2, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_0_bits_lrs3, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_dst_rtype, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_lrs1_rtype, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_lrs2_rtype, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_frs3_en, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fcn_dw, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_0_bits_fcn_op, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_val, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_0_bits_fp_rm, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_fp_typ, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_xcpt_pf_if, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_xcpt_ae_if, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_xcpt_ma_if, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_bp_debug_if, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_bp_xcpt_if, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_0_bits_debug_fsrc, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_0_bits_debug_tsrc, // @[issue-unit.scala:44:14] output io_dis_uops_1_ready, // @[issue-unit.scala:44:14] input io_dis_uops_1_valid, // @[issue-unit.scala:44:14] input [31:0] io_dis_uops_1_bits_inst, // @[issue-unit.scala:44:14] input [31:0] io_dis_uops_1_bits_debug_inst, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_rvc, // @[issue-unit.scala:44:14] input [39:0] io_dis_uops_1_bits_debug_pc, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iq_type_0, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iq_type_1, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iq_type_2, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iq_type_3, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_0, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_1, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_2, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_3, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_4, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_5, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_6, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_7, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_8, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_9, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iw_issued, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iw_issued_partial_agen, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iw_issued_partial_dgen, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_1_bits_iw_p1_speculative_child, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_1_bits_iw_p2_speculative_child, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iw_p1_bypass_hint, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iw_p2_bypass_hint, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iw_p3_bypass_hint, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_1_bits_dis_col_sel, // @[issue-unit.scala:44:14] input [15:0] io_dis_uops_1_bits_br_mask, // @[issue-unit.scala:44:14] input [3:0] io_dis_uops_1_bits_br_tag, // @[issue-unit.scala:44:14] input [3:0] io_dis_uops_1_bits_br_type, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_sfb, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_fence, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_fencei, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_sfence, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_amo, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_eret, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_sys_pc2epc, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_rocc, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_mov, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_1_bits_ftq_idx, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_edge_inst, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_1_bits_pc_lob, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_taken, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_imm_rename, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_1_bits_imm_sel, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_1_bits_pimm, // @[issue-unit.scala:44:14] input [19:0] io_dis_uops_1_bits_imm_packed, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_op1_sel, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_1_bits_op2_sel, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_ldst, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_wen, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_ren1, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_ren2, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_ren3, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_swap12, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_swap23, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_fromint, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_toint, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_fma, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_div, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_sqrt, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_wflags, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_vec, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_1_bits_rob_idx, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_1_bits_ldq_idx, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_1_bits_stq_idx, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_rxq_idx, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_1_bits_pdst, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_1_bits_prs1, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_1_bits_prs2, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_1_bits_prs3, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_1_bits_ppred, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_prs1_busy, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_prs2_busy, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_prs3_busy, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_ppred_busy, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_1_bits_stale_pdst, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_exception, // @[issue-unit.scala:44:14] input [63:0] io_dis_uops_1_bits_exc_cause, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_1_bits_mem_cmd, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_mem_size, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_mem_signed, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_uses_ldq, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_uses_stq, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_unique, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_flush_on_commit, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_1_bits_csr_cmd, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_ldst_is_rs1, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_1_bits_ldst, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_1_bits_lrs1, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_1_bits_lrs2, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_1_bits_lrs3, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_dst_rtype, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_lrs1_rtype, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_lrs2_rtype, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_frs3_en, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fcn_dw, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_1_bits_fcn_op, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_val, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_1_bits_fp_rm, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_fp_typ, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_xcpt_pf_if, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_xcpt_ae_if, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_xcpt_ma_if, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_bp_debug_if, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_bp_xcpt_if, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_1_bits_debug_fsrc, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_1_bits_debug_tsrc, // @[issue-unit.scala:44:14] output io_dis_uops_2_ready, // @[issue-unit.scala:44:14] input io_dis_uops_2_valid, // @[issue-unit.scala:44:14] input [31:0] io_dis_uops_2_bits_inst, // @[issue-unit.scala:44:14] input [31:0] io_dis_uops_2_bits_debug_inst, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_is_rvc, // @[issue-unit.scala:44:14] input [39:0] io_dis_uops_2_bits_debug_pc, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_iq_type_0, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_iq_type_1, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_iq_type_2, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_iq_type_3, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fu_code_0, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fu_code_1, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fu_code_2, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fu_code_3, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fu_code_4, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fu_code_5, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fu_code_6, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fu_code_7, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fu_code_8, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fu_code_9, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_iw_issued, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_iw_issued_partial_agen, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_iw_issued_partial_dgen, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_2_bits_iw_p1_speculative_child, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_2_bits_iw_p2_speculative_child, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_iw_p1_bypass_hint, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_iw_p2_bypass_hint, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_iw_p3_bypass_hint, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_2_bits_dis_col_sel, // @[issue-unit.scala:44:14] input [15:0] io_dis_uops_2_bits_br_mask, // @[issue-unit.scala:44:14] input [3:0] io_dis_uops_2_bits_br_tag, // @[issue-unit.scala:44:14] input [3:0] io_dis_uops_2_bits_br_type, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_is_sfb, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_is_fence, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_is_fencei, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_is_sfence, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_is_amo, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_is_eret, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_is_sys_pc2epc, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_is_rocc, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_is_mov, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_2_bits_ftq_idx, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_edge_inst, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_2_bits_pc_lob, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_taken, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_imm_rename, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_2_bits_imm_sel, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_2_bits_pimm, // @[issue-unit.scala:44:14] input [19:0] io_dis_uops_2_bits_imm_packed, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_2_bits_op1_sel, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_2_bits_op2_sel, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_ldst, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_wen, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_ren1, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_ren2, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_ren3, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_swap12, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_swap23, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_2_bits_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_2_bits_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_fromint, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_toint, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_fma, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_div, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_sqrt, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_wflags, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_vec, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_2_bits_rob_idx, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_2_bits_ldq_idx, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_2_bits_stq_idx, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_2_bits_rxq_idx, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_2_bits_pdst, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_2_bits_prs1, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_2_bits_prs2, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_2_bits_prs3, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_2_bits_ppred, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_prs1_busy, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_prs2_busy, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_prs3_busy, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_ppred_busy, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_2_bits_stale_pdst, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_exception, // @[issue-unit.scala:44:14] input [63:0] io_dis_uops_2_bits_exc_cause, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_2_bits_mem_cmd, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_2_bits_mem_size, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_mem_signed, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_uses_ldq, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_uses_stq, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_is_unique, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_flush_on_commit, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_2_bits_csr_cmd, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_ldst_is_rs1, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_2_bits_ldst, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_2_bits_lrs1, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_2_bits_lrs2, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_2_bits_lrs3, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_2_bits_dst_rtype, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_2_bits_lrs1_rtype, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_2_bits_lrs2_rtype, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_frs3_en, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fcn_dw, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_2_bits_fcn_op, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_val, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_2_bits_fp_rm, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_2_bits_fp_typ, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_xcpt_pf_if, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_xcpt_ae_if, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_xcpt_ma_if, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_bp_debug_if, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_bp_xcpt_if, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_2_bits_debug_fsrc, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_2_bits_debug_tsrc, // @[issue-unit.scala:44:14] output io_iss_uops_0_valid, // @[issue-unit.scala:44:14] output [31:0] io_iss_uops_0_bits_inst, // @[issue-unit.scala:44:14] output [31:0] io_iss_uops_0_bits_debug_inst, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_rvc, // @[issue-unit.scala:44:14] output [39:0] io_iss_uops_0_bits_debug_pc, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_iq_type_0, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_iq_type_1, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_iq_type_2, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_iq_type_3, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_0, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_1, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_2, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_3, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_4, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_5, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_6, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_7, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_8, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_9, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_iw_issued, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_iw_issued_partial_agen, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_iw_issued_partial_dgen, // @[issue-unit.scala:44:14] output [2:0] io_iss_uops_0_bits_iw_p1_speculative_child, // @[issue-unit.scala:44:14] output [2:0] io_iss_uops_0_bits_iw_p2_speculative_child, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_iw_p1_bypass_hint, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_iw_p2_bypass_hint, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_iw_p3_bypass_hint, // @[issue-unit.scala:44:14] output [2:0] io_iss_uops_0_bits_dis_col_sel, // @[issue-unit.scala:44:14] output [15:0] io_iss_uops_0_bits_br_mask, // @[issue-unit.scala:44:14] output [3:0] io_iss_uops_0_bits_br_tag, // @[issue-unit.scala:44:14] output [3:0] io_iss_uops_0_bits_br_type, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_sfb, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_fence, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_fencei, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_sfence, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_amo, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_eret, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_sys_pc2epc, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_rocc, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_mov, // @[issue-unit.scala:44:14] output [4:0] io_iss_uops_0_bits_ftq_idx, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_edge_inst, // @[issue-unit.scala:44:14] output [5:0] io_iss_uops_0_bits_pc_lob, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_taken, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_imm_rename, // @[issue-unit.scala:44:14] output [2:0] io_iss_uops_0_bits_imm_sel, // @[issue-unit.scala:44:14] output [4:0] io_iss_uops_0_bits_pimm, // @[issue-unit.scala:44:14] output [19:0] io_iss_uops_0_bits_imm_packed, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_op1_sel, // @[issue-unit.scala:44:14] output [2:0] io_iss_uops_0_bits_op2_sel, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_ldst, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_wen, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_ren1, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_ren2, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_ren3, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_swap12, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_swap23, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_fromint, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_toint, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_fma, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_div, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_sqrt, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_wflags, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_vec, // @[issue-unit.scala:44:14] output [6:0] io_iss_uops_0_bits_rob_idx, // @[issue-unit.scala:44:14] output [4:0] io_iss_uops_0_bits_ldq_idx, // @[issue-unit.scala:44:14] output [4:0] io_iss_uops_0_bits_stq_idx, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_rxq_idx, // @[issue-unit.scala:44:14] output [6:0] io_iss_uops_0_bits_pdst, // @[issue-unit.scala:44:14] output [6:0] io_iss_uops_0_bits_prs1, // @[issue-unit.scala:44:14] output [6:0] io_iss_uops_0_bits_prs2, // @[issue-unit.scala:44:14] output [6:0] io_iss_uops_0_bits_prs3, // @[issue-unit.scala:44:14] output [4:0] io_iss_uops_0_bits_ppred, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_prs1_busy, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_prs2_busy, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_prs3_busy, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_ppred_busy, // @[issue-unit.scala:44:14] output [6:0] io_iss_uops_0_bits_stale_pdst, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_exception, // @[issue-unit.scala:44:14] output [63:0] io_iss_uops_0_bits_exc_cause, // @[issue-unit.scala:44:14] output [4:0] io_iss_uops_0_bits_mem_cmd, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_mem_size, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_mem_signed, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_uses_ldq, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_uses_stq, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_unique, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_flush_on_commit, // @[issue-unit.scala:44:14] output [2:0] io_iss_uops_0_bits_csr_cmd, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_ldst_is_rs1, // @[issue-unit.scala:44:14] output [5:0] io_iss_uops_0_bits_ldst, // @[issue-unit.scala:44:14] output [5:0] io_iss_uops_0_bits_lrs1, // @[issue-unit.scala:44:14] output [5:0] io_iss_uops_0_bits_lrs2, // @[issue-unit.scala:44:14] output [5:0] io_iss_uops_0_bits_lrs3, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_dst_rtype, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_lrs1_rtype, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_frs3_en, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fcn_dw, // @[issue-unit.scala:44:14] output [4:0] io_iss_uops_0_bits_fcn_op, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_val, // @[issue-unit.scala:44:14] output [2:0] io_iss_uops_0_bits_fp_rm, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_fp_typ, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_xcpt_pf_if, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_xcpt_ae_if, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_xcpt_ma_if, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_bp_debug_if, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_bp_xcpt_if, // @[issue-unit.scala:44:14] output [2:0] io_iss_uops_0_bits_debug_fsrc, // @[issue-unit.scala:44:14] output [2:0] io_iss_uops_0_bits_debug_tsrc, // @[issue-unit.scala:44:14] output io_iss_uops_1_valid, // @[issue-unit.scala:44:14] output [31:0] io_iss_uops_1_bits_inst, // @[issue-unit.scala:44:14] output [31:0] io_iss_uops_1_bits_debug_inst, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_is_rvc, // @[issue-unit.scala:44:14] output [39:0] io_iss_uops_1_bits_debug_pc, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_iq_type_0, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_iq_type_1, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_iq_type_2, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_iq_type_3, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_fu_code_0, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_fu_code_1, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_fu_code_2, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_fu_code_3, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_fu_code_4, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_fu_code_5, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_fu_code_6, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_fu_code_7, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_fu_code_8, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_fu_code_9, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_iw_issued, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_iw_issued_partial_agen, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_iw_issued_partial_dgen, // @[issue-unit.scala:44:14] output [2:0] io_iss_uops_1_bits_iw_p1_speculative_child, // @[issue-unit.scala:44:14] output [2:0] io_iss_uops_1_bits_iw_p2_speculative_child, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_iw_p1_bypass_hint, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_iw_p2_bypass_hint, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_iw_p3_bypass_hint, // @[issue-unit.scala:44:14] output [2:0] io_iss_uops_1_bits_dis_col_sel, // @[issue-unit.scala:44:14] output [15:0] io_iss_uops_1_bits_br_mask, // @[issue-unit.scala:44:14] output [3:0] io_iss_uops_1_bits_br_tag, // @[issue-unit.scala:44:14] output [3:0] io_iss_uops_1_bits_br_type, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_is_sfb, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_is_fence, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_is_fencei, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_is_sfence, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_is_amo, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_is_eret, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_is_sys_pc2epc, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_is_rocc, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_is_mov, // @[issue-unit.scala:44:14] output [4:0] io_iss_uops_1_bits_ftq_idx, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_edge_inst, // @[issue-unit.scala:44:14] output [5:0] io_iss_uops_1_bits_pc_lob, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_taken, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_imm_rename, // @[issue-unit.scala:44:14] output [2:0] io_iss_uops_1_bits_imm_sel, // @[issue-unit.scala:44:14] output [4:0] io_iss_uops_1_bits_pimm, // @[issue-unit.scala:44:14] output [19:0] io_iss_uops_1_bits_imm_packed, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_1_bits_op1_sel, // @[issue-unit.scala:44:14] output [2:0] io_iss_uops_1_bits_op2_sel, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_fp_ctrl_ldst, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_fp_ctrl_wen, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_fp_ctrl_ren1, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_fp_ctrl_ren2, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_fp_ctrl_ren3, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_fp_ctrl_swap12, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_fp_ctrl_swap23, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_1_bits_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_1_bits_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_fp_ctrl_fromint, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_fp_ctrl_toint, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_fp_ctrl_fma, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_fp_ctrl_div, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_fp_ctrl_sqrt, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_fp_ctrl_wflags, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_fp_ctrl_vec, // @[issue-unit.scala:44:14] output [6:0] io_iss_uops_1_bits_rob_idx, // @[issue-unit.scala:44:14] output [4:0] io_iss_uops_1_bits_ldq_idx, // @[issue-unit.scala:44:14] output [4:0] io_iss_uops_1_bits_stq_idx, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_1_bits_rxq_idx, // @[issue-unit.scala:44:14] output [6:0] io_iss_uops_1_bits_pdst, // @[issue-unit.scala:44:14] output [6:0] io_iss_uops_1_bits_prs1, // @[issue-unit.scala:44:14] output [6:0] io_iss_uops_1_bits_prs2, // @[issue-unit.scala:44:14] output [6:0] io_iss_uops_1_bits_prs3, // @[issue-unit.scala:44:14] output [4:0] io_iss_uops_1_bits_ppred, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_prs1_busy, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_prs2_busy, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_prs3_busy, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_ppred_busy, // @[issue-unit.scala:44:14] output [6:0] io_iss_uops_1_bits_stale_pdst, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_exception, // @[issue-unit.scala:44:14] output [63:0] io_iss_uops_1_bits_exc_cause, // @[issue-unit.scala:44:14] output [4:0] io_iss_uops_1_bits_mem_cmd, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_1_bits_mem_size, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_mem_signed, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_uses_ldq, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_uses_stq, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_is_unique, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_flush_on_commit, // @[issue-unit.scala:44:14] output [2:0] io_iss_uops_1_bits_csr_cmd, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_ldst_is_rs1, // @[issue-unit.scala:44:14] output [5:0] io_iss_uops_1_bits_ldst, // @[issue-unit.scala:44:14] output [5:0] io_iss_uops_1_bits_lrs1, // @[issue-unit.scala:44:14] output [5:0] io_iss_uops_1_bits_lrs2, // @[issue-unit.scala:44:14] output [5:0] io_iss_uops_1_bits_lrs3, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_1_bits_dst_rtype, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_1_bits_lrs1_rtype, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_frs3_en, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_fcn_dw, // @[issue-unit.scala:44:14] output [4:0] io_iss_uops_1_bits_fcn_op, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_fp_val, // @[issue-unit.scala:44:14] output [2:0] io_iss_uops_1_bits_fp_rm, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_1_bits_fp_typ, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_xcpt_pf_if, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_xcpt_ae_if, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_xcpt_ma_if, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_bp_debug_if, // @[issue-unit.scala:44:14] output io_iss_uops_1_bits_bp_xcpt_if, // @[issue-unit.scala:44:14] output [2:0] io_iss_uops_1_bits_debug_fsrc, // @[issue-unit.scala:44:14] output [2:0] io_iss_uops_1_bits_debug_tsrc, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_valid, // @[issue-unit.scala:44:14] input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-unit.scala:44:14] input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-unit.scala:44:14] input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-unit.scala:44:14] input [15:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-unit.scala:44:14] input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-unit.scala:44:14] input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_taken, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-unit.scala:44:14] input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_exception, // @[issue-unit.scala:44:14] input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_bypassable, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_0_bits_speculative_mask, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_rebusy, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_valid, // @[issue-unit.scala:44:14] input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-unit.scala:44:14] input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-unit.scala:44:14] input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-unit.scala:44:14] input [15:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-unit.scala:44:14] input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-unit.scala:44:14] input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_taken, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-unit.scala:44:14] input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_exception, // @[issue-unit.scala:44:14] input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_valid, // @[issue-unit.scala:44:14] input [31:0] io_wakeup_ports_2_bits_uop_inst, // @[issue-unit.scala:44:14] input [31:0] io_wakeup_ports_2_bits_uop_debug_inst, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_is_rvc, // @[issue-unit.scala:44:14] input [39:0] io_wakeup_ports_2_bits_uop_debug_pc, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_iq_type_0, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_iq_type_1, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_iq_type_2, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_iq_type_3, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fu_code_0, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fu_code_1, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fu_code_2, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fu_code_3, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fu_code_4, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fu_code_5, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fu_code_6, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fu_code_7, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fu_code_8, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fu_code_9, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_iw_issued, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel, // @[issue-unit.scala:44:14] input [15:0] io_wakeup_ports_2_bits_uop_br_mask, // @[issue-unit.scala:44:14] input [3:0] io_wakeup_ports_2_bits_uop_br_tag, // @[issue-unit.scala:44:14] input [3:0] io_wakeup_ports_2_bits_uop_br_type, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_is_sfb, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_is_fence, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_is_fencei, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_is_sfence, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_is_amo, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_is_eret, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_is_sys_pc2epc, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_is_rocc, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_is_mov, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_2_bits_uop_ftq_idx, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_edge_inst, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_2_bits_uop_pc_lob, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_taken, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_imm_rename, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_2_bits_uop_imm_sel, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_2_bits_uop_pimm, // @[issue-unit.scala:44:14] input [19:0] io_wakeup_ports_2_bits_uop_imm_packed, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_2_bits_uop_op1_sel, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_2_bits_uop_op2_sel, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ldst, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wen, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren1, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren2, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren3, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap12, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap23, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fromint, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_toint, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fma, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_div, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wflags, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_vec, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_2_bits_uop_rob_idx, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_2_bits_uop_ldq_idx, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_2_bits_uop_stq_idx, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_2_bits_uop_rxq_idx, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_2_bits_uop_pdst, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_2_bits_uop_prs1, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_2_bits_uop_prs2, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_2_bits_uop_prs3, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_2_bits_uop_ppred, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_prs1_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_prs2_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_prs3_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_ppred_busy, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_2_bits_uop_stale_pdst, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_exception, // @[issue-unit.scala:44:14] input [63:0] io_wakeup_ports_2_bits_uop_exc_cause, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_2_bits_uop_mem_cmd, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_2_bits_uop_mem_size, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_mem_signed, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_uses_ldq, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_uses_stq, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_is_unique, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_flush_on_commit, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_2_bits_uop_csr_cmd, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_ldst_is_rs1, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_2_bits_uop_ldst, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs1, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs2, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs3, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_2_bits_uop_dst_rtype, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_frs3_en, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fcn_dw, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_2_bits_uop_fcn_op, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fp_val, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_2_bits_uop_fp_rm, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_typ, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_xcpt_pf_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_xcpt_ae_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_xcpt_ma_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_bp_debug_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_bp_xcpt_if, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_valid, // @[issue-unit.scala:44:14] input [31:0] io_wakeup_ports_3_bits_uop_inst, // @[issue-unit.scala:44:14] input [31:0] io_wakeup_ports_3_bits_uop_debug_inst, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_is_rvc, // @[issue-unit.scala:44:14] input [39:0] io_wakeup_ports_3_bits_uop_debug_pc, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_iq_type_0, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_iq_type_1, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_iq_type_2, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_iq_type_3, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fu_code_0, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fu_code_1, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fu_code_2, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fu_code_3, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fu_code_4, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fu_code_5, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fu_code_6, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fu_code_7, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fu_code_8, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fu_code_9, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_iw_issued, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel, // @[issue-unit.scala:44:14] input [15:0] io_wakeup_ports_3_bits_uop_br_mask, // @[issue-unit.scala:44:14] input [3:0] io_wakeup_ports_3_bits_uop_br_tag, // @[issue-unit.scala:44:14] input [3:0] io_wakeup_ports_3_bits_uop_br_type, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_is_sfb, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_is_fence, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_is_fencei, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_is_sfence, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_is_amo, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_is_eret, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_is_sys_pc2epc, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_is_rocc, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_is_mov, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_3_bits_uop_ftq_idx, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_edge_inst, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_3_bits_uop_pc_lob, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_taken, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_imm_rename, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_3_bits_uop_imm_sel, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_3_bits_uop_pimm, // @[issue-unit.scala:44:14] input [19:0] io_wakeup_ports_3_bits_uop_imm_packed, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_3_bits_uop_op1_sel, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_3_bits_uop_op2_sel, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ldst, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wen, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren1, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren2, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren3, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap12, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap23, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fromint, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_toint, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fma, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_div, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wflags, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_vec, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_3_bits_uop_rob_idx, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_3_bits_uop_ldq_idx, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_3_bits_uop_stq_idx, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_3_bits_uop_rxq_idx, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_3_bits_uop_pdst, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_3_bits_uop_prs1, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_3_bits_uop_prs2, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_3_bits_uop_prs3, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_3_bits_uop_ppred, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_prs1_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_prs2_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_prs3_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_ppred_busy, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_3_bits_uop_stale_pdst, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_exception, // @[issue-unit.scala:44:14] input [63:0] io_wakeup_ports_3_bits_uop_exc_cause, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_3_bits_uop_mem_cmd, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_3_bits_uop_mem_size, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_mem_signed, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_uses_ldq, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_uses_stq, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_is_unique, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_flush_on_commit, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_3_bits_uop_csr_cmd, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_ldst_is_rs1, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_3_bits_uop_ldst, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs1, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs2, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs3, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_3_bits_uop_dst_rtype, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_frs3_en, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fcn_dw, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_3_bits_uop_fcn_op, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fp_val, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_3_bits_uop_fp_rm, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_typ, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_xcpt_pf_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_xcpt_ae_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_xcpt_ma_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_bp_debug_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_bp_xcpt_if, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_valid, // @[issue-unit.scala:44:14] input [31:0] io_wakeup_ports_4_bits_uop_inst, // @[issue-unit.scala:44:14] input [31:0] io_wakeup_ports_4_bits_uop_debug_inst, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_is_rvc, // @[issue-unit.scala:44:14] input [39:0] io_wakeup_ports_4_bits_uop_debug_pc, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_iq_type_0, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_iq_type_1, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_iq_type_2, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_iq_type_3, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fu_code_0, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fu_code_1, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fu_code_2, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fu_code_3, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fu_code_4, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fu_code_5, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fu_code_6, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fu_code_7, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fu_code_8, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fu_code_9, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_iw_issued, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel, // @[issue-unit.scala:44:14] input [15:0] io_wakeup_ports_4_bits_uop_br_mask, // @[issue-unit.scala:44:14] input [3:0] io_wakeup_ports_4_bits_uop_br_tag, // @[issue-unit.scala:44:14] input [3:0] io_wakeup_ports_4_bits_uop_br_type, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_is_sfb, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_is_fence, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_is_fencei, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_is_sfence, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_is_amo, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_is_eret, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_is_sys_pc2epc, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_is_rocc, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_is_mov, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_4_bits_uop_ftq_idx, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_edge_inst, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_4_bits_uop_pc_lob, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_taken, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_imm_rename, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_4_bits_uop_imm_sel, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_4_bits_uop_pimm, // @[issue-unit.scala:44:14] input [19:0] io_wakeup_ports_4_bits_uop_imm_packed, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_4_bits_uop_op1_sel, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_4_bits_uop_op2_sel, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ldst, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_wen, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ren1, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ren2, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ren3, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_swap12, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_swap23, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_fromint, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_toint, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_fma, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_div, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_wflags, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_vec, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_4_bits_uop_rob_idx, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_4_bits_uop_ldq_idx, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_4_bits_uop_stq_idx, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_4_bits_uop_rxq_idx, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_4_bits_uop_pdst, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_4_bits_uop_prs1, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_4_bits_uop_prs2, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_4_bits_uop_prs3, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_4_bits_uop_ppred, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_prs1_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_prs2_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_prs3_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_ppred_busy, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_4_bits_uop_stale_pdst, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_exception, // @[issue-unit.scala:44:14] input [63:0] io_wakeup_ports_4_bits_uop_exc_cause, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_4_bits_uop_mem_cmd, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_4_bits_uop_mem_size, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_mem_signed, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_uses_ldq, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_uses_stq, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_is_unique, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_flush_on_commit, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_4_bits_uop_csr_cmd, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_ldst_is_rs1, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_4_bits_uop_ldst, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_4_bits_uop_lrs1, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_4_bits_uop_lrs2, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_4_bits_uop_lrs3, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_4_bits_uop_dst_rtype, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_frs3_en, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fcn_dw, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_4_bits_uop_fcn_op, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fp_val, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_4_bits_uop_fp_rm, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_4_bits_uop_fp_typ, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_xcpt_pf_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_xcpt_ae_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_xcpt_ma_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_bp_debug_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_bp_xcpt_if, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc, // @[issue-unit.scala:44:14] input [2:0] io_child_rebusys, // @[issue-unit.scala:44:14] input io_fu_types_1_1, // @[issue-unit.scala:44:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-unit.scala:44:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-unit.scala:44:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-unit.scala:44:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_rvc, // @[issue-unit.scala:44:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iq_type_0, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iq_type_1, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iq_type_2, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iq_type_3, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_0, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_1, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_2, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_3, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_4, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_5, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_6, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_7, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_8, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_9, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iw_issued, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-unit.scala:44:14] input [2:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-unit.scala:44:14] input [2:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-unit.scala:44:14] input [2:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-unit.scala:44:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-unit.scala:44:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-unit.scala:44:14] input [3:0] io_brupdate_b2_uop_br_type, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_sfb, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_fence, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_fencei, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_sfence, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_amo, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_eret, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_rocc, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_mov, // @[issue-unit.scala:44:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_edge_inst, // @[issue-unit.scala:44:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_taken, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_imm_rename, // @[issue-unit.scala:44:14] input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-unit.scala:44:14] input [4:0] io_brupdate_b2_uop_pimm, // @[issue-unit.scala:44:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-unit.scala:44:14] input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-unit.scala:44:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-unit.scala:44:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-unit.scala:44:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-unit.scala:44:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-unit.scala:44:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-unit.scala:44:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-unit.scala:44:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-unit.scala:44:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-unit.scala:44:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_exception, // @[issue-unit.scala:44:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-unit.scala:44:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_mem_signed, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_uses_stq, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_unique, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-unit.scala:44:14] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-unit.scala:44:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-unit.scala:44:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-unit.scala:44:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-unit.scala:44:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_frs3_en, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fcn_dw, // @[issue-unit.scala:44:14] input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_val, // @[issue-unit.scala:44:14] input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-unit.scala:44:14] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-unit.scala:44:14] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-unit.scala:44:14] input io_brupdate_b2_mispredict, // @[issue-unit.scala:44:14] input io_brupdate_b2_taken, // @[issue-unit.scala:44:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-unit.scala:44:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-unit.scala:44:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-unit.scala:44:14] input io_flush_pipeline, // @[issue-unit.scala:44:14] input io_squash_grant, // @[issue-unit.scala:44:14] input [63:0] io_tsc_reg // @[issue-unit.scala:44:14] ); wire issue_slots_15_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire io_dis_uops_0_valid_0 = io_dis_uops_0_valid; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_dis_uops_0_bits_inst_0 = io_dis_uops_0_bits_inst; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_dis_uops_0_bits_debug_inst_0 = io_dis_uops_0_bits_debug_inst; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_rvc_0 = io_dis_uops_0_bits_is_rvc; // @[issue-unit-age-ordered.scala:22:7] wire [39:0] io_dis_uops_0_bits_debug_pc_0 = io_dis_uops_0_bits_debug_pc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iq_type_0_0 = io_dis_uops_0_bits_iq_type_0; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iq_type_1_0 = io_dis_uops_0_bits_iq_type_1; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iq_type_2_0 = io_dis_uops_0_bits_iq_type_2; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iq_type_3_0 = io_dis_uops_0_bits_iq_type_3; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_0_0 = io_dis_uops_0_bits_fu_code_0; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_1_0 = io_dis_uops_0_bits_fu_code_1; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_2_0 = io_dis_uops_0_bits_fu_code_2; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_3_0 = io_dis_uops_0_bits_fu_code_3; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_4_0 = io_dis_uops_0_bits_fu_code_4; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_5_0 = io_dis_uops_0_bits_fu_code_5; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_6_0 = io_dis_uops_0_bits_fu_code_6; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_7_0 = io_dis_uops_0_bits_fu_code_7; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_8_0 = io_dis_uops_0_bits_fu_code_8; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_9_0 = io_dis_uops_0_bits_fu_code_9; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iw_issued_0 = io_dis_uops_0_bits_iw_issued; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iw_issued_partial_agen_0 = io_dis_uops_0_bits_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iw_issued_partial_dgen_0 = io_dis_uops_0_bits_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_0_bits_iw_p1_speculative_child_0 = io_dis_uops_0_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_0_bits_iw_p2_speculative_child_0 = io_dis_uops_0_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iw_p1_bypass_hint_0 = io_dis_uops_0_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iw_p2_bypass_hint_0 = io_dis_uops_0_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iw_p3_bypass_hint_0 = io_dis_uops_0_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_0_bits_dis_col_sel_0 = io_dis_uops_0_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7] wire [15:0] io_dis_uops_0_bits_br_mask_0 = io_dis_uops_0_bits_br_mask; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_dis_uops_0_bits_br_tag_0 = io_dis_uops_0_bits_br_tag; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_dis_uops_0_bits_br_type_0 = io_dis_uops_0_bits_br_type; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_sfb_0 = io_dis_uops_0_bits_is_sfb; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_fence_0 = io_dis_uops_0_bits_is_fence; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_fencei_0 = io_dis_uops_0_bits_is_fencei; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_sfence_0 = io_dis_uops_0_bits_is_sfence; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_amo_0 = io_dis_uops_0_bits_is_amo; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_eret_0 = io_dis_uops_0_bits_is_eret; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_sys_pc2epc_0 = io_dis_uops_0_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_rocc_0 = io_dis_uops_0_bits_is_rocc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_mov_0 = io_dis_uops_0_bits_is_mov; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_0_bits_ftq_idx_0 = io_dis_uops_0_bits_ftq_idx; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_edge_inst_0 = io_dis_uops_0_bits_edge_inst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_0_bits_pc_lob_0 = io_dis_uops_0_bits_pc_lob; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_taken_0 = io_dis_uops_0_bits_taken; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_imm_rename_0 = io_dis_uops_0_bits_imm_rename; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_0_bits_imm_sel_0 = io_dis_uops_0_bits_imm_sel; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_0_bits_pimm_0 = io_dis_uops_0_bits_pimm; // @[issue-unit-age-ordered.scala:22:7] wire [19:0] io_dis_uops_0_bits_imm_packed_0 = io_dis_uops_0_bits_imm_packed; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_op1_sel_0 = io_dis_uops_0_bits_op1_sel; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_0_bits_op2_sel_0 = io_dis_uops_0_bits_op2_sel; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_ldst_0 = io_dis_uops_0_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_wen_0 = io_dis_uops_0_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_ren1_0 = io_dis_uops_0_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_ren2_0 = io_dis_uops_0_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_ren3_0 = io_dis_uops_0_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_swap12_0 = io_dis_uops_0_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_swap23_0 = io_dis_uops_0_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_fp_ctrl_typeTagIn_0 = io_dis_uops_0_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_fp_ctrl_typeTagOut_0 = io_dis_uops_0_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_fromint_0 = io_dis_uops_0_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_toint_0 = io_dis_uops_0_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_fastpipe_0 = io_dis_uops_0_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_fma_0 = io_dis_uops_0_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_div_0 = io_dis_uops_0_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_sqrt_0 = io_dis_uops_0_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_wflags_0 = io_dis_uops_0_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_vec_0 = io_dis_uops_0_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_0_bits_rob_idx_0 = io_dis_uops_0_bits_rob_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_0_bits_ldq_idx_0 = io_dis_uops_0_bits_ldq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_0_bits_stq_idx_0 = io_dis_uops_0_bits_stq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_rxq_idx_0 = io_dis_uops_0_bits_rxq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_0_bits_pdst_0 = io_dis_uops_0_bits_pdst; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_0_bits_prs1_0 = io_dis_uops_0_bits_prs1; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_0_bits_prs2_0 = io_dis_uops_0_bits_prs2; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_0_bits_prs3_0 = io_dis_uops_0_bits_prs3; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_0_bits_ppred_0 = io_dis_uops_0_bits_ppred; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_prs1_busy_0 = io_dis_uops_0_bits_prs1_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_prs2_busy_0 = io_dis_uops_0_bits_prs2_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_prs3_busy_0 = io_dis_uops_0_bits_prs3_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_ppred_busy_0 = io_dis_uops_0_bits_ppred_busy; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_0_bits_stale_pdst_0 = io_dis_uops_0_bits_stale_pdst; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_exception_0 = io_dis_uops_0_bits_exception; // @[issue-unit-age-ordered.scala:22:7] wire [63:0] io_dis_uops_0_bits_exc_cause_0 = io_dis_uops_0_bits_exc_cause; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_0_bits_mem_cmd_0 = io_dis_uops_0_bits_mem_cmd; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_mem_size_0 = io_dis_uops_0_bits_mem_size; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_mem_signed_0 = io_dis_uops_0_bits_mem_signed; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_uses_ldq_0 = io_dis_uops_0_bits_uses_ldq; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_uses_stq_0 = io_dis_uops_0_bits_uses_stq; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_unique_0 = io_dis_uops_0_bits_is_unique; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_flush_on_commit_0 = io_dis_uops_0_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_0_bits_csr_cmd_0 = io_dis_uops_0_bits_csr_cmd; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_ldst_is_rs1_0 = io_dis_uops_0_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_0_bits_ldst_0 = io_dis_uops_0_bits_ldst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_0_bits_lrs1_0 = io_dis_uops_0_bits_lrs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_0_bits_lrs2_0 = io_dis_uops_0_bits_lrs2; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_0_bits_lrs3_0 = io_dis_uops_0_bits_lrs3; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_dst_rtype_0 = io_dis_uops_0_bits_dst_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_lrs1_rtype_0 = io_dis_uops_0_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_lrs2_rtype_0 = io_dis_uops_0_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_frs3_en_0 = io_dis_uops_0_bits_frs3_en; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fcn_dw_0 = io_dis_uops_0_bits_fcn_dw; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_0_bits_fcn_op_0 = io_dis_uops_0_bits_fcn_op; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_val_0 = io_dis_uops_0_bits_fp_val; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_0_bits_fp_rm_0 = io_dis_uops_0_bits_fp_rm; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_fp_typ_0 = io_dis_uops_0_bits_fp_typ; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_xcpt_pf_if_0 = io_dis_uops_0_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_xcpt_ae_if_0 = io_dis_uops_0_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_xcpt_ma_if_0 = io_dis_uops_0_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_bp_debug_if_0 = io_dis_uops_0_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_bp_xcpt_if_0 = io_dis_uops_0_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_0_bits_debug_fsrc_0 = io_dis_uops_0_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_0_bits_debug_tsrc_0 = io_dis_uops_0_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_valid_0 = io_dis_uops_1_valid; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_dis_uops_1_bits_inst_0 = io_dis_uops_1_bits_inst; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_dis_uops_1_bits_debug_inst_0 = io_dis_uops_1_bits_debug_inst; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_rvc_0 = io_dis_uops_1_bits_is_rvc; // @[issue-unit-age-ordered.scala:22:7] wire [39:0] io_dis_uops_1_bits_debug_pc_0 = io_dis_uops_1_bits_debug_pc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iq_type_0_0 = io_dis_uops_1_bits_iq_type_0; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iq_type_1_0 = io_dis_uops_1_bits_iq_type_1; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iq_type_2_0 = io_dis_uops_1_bits_iq_type_2; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iq_type_3_0 = io_dis_uops_1_bits_iq_type_3; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_0_0 = io_dis_uops_1_bits_fu_code_0; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_1_0 = io_dis_uops_1_bits_fu_code_1; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_2_0 = io_dis_uops_1_bits_fu_code_2; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_3_0 = io_dis_uops_1_bits_fu_code_3; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_4_0 = io_dis_uops_1_bits_fu_code_4; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_5_0 = io_dis_uops_1_bits_fu_code_5; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_6_0 = io_dis_uops_1_bits_fu_code_6; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_7_0 = io_dis_uops_1_bits_fu_code_7; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_8_0 = io_dis_uops_1_bits_fu_code_8; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_9_0 = io_dis_uops_1_bits_fu_code_9; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iw_issued_0 = io_dis_uops_1_bits_iw_issued; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iw_issued_partial_agen_0 = io_dis_uops_1_bits_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iw_issued_partial_dgen_0 = io_dis_uops_1_bits_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_1_bits_iw_p1_speculative_child_0 = io_dis_uops_1_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_1_bits_iw_p2_speculative_child_0 = io_dis_uops_1_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iw_p1_bypass_hint_0 = io_dis_uops_1_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iw_p2_bypass_hint_0 = io_dis_uops_1_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iw_p3_bypass_hint_0 = io_dis_uops_1_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_1_bits_dis_col_sel_0 = io_dis_uops_1_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7] wire [15:0] io_dis_uops_1_bits_br_mask_0 = io_dis_uops_1_bits_br_mask; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_dis_uops_1_bits_br_tag_0 = io_dis_uops_1_bits_br_tag; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_dis_uops_1_bits_br_type_0 = io_dis_uops_1_bits_br_type; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_sfb_0 = io_dis_uops_1_bits_is_sfb; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_fence_0 = io_dis_uops_1_bits_is_fence; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_fencei_0 = io_dis_uops_1_bits_is_fencei; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_sfence_0 = io_dis_uops_1_bits_is_sfence; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_amo_0 = io_dis_uops_1_bits_is_amo; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_eret_0 = io_dis_uops_1_bits_is_eret; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_sys_pc2epc_0 = io_dis_uops_1_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_rocc_0 = io_dis_uops_1_bits_is_rocc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_mov_0 = io_dis_uops_1_bits_is_mov; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_1_bits_ftq_idx_0 = io_dis_uops_1_bits_ftq_idx; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_edge_inst_0 = io_dis_uops_1_bits_edge_inst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_1_bits_pc_lob_0 = io_dis_uops_1_bits_pc_lob; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_taken_0 = io_dis_uops_1_bits_taken; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_imm_rename_0 = io_dis_uops_1_bits_imm_rename; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_1_bits_imm_sel_0 = io_dis_uops_1_bits_imm_sel; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_1_bits_pimm_0 = io_dis_uops_1_bits_pimm; // @[issue-unit-age-ordered.scala:22:7] wire [19:0] io_dis_uops_1_bits_imm_packed_0 = io_dis_uops_1_bits_imm_packed; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_op1_sel_0 = io_dis_uops_1_bits_op1_sel; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_1_bits_op2_sel_0 = io_dis_uops_1_bits_op2_sel; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_ldst_0 = io_dis_uops_1_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_wen_0 = io_dis_uops_1_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_ren1_0 = io_dis_uops_1_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_ren2_0 = io_dis_uops_1_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_ren3_0 = io_dis_uops_1_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_swap12_0 = io_dis_uops_1_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_swap23_0 = io_dis_uops_1_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_fp_ctrl_typeTagIn_0 = io_dis_uops_1_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_fp_ctrl_typeTagOut_0 = io_dis_uops_1_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_fromint_0 = io_dis_uops_1_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_toint_0 = io_dis_uops_1_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_fastpipe_0 = io_dis_uops_1_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_fma_0 = io_dis_uops_1_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_div_0 = io_dis_uops_1_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_sqrt_0 = io_dis_uops_1_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_wflags_0 = io_dis_uops_1_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_vec_0 = io_dis_uops_1_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_1_bits_rob_idx_0 = io_dis_uops_1_bits_rob_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_1_bits_ldq_idx_0 = io_dis_uops_1_bits_ldq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_1_bits_stq_idx_0 = io_dis_uops_1_bits_stq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_rxq_idx_0 = io_dis_uops_1_bits_rxq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_1_bits_pdst_0 = io_dis_uops_1_bits_pdst; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_1_bits_prs1_0 = io_dis_uops_1_bits_prs1; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_1_bits_prs2_0 = io_dis_uops_1_bits_prs2; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_1_bits_prs3_0 = io_dis_uops_1_bits_prs3; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_1_bits_ppred_0 = io_dis_uops_1_bits_ppred; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_prs1_busy_0 = io_dis_uops_1_bits_prs1_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_prs2_busy_0 = io_dis_uops_1_bits_prs2_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_prs3_busy_0 = io_dis_uops_1_bits_prs3_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_ppred_busy_0 = io_dis_uops_1_bits_ppred_busy; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_1_bits_stale_pdst_0 = io_dis_uops_1_bits_stale_pdst; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_exception_0 = io_dis_uops_1_bits_exception; // @[issue-unit-age-ordered.scala:22:7] wire [63:0] io_dis_uops_1_bits_exc_cause_0 = io_dis_uops_1_bits_exc_cause; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_1_bits_mem_cmd_0 = io_dis_uops_1_bits_mem_cmd; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_mem_size_0 = io_dis_uops_1_bits_mem_size; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_mem_signed_0 = io_dis_uops_1_bits_mem_signed; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_uses_ldq_0 = io_dis_uops_1_bits_uses_ldq; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_uses_stq_0 = io_dis_uops_1_bits_uses_stq; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_unique_0 = io_dis_uops_1_bits_is_unique; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_flush_on_commit_0 = io_dis_uops_1_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_1_bits_csr_cmd_0 = io_dis_uops_1_bits_csr_cmd; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_ldst_is_rs1_0 = io_dis_uops_1_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_1_bits_ldst_0 = io_dis_uops_1_bits_ldst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_1_bits_lrs1_0 = io_dis_uops_1_bits_lrs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_1_bits_lrs2_0 = io_dis_uops_1_bits_lrs2; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_1_bits_lrs3_0 = io_dis_uops_1_bits_lrs3; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_dst_rtype_0 = io_dis_uops_1_bits_dst_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_lrs1_rtype_0 = io_dis_uops_1_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_lrs2_rtype_0 = io_dis_uops_1_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_frs3_en_0 = io_dis_uops_1_bits_frs3_en; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fcn_dw_0 = io_dis_uops_1_bits_fcn_dw; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_1_bits_fcn_op_0 = io_dis_uops_1_bits_fcn_op; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_val_0 = io_dis_uops_1_bits_fp_val; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_1_bits_fp_rm_0 = io_dis_uops_1_bits_fp_rm; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_fp_typ_0 = io_dis_uops_1_bits_fp_typ; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_xcpt_pf_if_0 = io_dis_uops_1_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_xcpt_ae_if_0 = io_dis_uops_1_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_xcpt_ma_if_0 = io_dis_uops_1_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_bp_debug_if_0 = io_dis_uops_1_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_bp_xcpt_if_0 = io_dis_uops_1_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_1_bits_debug_fsrc_0 = io_dis_uops_1_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_1_bits_debug_tsrc_0 = io_dis_uops_1_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_valid_0 = io_dis_uops_2_valid; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_dis_uops_2_bits_inst_0 = io_dis_uops_2_bits_inst; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_dis_uops_2_bits_debug_inst_0 = io_dis_uops_2_bits_debug_inst; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_is_rvc_0 = io_dis_uops_2_bits_is_rvc; // @[issue-unit-age-ordered.scala:22:7] wire [39:0] io_dis_uops_2_bits_debug_pc_0 = io_dis_uops_2_bits_debug_pc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_iq_type_0_0 = io_dis_uops_2_bits_iq_type_0; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_iq_type_1_0 = io_dis_uops_2_bits_iq_type_1; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_iq_type_2_0 = io_dis_uops_2_bits_iq_type_2; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_iq_type_3_0 = io_dis_uops_2_bits_iq_type_3; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fu_code_0_0 = io_dis_uops_2_bits_fu_code_0; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fu_code_1_0 = io_dis_uops_2_bits_fu_code_1; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fu_code_2_0 = io_dis_uops_2_bits_fu_code_2; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fu_code_3_0 = io_dis_uops_2_bits_fu_code_3; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fu_code_4_0 = io_dis_uops_2_bits_fu_code_4; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fu_code_5_0 = io_dis_uops_2_bits_fu_code_5; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fu_code_6_0 = io_dis_uops_2_bits_fu_code_6; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fu_code_7_0 = io_dis_uops_2_bits_fu_code_7; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fu_code_8_0 = io_dis_uops_2_bits_fu_code_8; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fu_code_9_0 = io_dis_uops_2_bits_fu_code_9; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_iw_issued_0 = io_dis_uops_2_bits_iw_issued; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_iw_issued_partial_agen_0 = io_dis_uops_2_bits_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_iw_issued_partial_dgen_0 = io_dis_uops_2_bits_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_2_bits_iw_p1_speculative_child_0 = io_dis_uops_2_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_2_bits_iw_p2_speculative_child_0 = io_dis_uops_2_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_iw_p1_bypass_hint_0 = io_dis_uops_2_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_iw_p2_bypass_hint_0 = io_dis_uops_2_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_iw_p3_bypass_hint_0 = io_dis_uops_2_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_2_bits_dis_col_sel_0 = io_dis_uops_2_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7] wire [15:0] io_dis_uops_2_bits_br_mask_0 = io_dis_uops_2_bits_br_mask; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_dis_uops_2_bits_br_tag_0 = io_dis_uops_2_bits_br_tag; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_dis_uops_2_bits_br_type_0 = io_dis_uops_2_bits_br_type; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_is_sfb_0 = io_dis_uops_2_bits_is_sfb; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_is_fence_0 = io_dis_uops_2_bits_is_fence; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_is_fencei_0 = io_dis_uops_2_bits_is_fencei; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_is_sfence_0 = io_dis_uops_2_bits_is_sfence; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_is_amo_0 = io_dis_uops_2_bits_is_amo; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_is_eret_0 = io_dis_uops_2_bits_is_eret; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_is_sys_pc2epc_0 = io_dis_uops_2_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_is_rocc_0 = io_dis_uops_2_bits_is_rocc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_is_mov_0 = io_dis_uops_2_bits_is_mov; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_2_bits_ftq_idx_0 = io_dis_uops_2_bits_ftq_idx; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_edge_inst_0 = io_dis_uops_2_bits_edge_inst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_2_bits_pc_lob_0 = io_dis_uops_2_bits_pc_lob; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_taken_0 = io_dis_uops_2_bits_taken; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_imm_rename_0 = io_dis_uops_2_bits_imm_rename; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_2_bits_imm_sel_0 = io_dis_uops_2_bits_imm_sel; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_2_bits_pimm_0 = io_dis_uops_2_bits_pimm; // @[issue-unit-age-ordered.scala:22:7] wire [19:0] io_dis_uops_2_bits_imm_packed_0 = io_dis_uops_2_bits_imm_packed; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_2_bits_op1_sel_0 = io_dis_uops_2_bits_op1_sel; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_2_bits_op2_sel_0 = io_dis_uops_2_bits_op2_sel; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_ldst_0 = io_dis_uops_2_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_wen_0 = io_dis_uops_2_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_ren1_0 = io_dis_uops_2_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_ren2_0 = io_dis_uops_2_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_ren3_0 = io_dis_uops_2_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_swap12_0 = io_dis_uops_2_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_swap23_0 = io_dis_uops_2_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_2_bits_fp_ctrl_typeTagIn_0 = io_dis_uops_2_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_2_bits_fp_ctrl_typeTagOut_0 = io_dis_uops_2_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_fromint_0 = io_dis_uops_2_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_toint_0 = io_dis_uops_2_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_fastpipe_0 = io_dis_uops_2_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_fma_0 = io_dis_uops_2_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_div_0 = io_dis_uops_2_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_sqrt_0 = io_dis_uops_2_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_wflags_0 = io_dis_uops_2_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_vec_0 = io_dis_uops_2_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_2_bits_rob_idx_0 = io_dis_uops_2_bits_rob_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_2_bits_ldq_idx_0 = io_dis_uops_2_bits_ldq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_2_bits_stq_idx_0 = io_dis_uops_2_bits_stq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_2_bits_rxq_idx_0 = io_dis_uops_2_bits_rxq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_2_bits_pdst_0 = io_dis_uops_2_bits_pdst; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_2_bits_prs1_0 = io_dis_uops_2_bits_prs1; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_2_bits_prs2_0 = io_dis_uops_2_bits_prs2; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_2_bits_prs3_0 = io_dis_uops_2_bits_prs3; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_2_bits_ppred_0 = io_dis_uops_2_bits_ppred; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_prs1_busy_0 = io_dis_uops_2_bits_prs1_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_prs2_busy_0 = io_dis_uops_2_bits_prs2_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_prs3_busy_0 = io_dis_uops_2_bits_prs3_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_ppred_busy_0 = io_dis_uops_2_bits_ppred_busy; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_2_bits_stale_pdst_0 = io_dis_uops_2_bits_stale_pdst; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_exception_0 = io_dis_uops_2_bits_exception; // @[issue-unit-age-ordered.scala:22:7] wire [63:0] io_dis_uops_2_bits_exc_cause_0 = io_dis_uops_2_bits_exc_cause; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_2_bits_mem_cmd_0 = io_dis_uops_2_bits_mem_cmd; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_2_bits_mem_size_0 = io_dis_uops_2_bits_mem_size; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_mem_signed_0 = io_dis_uops_2_bits_mem_signed; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_uses_ldq_0 = io_dis_uops_2_bits_uses_ldq; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_uses_stq_0 = io_dis_uops_2_bits_uses_stq; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_is_unique_0 = io_dis_uops_2_bits_is_unique; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_flush_on_commit_0 = io_dis_uops_2_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_2_bits_csr_cmd_0 = io_dis_uops_2_bits_csr_cmd; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_ldst_is_rs1_0 = io_dis_uops_2_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_2_bits_ldst_0 = io_dis_uops_2_bits_ldst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_2_bits_lrs1_0 = io_dis_uops_2_bits_lrs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_2_bits_lrs2_0 = io_dis_uops_2_bits_lrs2; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_2_bits_lrs3_0 = io_dis_uops_2_bits_lrs3; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_2_bits_dst_rtype_0 = io_dis_uops_2_bits_dst_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_2_bits_lrs1_rtype_0 = io_dis_uops_2_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_2_bits_lrs2_rtype_0 = io_dis_uops_2_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_frs3_en_0 = io_dis_uops_2_bits_frs3_en; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fcn_dw_0 = io_dis_uops_2_bits_fcn_dw; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_2_bits_fcn_op_0 = io_dis_uops_2_bits_fcn_op; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_val_0 = io_dis_uops_2_bits_fp_val; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_2_bits_fp_rm_0 = io_dis_uops_2_bits_fp_rm; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_2_bits_fp_typ_0 = io_dis_uops_2_bits_fp_typ; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_xcpt_pf_if_0 = io_dis_uops_2_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_xcpt_ae_if_0 = io_dis_uops_2_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_xcpt_ma_if_0 = io_dis_uops_2_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_bp_debug_if_0 = io_dis_uops_2_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_bp_xcpt_if_0 = io_dis_uops_2_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_2_bits_debug_fsrc_0 = io_dis_uops_2_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_2_bits_debug_tsrc_0 = io_dis_uops_2_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-unit-age-ordered.scala:22:7] wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7] wire [15:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-unit-age-ordered.scala:22:7] wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-unit-age-ordered.scala:22:7] wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_bypassable_0 = io_wakeup_ports_0_bits_bypassable; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_0_bits_speculative_mask_0 = io_wakeup_ports_0_bits_speculative_mask; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_rebusy_0 = io_wakeup_ports_0_bits_rebusy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-unit-age-ordered.scala:22:7] wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7] wire [15:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-unit-age-ordered.scala:22:7] wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-unit-age-ordered.scala:22:7] wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_wakeup_ports_2_bits_uop_inst_0 = io_wakeup_ports_2_bits_uop_inst; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_wakeup_ports_2_bits_uop_debug_inst_0 = io_wakeup_ports_2_bits_uop_debug_inst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_is_rvc_0 = io_wakeup_ports_2_bits_uop_is_rvc; // @[issue-unit-age-ordered.scala:22:7] wire [39:0] io_wakeup_ports_2_bits_uop_debug_pc_0 = io_wakeup_ports_2_bits_uop_debug_pc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_iq_type_0_0 = io_wakeup_ports_2_bits_uop_iq_type_0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_iq_type_1_0 = io_wakeup_ports_2_bits_uop_iq_type_1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_iq_type_2_0 = io_wakeup_ports_2_bits_uop_iq_type_2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_iq_type_3_0 = io_wakeup_ports_2_bits_uop_iq_type_3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fu_code_0_0 = io_wakeup_ports_2_bits_uop_fu_code_0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fu_code_1_0 = io_wakeup_ports_2_bits_uop_fu_code_1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fu_code_2_0 = io_wakeup_ports_2_bits_uop_fu_code_2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fu_code_3_0 = io_wakeup_ports_2_bits_uop_fu_code_3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fu_code_4_0 = io_wakeup_ports_2_bits_uop_fu_code_4; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fu_code_5_0 = io_wakeup_ports_2_bits_uop_fu_code_5; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fu_code_6_0 = io_wakeup_ports_2_bits_uop_fu_code_6; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fu_code_7_0 = io_wakeup_ports_2_bits_uop_fu_code_7; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fu_code_8_0 = io_wakeup_ports_2_bits_uop_fu_code_8; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fu_code_9_0 = io_wakeup_ports_2_bits_uop_fu_code_9; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_iw_issued_0 = io_wakeup_ports_2_bits_uop_iw_issued; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel_0 = io_wakeup_ports_2_bits_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7] wire [15:0] io_wakeup_ports_2_bits_uop_br_mask_0 = io_wakeup_ports_2_bits_uop_br_mask; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_tag_0 = io_wakeup_ports_2_bits_uop_br_tag; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_type_0 = io_wakeup_ports_2_bits_uop_br_type; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_is_sfb_0 = io_wakeup_ports_2_bits_uop_is_sfb; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_is_fence_0 = io_wakeup_ports_2_bits_uop_is_fence; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_is_fencei_0 = io_wakeup_ports_2_bits_uop_is_fencei; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_is_sfence_0 = io_wakeup_ports_2_bits_uop_is_sfence; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_is_amo_0 = io_wakeup_ports_2_bits_uop_is_amo; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_is_eret_0 = io_wakeup_ports_2_bits_uop_is_eret; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_2_bits_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_is_rocc_0 = io_wakeup_ports_2_bits_uop_is_rocc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_is_mov_0 = io_wakeup_ports_2_bits_uop_is_mov; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_2_bits_uop_ftq_idx_0 = io_wakeup_ports_2_bits_uop_ftq_idx; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_edge_inst_0 = io_wakeup_ports_2_bits_uop_edge_inst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_2_bits_uop_pc_lob_0 = io_wakeup_ports_2_bits_uop_pc_lob; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_taken_0 = io_wakeup_ports_2_bits_uop_taken; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_imm_rename_0 = io_wakeup_ports_2_bits_uop_imm_rename; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_2_bits_uop_imm_sel_0 = io_wakeup_ports_2_bits_uop_imm_sel; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_2_bits_uop_pimm_0 = io_wakeup_ports_2_bits_uop_pimm; // @[issue-unit-age-ordered.scala:22:7] wire [19:0] io_wakeup_ports_2_bits_uop_imm_packed_0 = io_wakeup_ports_2_bits_uop_imm_packed; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_2_bits_uop_op1_sel_0 = io_wakeup_ports_2_bits_uop_op1_sel; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_2_bits_uop_op2_sel_0 = io_wakeup_ports_2_bits_uop_op2_sel; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_2_bits_uop_rob_idx_0 = io_wakeup_ports_2_bits_uop_rob_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_2_bits_uop_ldq_idx_0 = io_wakeup_ports_2_bits_uop_ldq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_2_bits_uop_stq_idx_0 = io_wakeup_ports_2_bits_uop_stq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_2_bits_uop_rxq_idx_0 = io_wakeup_ports_2_bits_uop_rxq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_2_bits_uop_pdst_0 = io_wakeup_ports_2_bits_uop_pdst; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs1_0 = io_wakeup_ports_2_bits_uop_prs1; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs2_0 = io_wakeup_ports_2_bits_uop_prs2; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs3_0 = io_wakeup_ports_2_bits_uop_prs3; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_2_bits_uop_ppred_0 = io_wakeup_ports_2_bits_uop_ppred; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_prs1_busy_0 = io_wakeup_ports_2_bits_uop_prs1_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_prs2_busy_0 = io_wakeup_ports_2_bits_uop_prs2_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_prs3_busy_0 = io_wakeup_ports_2_bits_uop_prs3_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_ppred_busy_0 = io_wakeup_ports_2_bits_uop_ppred_busy; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_2_bits_uop_stale_pdst_0 = io_wakeup_ports_2_bits_uop_stale_pdst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_exception_0 = io_wakeup_ports_2_bits_uop_exception; // @[issue-unit-age-ordered.scala:22:7] wire [63:0] io_wakeup_ports_2_bits_uop_exc_cause_0 = io_wakeup_ports_2_bits_uop_exc_cause; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_2_bits_uop_mem_cmd_0 = io_wakeup_ports_2_bits_uop_mem_cmd; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_2_bits_uop_mem_size_0 = io_wakeup_ports_2_bits_uop_mem_size; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_mem_signed_0 = io_wakeup_ports_2_bits_uop_mem_signed; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_uses_ldq_0 = io_wakeup_ports_2_bits_uop_uses_ldq; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_uses_stq_0 = io_wakeup_ports_2_bits_uop_uses_stq; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_is_unique_0 = io_wakeup_ports_2_bits_uop_is_unique; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_flush_on_commit_0 = io_wakeup_ports_2_bits_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_2_bits_uop_csr_cmd_0 = io_wakeup_ports_2_bits_uop_csr_cmd; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_2_bits_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_2_bits_uop_ldst_0 = io_wakeup_ports_2_bits_uop_ldst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs1_0 = io_wakeup_ports_2_bits_uop_lrs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs2_0 = io_wakeup_ports_2_bits_uop_lrs2; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs3_0 = io_wakeup_ports_2_bits_uop_lrs3; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_2_bits_uop_dst_rtype_0 = io_wakeup_ports_2_bits_uop_dst_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype_0 = io_wakeup_ports_2_bits_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype_0 = io_wakeup_ports_2_bits_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_frs3_en_0 = io_wakeup_ports_2_bits_uop_frs3_en; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fcn_dw_0 = io_wakeup_ports_2_bits_uop_fcn_dw; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_2_bits_uop_fcn_op_0 = io_wakeup_ports_2_bits_uop_fcn_op; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fp_val_0 = io_wakeup_ports_2_bits_uop_fp_val; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_2_bits_uop_fp_rm_0 = io_wakeup_ports_2_bits_uop_fp_rm; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_typ_0 = io_wakeup_ports_2_bits_uop_fp_typ; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_2_bits_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_bp_debug_if_0 = io_wakeup_ports_2_bits_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_2_bits_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc_0 = io_wakeup_ports_2_bits_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc_0 = io_wakeup_ports_2_bits_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_wakeup_ports_3_bits_uop_inst_0 = io_wakeup_ports_3_bits_uop_inst; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_wakeup_ports_3_bits_uop_debug_inst_0 = io_wakeup_ports_3_bits_uop_debug_inst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_is_rvc_0 = io_wakeup_ports_3_bits_uop_is_rvc; // @[issue-unit-age-ordered.scala:22:7] wire [39:0] io_wakeup_ports_3_bits_uop_debug_pc_0 = io_wakeup_ports_3_bits_uop_debug_pc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_iq_type_0_0 = io_wakeup_ports_3_bits_uop_iq_type_0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_iq_type_1_0 = io_wakeup_ports_3_bits_uop_iq_type_1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_iq_type_2_0 = io_wakeup_ports_3_bits_uop_iq_type_2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_iq_type_3_0 = io_wakeup_ports_3_bits_uop_iq_type_3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fu_code_0_0 = io_wakeup_ports_3_bits_uop_fu_code_0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fu_code_1_0 = io_wakeup_ports_3_bits_uop_fu_code_1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fu_code_2_0 = io_wakeup_ports_3_bits_uop_fu_code_2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fu_code_3_0 = io_wakeup_ports_3_bits_uop_fu_code_3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fu_code_4_0 = io_wakeup_ports_3_bits_uop_fu_code_4; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fu_code_5_0 = io_wakeup_ports_3_bits_uop_fu_code_5; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fu_code_6_0 = io_wakeup_ports_3_bits_uop_fu_code_6; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fu_code_7_0 = io_wakeup_ports_3_bits_uop_fu_code_7; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fu_code_8_0 = io_wakeup_ports_3_bits_uop_fu_code_8; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fu_code_9_0 = io_wakeup_ports_3_bits_uop_fu_code_9; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_iw_issued_0 = io_wakeup_ports_3_bits_uop_iw_issued; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel_0 = io_wakeup_ports_3_bits_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7] wire [15:0] io_wakeup_ports_3_bits_uop_br_mask_0 = io_wakeup_ports_3_bits_uop_br_mask; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_tag_0 = io_wakeup_ports_3_bits_uop_br_tag; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_type_0 = io_wakeup_ports_3_bits_uop_br_type; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_is_sfb_0 = io_wakeup_ports_3_bits_uop_is_sfb; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_is_fence_0 = io_wakeup_ports_3_bits_uop_is_fence; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_is_fencei_0 = io_wakeup_ports_3_bits_uop_is_fencei; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_is_sfence_0 = io_wakeup_ports_3_bits_uop_is_sfence; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_is_amo_0 = io_wakeup_ports_3_bits_uop_is_amo; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_is_eret_0 = io_wakeup_ports_3_bits_uop_is_eret; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_3_bits_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_is_rocc_0 = io_wakeup_ports_3_bits_uop_is_rocc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_is_mov_0 = io_wakeup_ports_3_bits_uop_is_mov; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_3_bits_uop_ftq_idx_0 = io_wakeup_ports_3_bits_uop_ftq_idx; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_edge_inst_0 = io_wakeup_ports_3_bits_uop_edge_inst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_3_bits_uop_pc_lob_0 = io_wakeup_ports_3_bits_uop_pc_lob; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_taken_0 = io_wakeup_ports_3_bits_uop_taken; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_imm_rename_0 = io_wakeup_ports_3_bits_uop_imm_rename; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_3_bits_uop_imm_sel_0 = io_wakeup_ports_3_bits_uop_imm_sel; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_3_bits_uop_pimm_0 = io_wakeup_ports_3_bits_uop_pimm; // @[issue-unit-age-ordered.scala:22:7] wire [19:0] io_wakeup_ports_3_bits_uop_imm_packed_0 = io_wakeup_ports_3_bits_uop_imm_packed; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_3_bits_uop_op1_sel_0 = io_wakeup_ports_3_bits_uop_op1_sel; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_3_bits_uop_op2_sel_0 = io_wakeup_ports_3_bits_uop_op2_sel; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_3_bits_uop_rob_idx_0 = io_wakeup_ports_3_bits_uop_rob_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_3_bits_uop_ldq_idx_0 = io_wakeup_ports_3_bits_uop_ldq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_3_bits_uop_stq_idx_0 = io_wakeup_ports_3_bits_uop_stq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_3_bits_uop_rxq_idx_0 = io_wakeup_ports_3_bits_uop_rxq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_3_bits_uop_pdst_0 = io_wakeup_ports_3_bits_uop_pdst; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs1_0 = io_wakeup_ports_3_bits_uop_prs1; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs2_0 = io_wakeup_ports_3_bits_uop_prs2; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs3_0 = io_wakeup_ports_3_bits_uop_prs3; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_3_bits_uop_ppred_0 = io_wakeup_ports_3_bits_uop_ppred; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_prs1_busy_0 = io_wakeup_ports_3_bits_uop_prs1_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_prs2_busy_0 = io_wakeup_ports_3_bits_uop_prs2_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_prs3_busy_0 = io_wakeup_ports_3_bits_uop_prs3_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_ppred_busy_0 = io_wakeup_ports_3_bits_uop_ppred_busy; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_3_bits_uop_stale_pdst_0 = io_wakeup_ports_3_bits_uop_stale_pdst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_exception_0 = io_wakeup_ports_3_bits_uop_exception; // @[issue-unit-age-ordered.scala:22:7] wire [63:0] io_wakeup_ports_3_bits_uop_exc_cause_0 = io_wakeup_ports_3_bits_uop_exc_cause; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_3_bits_uop_mem_cmd_0 = io_wakeup_ports_3_bits_uop_mem_cmd; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_3_bits_uop_mem_size_0 = io_wakeup_ports_3_bits_uop_mem_size; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_mem_signed_0 = io_wakeup_ports_3_bits_uop_mem_signed; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_uses_ldq_0 = io_wakeup_ports_3_bits_uop_uses_ldq; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_uses_stq_0 = io_wakeup_ports_3_bits_uop_uses_stq; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_is_unique_0 = io_wakeup_ports_3_bits_uop_is_unique; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_flush_on_commit_0 = io_wakeup_ports_3_bits_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_3_bits_uop_csr_cmd_0 = io_wakeup_ports_3_bits_uop_csr_cmd; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_3_bits_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_3_bits_uop_ldst_0 = io_wakeup_ports_3_bits_uop_ldst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs1_0 = io_wakeup_ports_3_bits_uop_lrs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs2_0 = io_wakeup_ports_3_bits_uop_lrs2; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs3_0 = io_wakeup_ports_3_bits_uop_lrs3; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_3_bits_uop_dst_rtype_0 = io_wakeup_ports_3_bits_uop_dst_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype_0 = io_wakeup_ports_3_bits_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype_0 = io_wakeup_ports_3_bits_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_frs3_en_0 = io_wakeup_ports_3_bits_uop_frs3_en; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fcn_dw_0 = io_wakeup_ports_3_bits_uop_fcn_dw; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_3_bits_uop_fcn_op_0 = io_wakeup_ports_3_bits_uop_fcn_op; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fp_val_0 = io_wakeup_ports_3_bits_uop_fp_val; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_3_bits_uop_fp_rm_0 = io_wakeup_ports_3_bits_uop_fp_rm; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_typ_0 = io_wakeup_ports_3_bits_uop_fp_typ; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_3_bits_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_bp_debug_if_0 = io_wakeup_ports_3_bits_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_3_bits_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc_0 = io_wakeup_ports_3_bits_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc_0 = io_wakeup_ports_3_bits_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_wakeup_ports_4_bits_uop_inst_0 = io_wakeup_ports_4_bits_uop_inst; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_wakeup_ports_4_bits_uop_debug_inst_0 = io_wakeup_ports_4_bits_uop_debug_inst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_is_rvc_0 = io_wakeup_ports_4_bits_uop_is_rvc; // @[issue-unit-age-ordered.scala:22:7] wire [39:0] io_wakeup_ports_4_bits_uop_debug_pc_0 = io_wakeup_ports_4_bits_uop_debug_pc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_iq_type_0_0 = io_wakeup_ports_4_bits_uop_iq_type_0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_iq_type_1_0 = io_wakeup_ports_4_bits_uop_iq_type_1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_iq_type_2_0 = io_wakeup_ports_4_bits_uop_iq_type_2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_iq_type_3_0 = io_wakeup_ports_4_bits_uop_iq_type_3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fu_code_0_0 = io_wakeup_ports_4_bits_uop_fu_code_0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fu_code_1_0 = io_wakeup_ports_4_bits_uop_fu_code_1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fu_code_2_0 = io_wakeup_ports_4_bits_uop_fu_code_2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fu_code_3_0 = io_wakeup_ports_4_bits_uop_fu_code_3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fu_code_4_0 = io_wakeup_ports_4_bits_uop_fu_code_4; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fu_code_5_0 = io_wakeup_ports_4_bits_uop_fu_code_5; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fu_code_6_0 = io_wakeup_ports_4_bits_uop_fu_code_6; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fu_code_7_0 = io_wakeup_ports_4_bits_uop_fu_code_7; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fu_code_8_0 = io_wakeup_ports_4_bits_uop_fu_code_8; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fu_code_9_0 = io_wakeup_ports_4_bits_uop_fu_code_9; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_iw_issued_0 = io_wakeup_ports_4_bits_uop_iw_issued; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel_0 = io_wakeup_ports_4_bits_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7] wire [15:0] io_wakeup_ports_4_bits_uop_br_mask_0 = io_wakeup_ports_4_bits_uop_br_mask; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_wakeup_ports_4_bits_uop_br_tag_0 = io_wakeup_ports_4_bits_uop_br_tag; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_wakeup_ports_4_bits_uop_br_type_0 = io_wakeup_ports_4_bits_uop_br_type; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_is_sfb_0 = io_wakeup_ports_4_bits_uop_is_sfb; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_is_fence_0 = io_wakeup_ports_4_bits_uop_is_fence; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_is_fencei_0 = io_wakeup_ports_4_bits_uop_is_fencei; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_is_sfence_0 = io_wakeup_ports_4_bits_uop_is_sfence; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_is_amo_0 = io_wakeup_ports_4_bits_uop_is_amo; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_is_eret_0 = io_wakeup_ports_4_bits_uop_is_eret; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_4_bits_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_is_rocc_0 = io_wakeup_ports_4_bits_uop_is_rocc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_is_mov_0 = io_wakeup_ports_4_bits_uop_is_mov; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_4_bits_uop_ftq_idx_0 = io_wakeup_ports_4_bits_uop_ftq_idx; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_edge_inst_0 = io_wakeup_ports_4_bits_uop_edge_inst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_4_bits_uop_pc_lob_0 = io_wakeup_ports_4_bits_uop_pc_lob; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_taken_0 = io_wakeup_ports_4_bits_uop_taken; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_imm_rename_0 = io_wakeup_ports_4_bits_uop_imm_rename; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_4_bits_uop_imm_sel_0 = io_wakeup_ports_4_bits_uop_imm_sel; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_4_bits_uop_pimm_0 = io_wakeup_ports_4_bits_uop_pimm; // @[issue-unit-age-ordered.scala:22:7] wire [19:0] io_wakeup_ports_4_bits_uop_imm_packed_0 = io_wakeup_ports_4_bits_uop_imm_packed; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_4_bits_uop_op1_sel_0 = io_wakeup_ports_4_bits_uop_op1_sel; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_4_bits_uop_op2_sel_0 = io_wakeup_ports_4_bits_uop_op2_sel; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_4_bits_uop_rob_idx_0 = io_wakeup_ports_4_bits_uop_rob_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_4_bits_uop_ldq_idx_0 = io_wakeup_ports_4_bits_uop_ldq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_4_bits_uop_stq_idx_0 = io_wakeup_ports_4_bits_uop_stq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_4_bits_uop_rxq_idx_0 = io_wakeup_ports_4_bits_uop_rxq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_4_bits_uop_pdst_0 = io_wakeup_ports_4_bits_uop_pdst; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_4_bits_uop_prs1_0 = io_wakeup_ports_4_bits_uop_prs1; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_4_bits_uop_prs2_0 = io_wakeup_ports_4_bits_uop_prs2; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_4_bits_uop_prs3_0 = io_wakeup_ports_4_bits_uop_prs3; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_4_bits_uop_ppred_0 = io_wakeup_ports_4_bits_uop_ppred; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_prs1_busy_0 = io_wakeup_ports_4_bits_uop_prs1_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_prs2_busy_0 = io_wakeup_ports_4_bits_uop_prs2_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_prs3_busy_0 = io_wakeup_ports_4_bits_uop_prs3_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_ppred_busy_0 = io_wakeup_ports_4_bits_uop_ppred_busy; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_4_bits_uop_stale_pdst_0 = io_wakeup_ports_4_bits_uop_stale_pdst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_exception_0 = io_wakeup_ports_4_bits_uop_exception; // @[issue-unit-age-ordered.scala:22:7] wire [63:0] io_wakeup_ports_4_bits_uop_exc_cause_0 = io_wakeup_ports_4_bits_uop_exc_cause; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_4_bits_uop_mem_cmd_0 = io_wakeup_ports_4_bits_uop_mem_cmd; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_4_bits_uop_mem_size_0 = io_wakeup_ports_4_bits_uop_mem_size; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_mem_signed_0 = io_wakeup_ports_4_bits_uop_mem_signed; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_uses_ldq_0 = io_wakeup_ports_4_bits_uop_uses_ldq; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_uses_stq_0 = io_wakeup_ports_4_bits_uop_uses_stq; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_is_unique_0 = io_wakeup_ports_4_bits_uop_is_unique; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_flush_on_commit_0 = io_wakeup_ports_4_bits_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_4_bits_uop_csr_cmd_0 = io_wakeup_ports_4_bits_uop_csr_cmd; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_4_bits_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_4_bits_uop_ldst_0 = io_wakeup_ports_4_bits_uop_ldst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_4_bits_uop_lrs1_0 = io_wakeup_ports_4_bits_uop_lrs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_4_bits_uop_lrs2_0 = io_wakeup_ports_4_bits_uop_lrs2; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_4_bits_uop_lrs3_0 = io_wakeup_ports_4_bits_uop_lrs3; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_4_bits_uop_dst_rtype_0 = io_wakeup_ports_4_bits_uop_dst_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype_0 = io_wakeup_ports_4_bits_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype_0 = io_wakeup_ports_4_bits_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_frs3_en_0 = io_wakeup_ports_4_bits_uop_frs3_en; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fcn_dw_0 = io_wakeup_ports_4_bits_uop_fcn_dw; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_4_bits_uop_fcn_op_0 = io_wakeup_ports_4_bits_uop_fcn_op; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fp_val_0 = io_wakeup_ports_4_bits_uop_fp_val; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_4_bits_uop_fp_rm_0 = io_wakeup_ports_4_bits_uop_fp_rm; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_4_bits_uop_fp_typ_0 = io_wakeup_ports_4_bits_uop_fp_typ; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_4_bits_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_bp_debug_if_0 = io_wakeup_ports_4_bits_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_4_bits_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc_0 = io_wakeup_ports_4_bits_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc_0 = io_wakeup_ports_4_bits_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_child_rebusys_0 = io_child_rebusys; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_1_1_0 = io_fu_types_1_1; // @[issue-unit-age-ordered.scala:22:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-unit-age-ordered.scala:22:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-unit-age-ordered.scala:22:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-unit-age-ordered.scala:22:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-unit-age-ordered.scala:22:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-unit-age-ordered.scala:22:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-unit-age-ordered.scala:22:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-unit-age-ordered.scala:22:7] wire io_flush_pipeline_0 = io_flush_pipeline; // @[issue-unit-age-ordered.scala:22:7] wire io_squash_grant_0 = io_squash_grant; // @[issue-unit-age-ordered.scala:22:7] wire [63:0] io_tsc_reg_0 = io_tsc_reg; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_0 = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_1 = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_3 = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_4 = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_5 = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_6 = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_7 = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_8 = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_9 = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_1_0 = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_1_3 = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_1_4 = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_1_5 = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_1_6 = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_1_7 = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_1_8 = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_1_9 = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire prs1_rebusys_1 = 1'h0; // @[issue-unit-age-ordered.scala:50:95] wire prs1_rebusys_2 = 1'h0; // @[issue-unit-age-ordered.scala:50:95] wire prs1_rebusys_3 = 1'h0; // @[issue-unit-age-ordered.scala:50:95] wire prs1_rebusys_4 = 1'h0; // @[issue-unit-age-ordered.scala:50:95] wire prs2_rebusys_1 = 1'h0; // @[issue-unit-age-ordered.scala:51:95] wire prs2_rebusys_2 = 1'h0; // @[issue-unit-age-ordered.scala:51:95] wire prs2_rebusys_3 = 1'h0; // @[issue-unit-age-ordered.scala:51:95] wire prs2_rebusys_4 = 1'h0; // @[issue-unit-age-ordered.scala:51:95] wire prs1_rebusys_1_1 = 1'h0; // @[issue-unit-age-ordered.scala:50:95] wire prs1_rebusys_2_1 = 1'h0; // @[issue-unit-age-ordered.scala:50:95] wire prs1_rebusys_3_1 = 1'h0; // @[issue-unit-age-ordered.scala:50:95] wire prs1_rebusys_4_1 = 1'h0; // @[issue-unit-age-ordered.scala:50:95] wire prs2_rebusys_1_1 = 1'h0; // @[issue-unit-age-ordered.scala:51:95] wire prs2_rebusys_2_1 = 1'h0; // @[issue-unit-age-ordered.scala:51:95] wire prs2_rebusys_3_1 = 1'h0; // @[issue-unit-age-ordered.scala:51:95] wire prs2_rebusys_4_1 = 1'h0; // @[issue-unit-age-ordered.scala:51:95] wire prs1_rebusys_1_2 = 1'h0; // @[issue-unit-age-ordered.scala:50:95] wire prs1_rebusys_2_2 = 1'h0; // @[issue-unit-age-ordered.scala:50:95] wire prs1_rebusys_3_2 = 1'h0; // @[issue-unit-age-ordered.scala:50:95] wire prs1_rebusys_4_2 = 1'h0; // @[issue-unit-age-ordered.scala:50:95] wire prs2_rebusys_1_2 = 1'h0; // @[issue-unit-age-ordered.scala:51:95] wire prs2_rebusys_2_2 = 1'h0; // @[issue-unit-age-ordered.scala:51:95] wire prs2_rebusys_3_2 = 1'h0; // @[issue-unit-age-ordered.scala:51:95] wire prs2_rebusys_4_2 = 1'h0; // @[issue-unit-age-ordered.scala:51:95] wire issue_slots_0_clear = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_iw_issued = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_prs3_busy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_ppred_busy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire _shamts_oh_1_T_2 = 1'h0; // @[issue-unit-age-ordered.scala:165:28] wire _issue_slots_0_clear_T = 1'h0; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_1 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_3 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_4 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_5 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_6 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_7 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_8 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_9 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_10 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_18 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_21 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_22 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_23 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_24 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_25 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_26 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_27 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_36 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_37 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_39 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_40 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_41 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_42 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_43 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_44 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_45 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_46 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_54 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_57 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_58 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_59 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_60 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_61 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_62 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_63 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_72 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_73 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_75 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_76 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_77 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_78 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_79 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_80 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_81 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_82 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_90 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_93 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_94 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_95 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_96 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_97 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_98 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_99 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_108 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_109 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_111 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_112 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_113 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_114 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_115 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_116 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_117 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_118 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_126 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_129 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_130 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_131 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_132 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_133 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_134 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_135 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_144 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_145 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_147 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_148 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_149 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_150 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_151 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_152 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_153 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_154 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_162 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_165 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_166 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_167 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_168 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_169 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_170 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_171 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_180 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_181 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_183 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_184 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_185 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_186 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_187 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_188 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_189 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_190 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_198 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_201 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_202 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_203 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_204 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_205 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_206 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_207 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_216 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_217 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_219 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_220 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_221 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_222 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_223 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_224 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_225 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_226 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_234 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_237 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_238 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_239 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_240 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_241 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_242 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_243 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_252 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_253 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_255 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_256 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_257 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_258 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_259 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_260 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_261 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_262 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_270 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_273 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_274 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_275 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_276 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_277 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_278 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_279 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_288 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_289 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_291 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_292 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_293 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_294 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_295 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_296 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_297 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_298 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_306 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_309 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_310 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_311 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_312 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_313 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_314 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_315 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_324 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_325 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_327 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_328 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_329 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_330 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_331 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_332 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_333 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_334 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_342 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_345 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_346 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_347 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_348 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_349 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_350 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_351 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_360 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_361 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_363 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_364 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_365 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_366 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_367 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_368 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_369 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_370 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_378 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_381 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_382 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_383 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_384 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_385 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_386 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_387 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_396 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_397 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_399 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_400 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_401 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_402 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_403 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_404 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_405 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_406 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_414 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_417 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_418 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_419 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_420 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_421 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_422 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_423 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_432 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_433 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_435 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_436 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_437 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_438 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_439 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_440 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_441 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_442 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_450 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_453 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_454 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_455 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_456 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_457 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_458 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_459 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_468 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_469 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_471 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_472 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_473 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_474 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_475 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_476 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_477 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_478 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_486 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_489 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_490 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_491 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_492 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_493 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_494 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_495 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_504 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_505 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_507 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_508 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_509 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_510 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_511 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_512 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_513 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_514 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_522 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_525 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_526 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_527 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_528 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_529 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_530 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_531 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_540 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_541 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_543 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_544 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_545 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_546 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_547 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_548 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_549 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_550 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_558 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_561 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_562 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_563 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_564 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_565 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_566 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_567 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire [1:0] io_iss_uops_0_bits_lrs2_rtype = 2'h2; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_1_bits_lrs2_rtype = 2'h2; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] issue_slots_0_iss_uop_lrs2_rtype = 2'h2; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_lrs2_rtype = 2'h2; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_lrs2_rtype = 2'h2; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_lrs2_rtype = 2'h2; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_lrs2_rtype = 2'h2; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_lrs2_rtype = 2'h2; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_lrs2_rtype = 2'h2; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_lrs2_rtype = 2'h2; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_lrs2_rtype = 2'h2; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_lrs2_rtype = 2'h2; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_lrs2_rtype = 2'h2; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_lrs2_rtype = 2'h2; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_iss_uop_lrs2_rtype = 2'h2; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_iss_uop_lrs2_rtype = 2'h2; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_iss_uop_lrs2_rtype = 2'h2; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_iss_uop_lrs2_rtype = 2'h2; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] iss_uops_0_bits_lrs2_rtype = 2'h2; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_1_bits_lrs2_rtype = 2'h2; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] io_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] issue_slots_0_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] shamts_oh_0 = 3'h0; // @[issue-unit-age-ordered.scala:158:23] wire io_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_2 = 1'h1; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_1_2 = 1'h1; // @[issue-unit-age-ordered.scala:22:7] wire issue_slots_0_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire _shamts_oh_1_T = 1'h1; // @[issue-unit-age-ordered.scala:163:21] wire _shamts_oh_1_T_3 = 1'h1; // @[issue-unit-age-ordered.scala:165:19] wire [2:0] io_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] issue_slots_0_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] io_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] issue_slots_0_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] io_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] issue_slots_0_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] issue_slots_0_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] _shamts_oh_1_next_T = 4'h0; // @[issue-unit-age-ordered.scala:166:26] wire [31:0] iss_uops_0_bits_inst; // @[issue-unit-age-ordered.scala:241:22] wire [31:0] iss_uops_0_bits_debug_inst; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_rvc; // @[issue-unit-age-ordered.scala:241:22] wire [39:0] iss_uops_0_bits_debug_pc; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_iq_type_0; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_iq_type_1; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_iq_type_2; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_iq_type_3; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_0; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_1; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_2; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_3; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_4; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_5; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_6; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_7; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_8; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_9; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_iw_issued; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] iss_uops_0_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] iss_uops_0_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] iss_uops_0_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:241:22] wire [15:0] iss_uops_0_bits_br_mask; // @[issue-unit-age-ordered.scala:241:22] wire [3:0] iss_uops_0_bits_br_tag; // @[issue-unit-age-ordered.scala:241:22] wire [3:0] iss_uops_0_bits_br_type; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_sfb; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_fence; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_fencei; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_sfence; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_amo; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_eret; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_rocc; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_mov; // @[issue-unit-age-ordered.scala:241:22] wire [4:0] iss_uops_0_bits_ftq_idx; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_edge_inst; // @[issue-unit-age-ordered.scala:241:22] wire [5:0] iss_uops_0_bits_pc_lob; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_taken; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_imm_rename; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] iss_uops_0_bits_imm_sel; // @[issue-unit-age-ordered.scala:241:22] wire [4:0] iss_uops_0_bits_pimm; // @[issue-unit-age-ordered.scala:241:22] wire [19:0] iss_uops_0_bits_imm_packed; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_op1_sel; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] iss_uops_0_bits_op2_sel; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:241:22] wire [6:0] iss_uops_0_bits_rob_idx; // @[issue-unit-age-ordered.scala:241:22] wire [4:0] iss_uops_0_bits_ldq_idx; // @[issue-unit-age-ordered.scala:241:22] wire [4:0] iss_uops_0_bits_stq_idx; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_rxq_idx; // @[issue-unit-age-ordered.scala:241:22] wire [6:0] iss_uops_0_bits_pdst; // @[issue-unit-age-ordered.scala:241:22] wire [6:0] iss_uops_0_bits_prs1; // @[issue-unit-age-ordered.scala:241:22] wire [6:0] iss_uops_0_bits_prs2; // @[issue-unit-age-ordered.scala:241:22] wire [6:0] iss_uops_0_bits_prs3; // @[issue-unit-age-ordered.scala:241:22] wire [4:0] iss_uops_0_bits_ppred; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_prs1_busy; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_prs2_busy; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_prs3_busy; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_ppred_busy; // @[issue-unit-age-ordered.scala:241:22] wire [6:0] iss_uops_0_bits_stale_pdst; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_exception; // @[issue-unit-age-ordered.scala:241:22] wire [63:0] iss_uops_0_bits_exc_cause; // @[issue-unit-age-ordered.scala:241:22] wire [4:0] iss_uops_0_bits_mem_cmd; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_mem_size; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_mem_signed; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_uses_ldq; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_uses_stq; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_unique; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] iss_uops_0_bits_csr_cmd; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:241:22] wire [5:0] iss_uops_0_bits_ldst; // @[issue-unit-age-ordered.scala:241:22] wire [5:0] iss_uops_0_bits_lrs1; // @[issue-unit-age-ordered.scala:241:22] wire [5:0] iss_uops_0_bits_lrs2; // @[issue-unit-age-ordered.scala:241:22] wire [5:0] iss_uops_0_bits_lrs3; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_dst_rtype; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_frs3_en; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fcn_dw; // @[issue-unit-age-ordered.scala:241:22] wire [4:0] iss_uops_0_bits_fcn_op; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_val; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] iss_uops_0_bits_fp_rm; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_fp_typ; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] iss_uops_0_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] iss_uops_0_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:241:22] wire [31:0] iss_uops_1_bits_inst; // @[issue-unit-age-ordered.scala:241:22] wire [31:0] iss_uops_1_bits_debug_inst; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_is_rvc; // @[issue-unit-age-ordered.scala:241:22] wire [39:0] iss_uops_1_bits_debug_pc; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_iq_type_0; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_iq_type_1; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_iq_type_2; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_iq_type_3; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_fu_code_0; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_fu_code_1; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_fu_code_2; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_fu_code_3; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_fu_code_4; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_fu_code_5; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_fu_code_6; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_fu_code_7; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_fu_code_8; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_fu_code_9; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_iw_issued; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] iss_uops_1_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] iss_uops_1_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] iss_uops_1_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:241:22] wire [15:0] iss_uops_1_bits_br_mask; // @[issue-unit-age-ordered.scala:241:22] wire [3:0] iss_uops_1_bits_br_tag; // @[issue-unit-age-ordered.scala:241:22] wire [3:0] iss_uops_1_bits_br_type; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_is_sfb; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_is_fence; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_is_fencei; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_is_sfence; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_is_amo; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_is_eret; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_is_rocc; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_is_mov; // @[issue-unit-age-ordered.scala:241:22] wire [4:0] iss_uops_1_bits_ftq_idx; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_edge_inst; // @[issue-unit-age-ordered.scala:241:22] wire [5:0] iss_uops_1_bits_pc_lob; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_taken; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_imm_rename; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] iss_uops_1_bits_imm_sel; // @[issue-unit-age-ordered.scala:241:22] wire [4:0] iss_uops_1_bits_pimm; // @[issue-unit-age-ordered.scala:241:22] wire [19:0] iss_uops_1_bits_imm_packed; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_1_bits_op1_sel; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] iss_uops_1_bits_op2_sel; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_1_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_1_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:241:22] wire [6:0] iss_uops_1_bits_rob_idx; // @[issue-unit-age-ordered.scala:241:22] wire [4:0] iss_uops_1_bits_ldq_idx; // @[issue-unit-age-ordered.scala:241:22] wire [4:0] iss_uops_1_bits_stq_idx; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_1_bits_rxq_idx; // @[issue-unit-age-ordered.scala:241:22] wire [6:0] iss_uops_1_bits_pdst; // @[issue-unit-age-ordered.scala:241:22] wire [6:0] iss_uops_1_bits_prs1; // @[issue-unit-age-ordered.scala:241:22] wire [6:0] iss_uops_1_bits_prs2; // @[issue-unit-age-ordered.scala:241:22] wire [6:0] iss_uops_1_bits_prs3; // @[issue-unit-age-ordered.scala:241:22] wire [4:0] iss_uops_1_bits_ppred; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_prs1_busy; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_prs2_busy; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_prs3_busy; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_ppred_busy; // @[issue-unit-age-ordered.scala:241:22] wire [6:0] iss_uops_1_bits_stale_pdst; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_exception; // @[issue-unit-age-ordered.scala:241:22] wire [63:0] iss_uops_1_bits_exc_cause; // @[issue-unit-age-ordered.scala:241:22] wire [4:0] iss_uops_1_bits_mem_cmd; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_1_bits_mem_size; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_mem_signed; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_uses_ldq; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_uses_stq; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_is_unique; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] iss_uops_1_bits_csr_cmd; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:241:22] wire [5:0] iss_uops_1_bits_ldst; // @[issue-unit-age-ordered.scala:241:22] wire [5:0] iss_uops_1_bits_lrs1; // @[issue-unit-age-ordered.scala:241:22] wire [5:0] iss_uops_1_bits_lrs2; // @[issue-unit-age-ordered.scala:241:22] wire [5:0] iss_uops_1_bits_lrs3; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_1_bits_dst_rtype; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_1_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_frs3_en; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_fcn_dw; // @[issue-unit-age-ordered.scala:241:22] wire [4:0] iss_uops_1_bits_fcn_op; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_fp_val; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] iss_uops_1_bits_fp_rm; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_1_bits_fp_typ; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_1_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] iss_uops_1_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] iss_uops_1_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:241:22] wire issue_slots_0_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_0_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_1_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_2_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_3_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_4_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_5_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_6_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_7_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_8_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_9_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_10_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_11_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_12_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_13_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_14_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_15_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_0_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_1_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_2_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_3_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_4_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_5_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_6_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_7_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_8_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_9_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_10_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_11_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_12_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_13_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_14_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_15_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_0_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_1_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_2_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_3_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_4_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_5_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_6_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_7_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_8_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_9_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_10_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_11_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_12_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_13_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_14_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_15_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_0_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_1_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_2_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_3_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_4_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_5_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_6_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_7_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_8_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_9_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_10_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_11_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_12_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_13_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_14_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_15_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_12_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_13_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_14_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_15_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_12_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_13_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_14_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_15_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_0_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_1_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_2_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_3_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_4_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_5_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_6_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_7_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_8_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_9_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_10_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_11_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_12_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_13_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_14_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_15_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_0_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_1_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_2_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_3_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_4_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_5_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_6_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_7_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_8_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_9_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_10_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_11_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_12_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_13_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_14_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_15_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_0_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_1_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_2_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_3_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_4_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_5_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_6_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_7_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_8_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_9_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_10_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_11_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_12_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_13_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_14_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_15_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_0_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_1_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_2_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_3_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_4_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_5_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_6_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_7_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_8_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_9_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_10_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_11_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_12_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_13_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_14_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_15_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_0_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_1_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_2_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_3_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_4_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_5_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_6_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_7_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_8_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_9_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_10_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_11_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_12_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_13_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_14_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_15_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_0_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_1_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_2_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_3_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_4_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_5_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_6_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_7_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_8_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_9_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_10_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_11_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_12_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_13_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_14_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_15_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_12_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_13_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_14_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_15_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_12_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_13_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_14_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_15_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_0_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_1_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_2_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_3_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_4_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_5_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_6_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_7_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_8_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_9_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_10_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_11_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_12_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_13_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_14_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_15_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_0_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_1_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_2_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_3_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_4_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_5_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_6_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_7_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_8_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_9_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_10_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_11_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_12_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_13_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_14_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_15_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_0_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_1_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_2_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_3_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_4_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_5_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_6_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_7_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_8_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_9_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_10_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_11_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_12_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_13_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_14_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_15_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_0_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_1_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_2_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_3_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_4_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_5_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_6_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_7_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_8_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_9_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_10_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_11_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_12_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_13_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_14_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_15_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_0_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_1_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_2_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_3_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_4_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_5_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_6_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_7_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_8_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_9_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_10_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_11_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_12_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_13_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_14_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_15_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_0_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_1_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_2_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_3_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_4_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_5_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_6_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_7_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_8_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_9_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_10_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_11_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_12_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_13_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_14_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_15_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_12_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_13_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_14_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_15_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_12_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_13_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_14_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_15_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_0_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_1_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_2_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_3_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_4_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_5_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_6_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_7_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_8_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_9_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_10_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_11_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_12_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_13_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_14_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_15_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_0_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_1_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_2_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_3_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_4_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_5_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_6_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_7_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_8_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_9_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_10_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_11_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_12_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_13_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_14_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_15_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_0_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_1_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_2_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_3_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_4_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_5_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_6_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_7_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_8_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_9_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_10_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_11_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_12_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_13_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_14_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_15_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_0_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_1_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_2_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_3_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_4_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_5_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_6_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_7_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_8_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_9_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_10_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_11_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_12_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_13_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_14_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_15_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_0_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_1_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_2_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_3_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_4_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_5_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_6_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_7_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_8_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_9_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_10_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_11_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_12_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_13_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_14_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_15_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_0_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_1_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_2_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_3_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_4_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_5_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_6_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_7_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_8_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_9_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_10_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_11_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_12_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_13_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_14_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_15_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_12_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_13_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_14_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_15_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_12_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_13_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_14_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_15_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_0_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_1_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_2_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_3_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_4_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_5_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_6_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_7_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_8_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_9_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_10_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_11_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_12_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_13_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_14_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_15_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_0_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_1_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_2_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_3_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_4_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_5_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_6_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_7_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_8_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_9_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_10_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_11_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_12_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_13_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_14_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_15_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_0_wakeup_ports_4_bits_uop_inst = io_wakeup_ports_4_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_1_wakeup_ports_4_bits_uop_inst = io_wakeup_ports_4_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_2_wakeup_ports_4_bits_uop_inst = io_wakeup_ports_4_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_3_wakeup_ports_4_bits_uop_inst = io_wakeup_ports_4_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_4_wakeup_ports_4_bits_uop_inst = io_wakeup_ports_4_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_5_wakeup_ports_4_bits_uop_inst = io_wakeup_ports_4_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_6_wakeup_ports_4_bits_uop_inst = io_wakeup_ports_4_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_7_wakeup_ports_4_bits_uop_inst = io_wakeup_ports_4_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_8_wakeup_ports_4_bits_uop_inst = io_wakeup_ports_4_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_9_wakeup_ports_4_bits_uop_inst = io_wakeup_ports_4_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_10_wakeup_ports_4_bits_uop_inst = io_wakeup_ports_4_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_11_wakeup_ports_4_bits_uop_inst = io_wakeup_ports_4_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_12_wakeup_ports_4_bits_uop_inst = io_wakeup_ports_4_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_13_wakeup_ports_4_bits_uop_inst = io_wakeup_ports_4_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_14_wakeup_ports_4_bits_uop_inst = io_wakeup_ports_4_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_15_wakeup_ports_4_bits_uop_inst = io_wakeup_ports_4_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_0_wakeup_ports_4_bits_uop_debug_inst = io_wakeup_ports_4_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_1_wakeup_ports_4_bits_uop_debug_inst = io_wakeup_ports_4_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_2_wakeup_ports_4_bits_uop_debug_inst = io_wakeup_ports_4_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_3_wakeup_ports_4_bits_uop_debug_inst = io_wakeup_ports_4_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_4_wakeup_ports_4_bits_uop_debug_inst = io_wakeup_ports_4_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_5_wakeup_ports_4_bits_uop_debug_inst = io_wakeup_ports_4_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_6_wakeup_ports_4_bits_uop_debug_inst = io_wakeup_ports_4_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_7_wakeup_ports_4_bits_uop_debug_inst = io_wakeup_ports_4_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_8_wakeup_ports_4_bits_uop_debug_inst = io_wakeup_ports_4_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_9_wakeup_ports_4_bits_uop_debug_inst = io_wakeup_ports_4_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_10_wakeup_ports_4_bits_uop_debug_inst = io_wakeup_ports_4_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_11_wakeup_ports_4_bits_uop_debug_inst = io_wakeup_ports_4_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_12_wakeup_ports_4_bits_uop_debug_inst = io_wakeup_ports_4_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_13_wakeup_ports_4_bits_uop_debug_inst = io_wakeup_ports_4_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_14_wakeup_ports_4_bits_uop_debug_inst = io_wakeup_ports_4_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_15_wakeup_ports_4_bits_uop_debug_inst = io_wakeup_ports_4_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_is_rvc = io_wakeup_ports_4_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_is_rvc = io_wakeup_ports_4_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_is_rvc = io_wakeup_ports_4_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_is_rvc = io_wakeup_ports_4_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_is_rvc = io_wakeup_ports_4_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_is_rvc = io_wakeup_ports_4_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_is_rvc = io_wakeup_ports_4_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_is_rvc = io_wakeup_ports_4_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_is_rvc = io_wakeup_ports_4_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_is_rvc = io_wakeup_ports_4_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_is_rvc = io_wakeup_ports_4_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_is_rvc = io_wakeup_ports_4_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_is_rvc = io_wakeup_ports_4_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_is_rvc = io_wakeup_ports_4_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_is_rvc = io_wakeup_ports_4_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_is_rvc = io_wakeup_ports_4_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_0_wakeup_ports_4_bits_uop_debug_pc = io_wakeup_ports_4_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_1_wakeup_ports_4_bits_uop_debug_pc = io_wakeup_ports_4_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_2_wakeup_ports_4_bits_uop_debug_pc = io_wakeup_ports_4_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_3_wakeup_ports_4_bits_uop_debug_pc = io_wakeup_ports_4_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_4_wakeup_ports_4_bits_uop_debug_pc = io_wakeup_ports_4_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_5_wakeup_ports_4_bits_uop_debug_pc = io_wakeup_ports_4_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_6_wakeup_ports_4_bits_uop_debug_pc = io_wakeup_ports_4_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_7_wakeup_ports_4_bits_uop_debug_pc = io_wakeup_ports_4_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_8_wakeup_ports_4_bits_uop_debug_pc = io_wakeup_ports_4_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_9_wakeup_ports_4_bits_uop_debug_pc = io_wakeup_ports_4_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_10_wakeup_ports_4_bits_uop_debug_pc = io_wakeup_ports_4_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_11_wakeup_ports_4_bits_uop_debug_pc = io_wakeup_ports_4_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_12_wakeup_ports_4_bits_uop_debug_pc = io_wakeup_ports_4_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_13_wakeup_ports_4_bits_uop_debug_pc = io_wakeup_ports_4_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_14_wakeup_ports_4_bits_uop_debug_pc = io_wakeup_ports_4_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_15_wakeup_ports_4_bits_uop_debug_pc = io_wakeup_ports_4_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_iq_type_0 = io_wakeup_ports_4_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_iq_type_0 = io_wakeup_ports_4_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_iq_type_0 = io_wakeup_ports_4_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_iq_type_0 = io_wakeup_ports_4_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_iq_type_0 = io_wakeup_ports_4_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_iq_type_0 = io_wakeup_ports_4_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_iq_type_0 = io_wakeup_ports_4_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_iq_type_0 = io_wakeup_ports_4_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_iq_type_0 = io_wakeup_ports_4_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_iq_type_0 = io_wakeup_ports_4_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_iq_type_0 = io_wakeup_ports_4_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_iq_type_0 = io_wakeup_ports_4_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_iq_type_0 = io_wakeup_ports_4_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_iq_type_0 = io_wakeup_ports_4_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_iq_type_0 = io_wakeup_ports_4_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_iq_type_0 = io_wakeup_ports_4_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_iq_type_1 = io_wakeup_ports_4_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_iq_type_1 = io_wakeup_ports_4_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_iq_type_1 = io_wakeup_ports_4_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_iq_type_1 = io_wakeup_ports_4_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_iq_type_1 = io_wakeup_ports_4_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_iq_type_1 = io_wakeup_ports_4_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_iq_type_1 = io_wakeup_ports_4_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_iq_type_1 = io_wakeup_ports_4_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_iq_type_1 = io_wakeup_ports_4_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_iq_type_1 = io_wakeup_ports_4_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_iq_type_1 = io_wakeup_ports_4_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_iq_type_1 = io_wakeup_ports_4_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_iq_type_1 = io_wakeup_ports_4_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_iq_type_1 = io_wakeup_ports_4_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_iq_type_1 = io_wakeup_ports_4_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_iq_type_1 = io_wakeup_ports_4_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_iq_type_2 = io_wakeup_ports_4_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_iq_type_2 = io_wakeup_ports_4_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_iq_type_2 = io_wakeup_ports_4_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_iq_type_2 = io_wakeup_ports_4_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_iq_type_2 = io_wakeup_ports_4_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_iq_type_2 = io_wakeup_ports_4_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_iq_type_2 = io_wakeup_ports_4_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_iq_type_2 = io_wakeup_ports_4_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_iq_type_2 = io_wakeup_ports_4_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_iq_type_2 = io_wakeup_ports_4_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_iq_type_2 = io_wakeup_ports_4_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_iq_type_2 = io_wakeup_ports_4_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_iq_type_2 = io_wakeup_ports_4_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_iq_type_2 = io_wakeup_ports_4_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_iq_type_2 = io_wakeup_ports_4_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_iq_type_2 = io_wakeup_ports_4_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_iq_type_3 = io_wakeup_ports_4_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_iq_type_3 = io_wakeup_ports_4_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_iq_type_3 = io_wakeup_ports_4_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_iq_type_3 = io_wakeup_ports_4_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_iq_type_3 = io_wakeup_ports_4_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_iq_type_3 = io_wakeup_ports_4_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_iq_type_3 = io_wakeup_ports_4_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_iq_type_3 = io_wakeup_ports_4_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_iq_type_3 = io_wakeup_ports_4_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_iq_type_3 = io_wakeup_ports_4_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_iq_type_3 = io_wakeup_ports_4_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_iq_type_3 = io_wakeup_ports_4_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_iq_type_3 = io_wakeup_ports_4_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_iq_type_3 = io_wakeup_ports_4_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_iq_type_3 = io_wakeup_ports_4_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_iq_type_3 = io_wakeup_ports_4_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fu_code_0 = io_wakeup_ports_4_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fu_code_0 = io_wakeup_ports_4_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fu_code_0 = io_wakeup_ports_4_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fu_code_0 = io_wakeup_ports_4_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fu_code_0 = io_wakeup_ports_4_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fu_code_0 = io_wakeup_ports_4_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fu_code_0 = io_wakeup_ports_4_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fu_code_0 = io_wakeup_ports_4_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fu_code_0 = io_wakeup_ports_4_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fu_code_0 = io_wakeup_ports_4_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fu_code_0 = io_wakeup_ports_4_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fu_code_0 = io_wakeup_ports_4_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fu_code_0 = io_wakeup_ports_4_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fu_code_0 = io_wakeup_ports_4_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fu_code_0 = io_wakeup_ports_4_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fu_code_0 = io_wakeup_ports_4_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fu_code_1 = io_wakeup_ports_4_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fu_code_1 = io_wakeup_ports_4_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fu_code_1 = io_wakeup_ports_4_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fu_code_1 = io_wakeup_ports_4_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fu_code_1 = io_wakeup_ports_4_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fu_code_1 = io_wakeup_ports_4_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fu_code_1 = io_wakeup_ports_4_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fu_code_1 = io_wakeup_ports_4_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fu_code_1 = io_wakeup_ports_4_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fu_code_1 = io_wakeup_ports_4_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fu_code_1 = io_wakeup_ports_4_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fu_code_1 = io_wakeup_ports_4_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fu_code_1 = io_wakeup_ports_4_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fu_code_1 = io_wakeup_ports_4_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fu_code_1 = io_wakeup_ports_4_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fu_code_1 = io_wakeup_ports_4_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fu_code_2 = io_wakeup_ports_4_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fu_code_2 = io_wakeup_ports_4_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fu_code_2 = io_wakeup_ports_4_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fu_code_2 = io_wakeup_ports_4_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fu_code_2 = io_wakeup_ports_4_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fu_code_2 = io_wakeup_ports_4_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fu_code_2 = io_wakeup_ports_4_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fu_code_2 = io_wakeup_ports_4_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fu_code_2 = io_wakeup_ports_4_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fu_code_2 = io_wakeup_ports_4_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fu_code_2 = io_wakeup_ports_4_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fu_code_2 = io_wakeup_ports_4_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fu_code_2 = io_wakeup_ports_4_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fu_code_2 = io_wakeup_ports_4_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fu_code_2 = io_wakeup_ports_4_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fu_code_2 = io_wakeup_ports_4_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fu_code_3 = io_wakeup_ports_4_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fu_code_3 = io_wakeup_ports_4_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fu_code_3 = io_wakeup_ports_4_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fu_code_3 = io_wakeup_ports_4_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fu_code_3 = io_wakeup_ports_4_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fu_code_3 = io_wakeup_ports_4_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fu_code_3 = io_wakeup_ports_4_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fu_code_3 = io_wakeup_ports_4_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fu_code_3 = io_wakeup_ports_4_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fu_code_3 = io_wakeup_ports_4_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fu_code_3 = io_wakeup_ports_4_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fu_code_3 = io_wakeup_ports_4_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fu_code_3 = io_wakeup_ports_4_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fu_code_3 = io_wakeup_ports_4_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fu_code_3 = io_wakeup_ports_4_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fu_code_3 = io_wakeup_ports_4_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fu_code_4 = io_wakeup_ports_4_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fu_code_4 = io_wakeup_ports_4_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fu_code_4 = io_wakeup_ports_4_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fu_code_4 = io_wakeup_ports_4_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fu_code_4 = io_wakeup_ports_4_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fu_code_4 = io_wakeup_ports_4_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fu_code_4 = io_wakeup_ports_4_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fu_code_4 = io_wakeup_ports_4_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fu_code_4 = io_wakeup_ports_4_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fu_code_4 = io_wakeup_ports_4_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fu_code_4 = io_wakeup_ports_4_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fu_code_4 = io_wakeup_ports_4_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fu_code_4 = io_wakeup_ports_4_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fu_code_4 = io_wakeup_ports_4_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fu_code_4 = io_wakeup_ports_4_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fu_code_4 = io_wakeup_ports_4_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fu_code_5 = io_wakeup_ports_4_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fu_code_5 = io_wakeup_ports_4_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fu_code_5 = io_wakeup_ports_4_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fu_code_5 = io_wakeup_ports_4_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fu_code_5 = io_wakeup_ports_4_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fu_code_5 = io_wakeup_ports_4_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fu_code_5 = io_wakeup_ports_4_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fu_code_5 = io_wakeup_ports_4_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fu_code_5 = io_wakeup_ports_4_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fu_code_5 = io_wakeup_ports_4_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fu_code_5 = io_wakeup_ports_4_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fu_code_5 = io_wakeup_ports_4_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fu_code_5 = io_wakeup_ports_4_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fu_code_5 = io_wakeup_ports_4_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fu_code_5 = io_wakeup_ports_4_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fu_code_5 = io_wakeup_ports_4_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fu_code_6 = io_wakeup_ports_4_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fu_code_6 = io_wakeup_ports_4_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fu_code_6 = io_wakeup_ports_4_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fu_code_6 = io_wakeup_ports_4_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fu_code_6 = io_wakeup_ports_4_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fu_code_6 = io_wakeup_ports_4_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fu_code_6 = io_wakeup_ports_4_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fu_code_6 = io_wakeup_ports_4_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fu_code_6 = io_wakeup_ports_4_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fu_code_6 = io_wakeup_ports_4_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fu_code_6 = io_wakeup_ports_4_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fu_code_6 = io_wakeup_ports_4_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fu_code_6 = io_wakeup_ports_4_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fu_code_6 = io_wakeup_ports_4_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fu_code_6 = io_wakeup_ports_4_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fu_code_6 = io_wakeup_ports_4_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fu_code_7 = io_wakeup_ports_4_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fu_code_7 = io_wakeup_ports_4_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fu_code_7 = io_wakeup_ports_4_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fu_code_7 = io_wakeup_ports_4_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fu_code_7 = io_wakeup_ports_4_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fu_code_7 = io_wakeup_ports_4_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fu_code_7 = io_wakeup_ports_4_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fu_code_7 = io_wakeup_ports_4_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fu_code_7 = io_wakeup_ports_4_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fu_code_7 = io_wakeup_ports_4_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fu_code_7 = io_wakeup_ports_4_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fu_code_7 = io_wakeup_ports_4_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fu_code_7 = io_wakeup_ports_4_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fu_code_7 = io_wakeup_ports_4_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fu_code_7 = io_wakeup_ports_4_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fu_code_7 = io_wakeup_ports_4_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fu_code_8 = io_wakeup_ports_4_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fu_code_8 = io_wakeup_ports_4_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fu_code_8 = io_wakeup_ports_4_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fu_code_8 = io_wakeup_ports_4_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fu_code_8 = io_wakeup_ports_4_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fu_code_8 = io_wakeup_ports_4_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fu_code_8 = io_wakeup_ports_4_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fu_code_8 = io_wakeup_ports_4_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fu_code_8 = io_wakeup_ports_4_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fu_code_8 = io_wakeup_ports_4_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fu_code_8 = io_wakeup_ports_4_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fu_code_8 = io_wakeup_ports_4_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fu_code_8 = io_wakeup_ports_4_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fu_code_8 = io_wakeup_ports_4_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fu_code_8 = io_wakeup_ports_4_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fu_code_8 = io_wakeup_ports_4_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fu_code_9 = io_wakeup_ports_4_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fu_code_9 = io_wakeup_ports_4_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fu_code_9 = io_wakeup_ports_4_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fu_code_9 = io_wakeup_ports_4_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fu_code_9 = io_wakeup_ports_4_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fu_code_9 = io_wakeup_ports_4_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fu_code_9 = io_wakeup_ports_4_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fu_code_9 = io_wakeup_ports_4_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fu_code_9 = io_wakeup_ports_4_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fu_code_9 = io_wakeup_ports_4_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fu_code_9 = io_wakeup_ports_4_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fu_code_9 = io_wakeup_ports_4_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fu_code_9 = io_wakeup_ports_4_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fu_code_9 = io_wakeup_ports_4_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fu_code_9 = io_wakeup_ports_4_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fu_code_9 = io_wakeup_ports_4_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_iw_issued = io_wakeup_ports_4_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_iw_issued = io_wakeup_ports_4_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_iw_issued = io_wakeup_ports_4_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_iw_issued = io_wakeup_ports_4_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_iw_issued = io_wakeup_ports_4_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_iw_issued = io_wakeup_ports_4_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_iw_issued = io_wakeup_ports_4_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_iw_issued = io_wakeup_ports_4_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_iw_issued = io_wakeup_ports_4_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_iw_issued = io_wakeup_ports_4_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_iw_issued = io_wakeup_ports_4_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_iw_issued = io_wakeup_ports_4_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_iw_issued = io_wakeup_ports_4_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_iw_issued = io_wakeup_ports_4_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_iw_issued = io_wakeup_ports_4_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_iw_issued = io_wakeup_ports_4_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_4_bits_uop_iw_p1_speculative_child = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_4_bits_uop_iw_p1_speculative_child = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_4_bits_uop_iw_p1_speculative_child = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_4_bits_uop_iw_p1_speculative_child = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_4_bits_uop_iw_p1_speculative_child = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_4_bits_uop_iw_p1_speculative_child = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_4_bits_uop_iw_p1_speculative_child = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_4_bits_uop_iw_p1_speculative_child = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_4_bits_uop_iw_p1_speculative_child = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_4_bits_uop_iw_p1_speculative_child = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_4_bits_uop_iw_p1_speculative_child = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_4_bits_uop_iw_p1_speculative_child = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_4_bits_uop_iw_p1_speculative_child = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_4_bits_uop_iw_p1_speculative_child = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_4_bits_uop_iw_p1_speculative_child = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_4_bits_uop_iw_p1_speculative_child = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_4_bits_uop_iw_p2_speculative_child = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_4_bits_uop_iw_p2_speculative_child = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_4_bits_uop_iw_p2_speculative_child = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_4_bits_uop_iw_p2_speculative_child = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_4_bits_uop_iw_p2_speculative_child = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_4_bits_uop_iw_p2_speculative_child = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_4_bits_uop_iw_p2_speculative_child = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_4_bits_uop_iw_p2_speculative_child = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_4_bits_uop_iw_p2_speculative_child = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_4_bits_uop_iw_p2_speculative_child = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_4_bits_uop_iw_p2_speculative_child = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_4_bits_uop_iw_p2_speculative_child = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_4_bits_uop_iw_p2_speculative_child = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_4_bits_uop_iw_p2_speculative_child = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_4_bits_uop_iw_p2_speculative_child = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_4_bits_uop_iw_p2_speculative_child = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_4_bits_uop_dis_col_sel = io_wakeup_ports_4_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_4_bits_uop_dis_col_sel = io_wakeup_ports_4_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_4_bits_uop_dis_col_sel = io_wakeup_ports_4_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_4_bits_uop_dis_col_sel = io_wakeup_ports_4_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_4_bits_uop_dis_col_sel = io_wakeup_ports_4_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_4_bits_uop_dis_col_sel = io_wakeup_ports_4_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_4_bits_uop_dis_col_sel = io_wakeup_ports_4_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_4_bits_uop_dis_col_sel = io_wakeup_ports_4_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_4_bits_uop_dis_col_sel = io_wakeup_ports_4_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_4_bits_uop_dis_col_sel = io_wakeup_ports_4_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_4_bits_uop_dis_col_sel = io_wakeup_ports_4_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_4_bits_uop_dis_col_sel = io_wakeup_ports_4_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_4_bits_uop_dis_col_sel = io_wakeup_ports_4_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_4_bits_uop_dis_col_sel = io_wakeup_ports_4_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_4_bits_uop_dis_col_sel = io_wakeup_ports_4_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_4_bits_uop_dis_col_sel = io_wakeup_ports_4_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_0_wakeup_ports_4_bits_uop_br_mask = io_wakeup_ports_4_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_1_wakeup_ports_4_bits_uop_br_mask = io_wakeup_ports_4_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_2_wakeup_ports_4_bits_uop_br_mask = io_wakeup_ports_4_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_3_wakeup_ports_4_bits_uop_br_mask = io_wakeup_ports_4_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_4_wakeup_ports_4_bits_uop_br_mask = io_wakeup_ports_4_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_5_wakeup_ports_4_bits_uop_br_mask = io_wakeup_ports_4_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_6_wakeup_ports_4_bits_uop_br_mask = io_wakeup_ports_4_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_7_wakeup_ports_4_bits_uop_br_mask = io_wakeup_ports_4_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_8_wakeup_ports_4_bits_uop_br_mask = io_wakeup_ports_4_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_9_wakeup_ports_4_bits_uop_br_mask = io_wakeup_ports_4_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_10_wakeup_ports_4_bits_uop_br_mask = io_wakeup_ports_4_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_11_wakeup_ports_4_bits_uop_br_mask = io_wakeup_ports_4_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_12_wakeup_ports_4_bits_uop_br_mask = io_wakeup_ports_4_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_13_wakeup_ports_4_bits_uop_br_mask = io_wakeup_ports_4_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_14_wakeup_ports_4_bits_uop_br_mask = io_wakeup_ports_4_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_15_wakeup_ports_4_bits_uop_br_mask = io_wakeup_ports_4_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_wakeup_ports_4_bits_uop_br_tag = io_wakeup_ports_4_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_wakeup_ports_4_bits_uop_br_tag = io_wakeup_ports_4_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_wakeup_ports_4_bits_uop_br_tag = io_wakeup_ports_4_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_wakeup_ports_4_bits_uop_br_tag = io_wakeup_ports_4_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_wakeup_ports_4_bits_uop_br_tag = io_wakeup_ports_4_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_wakeup_ports_4_bits_uop_br_tag = io_wakeup_ports_4_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_wakeup_ports_4_bits_uop_br_tag = io_wakeup_ports_4_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_wakeup_ports_4_bits_uop_br_tag = io_wakeup_ports_4_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_wakeup_ports_4_bits_uop_br_tag = io_wakeup_ports_4_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_wakeup_ports_4_bits_uop_br_tag = io_wakeup_ports_4_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_wakeup_ports_4_bits_uop_br_tag = io_wakeup_ports_4_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_wakeup_ports_4_bits_uop_br_tag = io_wakeup_ports_4_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_12_wakeup_ports_4_bits_uop_br_tag = io_wakeup_ports_4_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_13_wakeup_ports_4_bits_uop_br_tag = io_wakeup_ports_4_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_14_wakeup_ports_4_bits_uop_br_tag = io_wakeup_ports_4_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_15_wakeup_ports_4_bits_uop_br_tag = io_wakeup_ports_4_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_wakeup_ports_4_bits_uop_br_type = io_wakeup_ports_4_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_wakeup_ports_4_bits_uop_br_type = io_wakeup_ports_4_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_wakeup_ports_4_bits_uop_br_type = io_wakeup_ports_4_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_wakeup_ports_4_bits_uop_br_type = io_wakeup_ports_4_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_wakeup_ports_4_bits_uop_br_type = io_wakeup_ports_4_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_wakeup_ports_4_bits_uop_br_type = io_wakeup_ports_4_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_wakeup_ports_4_bits_uop_br_type = io_wakeup_ports_4_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_wakeup_ports_4_bits_uop_br_type = io_wakeup_ports_4_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_wakeup_ports_4_bits_uop_br_type = io_wakeup_ports_4_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_wakeup_ports_4_bits_uop_br_type = io_wakeup_ports_4_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_wakeup_ports_4_bits_uop_br_type = io_wakeup_ports_4_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_wakeup_ports_4_bits_uop_br_type = io_wakeup_ports_4_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_12_wakeup_ports_4_bits_uop_br_type = io_wakeup_ports_4_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_13_wakeup_ports_4_bits_uop_br_type = io_wakeup_ports_4_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_14_wakeup_ports_4_bits_uop_br_type = io_wakeup_ports_4_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_15_wakeup_ports_4_bits_uop_br_type = io_wakeup_ports_4_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_is_sfb = io_wakeup_ports_4_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_is_sfb = io_wakeup_ports_4_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_is_sfb = io_wakeup_ports_4_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_is_sfb = io_wakeup_ports_4_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_is_sfb = io_wakeup_ports_4_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_is_sfb = io_wakeup_ports_4_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_is_sfb = io_wakeup_ports_4_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_is_sfb = io_wakeup_ports_4_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_is_sfb = io_wakeup_ports_4_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_is_sfb = io_wakeup_ports_4_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_is_sfb = io_wakeup_ports_4_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_is_sfb = io_wakeup_ports_4_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_is_sfb = io_wakeup_ports_4_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_is_sfb = io_wakeup_ports_4_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_is_sfb = io_wakeup_ports_4_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_is_sfb = io_wakeup_ports_4_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_is_fence = io_wakeup_ports_4_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_is_fence = io_wakeup_ports_4_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_is_fence = io_wakeup_ports_4_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_is_fence = io_wakeup_ports_4_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_is_fence = io_wakeup_ports_4_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_is_fence = io_wakeup_ports_4_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_is_fence = io_wakeup_ports_4_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_is_fence = io_wakeup_ports_4_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_is_fence = io_wakeup_ports_4_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_is_fence = io_wakeup_ports_4_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_is_fence = io_wakeup_ports_4_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_is_fence = io_wakeup_ports_4_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_is_fence = io_wakeup_ports_4_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_is_fence = io_wakeup_ports_4_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_is_fence = io_wakeup_ports_4_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_is_fence = io_wakeup_ports_4_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_is_fencei = io_wakeup_ports_4_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_is_fencei = io_wakeup_ports_4_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_is_fencei = io_wakeup_ports_4_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_is_fencei = io_wakeup_ports_4_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_is_fencei = io_wakeup_ports_4_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_is_fencei = io_wakeup_ports_4_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_is_fencei = io_wakeup_ports_4_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_is_fencei = io_wakeup_ports_4_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_is_fencei = io_wakeup_ports_4_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_is_fencei = io_wakeup_ports_4_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_is_fencei = io_wakeup_ports_4_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_is_fencei = io_wakeup_ports_4_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_is_fencei = io_wakeup_ports_4_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_is_fencei = io_wakeup_ports_4_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_is_fencei = io_wakeup_ports_4_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_is_fencei = io_wakeup_ports_4_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_is_sfence = io_wakeup_ports_4_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_is_sfence = io_wakeup_ports_4_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_is_sfence = io_wakeup_ports_4_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_is_sfence = io_wakeup_ports_4_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_is_sfence = io_wakeup_ports_4_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_is_sfence = io_wakeup_ports_4_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_is_sfence = io_wakeup_ports_4_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_is_sfence = io_wakeup_ports_4_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_is_sfence = io_wakeup_ports_4_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_is_sfence = io_wakeup_ports_4_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_is_sfence = io_wakeup_ports_4_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_is_sfence = io_wakeup_ports_4_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_is_sfence = io_wakeup_ports_4_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_is_sfence = io_wakeup_ports_4_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_is_sfence = io_wakeup_ports_4_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_is_sfence = io_wakeup_ports_4_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_is_amo = io_wakeup_ports_4_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_is_amo = io_wakeup_ports_4_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_is_amo = io_wakeup_ports_4_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_is_amo = io_wakeup_ports_4_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_is_amo = io_wakeup_ports_4_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_is_amo = io_wakeup_ports_4_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_is_amo = io_wakeup_ports_4_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_is_amo = io_wakeup_ports_4_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_is_amo = io_wakeup_ports_4_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_is_amo = io_wakeup_ports_4_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_is_amo = io_wakeup_ports_4_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_is_amo = io_wakeup_ports_4_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_is_amo = io_wakeup_ports_4_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_is_amo = io_wakeup_ports_4_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_is_amo = io_wakeup_ports_4_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_is_amo = io_wakeup_ports_4_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_is_eret = io_wakeup_ports_4_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_is_eret = io_wakeup_ports_4_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_is_eret = io_wakeup_ports_4_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_is_eret = io_wakeup_ports_4_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_is_eret = io_wakeup_ports_4_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_is_eret = io_wakeup_ports_4_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_is_eret = io_wakeup_ports_4_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_is_eret = io_wakeup_ports_4_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_is_eret = io_wakeup_ports_4_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_is_eret = io_wakeup_ports_4_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_is_eret = io_wakeup_ports_4_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_is_eret = io_wakeup_ports_4_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_is_eret = io_wakeup_ports_4_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_is_eret = io_wakeup_ports_4_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_is_eret = io_wakeup_ports_4_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_is_eret = io_wakeup_ports_4_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_is_sys_pc2epc = io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_is_sys_pc2epc = io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_is_sys_pc2epc = io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_is_sys_pc2epc = io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_is_sys_pc2epc = io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_is_sys_pc2epc = io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_is_sys_pc2epc = io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_is_sys_pc2epc = io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_is_sys_pc2epc = io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_is_sys_pc2epc = io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_is_sys_pc2epc = io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_is_sys_pc2epc = io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_is_sys_pc2epc = io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_is_sys_pc2epc = io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_is_sys_pc2epc = io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_is_sys_pc2epc = io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_is_rocc = io_wakeup_ports_4_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_is_rocc = io_wakeup_ports_4_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_is_rocc = io_wakeup_ports_4_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_is_rocc = io_wakeup_ports_4_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_is_rocc = io_wakeup_ports_4_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_is_rocc = io_wakeup_ports_4_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_is_rocc = io_wakeup_ports_4_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_is_rocc = io_wakeup_ports_4_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_is_rocc = io_wakeup_ports_4_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_is_rocc = io_wakeup_ports_4_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_is_rocc = io_wakeup_ports_4_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_is_rocc = io_wakeup_ports_4_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_is_rocc = io_wakeup_ports_4_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_is_rocc = io_wakeup_ports_4_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_is_rocc = io_wakeup_ports_4_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_is_rocc = io_wakeup_ports_4_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_is_mov = io_wakeup_ports_4_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_is_mov = io_wakeup_ports_4_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_is_mov = io_wakeup_ports_4_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_is_mov = io_wakeup_ports_4_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_is_mov = io_wakeup_ports_4_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_is_mov = io_wakeup_ports_4_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_is_mov = io_wakeup_ports_4_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_is_mov = io_wakeup_ports_4_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_is_mov = io_wakeup_ports_4_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_is_mov = io_wakeup_ports_4_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_is_mov = io_wakeup_ports_4_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_is_mov = io_wakeup_ports_4_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_is_mov = io_wakeup_ports_4_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_is_mov = io_wakeup_ports_4_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_is_mov = io_wakeup_ports_4_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_is_mov = io_wakeup_ports_4_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_4_bits_uop_ftq_idx = io_wakeup_ports_4_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_4_bits_uop_ftq_idx = io_wakeup_ports_4_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_4_bits_uop_ftq_idx = io_wakeup_ports_4_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_4_bits_uop_ftq_idx = io_wakeup_ports_4_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_4_bits_uop_ftq_idx = io_wakeup_ports_4_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_4_bits_uop_ftq_idx = io_wakeup_ports_4_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_4_bits_uop_ftq_idx = io_wakeup_ports_4_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_4_bits_uop_ftq_idx = io_wakeup_ports_4_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_4_bits_uop_ftq_idx = io_wakeup_ports_4_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_4_bits_uop_ftq_idx = io_wakeup_ports_4_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_4_bits_uop_ftq_idx = io_wakeup_ports_4_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_4_bits_uop_ftq_idx = io_wakeup_ports_4_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_4_bits_uop_ftq_idx = io_wakeup_ports_4_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_4_bits_uop_ftq_idx = io_wakeup_ports_4_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_4_bits_uop_ftq_idx = io_wakeup_ports_4_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_4_bits_uop_ftq_idx = io_wakeup_ports_4_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_edge_inst = io_wakeup_ports_4_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_edge_inst = io_wakeup_ports_4_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_edge_inst = io_wakeup_ports_4_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_edge_inst = io_wakeup_ports_4_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_edge_inst = io_wakeup_ports_4_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_edge_inst = io_wakeup_ports_4_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_edge_inst = io_wakeup_ports_4_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_edge_inst = io_wakeup_ports_4_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_edge_inst = io_wakeup_ports_4_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_edge_inst = io_wakeup_ports_4_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_edge_inst = io_wakeup_ports_4_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_edge_inst = io_wakeup_ports_4_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_edge_inst = io_wakeup_ports_4_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_edge_inst = io_wakeup_ports_4_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_edge_inst = io_wakeup_ports_4_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_edge_inst = io_wakeup_ports_4_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_4_bits_uop_pc_lob = io_wakeup_ports_4_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_4_bits_uop_pc_lob = io_wakeup_ports_4_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_4_bits_uop_pc_lob = io_wakeup_ports_4_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_4_bits_uop_pc_lob = io_wakeup_ports_4_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_4_bits_uop_pc_lob = io_wakeup_ports_4_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_4_bits_uop_pc_lob = io_wakeup_ports_4_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_4_bits_uop_pc_lob = io_wakeup_ports_4_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_4_bits_uop_pc_lob = io_wakeup_ports_4_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_4_bits_uop_pc_lob = io_wakeup_ports_4_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_4_bits_uop_pc_lob = io_wakeup_ports_4_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_4_bits_uop_pc_lob = io_wakeup_ports_4_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_4_bits_uop_pc_lob = io_wakeup_ports_4_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_4_bits_uop_pc_lob = io_wakeup_ports_4_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_4_bits_uop_pc_lob = io_wakeup_ports_4_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_4_bits_uop_pc_lob = io_wakeup_ports_4_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_4_bits_uop_pc_lob = io_wakeup_ports_4_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_taken = io_wakeup_ports_4_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_taken = io_wakeup_ports_4_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_taken = io_wakeup_ports_4_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_taken = io_wakeup_ports_4_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_taken = io_wakeup_ports_4_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_taken = io_wakeup_ports_4_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_taken = io_wakeup_ports_4_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_taken = io_wakeup_ports_4_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_taken = io_wakeup_ports_4_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_taken = io_wakeup_ports_4_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_taken = io_wakeup_ports_4_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_taken = io_wakeup_ports_4_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_taken = io_wakeup_ports_4_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_taken = io_wakeup_ports_4_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_taken = io_wakeup_ports_4_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_taken = io_wakeup_ports_4_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_imm_rename = io_wakeup_ports_4_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_imm_rename = io_wakeup_ports_4_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_imm_rename = io_wakeup_ports_4_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_imm_rename = io_wakeup_ports_4_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_imm_rename = io_wakeup_ports_4_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_imm_rename = io_wakeup_ports_4_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_imm_rename = io_wakeup_ports_4_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_imm_rename = io_wakeup_ports_4_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_imm_rename = io_wakeup_ports_4_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_imm_rename = io_wakeup_ports_4_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_imm_rename = io_wakeup_ports_4_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_imm_rename = io_wakeup_ports_4_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_imm_rename = io_wakeup_ports_4_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_imm_rename = io_wakeup_ports_4_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_imm_rename = io_wakeup_ports_4_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_imm_rename = io_wakeup_ports_4_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_4_bits_uop_imm_sel = io_wakeup_ports_4_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_4_bits_uop_imm_sel = io_wakeup_ports_4_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_4_bits_uop_imm_sel = io_wakeup_ports_4_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_4_bits_uop_imm_sel = io_wakeup_ports_4_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_4_bits_uop_imm_sel = io_wakeup_ports_4_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_4_bits_uop_imm_sel = io_wakeup_ports_4_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_4_bits_uop_imm_sel = io_wakeup_ports_4_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_4_bits_uop_imm_sel = io_wakeup_ports_4_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_4_bits_uop_imm_sel = io_wakeup_ports_4_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_4_bits_uop_imm_sel = io_wakeup_ports_4_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_4_bits_uop_imm_sel = io_wakeup_ports_4_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_4_bits_uop_imm_sel = io_wakeup_ports_4_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_4_bits_uop_imm_sel = io_wakeup_ports_4_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_4_bits_uop_imm_sel = io_wakeup_ports_4_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_4_bits_uop_imm_sel = io_wakeup_ports_4_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_4_bits_uop_imm_sel = io_wakeup_ports_4_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_4_bits_uop_pimm = io_wakeup_ports_4_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_4_bits_uop_pimm = io_wakeup_ports_4_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_4_bits_uop_pimm = io_wakeup_ports_4_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_4_bits_uop_pimm = io_wakeup_ports_4_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_4_bits_uop_pimm = io_wakeup_ports_4_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_4_bits_uop_pimm = io_wakeup_ports_4_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_4_bits_uop_pimm = io_wakeup_ports_4_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_4_bits_uop_pimm = io_wakeup_ports_4_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_4_bits_uop_pimm = io_wakeup_ports_4_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_4_bits_uop_pimm = io_wakeup_ports_4_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_4_bits_uop_pimm = io_wakeup_ports_4_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_4_bits_uop_pimm = io_wakeup_ports_4_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_4_bits_uop_pimm = io_wakeup_ports_4_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_4_bits_uop_pimm = io_wakeup_ports_4_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_4_bits_uop_pimm = io_wakeup_ports_4_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_4_bits_uop_pimm = io_wakeup_ports_4_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_0_wakeup_ports_4_bits_uop_imm_packed = io_wakeup_ports_4_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_1_wakeup_ports_4_bits_uop_imm_packed = io_wakeup_ports_4_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_2_wakeup_ports_4_bits_uop_imm_packed = io_wakeup_ports_4_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_3_wakeup_ports_4_bits_uop_imm_packed = io_wakeup_ports_4_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_4_wakeup_ports_4_bits_uop_imm_packed = io_wakeup_ports_4_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_5_wakeup_ports_4_bits_uop_imm_packed = io_wakeup_ports_4_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_6_wakeup_ports_4_bits_uop_imm_packed = io_wakeup_ports_4_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_7_wakeup_ports_4_bits_uop_imm_packed = io_wakeup_ports_4_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_8_wakeup_ports_4_bits_uop_imm_packed = io_wakeup_ports_4_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_9_wakeup_ports_4_bits_uop_imm_packed = io_wakeup_ports_4_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_10_wakeup_ports_4_bits_uop_imm_packed = io_wakeup_ports_4_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_11_wakeup_ports_4_bits_uop_imm_packed = io_wakeup_ports_4_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_12_wakeup_ports_4_bits_uop_imm_packed = io_wakeup_ports_4_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_13_wakeup_ports_4_bits_uop_imm_packed = io_wakeup_ports_4_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_14_wakeup_ports_4_bits_uop_imm_packed = io_wakeup_ports_4_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_15_wakeup_ports_4_bits_uop_imm_packed = io_wakeup_ports_4_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_4_bits_uop_op1_sel = io_wakeup_ports_4_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_4_bits_uop_op1_sel = io_wakeup_ports_4_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_4_bits_uop_op1_sel = io_wakeup_ports_4_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_4_bits_uop_op1_sel = io_wakeup_ports_4_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_4_bits_uop_op1_sel = io_wakeup_ports_4_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_4_bits_uop_op1_sel = io_wakeup_ports_4_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_4_bits_uop_op1_sel = io_wakeup_ports_4_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_4_bits_uop_op1_sel = io_wakeup_ports_4_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_4_bits_uop_op1_sel = io_wakeup_ports_4_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_4_bits_uop_op1_sel = io_wakeup_ports_4_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_4_bits_uop_op1_sel = io_wakeup_ports_4_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_4_bits_uop_op1_sel = io_wakeup_ports_4_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_4_bits_uop_op1_sel = io_wakeup_ports_4_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_4_bits_uop_op1_sel = io_wakeup_ports_4_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_4_bits_uop_op1_sel = io_wakeup_ports_4_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_4_bits_uop_op1_sel = io_wakeup_ports_4_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_4_bits_uop_op2_sel = io_wakeup_ports_4_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_4_bits_uop_op2_sel = io_wakeup_ports_4_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_4_bits_uop_op2_sel = io_wakeup_ports_4_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_4_bits_uop_op2_sel = io_wakeup_ports_4_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_4_bits_uop_op2_sel = io_wakeup_ports_4_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_4_bits_uop_op2_sel = io_wakeup_ports_4_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_4_bits_uop_op2_sel = io_wakeup_ports_4_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_4_bits_uop_op2_sel = io_wakeup_ports_4_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_4_bits_uop_op2_sel = io_wakeup_ports_4_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_4_bits_uop_op2_sel = io_wakeup_ports_4_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_4_bits_uop_op2_sel = io_wakeup_ports_4_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_4_bits_uop_op2_sel = io_wakeup_ports_4_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_4_bits_uop_op2_sel = io_wakeup_ports_4_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_4_bits_uop_op2_sel = io_wakeup_ports_4_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_4_bits_uop_op2_sel = io_wakeup_ports_4_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_4_bits_uop_op2_sel = io_wakeup_ports_4_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fp_ctrl_ldst = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fp_ctrl_ldst = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fp_ctrl_ldst = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fp_ctrl_ldst = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fp_ctrl_ldst = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fp_ctrl_ldst = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fp_ctrl_ldst = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fp_ctrl_ldst = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fp_ctrl_ldst = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fp_ctrl_ldst = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fp_ctrl_ldst = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fp_ctrl_ldst = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fp_ctrl_ldst = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fp_ctrl_ldst = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fp_ctrl_ldst = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fp_ctrl_ldst = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fp_ctrl_wen = io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fp_ctrl_wen = io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fp_ctrl_wen = io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fp_ctrl_wen = io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fp_ctrl_wen = io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fp_ctrl_wen = io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fp_ctrl_wen = io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fp_ctrl_wen = io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fp_ctrl_wen = io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fp_ctrl_wen = io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fp_ctrl_wen = io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fp_ctrl_wen = io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fp_ctrl_wen = io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fp_ctrl_wen = io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fp_ctrl_wen = io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fp_ctrl_wen = io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fp_ctrl_fromint = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fp_ctrl_fromint = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fp_ctrl_fromint = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fp_ctrl_fromint = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fp_ctrl_fromint = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fp_ctrl_fromint = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fp_ctrl_fromint = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fp_ctrl_fromint = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fp_ctrl_fromint = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fp_ctrl_fromint = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fp_ctrl_fromint = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fp_ctrl_fromint = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fp_ctrl_fromint = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fp_ctrl_fromint = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fp_ctrl_fromint = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fp_ctrl_fromint = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fp_ctrl_toint = io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fp_ctrl_toint = io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fp_ctrl_toint = io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fp_ctrl_toint = io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fp_ctrl_toint = io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fp_ctrl_toint = io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fp_ctrl_toint = io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fp_ctrl_toint = io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fp_ctrl_toint = io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fp_ctrl_toint = io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fp_ctrl_toint = io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fp_ctrl_toint = io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fp_ctrl_toint = io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fp_ctrl_toint = io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fp_ctrl_toint = io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fp_ctrl_toint = io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fp_ctrl_fma = io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fp_ctrl_fma = io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fp_ctrl_fma = io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fp_ctrl_fma = io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fp_ctrl_fma = io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fp_ctrl_fma = io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fp_ctrl_fma = io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fp_ctrl_fma = io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fp_ctrl_fma = io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fp_ctrl_fma = io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fp_ctrl_fma = io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fp_ctrl_fma = io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fp_ctrl_fma = io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fp_ctrl_fma = io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fp_ctrl_fma = io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fp_ctrl_fma = io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fp_ctrl_div = io_wakeup_ports_4_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fp_ctrl_div = io_wakeup_ports_4_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fp_ctrl_div = io_wakeup_ports_4_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fp_ctrl_div = io_wakeup_ports_4_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fp_ctrl_div = io_wakeup_ports_4_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fp_ctrl_div = io_wakeup_ports_4_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fp_ctrl_div = io_wakeup_ports_4_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fp_ctrl_div = io_wakeup_ports_4_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fp_ctrl_div = io_wakeup_ports_4_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fp_ctrl_div = io_wakeup_ports_4_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fp_ctrl_div = io_wakeup_ports_4_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fp_ctrl_div = io_wakeup_ports_4_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fp_ctrl_div = io_wakeup_ports_4_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fp_ctrl_div = io_wakeup_ports_4_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fp_ctrl_div = io_wakeup_ports_4_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fp_ctrl_div = io_wakeup_ports_4_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fp_ctrl_wflags = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fp_ctrl_wflags = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fp_ctrl_wflags = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fp_ctrl_wflags = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fp_ctrl_wflags = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fp_ctrl_wflags = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fp_ctrl_wflags = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fp_ctrl_wflags = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fp_ctrl_wflags = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fp_ctrl_wflags = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fp_ctrl_wflags = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fp_ctrl_wflags = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fp_ctrl_wflags = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fp_ctrl_wflags = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fp_ctrl_wflags = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fp_ctrl_wflags = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fp_ctrl_vec = io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fp_ctrl_vec = io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fp_ctrl_vec = io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fp_ctrl_vec = io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fp_ctrl_vec = io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fp_ctrl_vec = io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fp_ctrl_vec = io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fp_ctrl_vec = io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fp_ctrl_vec = io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fp_ctrl_vec = io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fp_ctrl_vec = io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fp_ctrl_vec = io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fp_ctrl_vec = io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fp_ctrl_vec = io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fp_ctrl_vec = io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fp_ctrl_vec = io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_4_bits_uop_rob_idx = io_wakeup_ports_4_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_4_bits_uop_rob_idx = io_wakeup_ports_4_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_4_bits_uop_rob_idx = io_wakeup_ports_4_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_4_bits_uop_rob_idx = io_wakeup_ports_4_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_4_bits_uop_rob_idx = io_wakeup_ports_4_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_4_bits_uop_rob_idx = io_wakeup_ports_4_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_4_bits_uop_rob_idx = io_wakeup_ports_4_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_4_bits_uop_rob_idx = io_wakeup_ports_4_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_4_bits_uop_rob_idx = io_wakeup_ports_4_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_4_bits_uop_rob_idx = io_wakeup_ports_4_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_4_bits_uop_rob_idx = io_wakeup_ports_4_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_4_bits_uop_rob_idx = io_wakeup_ports_4_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_4_bits_uop_rob_idx = io_wakeup_ports_4_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_4_bits_uop_rob_idx = io_wakeup_ports_4_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_4_bits_uop_rob_idx = io_wakeup_ports_4_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_4_bits_uop_rob_idx = io_wakeup_ports_4_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_4_bits_uop_ldq_idx = io_wakeup_ports_4_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_4_bits_uop_ldq_idx = io_wakeup_ports_4_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_4_bits_uop_ldq_idx = io_wakeup_ports_4_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_4_bits_uop_ldq_idx = io_wakeup_ports_4_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_4_bits_uop_ldq_idx = io_wakeup_ports_4_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_4_bits_uop_ldq_idx = io_wakeup_ports_4_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_4_bits_uop_ldq_idx = io_wakeup_ports_4_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_4_bits_uop_ldq_idx = io_wakeup_ports_4_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_4_bits_uop_ldq_idx = io_wakeup_ports_4_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_4_bits_uop_ldq_idx = io_wakeup_ports_4_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_4_bits_uop_ldq_idx = io_wakeup_ports_4_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_4_bits_uop_ldq_idx = io_wakeup_ports_4_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_4_bits_uop_ldq_idx = io_wakeup_ports_4_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_4_bits_uop_ldq_idx = io_wakeup_ports_4_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_4_bits_uop_ldq_idx = io_wakeup_ports_4_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_4_bits_uop_ldq_idx = io_wakeup_ports_4_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_4_bits_uop_stq_idx = io_wakeup_ports_4_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_4_bits_uop_stq_idx = io_wakeup_ports_4_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_4_bits_uop_stq_idx = io_wakeup_ports_4_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_4_bits_uop_stq_idx = io_wakeup_ports_4_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_4_bits_uop_stq_idx = io_wakeup_ports_4_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_4_bits_uop_stq_idx = io_wakeup_ports_4_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_4_bits_uop_stq_idx = io_wakeup_ports_4_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_4_bits_uop_stq_idx = io_wakeup_ports_4_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_4_bits_uop_stq_idx = io_wakeup_ports_4_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_4_bits_uop_stq_idx = io_wakeup_ports_4_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_4_bits_uop_stq_idx = io_wakeup_ports_4_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_4_bits_uop_stq_idx = io_wakeup_ports_4_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_4_bits_uop_stq_idx = io_wakeup_ports_4_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_4_bits_uop_stq_idx = io_wakeup_ports_4_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_4_bits_uop_stq_idx = io_wakeup_ports_4_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_4_bits_uop_stq_idx = io_wakeup_ports_4_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_4_bits_uop_rxq_idx = io_wakeup_ports_4_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_4_bits_uop_rxq_idx = io_wakeup_ports_4_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_4_bits_uop_rxq_idx = io_wakeup_ports_4_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_4_bits_uop_rxq_idx = io_wakeup_ports_4_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_4_bits_uop_rxq_idx = io_wakeup_ports_4_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_4_bits_uop_rxq_idx = io_wakeup_ports_4_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_4_bits_uop_rxq_idx = io_wakeup_ports_4_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_4_bits_uop_rxq_idx = io_wakeup_ports_4_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_4_bits_uop_rxq_idx = io_wakeup_ports_4_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_4_bits_uop_rxq_idx = io_wakeup_ports_4_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_4_bits_uop_rxq_idx = io_wakeup_ports_4_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_4_bits_uop_rxq_idx = io_wakeup_ports_4_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_4_bits_uop_rxq_idx = io_wakeup_ports_4_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_4_bits_uop_rxq_idx = io_wakeup_ports_4_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_4_bits_uop_rxq_idx = io_wakeup_ports_4_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_4_bits_uop_rxq_idx = io_wakeup_ports_4_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_4_bits_uop_pdst = io_wakeup_ports_4_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_4_bits_uop_pdst = io_wakeup_ports_4_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_4_bits_uop_pdst = io_wakeup_ports_4_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_4_bits_uop_pdst = io_wakeup_ports_4_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_4_bits_uop_pdst = io_wakeup_ports_4_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_4_bits_uop_pdst = io_wakeup_ports_4_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_4_bits_uop_pdst = io_wakeup_ports_4_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_4_bits_uop_pdst = io_wakeup_ports_4_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_4_bits_uop_pdst = io_wakeup_ports_4_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_4_bits_uop_pdst = io_wakeup_ports_4_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_4_bits_uop_pdst = io_wakeup_ports_4_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_4_bits_uop_pdst = io_wakeup_ports_4_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_4_bits_uop_pdst = io_wakeup_ports_4_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_4_bits_uop_pdst = io_wakeup_ports_4_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_4_bits_uop_pdst = io_wakeup_ports_4_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_4_bits_uop_pdst = io_wakeup_ports_4_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_4_bits_uop_prs1 = io_wakeup_ports_4_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_4_bits_uop_prs1 = io_wakeup_ports_4_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_4_bits_uop_prs1 = io_wakeup_ports_4_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_4_bits_uop_prs1 = io_wakeup_ports_4_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_4_bits_uop_prs1 = io_wakeup_ports_4_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_4_bits_uop_prs1 = io_wakeup_ports_4_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_4_bits_uop_prs1 = io_wakeup_ports_4_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_4_bits_uop_prs1 = io_wakeup_ports_4_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_4_bits_uop_prs1 = io_wakeup_ports_4_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_4_bits_uop_prs1 = io_wakeup_ports_4_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_4_bits_uop_prs1 = io_wakeup_ports_4_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_4_bits_uop_prs1 = io_wakeup_ports_4_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_4_bits_uop_prs1 = io_wakeup_ports_4_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_4_bits_uop_prs1 = io_wakeup_ports_4_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_4_bits_uop_prs1 = io_wakeup_ports_4_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_4_bits_uop_prs1 = io_wakeup_ports_4_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_4_bits_uop_prs2 = io_wakeup_ports_4_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_4_bits_uop_prs2 = io_wakeup_ports_4_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_4_bits_uop_prs2 = io_wakeup_ports_4_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_4_bits_uop_prs2 = io_wakeup_ports_4_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_4_bits_uop_prs2 = io_wakeup_ports_4_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_4_bits_uop_prs2 = io_wakeup_ports_4_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_4_bits_uop_prs2 = io_wakeup_ports_4_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_4_bits_uop_prs2 = io_wakeup_ports_4_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_4_bits_uop_prs2 = io_wakeup_ports_4_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_4_bits_uop_prs2 = io_wakeup_ports_4_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_4_bits_uop_prs2 = io_wakeup_ports_4_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_4_bits_uop_prs2 = io_wakeup_ports_4_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_4_bits_uop_prs2 = io_wakeup_ports_4_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_4_bits_uop_prs2 = io_wakeup_ports_4_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_4_bits_uop_prs2 = io_wakeup_ports_4_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_4_bits_uop_prs2 = io_wakeup_ports_4_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_4_bits_uop_prs3 = io_wakeup_ports_4_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_4_bits_uop_prs3 = io_wakeup_ports_4_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_4_bits_uop_prs3 = io_wakeup_ports_4_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_4_bits_uop_prs3 = io_wakeup_ports_4_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_4_bits_uop_prs3 = io_wakeup_ports_4_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_4_bits_uop_prs3 = io_wakeup_ports_4_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_4_bits_uop_prs3 = io_wakeup_ports_4_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_4_bits_uop_prs3 = io_wakeup_ports_4_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_4_bits_uop_prs3 = io_wakeup_ports_4_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_4_bits_uop_prs3 = io_wakeup_ports_4_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_4_bits_uop_prs3 = io_wakeup_ports_4_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_4_bits_uop_prs3 = io_wakeup_ports_4_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_4_bits_uop_prs3 = io_wakeup_ports_4_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_4_bits_uop_prs3 = io_wakeup_ports_4_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_4_bits_uop_prs3 = io_wakeup_ports_4_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_4_bits_uop_prs3 = io_wakeup_ports_4_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_4_bits_uop_ppred = io_wakeup_ports_4_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_4_bits_uop_ppred = io_wakeup_ports_4_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_4_bits_uop_ppred = io_wakeup_ports_4_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_4_bits_uop_ppred = io_wakeup_ports_4_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_4_bits_uop_ppred = io_wakeup_ports_4_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_4_bits_uop_ppred = io_wakeup_ports_4_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_4_bits_uop_ppred = io_wakeup_ports_4_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_4_bits_uop_ppred = io_wakeup_ports_4_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_4_bits_uop_ppred = io_wakeup_ports_4_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_4_bits_uop_ppred = io_wakeup_ports_4_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_4_bits_uop_ppred = io_wakeup_ports_4_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_4_bits_uop_ppred = io_wakeup_ports_4_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_4_bits_uop_ppred = io_wakeup_ports_4_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_4_bits_uop_ppred = io_wakeup_ports_4_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_4_bits_uop_ppred = io_wakeup_ports_4_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_4_bits_uop_ppred = io_wakeup_ports_4_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_prs1_busy = io_wakeup_ports_4_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_prs1_busy = io_wakeup_ports_4_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_prs1_busy = io_wakeup_ports_4_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_prs1_busy = io_wakeup_ports_4_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_prs1_busy = io_wakeup_ports_4_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_prs1_busy = io_wakeup_ports_4_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_prs1_busy = io_wakeup_ports_4_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_prs1_busy = io_wakeup_ports_4_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_prs1_busy = io_wakeup_ports_4_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_prs1_busy = io_wakeup_ports_4_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_prs1_busy = io_wakeup_ports_4_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_prs1_busy = io_wakeup_ports_4_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_prs1_busy = io_wakeup_ports_4_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_prs1_busy = io_wakeup_ports_4_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_prs1_busy = io_wakeup_ports_4_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_prs1_busy = io_wakeup_ports_4_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_prs2_busy = io_wakeup_ports_4_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_prs2_busy = io_wakeup_ports_4_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_prs2_busy = io_wakeup_ports_4_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_prs2_busy = io_wakeup_ports_4_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_prs2_busy = io_wakeup_ports_4_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_prs2_busy = io_wakeup_ports_4_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_prs2_busy = io_wakeup_ports_4_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_prs2_busy = io_wakeup_ports_4_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_prs2_busy = io_wakeup_ports_4_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_prs2_busy = io_wakeup_ports_4_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_prs2_busy = io_wakeup_ports_4_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_prs2_busy = io_wakeup_ports_4_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_prs2_busy = io_wakeup_ports_4_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_prs2_busy = io_wakeup_ports_4_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_prs2_busy = io_wakeup_ports_4_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_prs2_busy = io_wakeup_ports_4_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_prs3_busy = io_wakeup_ports_4_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_prs3_busy = io_wakeup_ports_4_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_prs3_busy = io_wakeup_ports_4_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_prs3_busy = io_wakeup_ports_4_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_prs3_busy = io_wakeup_ports_4_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_prs3_busy = io_wakeup_ports_4_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_prs3_busy = io_wakeup_ports_4_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_prs3_busy = io_wakeup_ports_4_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_prs3_busy = io_wakeup_ports_4_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_prs3_busy = io_wakeup_ports_4_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_prs3_busy = io_wakeup_ports_4_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_prs3_busy = io_wakeup_ports_4_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_prs3_busy = io_wakeup_ports_4_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_prs3_busy = io_wakeup_ports_4_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_prs3_busy = io_wakeup_ports_4_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_prs3_busy = io_wakeup_ports_4_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_ppred_busy = io_wakeup_ports_4_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_ppred_busy = io_wakeup_ports_4_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_ppred_busy = io_wakeup_ports_4_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_ppred_busy = io_wakeup_ports_4_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_ppred_busy = io_wakeup_ports_4_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_ppred_busy = io_wakeup_ports_4_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_ppred_busy = io_wakeup_ports_4_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_ppred_busy = io_wakeup_ports_4_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_ppred_busy = io_wakeup_ports_4_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_ppred_busy = io_wakeup_ports_4_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_ppred_busy = io_wakeup_ports_4_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_ppred_busy = io_wakeup_ports_4_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_ppred_busy = io_wakeup_ports_4_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_ppred_busy = io_wakeup_ports_4_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_ppred_busy = io_wakeup_ports_4_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_ppred_busy = io_wakeup_ports_4_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_4_bits_uop_stale_pdst = io_wakeup_ports_4_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_4_bits_uop_stale_pdst = io_wakeup_ports_4_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_4_bits_uop_stale_pdst = io_wakeup_ports_4_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_4_bits_uop_stale_pdst = io_wakeup_ports_4_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_4_bits_uop_stale_pdst = io_wakeup_ports_4_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_4_bits_uop_stale_pdst = io_wakeup_ports_4_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_4_bits_uop_stale_pdst = io_wakeup_ports_4_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_4_bits_uop_stale_pdst = io_wakeup_ports_4_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_4_bits_uop_stale_pdst = io_wakeup_ports_4_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_4_bits_uop_stale_pdst = io_wakeup_ports_4_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_4_bits_uop_stale_pdst = io_wakeup_ports_4_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_4_bits_uop_stale_pdst = io_wakeup_ports_4_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_4_bits_uop_stale_pdst = io_wakeup_ports_4_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_4_bits_uop_stale_pdst = io_wakeup_ports_4_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_4_bits_uop_stale_pdst = io_wakeup_ports_4_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_4_bits_uop_stale_pdst = io_wakeup_ports_4_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_exception = io_wakeup_ports_4_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_exception = io_wakeup_ports_4_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_exception = io_wakeup_ports_4_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_exception = io_wakeup_ports_4_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_exception = io_wakeup_ports_4_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_exception = io_wakeup_ports_4_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_exception = io_wakeup_ports_4_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_exception = io_wakeup_ports_4_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_exception = io_wakeup_ports_4_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_exception = io_wakeup_ports_4_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_exception = io_wakeup_ports_4_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_exception = io_wakeup_ports_4_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_exception = io_wakeup_ports_4_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_exception = io_wakeup_ports_4_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_exception = io_wakeup_ports_4_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_exception = io_wakeup_ports_4_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_0_wakeup_ports_4_bits_uop_exc_cause = io_wakeup_ports_4_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_1_wakeup_ports_4_bits_uop_exc_cause = io_wakeup_ports_4_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_2_wakeup_ports_4_bits_uop_exc_cause = io_wakeup_ports_4_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_3_wakeup_ports_4_bits_uop_exc_cause = io_wakeup_ports_4_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_4_wakeup_ports_4_bits_uop_exc_cause = io_wakeup_ports_4_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_5_wakeup_ports_4_bits_uop_exc_cause = io_wakeup_ports_4_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_6_wakeup_ports_4_bits_uop_exc_cause = io_wakeup_ports_4_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_7_wakeup_ports_4_bits_uop_exc_cause = io_wakeup_ports_4_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_8_wakeup_ports_4_bits_uop_exc_cause = io_wakeup_ports_4_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_9_wakeup_ports_4_bits_uop_exc_cause = io_wakeup_ports_4_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_10_wakeup_ports_4_bits_uop_exc_cause = io_wakeup_ports_4_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_11_wakeup_ports_4_bits_uop_exc_cause = io_wakeup_ports_4_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_12_wakeup_ports_4_bits_uop_exc_cause = io_wakeup_ports_4_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_13_wakeup_ports_4_bits_uop_exc_cause = io_wakeup_ports_4_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_14_wakeup_ports_4_bits_uop_exc_cause = io_wakeup_ports_4_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_15_wakeup_ports_4_bits_uop_exc_cause = io_wakeup_ports_4_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_4_bits_uop_mem_cmd = io_wakeup_ports_4_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_4_bits_uop_mem_cmd = io_wakeup_ports_4_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_4_bits_uop_mem_cmd = io_wakeup_ports_4_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_4_bits_uop_mem_cmd = io_wakeup_ports_4_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_4_bits_uop_mem_cmd = io_wakeup_ports_4_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_4_bits_uop_mem_cmd = io_wakeup_ports_4_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_4_bits_uop_mem_cmd = io_wakeup_ports_4_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_4_bits_uop_mem_cmd = io_wakeup_ports_4_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_4_bits_uop_mem_cmd = io_wakeup_ports_4_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_4_bits_uop_mem_cmd = io_wakeup_ports_4_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_4_bits_uop_mem_cmd = io_wakeup_ports_4_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_4_bits_uop_mem_cmd = io_wakeup_ports_4_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_4_bits_uop_mem_cmd = io_wakeup_ports_4_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_4_bits_uop_mem_cmd = io_wakeup_ports_4_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_4_bits_uop_mem_cmd = io_wakeup_ports_4_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_4_bits_uop_mem_cmd = io_wakeup_ports_4_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_4_bits_uop_mem_size = io_wakeup_ports_4_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_4_bits_uop_mem_size = io_wakeup_ports_4_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_4_bits_uop_mem_size = io_wakeup_ports_4_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_4_bits_uop_mem_size = io_wakeup_ports_4_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_4_bits_uop_mem_size = io_wakeup_ports_4_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_4_bits_uop_mem_size = io_wakeup_ports_4_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_4_bits_uop_mem_size = io_wakeup_ports_4_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_4_bits_uop_mem_size = io_wakeup_ports_4_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_4_bits_uop_mem_size = io_wakeup_ports_4_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_4_bits_uop_mem_size = io_wakeup_ports_4_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_4_bits_uop_mem_size = io_wakeup_ports_4_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_4_bits_uop_mem_size = io_wakeup_ports_4_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_4_bits_uop_mem_size = io_wakeup_ports_4_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_4_bits_uop_mem_size = io_wakeup_ports_4_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_4_bits_uop_mem_size = io_wakeup_ports_4_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_4_bits_uop_mem_size = io_wakeup_ports_4_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_mem_signed = io_wakeup_ports_4_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_mem_signed = io_wakeup_ports_4_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_mem_signed = io_wakeup_ports_4_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_mem_signed = io_wakeup_ports_4_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_mem_signed = io_wakeup_ports_4_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_mem_signed = io_wakeup_ports_4_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_mem_signed = io_wakeup_ports_4_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_mem_signed = io_wakeup_ports_4_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_mem_signed = io_wakeup_ports_4_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_mem_signed = io_wakeup_ports_4_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_mem_signed = io_wakeup_ports_4_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_mem_signed = io_wakeup_ports_4_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_mem_signed = io_wakeup_ports_4_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_mem_signed = io_wakeup_ports_4_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_mem_signed = io_wakeup_ports_4_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_mem_signed = io_wakeup_ports_4_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_uses_ldq = io_wakeup_ports_4_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_uses_ldq = io_wakeup_ports_4_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_uses_ldq = io_wakeup_ports_4_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_uses_ldq = io_wakeup_ports_4_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_uses_ldq = io_wakeup_ports_4_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_uses_ldq = io_wakeup_ports_4_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_uses_ldq = io_wakeup_ports_4_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_uses_ldq = io_wakeup_ports_4_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_uses_ldq = io_wakeup_ports_4_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_uses_ldq = io_wakeup_ports_4_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_uses_ldq = io_wakeup_ports_4_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_uses_ldq = io_wakeup_ports_4_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_uses_ldq = io_wakeup_ports_4_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_uses_ldq = io_wakeup_ports_4_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_uses_ldq = io_wakeup_ports_4_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_uses_ldq = io_wakeup_ports_4_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_uses_stq = io_wakeup_ports_4_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_uses_stq = io_wakeup_ports_4_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_uses_stq = io_wakeup_ports_4_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_uses_stq = io_wakeup_ports_4_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_uses_stq = io_wakeup_ports_4_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_uses_stq = io_wakeup_ports_4_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_uses_stq = io_wakeup_ports_4_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_uses_stq = io_wakeup_ports_4_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_uses_stq = io_wakeup_ports_4_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_uses_stq = io_wakeup_ports_4_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_uses_stq = io_wakeup_ports_4_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_uses_stq = io_wakeup_ports_4_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_uses_stq = io_wakeup_ports_4_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_uses_stq = io_wakeup_ports_4_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_uses_stq = io_wakeup_ports_4_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_uses_stq = io_wakeup_ports_4_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_is_unique = io_wakeup_ports_4_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_is_unique = io_wakeup_ports_4_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_is_unique = io_wakeup_ports_4_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_is_unique = io_wakeup_ports_4_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_is_unique = io_wakeup_ports_4_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_is_unique = io_wakeup_ports_4_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_is_unique = io_wakeup_ports_4_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_is_unique = io_wakeup_ports_4_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_is_unique = io_wakeup_ports_4_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_is_unique = io_wakeup_ports_4_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_is_unique = io_wakeup_ports_4_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_is_unique = io_wakeup_ports_4_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_is_unique = io_wakeup_ports_4_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_is_unique = io_wakeup_ports_4_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_is_unique = io_wakeup_ports_4_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_is_unique = io_wakeup_ports_4_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_flush_on_commit = io_wakeup_ports_4_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_flush_on_commit = io_wakeup_ports_4_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_flush_on_commit = io_wakeup_ports_4_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_flush_on_commit = io_wakeup_ports_4_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_flush_on_commit = io_wakeup_ports_4_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_flush_on_commit = io_wakeup_ports_4_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_flush_on_commit = io_wakeup_ports_4_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_flush_on_commit = io_wakeup_ports_4_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_flush_on_commit = io_wakeup_ports_4_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_flush_on_commit = io_wakeup_ports_4_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_flush_on_commit = io_wakeup_ports_4_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_flush_on_commit = io_wakeup_ports_4_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_flush_on_commit = io_wakeup_ports_4_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_flush_on_commit = io_wakeup_ports_4_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_flush_on_commit = io_wakeup_ports_4_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_flush_on_commit = io_wakeup_ports_4_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_4_bits_uop_csr_cmd = io_wakeup_ports_4_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_4_bits_uop_csr_cmd = io_wakeup_ports_4_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_4_bits_uop_csr_cmd = io_wakeup_ports_4_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_4_bits_uop_csr_cmd = io_wakeup_ports_4_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_4_bits_uop_csr_cmd = io_wakeup_ports_4_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_4_bits_uop_csr_cmd = io_wakeup_ports_4_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_4_bits_uop_csr_cmd = io_wakeup_ports_4_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_4_bits_uop_csr_cmd = io_wakeup_ports_4_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_4_bits_uop_csr_cmd = io_wakeup_ports_4_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_4_bits_uop_csr_cmd = io_wakeup_ports_4_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_4_bits_uop_csr_cmd = io_wakeup_ports_4_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_4_bits_uop_csr_cmd = io_wakeup_ports_4_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_4_bits_uop_csr_cmd = io_wakeup_ports_4_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_4_bits_uop_csr_cmd = io_wakeup_ports_4_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_4_bits_uop_csr_cmd = io_wakeup_ports_4_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_4_bits_uop_csr_cmd = io_wakeup_ports_4_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_ldst_is_rs1 = io_wakeup_ports_4_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_ldst_is_rs1 = io_wakeup_ports_4_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_ldst_is_rs1 = io_wakeup_ports_4_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_ldst_is_rs1 = io_wakeup_ports_4_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_ldst_is_rs1 = io_wakeup_ports_4_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_ldst_is_rs1 = io_wakeup_ports_4_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_ldst_is_rs1 = io_wakeup_ports_4_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_ldst_is_rs1 = io_wakeup_ports_4_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_ldst_is_rs1 = io_wakeup_ports_4_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_ldst_is_rs1 = io_wakeup_ports_4_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_ldst_is_rs1 = io_wakeup_ports_4_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_ldst_is_rs1 = io_wakeup_ports_4_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_ldst_is_rs1 = io_wakeup_ports_4_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_ldst_is_rs1 = io_wakeup_ports_4_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_ldst_is_rs1 = io_wakeup_ports_4_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_ldst_is_rs1 = io_wakeup_ports_4_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_4_bits_uop_ldst = io_wakeup_ports_4_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_4_bits_uop_ldst = io_wakeup_ports_4_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_4_bits_uop_ldst = io_wakeup_ports_4_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_4_bits_uop_ldst = io_wakeup_ports_4_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_4_bits_uop_ldst = io_wakeup_ports_4_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_4_bits_uop_ldst = io_wakeup_ports_4_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_4_bits_uop_ldst = io_wakeup_ports_4_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_4_bits_uop_ldst = io_wakeup_ports_4_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_4_bits_uop_ldst = io_wakeup_ports_4_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_4_bits_uop_ldst = io_wakeup_ports_4_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_4_bits_uop_ldst = io_wakeup_ports_4_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_4_bits_uop_ldst = io_wakeup_ports_4_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_4_bits_uop_ldst = io_wakeup_ports_4_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_4_bits_uop_ldst = io_wakeup_ports_4_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_4_bits_uop_ldst = io_wakeup_ports_4_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_4_bits_uop_ldst = io_wakeup_ports_4_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_4_bits_uop_lrs1 = io_wakeup_ports_4_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_4_bits_uop_lrs1 = io_wakeup_ports_4_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_4_bits_uop_lrs1 = io_wakeup_ports_4_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_4_bits_uop_lrs1 = io_wakeup_ports_4_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_4_bits_uop_lrs1 = io_wakeup_ports_4_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_4_bits_uop_lrs1 = io_wakeup_ports_4_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_4_bits_uop_lrs1 = io_wakeup_ports_4_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_4_bits_uop_lrs1 = io_wakeup_ports_4_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_4_bits_uop_lrs1 = io_wakeup_ports_4_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_4_bits_uop_lrs1 = io_wakeup_ports_4_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_4_bits_uop_lrs1 = io_wakeup_ports_4_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_4_bits_uop_lrs1 = io_wakeup_ports_4_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_4_bits_uop_lrs1 = io_wakeup_ports_4_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_4_bits_uop_lrs1 = io_wakeup_ports_4_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_4_bits_uop_lrs1 = io_wakeup_ports_4_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_4_bits_uop_lrs1 = io_wakeup_ports_4_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_4_bits_uop_lrs2 = io_wakeup_ports_4_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_4_bits_uop_lrs2 = io_wakeup_ports_4_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_4_bits_uop_lrs2 = io_wakeup_ports_4_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_4_bits_uop_lrs2 = io_wakeup_ports_4_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_4_bits_uop_lrs2 = io_wakeup_ports_4_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_4_bits_uop_lrs2 = io_wakeup_ports_4_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_4_bits_uop_lrs2 = io_wakeup_ports_4_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_4_bits_uop_lrs2 = io_wakeup_ports_4_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_4_bits_uop_lrs2 = io_wakeup_ports_4_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_4_bits_uop_lrs2 = io_wakeup_ports_4_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_4_bits_uop_lrs2 = io_wakeup_ports_4_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_4_bits_uop_lrs2 = io_wakeup_ports_4_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_4_bits_uop_lrs2 = io_wakeup_ports_4_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_4_bits_uop_lrs2 = io_wakeup_ports_4_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_4_bits_uop_lrs2 = io_wakeup_ports_4_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_4_bits_uop_lrs2 = io_wakeup_ports_4_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_4_bits_uop_lrs3 = io_wakeup_ports_4_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_4_bits_uop_lrs3 = io_wakeup_ports_4_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_4_bits_uop_lrs3 = io_wakeup_ports_4_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_4_bits_uop_lrs3 = io_wakeup_ports_4_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_4_bits_uop_lrs3 = io_wakeup_ports_4_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_4_bits_uop_lrs3 = io_wakeup_ports_4_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_4_bits_uop_lrs3 = io_wakeup_ports_4_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_4_bits_uop_lrs3 = io_wakeup_ports_4_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_4_bits_uop_lrs3 = io_wakeup_ports_4_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_4_bits_uop_lrs3 = io_wakeup_ports_4_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_4_bits_uop_lrs3 = io_wakeup_ports_4_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_4_bits_uop_lrs3 = io_wakeup_ports_4_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_4_bits_uop_lrs3 = io_wakeup_ports_4_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_4_bits_uop_lrs3 = io_wakeup_ports_4_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_4_bits_uop_lrs3 = io_wakeup_ports_4_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_4_bits_uop_lrs3 = io_wakeup_ports_4_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_4_bits_uop_dst_rtype = io_wakeup_ports_4_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_4_bits_uop_dst_rtype = io_wakeup_ports_4_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_4_bits_uop_dst_rtype = io_wakeup_ports_4_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_4_bits_uop_dst_rtype = io_wakeup_ports_4_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_4_bits_uop_dst_rtype = io_wakeup_ports_4_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_4_bits_uop_dst_rtype = io_wakeup_ports_4_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_4_bits_uop_dst_rtype = io_wakeup_ports_4_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_4_bits_uop_dst_rtype = io_wakeup_ports_4_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_4_bits_uop_dst_rtype = io_wakeup_ports_4_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_4_bits_uop_dst_rtype = io_wakeup_ports_4_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_4_bits_uop_dst_rtype = io_wakeup_ports_4_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_4_bits_uop_dst_rtype = io_wakeup_ports_4_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_4_bits_uop_dst_rtype = io_wakeup_ports_4_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_4_bits_uop_dst_rtype = io_wakeup_ports_4_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_4_bits_uop_dst_rtype = io_wakeup_ports_4_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_4_bits_uop_dst_rtype = io_wakeup_ports_4_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_4_bits_uop_lrs1_rtype = io_wakeup_ports_4_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_4_bits_uop_lrs1_rtype = io_wakeup_ports_4_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_4_bits_uop_lrs1_rtype = io_wakeup_ports_4_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_4_bits_uop_lrs1_rtype = io_wakeup_ports_4_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_4_bits_uop_lrs1_rtype = io_wakeup_ports_4_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_4_bits_uop_lrs1_rtype = io_wakeup_ports_4_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_4_bits_uop_lrs1_rtype = io_wakeup_ports_4_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_4_bits_uop_lrs1_rtype = io_wakeup_ports_4_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_4_bits_uop_lrs1_rtype = io_wakeup_ports_4_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_4_bits_uop_lrs1_rtype = io_wakeup_ports_4_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_4_bits_uop_lrs1_rtype = io_wakeup_ports_4_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_4_bits_uop_lrs1_rtype = io_wakeup_ports_4_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_4_bits_uop_lrs1_rtype = io_wakeup_ports_4_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_4_bits_uop_lrs1_rtype = io_wakeup_ports_4_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_4_bits_uop_lrs1_rtype = io_wakeup_ports_4_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_4_bits_uop_lrs1_rtype = io_wakeup_ports_4_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_4_bits_uop_lrs2_rtype = io_wakeup_ports_4_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_4_bits_uop_lrs2_rtype = io_wakeup_ports_4_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_4_bits_uop_lrs2_rtype = io_wakeup_ports_4_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_4_bits_uop_lrs2_rtype = io_wakeup_ports_4_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_4_bits_uop_lrs2_rtype = io_wakeup_ports_4_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_4_bits_uop_lrs2_rtype = io_wakeup_ports_4_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_4_bits_uop_lrs2_rtype = io_wakeup_ports_4_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_4_bits_uop_lrs2_rtype = io_wakeup_ports_4_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_4_bits_uop_lrs2_rtype = io_wakeup_ports_4_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_4_bits_uop_lrs2_rtype = io_wakeup_ports_4_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_4_bits_uop_lrs2_rtype = io_wakeup_ports_4_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_4_bits_uop_lrs2_rtype = io_wakeup_ports_4_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_4_bits_uop_lrs2_rtype = io_wakeup_ports_4_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_4_bits_uop_lrs2_rtype = io_wakeup_ports_4_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_4_bits_uop_lrs2_rtype = io_wakeup_ports_4_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_4_bits_uop_lrs2_rtype = io_wakeup_ports_4_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_frs3_en = io_wakeup_ports_4_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_frs3_en = io_wakeup_ports_4_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_frs3_en = io_wakeup_ports_4_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_frs3_en = io_wakeup_ports_4_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_frs3_en = io_wakeup_ports_4_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_frs3_en = io_wakeup_ports_4_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_frs3_en = io_wakeup_ports_4_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_frs3_en = io_wakeup_ports_4_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_frs3_en = io_wakeup_ports_4_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_frs3_en = io_wakeup_ports_4_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_frs3_en = io_wakeup_ports_4_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_frs3_en = io_wakeup_ports_4_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_frs3_en = io_wakeup_ports_4_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_frs3_en = io_wakeup_ports_4_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_frs3_en = io_wakeup_ports_4_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_frs3_en = io_wakeup_ports_4_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fcn_dw = io_wakeup_ports_4_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fcn_dw = io_wakeup_ports_4_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fcn_dw = io_wakeup_ports_4_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fcn_dw = io_wakeup_ports_4_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fcn_dw = io_wakeup_ports_4_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fcn_dw = io_wakeup_ports_4_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fcn_dw = io_wakeup_ports_4_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fcn_dw = io_wakeup_ports_4_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fcn_dw = io_wakeup_ports_4_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fcn_dw = io_wakeup_ports_4_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fcn_dw = io_wakeup_ports_4_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fcn_dw = io_wakeup_ports_4_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fcn_dw = io_wakeup_ports_4_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fcn_dw = io_wakeup_ports_4_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fcn_dw = io_wakeup_ports_4_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fcn_dw = io_wakeup_ports_4_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_4_bits_uop_fcn_op = io_wakeup_ports_4_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_4_bits_uop_fcn_op = io_wakeup_ports_4_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_4_bits_uop_fcn_op = io_wakeup_ports_4_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_4_bits_uop_fcn_op = io_wakeup_ports_4_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_4_bits_uop_fcn_op = io_wakeup_ports_4_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_4_bits_uop_fcn_op = io_wakeup_ports_4_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_4_bits_uop_fcn_op = io_wakeup_ports_4_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_4_bits_uop_fcn_op = io_wakeup_ports_4_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_4_bits_uop_fcn_op = io_wakeup_ports_4_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_4_bits_uop_fcn_op = io_wakeup_ports_4_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_4_bits_uop_fcn_op = io_wakeup_ports_4_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_4_bits_uop_fcn_op = io_wakeup_ports_4_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_4_bits_uop_fcn_op = io_wakeup_ports_4_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_4_bits_uop_fcn_op = io_wakeup_ports_4_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_4_bits_uop_fcn_op = io_wakeup_ports_4_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_4_bits_uop_fcn_op = io_wakeup_ports_4_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fp_val = io_wakeup_ports_4_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fp_val = io_wakeup_ports_4_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fp_val = io_wakeup_ports_4_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fp_val = io_wakeup_ports_4_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fp_val = io_wakeup_ports_4_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fp_val = io_wakeup_ports_4_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fp_val = io_wakeup_ports_4_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fp_val = io_wakeup_ports_4_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fp_val = io_wakeup_ports_4_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fp_val = io_wakeup_ports_4_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fp_val = io_wakeup_ports_4_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fp_val = io_wakeup_ports_4_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fp_val = io_wakeup_ports_4_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fp_val = io_wakeup_ports_4_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fp_val = io_wakeup_ports_4_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fp_val = io_wakeup_ports_4_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_4_bits_uop_fp_rm = io_wakeup_ports_4_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_4_bits_uop_fp_rm = io_wakeup_ports_4_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_4_bits_uop_fp_rm = io_wakeup_ports_4_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_4_bits_uop_fp_rm = io_wakeup_ports_4_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_4_bits_uop_fp_rm = io_wakeup_ports_4_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_4_bits_uop_fp_rm = io_wakeup_ports_4_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_4_bits_uop_fp_rm = io_wakeup_ports_4_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_4_bits_uop_fp_rm = io_wakeup_ports_4_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_4_bits_uop_fp_rm = io_wakeup_ports_4_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_4_bits_uop_fp_rm = io_wakeup_ports_4_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_4_bits_uop_fp_rm = io_wakeup_ports_4_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_4_bits_uop_fp_rm = io_wakeup_ports_4_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_4_bits_uop_fp_rm = io_wakeup_ports_4_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_4_bits_uop_fp_rm = io_wakeup_ports_4_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_4_bits_uop_fp_rm = io_wakeup_ports_4_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_4_bits_uop_fp_rm = io_wakeup_ports_4_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_4_bits_uop_fp_typ = io_wakeup_ports_4_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_4_bits_uop_fp_typ = io_wakeup_ports_4_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_4_bits_uop_fp_typ = io_wakeup_ports_4_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_4_bits_uop_fp_typ = io_wakeup_ports_4_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_4_bits_uop_fp_typ = io_wakeup_ports_4_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_4_bits_uop_fp_typ = io_wakeup_ports_4_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_4_bits_uop_fp_typ = io_wakeup_ports_4_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_4_bits_uop_fp_typ = io_wakeup_ports_4_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_4_bits_uop_fp_typ = io_wakeup_ports_4_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_4_bits_uop_fp_typ = io_wakeup_ports_4_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_4_bits_uop_fp_typ = io_wakeup_ports_4_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_4_bits_uop_fp_typ = io_wakeup_ports_4_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_4_bits_uop_fp_typ = io_wakeup_ports_4_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_4_bits_uop_fp_typ = io_wakeup_ports_4_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_4_bits_uop_fp_typ = io_wakeup_ports_4_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_4_bits_uop_fp_typ = io_wakeup_ports_4_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_xcpt_pf_if = io_wakeup_ports_4_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_xcpt_pf_if = io_wakeup_ports_4_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_xcpt_pf_if = io_wakeup_ports_4_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_xcpt_pf_if = io_wakeup_ports_4_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_xcpt_pf_if = io_wakeup_ports_4_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_xcpt_pf_if = io_wakeup_ports_4_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_xcpt_pf_if = io_wakeup_ports_4_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_xcpt_pf_if = io_wakeup_ports_4_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_xcpt_pf_if = io_wakeup_ports_4_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_xcpt_pf_if = io_wakeup_ports_4_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_xcpt_pf_if = io_wakeup_ports_4_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_xcpt_pf_if = io_wakeup_ports_4_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_xcpt_pf_if = io_wakeup_ports_4_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_xcpt_pf_if = io_wakeup_ports_4_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_xcpt_pf_if = io_wakeup_ports_4_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_xcpt_pf_if = io_wakeup_ports_4_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_xcpt_ae_if = io_wakeup_ports_4_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_xcpt_ae_if = io_wakeup_ports_4_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_xcpt_ae_if = io_wakeup_ports_4_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_xcpt_ae_if = io_wakeup_ports_4_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_xcpt_ae_if = io_wakeup_ports_4_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_xcpt_ae_if = io_wakeup_ports_4_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_xcpt_ae_if = io_wakeup_ports_4_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_xcpt_ae_if = io_wakeup_ports_4_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_xcpt_ae_if = io_wakeup_ports_4_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_xcpt_ae_if = io_wakeup_ports_4_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_xcpt_ae_if = io_wakeup_ports_4_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_xcpt_ae_if = io_wakeup_ports_4_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_xcpt_ae_if = io_wakeup_ports_4_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_xcpt_ae_if = io_wakeup_ports_4_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_xcpt_ae_if = io_wakeup_ports_4_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_xcpt_ae_if = io_wakeup_ports_4_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_xcpt_ma_if = io_wakeup_ports_4_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_xcpt_ma_if = io_wakeup_ports_4_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_xcpt_ma_if = io_wakeup_ports_4_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_xcpt_ma_if = io_wakeup_ports_4_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_xcpt_ma_if = io_wakeup_ports_4_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_xcpt_ma_if = io_wakeup_ports_4_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_xcpt_ma_if = io_wakeup_ports_4_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_xcpt_ma_if = io_wakeup_ports_4_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_xcpt_ma_if = io_wakeup_ports_4_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_xcpt_ma_if = io_wakeup_ports_4_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_xcpt_ma_if = io_wakeup_ports_4_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_xcpt_ma_if = io_wakeup_ports_4_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_xcpt_ma_if = io_wakeup_ports_4_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_xcpt_ma_if = io_wakeup_ports_4_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_xcpt_ma_if = io_wakeup_ports_4_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_xcpt_ma_if = io_wakeup_ports_4_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_bp_debug_if = io_wakeup_ports_4_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_bp_debug_if = io_wakeup_ports_4_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_bp_debug_if = io_wakeup_ports_4_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_bp_debug_if = io_wakeup_ports_4_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_bp_debug_if = io_wakeup_ports_4_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_bp_debug_if = io_wakeup_ports_4_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_bp_debug_if = io_wakeup_ports_4_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_bp_debug_if = io_wakeup_ports_4_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_bp_debug_if = io_wakeup_ports_4_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_bp_debug_if = io_wakeup_ports_4_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_bp_debug_if = io_wakeup_ports_4_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_bp_debug_if = io_wakeup_ports_4_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_bp_debug_if = io_wakeup_ports_4_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_bp_debug_if = io_wakeup_ports_4_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_bp_debug_if = io_wakeup_ports_4_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_bp_debug_if = io_wakeup_ports_4_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_bp_xcpt_if = io_wakeup_ports_4_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_bp_xcpt_if = io_wakeup_ports_4_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_bp_xcpt_if = io_wakeup_ports_4_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_bp_xcpt_if = io_wakeup_ports_4_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_bp_xcpt_if = io_wakeup_ports_4_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_bp_xcpt_if = io_wakeup_ports_4_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_bp_xcpt_if = io_wakeup_ports_4_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_bp_xcpt_if = io_wakeup_ports_4_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_bp_xcpt_if = io_wakeup_ports_4_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_bp_xcpt_if = io_wakeup_ports_4_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_bp_xcpt_if = io_wakeup_ports_4_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_bp_xcpt_if = io_wakeup_ports_4_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_bp_xcpt_if = io_wakeup_ports_4_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_bp_xcpt_if = io_wakeup_ports_4_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_bp_xcpt_if = io_wakeup_ports_4_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_bp_xcpt_if = io_wakeup_ports_4_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_4_bits_uop_debug_fsrc = io_wakeup_ports_4_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_4_bits_uop_debug_fsrc = io_wakeup_ports_4_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_4_bits_uop_debug_fsrc = io_wakeup_ports_4_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_4_bits_uop_debug_fsrc = io_wakeup_ports_4_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_4_bits_uop_debug_fsrc = io_wakeup_ports_4_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_4_bits_uop_debug_fsrc = io_wakeup_ports_4_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_4_bits_uop_debug_fsrc = io_wakeup_ports_4_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_4_bits_uop_debug_fsrc = io_wakeup_ports_4_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_4_bits_uop_debug_fsrc = io_wakeup_ports_4_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_4_bits_uop_debug_fsrc = io_wakeup_ports_4_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_4_bits_uop_debug_fsrc = io_wakeup_ports_4_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_4_bits_uop_debug_fsrc = io_wakeup_ports_4_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_4_bits_uop_debug_fsrc = io_wakeup_ports_4_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_4_bits_uop_debug_fsrc = io_wakeup_ports_4_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_4_bits_uop_debug_fsrc = io_wakeup_ports_4_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_4_bits_uop_debug_fsrc = io_wakeup_ports_4_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_4_bits_uop_debug_tsrc = io_wakeup_ports_4_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_4_bits_uop_debug_tsrc = io_wakeup_ports_4_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_4_bits_uop_debug_tsrc = io_wakeup_ports_4_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_4_bits_uop_debug_tsrc = io_wakeup_ports_4_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_4_bits_uop_debug_tsrc = io_wakeup_ports_4_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_4_bits_uop_debug_tsrc = io_wakeup_ports_4_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_4_bits_uop_debug_tsrc = io_wakeup_ports_4_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_4_bits_uop_debug_tsrc = io_wakeup_ports_4_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_4_bits_uop_debug_tsrc = io_wakeup_ports_4_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_4_bits_uop_debug_tsrc = io_wakeup_ports_4_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_4_bits_uop_debug_tsrc = io_wakeup_ports_4_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_4_bits_uop_debug_tsrc = io_wakeup_ports_4_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_4_bits_uop_debug_tsrc = io_wakeup_ports_4_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_4_bits_uop_debug_tsrc = io_wakeup_ports_4_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_4_bits_uop_debug_tsrc = io_wakeup_ports_4_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_4_bits_uop_debug_tsrc = io_wakeup_ports_4_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_0_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_1_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_2_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_3_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_4_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_5_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_6_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_7_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_8_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_9_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_10_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_11_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_12_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_13_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_14_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_15_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_0_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_1_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_2_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_3_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_4_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_5_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_6_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_7_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_8_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_9_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_10_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_11_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_12_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_13_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_14_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_15_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_0_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_1_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_2_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_3_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_4_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_5_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_6_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_7_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_8_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_9_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_10_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_11_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_12_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_13_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_14_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_15_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_0_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_1_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_2_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_3_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_4_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_5_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_6_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_7_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_8_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_9_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_10_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_11_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_12_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_13_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_14_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_15_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_0_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_1_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_2_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_3_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_4_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_5_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_6_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_7_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_8_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_9_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_10_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_11_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_12_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_13_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_14_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_15_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_0_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_1_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_2_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_3_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_4_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_5_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_6_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_7_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_8_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_9_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_10_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_11_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_12_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_13_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_14_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_15_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_12_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_13_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_14_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_15_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_12_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_13_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_14_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_15_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_0_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_1_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_2_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_3_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_4_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_5_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_6_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_7_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_8_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_9_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_10_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_11_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_12_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_13_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_14_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_15_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_0_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_1_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_2_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_3_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_4_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_5_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_6_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_7_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_8_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_9_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_10_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_11_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_12_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_13_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_14_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_15_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_0_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_1_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_2_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_3_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_4_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_5_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_6_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_7_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_8_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_9_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_10_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_11_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_12_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_13_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_14_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_15_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_0_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_1_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_2_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_3_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_4_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_5_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_6_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_7_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_8_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_9_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_10_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_11_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_12_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_13_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_14_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_15_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire io_dis_uops_0_ready_0; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_ready_0; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_ready_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_iss_uops_0_bits_inst_0; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_iss_uops_0_bits_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7] wire [39:0] io_iss_uops_0_bits_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_iss_uops_0_bits_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_iss_uops_0_bits_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_iss_uops_0_bits_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7] wire [15:0] io_iss_uops_0_bits_br_mask_0; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_iss_uops_0_bits_br_tag_0; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_iss_uops_0_bits_br_type_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_fence_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_amo_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_eret_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_mov_0; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_iss_uops_0_bits_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_iss_uops_0_bits_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_taken_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_iss_uops_0_bits_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_iss_uops_0_bits_pimm_0; // @[issue-unit-age-ordered.scala:22:7] wire [19:0] io_iss_uops_0_bits_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_iss_uops_0_bits_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_iss_uops_0_bits_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_iss_uops_0_bits_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_iss_uops_0_bits_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_iss_uops_0_bits_pdst_0; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_iss_uops_0_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_iss_uops_0_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_iss_uops_0_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_iss_uops_0_bits_ppred_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_iss_uops_0_bits_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_exception_0; // @[issue-unit-age-ordered.scala:22:7] wire [63:0] io_iss_uops_0_bits_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_iss_uops_0_bits_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_mem_size_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_unique_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_iss_uops_0_bits_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_iss_uops_0_bits_ldst_0; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_iss_uops_0_bits_lrs1_0; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_iss_uops_0_bits_lrs2_0; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_iss_uops_0_bits_lrs3_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_iss_uops_0_bits_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_val_0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_iss_uops_0_bits_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_iss_uops_0_bits_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_iss_uops_0_bits_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_valid_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_1_bits_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_1_bits_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_iss_uops_1_bits_inst_0; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_iss_uops_1_bits_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7] wire [39:0] io_iss_uops_1_bits_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_iss_uops_1_bits_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_iss_uops_1_bits_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_iss_uops_1_bits_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7] wire [15:0] io_iss_uops_1_bits_br_mask_0; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_iss_uops_1_bits_br_tag_0; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_iss_uops_1_bits_br_type_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_is_fence_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_is_amo_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_is_eret_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_is_mov_0; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_iss_uops_1_bits_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_iss_uops_1_bits_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_taken_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_iss_uops_1_bits_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_iss_uops_1_bits_pimm_0; // @[issue-unit-age-ordered.scala:22:7] wire [19:0] io_iss_uops_1_bits_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_1_bits_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_iss_uops_1_bits_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_iss_uops_1_bits_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_iss_uops_1_bits_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_iss_uops_1_bits_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_1_bits_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_iss_uops_1_bits_pdst_0; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_iss_uops_1_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_iss_uops_1_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_iss_uops_1_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_iss_uops_1_bits_ppred_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_iss_uops_1_bits_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_exception_0; // @[issue-unit-age-ordered.scala:22:7] wire [63:0] io_iss_uops_1_bits_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_iss_uops_1_bits_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_1_bits_mem_size_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_is_unique_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_iss_uops_1_bits_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_iss_uops_1_bits_ldst_0; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_iss_uops_1_bits_lrs1_0; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_iss_uops_1_bits_lrs2_0; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_iss_uops_1_bits_lrs3_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_1_bits_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_1_bits_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_iss_uops_1_bits_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_fp_val_0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_iss_uops_1_bits_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_1_bits_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_bits_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_iss_uops_1_bits_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_iss_uops_1_bits_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_1_valid_0; // @[issue-unit-age-ordered.scala:22:7] wire prs1_matches_0 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_0_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs1_matches_1 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_0_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs1_matches_2 = io_wakeup_ports_2_bits_uop_pdst_0 == io_dis_uops_0_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs1_matches_3 = io_wakeup_ports_3_bits_uop_pdst_0 == io_dis_uops_0_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs1_matches_4 = io_wakeup_ports_4_bits_uop_pdst_0 == io_dis_uops_0_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs2_matches_0 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_0_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs2_matches_1 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_0_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs2_matches_2 = io_wakeup_ports_2_bits_uop_pdst_0 == io_dis_uops_0_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs2_matches_3 = io_wakeup_ports_3_bits_uop_pdst_0 == io_dis_uops_0_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs2_matches_4 = io_wakeup_ports_4_bits_uop_pdst_0 == io_dis_uops_0_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs3_matches_0 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_0_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs3_matches_1 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_0_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs3_matches_2 = io_wakeup_ports_2_bits_uop_pdst_0 == io_dis_uops_0_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs3_matches_3 = io_wakeup_ports_3_bits_uop_pdst_0 == io_dis_uops_0_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs3_matches_4 = io_wakeup_ports_4_bits_uop_pdst_0 == io_dis_uops_0_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs1_wakeups_0 = io_wakeup_ports_0_valid_0 & prs1_matches_0; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs1_wakeups_1 = io_wakeup_ports_1_valid_0 & prs1_matches_1; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs1_wakeups_2 = io_wakeup_ports_2_valid_0 & prs1_matches_2; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs1_wakeups_3 = io_wakeup_ports_3_valid_0 & prs1_matches_3; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs1_wakeups_4 = io_wakeup_ports_4_valid_0 & prs1_matches_4; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs2_wakeups_0 = io_wakeup_ports_0_valid_0 & prs2_matches_0; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs2_wakeups_1 = io_wakeup_ports_1_valid_0 & prs2_matches_1; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs2_wakeups_2 = io_wakeup_ports_2_valid_0 & prs2_matches_2; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs2_wakeups_3 = io_wakeup_ports_3_valid_0 & prs2_matches_3; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs2_wakeups_4 = io_wakeup_ports_4_valid_0 & prs2_matches_4; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs3_wakeups_0 = io_wakeup_ports_0_valid_0 & prs3_matches_0; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire prs3_wakeups_1 = io_wakeup_ports_1_valid_0 & prs3_matches_1; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire prs3_wakeups_2 = io_wakeup_ports_2_valid_0 & prs3_matches_2; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire prs3_wakeups_3 = io_wakeup_ports_3_valid_0 & prs3_matches_3; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire prs3_wakeups_4 = io_wakeup_ports_4_valid_0 & prs3_matches_4; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire prs1_rebusys_0 = io_wakeup_ports_0_bits_rebusy_0 & prs1_matches_0; // @[issue-unit-age-ordered.scala:22:7, :44:69, :50:95] wire prs2_rebusys_0 = io_wakeup_ports_0_bits_rebusy_0 & prs2_matches_0; // @[issue-unit-age-ordered.scala:22:7, :45:69, :51:95] wire _T_3 = prs1_wakeups_0 | prs1_wakeups_1 | prs1_wakeups_2 | prs1_wakeups_3 | prs1_wakeups_4; // @[issue-unit-age-ordered.scala:47:89, :57:32] wire [2:0] _WIRE_iw_p1_speculative_child = _T_3 ? (prs1_wakeups_0 ? io_wakeup_ports_0_bits_speculative_mask_0 : 3'h0) | {prs1_wakeups_4, prs1_wakeups_3, prs1_wakeups_2} : io_dis_uops_0_bits_iw_p1_speculative_child_0; // @[Mux.scala:30:73] wire _WIRE_iw_p1_bypass_hint = _T_3 & (prs1_wakeups_0 & io_wakeup_ports_0_bits_bypassable_0 | prs1_wakeups_2 | prs1_wakeups_3 | prs1_wakeups_4); // @[Mux.scala:30:73] wire _WIRE_prs1_busy = (|{prs1_rebusys_0, io_child_rebusys_0 & io_dis_uops_0_bits_iw_p1_speculative_child_0}) ? io_dis_uops_0_bits_lrs1_rtype_0 == 2'h0 : ~_T_3 & io_dis_uops_0_bits_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :35:17, :50:95, :57:{32,38}, :58:29, :62:{37,59,106,116}, :63:{29,63}] wire _T_33 = prs2_wakeups_0 | prs2_wakeups_1 | prs2_wakeups_2 | prs2_wakeups_3 | prs2_wakeups_4; // @[issue-unit-age-ordered.scala:48:89, :65:32] wire [2:0] _WIRE_iw_p2_speculative_child = _T_33 ? (prs2_wakeups_0 ? io_wakeup_ports_0_bits_speculative_mask_0 : 3'h0) | {prs2_wakeups_4, prs2_wakeups_3, prs2_wakeups_2} : io_dis_uops_0_bits_iw_p2_speculative_child_0; // @[Mux.scala:30:73] wire _WIRE_iw_p2_bypass_hint = _T_33 & (prs2_wakeups_0 & io_wakeup_ports_0_bits_bypassable_0 | prs2_wakeups_2 | prs2_wakeups_3 | prs2_wakeups_4); // @[Mux.scala:30:73] wire _WIRE_iw_p3_bypass_hint = (prs3_wakeups_0 | prs3_wakeups_1 | prs3_wakeups_2 | prs3_wakeups_3 | prs3_wakeups_4) & (prs3_wakeups_0 & io_wakeup_ports_0_bits_bypassable_0 | prs3_wakeups_2 | prs3_wakeups_3 | prs3_wakeups_4); // @[Mux.scala:30:73] wire _T_76 = io_dis_uops_0_bits_uses_stq_0 & io_dis_uops_0_bits_lrs2_rtype_0 == 2'h1; // @[issue-unit-age-ordered.scala:22:7, :96:{42,76}] wire [1:0] _WIRE_lrs2_rtype = _T_76 ? 2'h2 : io_dis_uops_0_bits_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :35:17, :96:{42,88}, :97:32] wire _WIRE_prs2_busy = ~_T_76 & ((|{prs2_rebusys_0, io_child_rebusys_0 & io_dis_uops_0_bits_iw_p2_speculative_child_0}) ? io_dis_uops_0_bits_lrs2_rtype_0 == 2'h0 : ~_T_33 & io_dis_uops_0_bits_prs2_busy_0); // @[issue-unit-age-ordered.scala:22:7, :35:17, :51:95, :65:{32,38}, :66:29, :71:{37,59,106,116}, :72:{29,63}, :96:{42,88}, :98:32] wire prs1_matches_0_1 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_1_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs1_matches_1_1 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_1_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs1_matches_2_1 = io_wakeup_ports_2_bits_uop_pdst_0 == io_dis_uops_1_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs1_matches_3_1 = io_wakeup_ports_3_bits_uop_pdst_0 == io_dis_uops_1_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs1_matches_4_1 = io_wakeup_ports_4_bits_uop_pdst_0 == io_dis_uops_1_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs2_matches_0_1 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_1_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs2_matches_1_1 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_1_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs2_matches_2_1 = io_wakeup_ports_2_bits_uop_pdst_0 == io_dis_uops_1_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs2_matches_3_1 = io_wakeup_ports_3_bits_uop_pdst_0 == io_dis_uops_1_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs2_matches_4_1 = io_wakeup_ports_4_bits_uop_pdst_0 == io_dis_uops_1_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs3_matches_0_1 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_1_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs3_matches_1_1 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_1_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs3_matches_2_1 = io_wakeup_ports_2_bits_uop_pdst_0 == io_dis_uops_1_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs3_matches_3_1 = io_wakeup_ports_3_bits_uop_pdst_0 == io_dis_uops_1_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs3_matches_4_1 = io_wakeup_ports_4_bits_uop_pdst_0 == io_dis_uops_1_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs1_wakeups_0_1 = io_wakeup_ports_0_valid_0 & prs1_matches_0_1; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs1_wakeups_1_1 = io_wakeup_ports_1_valid_0 & prs1_matches_1_1; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs1_wakeups_2_1 = io_wakeup_ports_2_valid_0 & prs1_matches_2_1; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs1_wakeups_3_1 = io_wakeup_ports_3_valid_0 & prs1_matches_3_1; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs1_wakeups_4_1 = io_wakeup_ports_4_valid_0 & prs1_matches_4_1; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs2_wakeups_0_1 = io_wakeup_ports_0_valid_0 & prs2_matches_0_1; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs2_wakeups_1_1 = io_wakeup_ports_1_valid_0 & prs2_matches_1_1; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs2_wakeups_2_1 = io_wakeup_ports_2_valid_0 & prs2_matches_2_1; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs2_wakeups_3_1 = io_wakeup_ports_3_valid_0 & prs2_matches_3_1; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs2_wakeups_4_1 = io_wakeup_ports_4_valid_0 & prs2_matches_4_1; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs3_wakeups_0_1 = io_wakeup_ports_0_valid_0 & prs3_matches_0_1; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire prs3_wakeups_1_1 = io_wakeup_ports_1_valid_0 & prs3_matches_1_1; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire prs3_wakeups_2_1 = io_wakeup_ports_2_valid_0 & prs3_matches_2_1; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire prs3_wakeups_3_1 = io_wakeup_ports_3_valid_0 & prs3_matches_3_1; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire prs3_wakeups_4_1 = io_wakeup_ports_4_valid_0 & prs3_matches_4_1; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire prs1_rebusys_0_1 = io_wakeup_ports_0_bits_rebusy_0 & prs1_matches_0_1; // @[issue-unit-age-ordered.scala:22:7, :44:69, :50:95] wire prs2_rebusys_0_1 = io_wakeup_ports_0_bits_rebusy_0 & prs2_matches_0_1; // @[issue-unit-age-ordered.scala:22:7, :45:69, :51:95] wire _T_85 = prs1_wakeups_0_1 | prs1_wakeups_1_1 | prs1_wakeups_2_1 | prs1_wakeups_3_1 | prs1_wakeups_4_1; // @[issue-unit-age-ordered.scala:47:89, :57:32] wire [2:0] _WIRE_1_iw_p1_speculative_child = _T_85 ? (prs1_wakeups_0_1 ? io_wakeup_ports_0_bits_speculative_mask_0 : 3'h0) | {prs1_wakeups_4_1, prs1_wakeups_3_1, prs1_wakeups_2_1} : io_dis_uops_1_bits_iw_p1_speculative_child_0; // @[Mux.scala:30:73] wire _WIRE_1_iw_p1_bypass_hint = _T_85 & (prs1_wakeups_0_1 & io_wakeup_ports_0_bits_bypassable_0 | prs1_wakeups_2_1 | prs1_wakeups_3_1 | prs1_wakeups_4_1); // @[Mux.scala:30:73] wire _WIRE_1_prs1_busy = (|{prs1_rebusys_0_1, io_child_rebusys_0 & io_dis_uops_1_bits_iw_p1_speculative_child_0}) ? io_dis_uops_1_bits_lrs1_rtype_0 == 2'h0 : ~_T_85 & io_dis_uops_1_bits_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :35:17, :50:95, :57:{32,38}, :58:29, :62:{37,59,106,116}, :63:{29,63}] wire _T_115 = prs2_wakeups_0_1 | prs2_wakeups_1_1 | prs2_wakeups_2_1 | prs2_wakeups_3_1 | prs2_wakeups_4_1; // @[issue-unit-age-ordered.scala:48:89, :65:32] wire [2:0] _WIRE_1_iw_p2_speculative_child = _T_115 ? (prs2_wakeups_0_1 ? io_wakeup_ports_0_bits_speculative_mask_0 : 3'h0) | {prs2_wakeups_4_1, prs2_wakeups_3_1, prs2_wakeups_2_1} : io_dis_uops_1_bits_iw_p2_speculative_child_0; // @[Mux.scala:30:73] wire _WIRE_1_iw_p2_bypass_hint = _T_115 & (prs2_wakeups_0_1 & io_wakeup_ports_0_bits_bypassable_0 | prs2_wakeups_2_1 | prs2_wakeups_3_1 | prs2_wakeups_4_1); // @[Mux.scala:30:73] wire _WIRE_1_iw_p3_bypass_hint = (prs3_wakeups_0_1 | prs3_wakeups_1_1 | prs3_wakeups_2_1 | prs3_wakeups_3_1 | prs3_wakeups_4_1) & (prs3_wakeups_0_1 & io_wakeup_ports_0_bits_bypassable_0 | prs3_wakeups_2_1 | prs3_wakeups_3_1 | prs3_wakeups_4_1); // @[Mux.scala:30:73] wire _T_158 = io_dis_uops_1_bits_uses_stq_0 & io_dis_uops_1_bits_lrs2_rtype_0 == 2'h1; // @[issue-unit-age-ordered.scala:22:7, :96:{42,76}] wire [1:0] _WIRE_1_lrs2_rtype = _T_158 ? 2'h2 : io_dis_uops_1_bits_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :35:17, :96:{42,88}, :97:32] wire _WIRE_1_prs2_busy = ~_T_158 & ((|{prs2_rebusys_0_1, io_child_rebusys_0 & io_dis_uops_1_bits_iw_p2_speculative_child_0}) ? io_dis_uops_1_bits_lrs2_rtype_0 == 2'h0 : ~_T_115 & io_dis_uops_1_bits_prs2_busy_0); // @[issue-unit-age-ordered.scala:22:7, :35:17, :51:95, :65:{32,38}, :66:29, :71:{37,59,106,116}, :72:{29,63}, :96:{42,88}, :98:32] wire prs1_matches_0_2 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_2_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs1_matches_1_2 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_2_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs1_matches_2_2 = io_wakeup_ports_2_bits_uop_pdst_0 == io_dis_uops_2_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs1_matches_3_2 = io_wakeup_ports_3_bits_uop_pdst_0 == io_dis_uops_2_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs1_matches_4_2 = io_wakeup_ports_4_bits_uop_pdst_0 == io_dis_uops_2_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs2_matches_0_2 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_2_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs2_matches_1_2 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_2_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs2_matches_2_2 = io_wakeup_ports_2_bits_uop_pdst_0 == io_dis_uops_2_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs2_matches_3_2 = io_wakeup_ports_3_bits_uop_pdst_0 == io_dis_uops_2_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs2_matches_4_2 = io_wakeup_ports_4_bits_uop_pdst_0 == io_dis_uops_2_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs3_matches_0_2 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_2_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs3_matches_1_2 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_2_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs3_matches_2_2 = io_wakeup_ports_2_bits_uop_pdst_0 == io_dis_uops_2_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs3_matches_3_2 = io_wakeup_ports_3_bits_uop_pdst_0 == io_dis_uops_2_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs3_matches_4_2 = io_wakeup_ports_4_bits_uop_pdst_0 == io_dis_uops_2_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs1_wakeups_0_2 = io_wakeup_ports_0_valid_0 & prs1_matches_0_2; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs1_wakeups_1_2 = io_wakeup_ports_1_valid_0 & prs1_matches_1_2; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs1_wakeups_2_2 = io_wakeup_ports_2_valid_0 & prs1_matches_2_2; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs1_wakeups_3_2 = io_wakeup_ports_3_valid_0 & prs1_matches_3_2; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs1_wakeups_4_2 = io_wakeup_ports_4_valid_0 & prs1_matches_4_2; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs2_wakeups_0_2 = io_wakeup_ports_0_valid_0 & prs2_matches_0_2; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs2_wakeups_1_2 = io_wakeup_ports_1_valid_0 & prs2_matches_1_2; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs2_wakeups_2_2 = io_wakeup_ports_2_valid_0 & prs2_matches_2_2; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs2_wakeups_3_2 = io_wakeup_ports_3_valid_0 & prs2_matches_3_2; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs2_wakeups_4_2 = io_wakeup_ports_4_valid_0 & prs2_matches_4_2; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs3_wakeups_0_2 = io_wakeup_ports_0_valid_0 & prs3_matches_0_2; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire prs3_wakeups_1_2 = io_wakeup_ports_1_valid_0 & prs3_matches_1_2; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire prs3_wakeups_2_2 = io_wakeup_ports_2_valid_0 & prs3_matches_2_2; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire prs3_wakeups_3_2 = io_wakeup_ports_3_valid_0 & prs3_matches_3_2; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire prs3_wakeups_4_2 = io_wakeup_ports_4_valid_0 & prs3_matches_4_2; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire prs1_rebusys_0_2 = io_wakeup_ports_0_bits_rebusy_0 & prs1_matches_0_2; // @[issue-unit-age-ordered.scala:22:7, :44:69, :50:95] wire prs2_rebusys_0_2 = io_wakeup_ports_0_bits_rebusy_0 & prs2_matches_0_2; // @[issue-unit-age-ordered.scala:22:7, :45:69, :51:95] wire _T_167 = prs1_wakeups_0_2 | prs1_wakeups_1_2 | prs1_wakeups_2_2 | prs1_wakeups_3_2 | prs1_wakeups_4_2; // @[issue-unit-age-ordered.scala:47:89, :57:32] wire _T_197 = prs2_wakeups_0_2 | prs2_wakeups_1_2 | prs2_wakeups_2_2 | prs2_wakeups_3_2 | prs2_wakeups_4_2; // @[issue-unit-age-ordered.scala:48:89, :65:32] wire _T_240 = io_dis_uops_2_bits_uses_stq_0 & io_dis_uops_2_bits_lrs2_rtype_0 == 2'h1; // @[issue-unit-age-ordered.scala:22:7, :96:{42,76}] wire _fu_code_match_T_2 = issue_slots_0_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _fu_code_match_T_20 = issue_slots_0_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _fu_code_match_T_38 = issue_slots_1_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _fu_code_match_T_56 = issue_slots_1_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_1_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_74 = issue_slots_2_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _fu_code_match_T_92 = issue_slots_2_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_2_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_110 = issue_slots_3_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _fu_code_match_T_128 = issue_slots_3_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_3_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_146 = issue_slots_4_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _fu_code_match_T_164 = issue_slots_4_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_4_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_182 = issue_slots_5_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _fu_code_match_T_200 = issue_slots_5_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_5_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_218 = issue_slots_6_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _fu_code_match_T_236 = issue_slots_6_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_6_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_254 = issue_slots_7_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _fu_code_match_T_272 = issue_slots_7_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_7_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_290 = issue_slots_8_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _fu_code_match_T_308 = issue_slots_8_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_8_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_326 = issue_slots_9_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _fu_code_match_T_344 = issue_slots_9_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_9_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_362 = issue_slots_10_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _fu_code_match_T_380 = issue_slots_10_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_10_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_398 = issue_slots_11_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _fu_code_match_T_416 = issue_slots_11_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_11_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_434 = issue_slots_12_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _fu_code_match_T_452 = issue_slots_12_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_12_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_470 = issue_slots_13_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _fu_code_match_T_488 = issue_slots_13_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_13_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_506 = issue_slots_14_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _fu_code_match_T_524 = issue_slots_14_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_14_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_542 = issue_slots_15_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _fu_code_match_T_560 = issue_slots_15_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_15_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire issue_slots_0_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_0_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_0_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_0_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_0_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_0_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_0_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_0_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_0_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_0_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_0_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_0_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_0_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_0_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_0_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_0_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_0_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_0_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_0_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_0_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_0_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_0_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_0_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_0_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_0_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_1_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_1_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_1_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_1_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_1_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_1_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_1_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_1_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_1_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_1_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_1_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_1_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_1_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_1_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_1_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_1_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_1_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_1_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_1_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_1_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_1_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_1_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_1_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_1_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_2_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_2_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_2_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_2_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_2_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_2_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_2_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_2_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_2_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_2_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_2_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_2_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_2_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_2_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_2_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_2_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_2_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_2_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_2_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_2_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_2_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_2_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_2_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_2_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_3_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_3_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_3_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_3_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_3_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_3_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_3_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_3_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_3_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_3_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_3_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_3_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_3_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_3_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_3_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_3_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_3_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_3_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_3_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_3_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_3_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_3_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_3_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_3_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_4_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_4_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_4_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_4_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_4_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_4_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_4_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_4_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_4_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_4_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_4_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_4_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_4_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_4_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_4_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_4_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_4_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_4_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_4_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_4_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_4_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_4_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_4_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_4_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_5_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_5_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_5_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_5_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_5_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_5_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_5_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_5_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_5_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_5_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_5_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_5_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_5_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_5_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_5_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_5_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_5_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_5_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_5_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_5_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_5_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_5_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_5_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_5_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_6_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_6_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_6_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_6_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_6_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_6_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_6_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_6_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_6_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_6_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_6_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_6_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_6_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_6_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_6_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_6_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_6_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_6_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_6_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_6_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_6_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_6_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_6_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_6_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_7_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_7_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_7_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_7_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_7_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_7_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_7_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_7_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_7_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_7_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_7_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_7_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_7_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_7_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_7_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_7_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_7_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_7_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_7_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_7_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_7_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_7_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_7_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_7_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_8_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_8_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_8_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_8_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_8_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_8_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_8_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_8_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_8_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_8_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_8_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_8_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_8_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_8_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_8_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_8_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_8_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_8_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_8_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_8_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_8_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_8_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_8_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_8_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_9_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_9_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_9_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_9_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_9_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_9_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_9_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_9_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_9_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_9_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_9_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_9_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_9_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_9_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_9_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_9_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_9_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_9_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_9_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_9_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_9_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_9_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_9_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_9_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_10_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_10_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_10_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_10_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_10_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_10_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_10_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_10_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_10_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_10_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_10_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_10_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_10_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_10_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_10_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_10_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_10_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_10_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_10_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_10_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_10_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_10_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_10_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_10_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_11_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_11_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_11_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_11_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_11_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_11_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_11_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_11_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_11_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_11_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_11_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_11_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_11_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_11_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_11_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_11_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_11_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_11_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_11_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_11_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_11_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_11_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_11_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_11_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_12_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_12_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_12_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_12_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_12_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_12_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_12_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_12_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_12_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_12_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_12_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_12_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_12_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_12_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_12_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_12_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_12_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_12_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_12_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_12_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_12_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_12_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_12_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_12_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_13_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_13_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_13_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_13_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_13_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_13_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_13_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_13_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_13_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_13_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_13_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_13_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_13_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_13_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_13_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_13_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_13_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_13_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_13_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_13_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_13_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_13_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_13_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_13_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_14_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_14_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_14_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_14_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_14_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_14_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_14_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_14_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_14_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_14_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_14_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_14_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_14_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_14_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_14_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_14_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_14_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_14_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_14_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_14_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_14_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_14_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_14_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_14_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_15_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_15_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_15_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_15_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_15_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_15_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_15_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_15_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_15_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_15_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_15_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_15_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_15_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_15_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_15_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_15_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_15_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_15_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_15_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_15_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_15_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_15_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_15_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_15_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_clear; // @[issue-unit-age-ordered.scala:122:28] wire vacants_0 = ~issue_slots_0_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire _shamts_oh_1_T_1 = vacants_0; // @[issue-unit-age-ordered.scala:157:38, :163:29] wire _shamts_oh_1_T_4 = vacants_0; // @[issue-unit-age-ordered.scala:157:38, :165:36] wire vacants_1 = ~issue_slots_1_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_2 = ~issue_slots_2_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_3 = ~issue_slots_3_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_4 = ~issue_slots_4_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_5 = ~issue_slots_5_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_6 = ~issue_slots_6_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_7 = ~issue_slots_7_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_8 = ~issue_slots_8_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_9 = ~issue_slots_9_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_10 = ~issue_slots_10_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_11 = ~issue_slots_11_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_12 = ~issue_slots_12_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_13 = ~issue_slots_13_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_14 = ~issue_slots_14_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_15 = ~issue_slots_15_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_16 = ~io_dis_uops_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :157:82] wire vacants_17 = ~io_dis_uops_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :157:82] wire vacants_18 = ~io_dis_uops_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :157:82] wire [2:0] shamts_oh_1_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_2_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_3_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_4_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_5_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_6_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_7_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_8_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_9_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_10_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_11_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_12_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_13_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_14_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_15_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_16_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_17_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_18_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_1; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_2; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_3; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_4; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_5; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_6; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_7; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_8; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_9; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_10; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_11; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_12; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_13; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_14; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_15; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_16; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_17; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_18; // @[issue-unit-age-ordered.scala:158:23] assign shamts_oh_1 = shamts_oh_1_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] assign shamts_oh_1_next = {2'h0, _shamts_oh_1_T_1}; // @[issue-unit-age-ordered.scala:161:21, :163:{29,37}, :164:13, :165:44] assign shamts_oh_2 = shamts_oh_2_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_2_T = ~(|shamts_oh_1); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_2_T_1 = _shamts_oh_2_T & vacants_1; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_2_T_2 = shamts_oh_1[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_2_T_3 = ~_shamts_oh_2_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_2_T_4 = _shamts_oh_2_T_3 & vacants_1; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_2_next_T = {shamts_oh_1, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_2_next = _shamts_oh_2_T_1 ? 3'h1 : _shamts_oh_2_T_4 ? _shamts_oh_2_next_T[2:0] : shamts_oh_1; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_3 = shamts_oh_3_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_3_T = ~(|shamts_oh_2); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_3_T_1 = _shamts_oh_3_T & vacants_2; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_3_T_2 = shamts_oh_2[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_3_T_3 = ~_shamts_oh_3_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_3_T_4 = _shamts_oh_3_T_3 & vacants_2; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_3_next_T = {shamts_oh_2, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_3_next = _shamts_oh_3_T_1 ? 3'h1 : _shamts_oh_3_T_4 ? _shamts_oh_3_next_T[2:0] : shamts_oh_2; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_4 = shamts_oh_4_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_4_T = ~(|shamts_oh_3); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_4_T_1 = _shamts_oh_4_T & vacants_3; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_4_T_2 = shamts_oh_3[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_4_T_3 = ~_shamts_oh_4_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_4_T_4 = _shamts_oh_4_T_3 & vacants_3; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_4_next_T = {shamts_oh_3, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_4_next = _shamts_oh_4_T_1 ? 3'h1 : _shamts_oh_4_T_4 ? _shamts_oh_4_next_T[2:0] : shamts_oh_3; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_5 = shamts_oh_5_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_5_T = ~(|shamts_oh_4); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_5_T_1 = _shamts_oh_5_T & vacants_4; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_5_T_2 = shamts_oh_4[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_5_T_3 = ~_shamts_oh_5_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_5_T_4 = _shamts_oh_5_T_3 & vacants_4; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_5_next_T = {shamts_oh_4, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_5_next = _shamts_oh_5_T_1 ? 3'h1 : _shamts_oh_5_T_4 ? _shamts_oh_5_next_T[2:0] : shamts_oh_4; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_6 = shamts_oh_6_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_6_T = ~(|shamts_oh_5); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_6_T_1 = _shamts_oh_6_T & vacants_5; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_6_T_2 = shamts_oh_5[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_6_T_3 = ~_shamts_oh_6_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_6_T_4 = _shamts_oh_6_T_3 & vacants_5; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_6_next_T = {shamts_oh_5, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_6_next = _shamts_oh_6_T_1 ? 3'h1 : _shamts_oh_6_T_4 ? _shamts_oh_6_next_T[2:0] : shamts_oh_5; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_7 = shamts_oh_7_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_7_T = ~(|shamts_oh_6); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_7_T_1 = _shamts_oh_7_T & vacants_6; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_7_T_2 = shamts_oh_6[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_7_T_3 = ~_shamts_oh_7_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_7_T_4 = _shamts_oh_7_T_3 & vacants_6; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_7_next_T = {shamts_oh_6, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_7_next = _shamts_oh_7_T_1 ? 3'h1 : _shamts_oh_7_T_4 ? _shamts_oh_7_next_T[2:0] : shamts_oh_6; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_8 = shamts_oh_8_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_8_T = ~(|shamts_oh_7); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_8_T_1 = _shamts_oh_8_T & vacants_7; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_8_T_2 = shamts_oh_7[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_8_T_3 = ~_shamts_oh_8_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_8_T_4 = _shamts_oh_8_T_3 & vacants_7; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_8_next_T = {shamts_oh_7, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_8_next = _shamts_oh_8_T_1 ? 3'h1 : _shamts_oh_8_T_4 ? _shamts_oh_8_next_T[2:0] : shamts_oh_7; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_9 = shamts_oh_9_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_9_T = ~(|shamts_oh_8); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_9_T_1 = _shamts_oh_9_T & vacants_8; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_9_T_2 = shamts_oh_8[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_9_T_3 = ~_shamts_oh_9_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_9_T_4 = _shamts_oh_9_T_3 & vacants_8; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_9_next_T = {shamts_oh_8, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_9_next = _shamts_oh_9_T_1 ? 3'h1 : _shamts_oh_9_T_4 ? _shamts_oh_9_next_T[2:0] : shamts_oh_8; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_10 = shamts_oh_10_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_10_T = ~(|shamts_oh_9); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_10_T_1 = _shamts_oh_10_T & vacants_9; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_10_T_2 = shamts_oh_9[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_10_T_3 = ~_shamts_oh_10_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_10_T_4 = _shamts_oh_10_T_3 & vacants_9; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_10_next_T = {shamts_oh_9, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_10_next = _shamts_oh_10_T_1 ? 3'h1 : _shamts_oh_10_T_4 ? _shamts_oh_10_next_T[2:0] : shamts_oh_9; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_11 = shamts_oh_11_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_11_T = ~(|shamts_oh_10); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_11_T_1 = _shamts_oh_11_T & vacants_10; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_11_T_2 = shamts_oh_10[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_11_T_3 = ~_shamts_oh_11_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_11_T_4 = _shamts_oh_11_T_3 & vacants_10; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_11_next_T = {shamts_oh_10, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_11_next = _shamts_oh_11_T_1 ? 3'h1 : _shamts_oh_11_T_4 ? _shamts_oh_11_next_T[2:0] : shamts_oh_10; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_12 = shamts_oh_12_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_12_T = ~(|shamts_oh_11); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_12_T_1 = _shamts_oh_12_T & vacants_11; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_12_T_2 = shamts_oh_11[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_12_T_3 = ~_shamts_oh_12_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_12_T_4 = _shamts_oh_12_T_3 & vacants_11; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_12_next_T = {shamts_oh_11, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_12_next = _shamts_oh_12_T_1 ? 3'h1 : _shamts_oh_12_T_4 ? _shamts_oh_12_next_T[2:0] : shamts_oh_11; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_13 = shamts_oh_13_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_13_T = ~(|shamts_oh_12); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_13_T_1 = _shamts_oh_13_T & vacants_12; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_13_T_2 = shamts_oh_12[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_13_T_3 = ~_shamts_oh_13_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_13_T_4 = _shamts_oh_13_T_3 & vacants_12; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_13_next_T = {shamts_oh_12, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_13_next = _shamts_oh_13_T_1 ? 3'h1 : _shamts_oh_13_T_4 ? _shamts_oh_13_next_T[2:0] : shamts_oh_12; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_14 = shamts_oh_14_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_14_T = ~(|shamts_oh_13); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_14_T_1 = _shamts_oh_14_T & vacants_13; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_14_T_2 = shamts_oh_13[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_14_T_3 = ~_shamts_oh_14_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_14_T_4 = _shamts_oh_14_T_3 & vacants_13; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_14_next_T = {shamts_oh_13, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_14_next = _shamts_oh_14_T_1 ? 3'h1 : _shamts_oh_14_T_4 ? _shamts_oh_14_next_T[2:0] : shamts_oh_13; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_15 = shamts_oh_15_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_15_T = ~(|shamts_oh_14); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_15_T_1 = _shamts_oh_15_T & vacants_14; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_15_T_2 = shamts_oh_14[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_15_T_3 = ~_shamts_oh_15_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_15_T_4 = _shamts_oh_15_T_3 & vacants_14; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_15_next_T = {shamts_oh_14, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_15_next = _shamts_oh_15_T_1 ? 3'h1 : _shamts_oh_15_T_4 ? _shamts_oh_15_next_T[2:0] : shamts_oh_14; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_16 = shamts_oh_16_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_16_T = ~(|shamts_oh_15); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_16_T_1 = _shamts_oh_16_T & vacants_15; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_16_T_2 = shamts_oh_15[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_16_T_3 = ~_shamts_oh_16_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_16_T_4 = _shamts_oh_16_T_3 & vacants_15; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_16_next_T = {shamts_oh_15, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_16_next = _shamts_oh_16_T_1 ? 3'h1 : _shamts_oh_16_T_4 ? _shamts_oh_16_next_T[2:0] : shamts_oh_15; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_17 = shamts_oh_17_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_17_T = shamts_oh_16 == 3'h0; // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_17_T_1 = _shamts_oh_17_T & vacants_16; // @[issue-unit-age-ordered.scala:157:82, :163:{21,29}] wire _shamts_oh_17_T_2 = shamts_oh_16[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_17_T_3 = ~_shamts_oh_17_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_17_T_4 = _shamts_oh_17_T_3 & vacants_16; // @[issue-unit-age-ordered.scala:157:82, :165:{19,36}] wire [3:0] _shamts_oh_17_next_T = {shamts_oh_16, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_17_next = _shamts_oh_17_T_1 ? 3'h1 : _shamts_oh_17_T_4 ? _shamts_oh_17_next_T[2:0] : shamts_oh_16; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_18 = shamts_oh_18_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_18_T = shamts_oh_17 == 3'h0; // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_18_T_1 = _shamts_oh_18_T & vacants_17; // @[issue-unit-age-ordered.scala:157:82, :163:{21,29}] wire _shamts_oh_18_T_2 = shamts_oh_17[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_18_T_3 = ~_shamts_oh_18_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_18_T_4 = _shamts_oh_18_T_3 & vacants_17; // @[issue-unit-age-ordered.scala:157:82, :165:{19,36}] wire [3:0] _shamts_oh_18_next_T = {shamts_oh_17, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_18_next = _shamts_oh_18_T_1 ? 3'h1 : _shamts_oh_18_T_4 ? _shamts_oh_18_next_T[2:0] : shamts_oh_17; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] wire _will_be_valid_T = ~io_dis_uops_0_bits_exception_0; // @[issue-unit-age-ordered.scala:22:7, :185:57] wire _will_be_valid_T_1 = io_dis_uops_0_valid_0 & _will_be_valid_T; // @[issue-unit-age-ordered.scala:22:7, :184:77, :185:57] wire _will_be_valid_T_2 = ~io_dis_uops_0_bits_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :186:57] wire _will_be_valid_T_3 = _will_be_valid_T_1 & _will_be_valid_T_2; // @[issue-unit-age-ordered.scala:184:77, :185:80, :186:57] wire _will_be_valid_T_4 = ~io_dis_uops_0_bits_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :187:57] wire will_be_valid_16 = _will_be_valid_T_3 & _will_be_valid_T_4; // @[issue-unit-age-ordered.scala:185:80, :186:79, :187:57] wire _will_be_valid_T_5 = ~io_dis_uops_1_bits_exception_0; // @[issue-unit-age-ordered.scala:22:7, :185:57] wire _will_be_valid_T_6 = io_dis_uops_1_valid_0 & _will_be_valid_T_5; // @[issue-unit-age-ordered.scala:22:7, :184:77, :185:57] wire _will_be_valid_T_7 = ~io_dis_uops_1_bits_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :186:57] wire _will_be_valid_T_8 = _will_be_valid_T_6 & _will_be_valid_T_7; // @[issue-unit-age-ordered.scala:184:77, :185:80, :186:57] wire _will_be_valid_T_9 = ~io_dis_uops_1_bits_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :187:57] wire will_be_valid_17 = _will_be_valid_T_8 & _will_be_valid_T_9; // @[issue-unit-age-ordered.scala:185:80, :186:79, :187:57] wire _will_be_valid_T_10 = ~io_dis_uops_2_bits_exception_0; // @[issue-unit-age-ordered.scala:22:7, :185:57] wire _will_be_valid_T_11 = io_dis_uops_2_valid_0 & _will_be_valid_T_10; // @[issue-unit-age-ordered.scala:22:7, :184:77, :185:57] wire _will_be_valid_T_12 = ~io_dis_uops_2_bits_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :186:57] wire _will_be_valid_T_13 = _will_be_valid_T_11 & _will_be_valid_T_12; // @[issue-unit-age-ordered.scala:184:77, :185:80, :186:57] wire _will_be_valid_T_14 = ~io_dis_uops_2_bits_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :187:57] wire will_be_valid_18 = _will_be_valid_T_13 & _will_be_valid_T_14; // @[issue-unit-age-ordered.scala:185:80, :186:79, :187:57] wire _T_281 = shamts_oh_2 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_282 = shamts_oh_3 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_0_in_uop_valid = _T_282 ? issue_slots_3_will_be_valid : _T_281 ? issue_slots_2_will_be_valid : shamts_oh_1 == 3'h1 & issue_slots_1_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_0_in_uop_bits_debug_tsrc = _T_282 ? issue_slots_3_out_uop_debug_tsrc : _T_281 ? issue_slots_2_out_uop_debug_tsrc : issue_slots_1_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_debug_fsrc = _T_282 ? issue_slots_3_out_uop_debug_fsrc : _T_281 ? issue_slots_2_out_uop_debug_fsrc : issue_slots_1_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_bp_xcpt_if = _T_282 ? issue_slots_3_out_uop_bp_xcpt_if : _T_281 ? issue_slots_2_out_uop_bp_xcpt_if : issue_slots_1_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_bp_debug_if = _T_282 ? issue_slots_3_out_uop_bp_debug_if : _T_281 ? issue_slots_2_out_uop_bp_debug_if : issue_slots_1_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_xcpt_ma_if = _T_282 ? issue_slots_3_out_uop_xcpt_ma_if : _T_281 ? issue_slots_2_out_uop_xcpt_ma_if : issue_slots_1_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_xcpt_ae_if = _T_282 ? issue_slots_3_out_uop_xcpt_ae_if : _T_281 ? issue_slots_2_out_uop_xcpt_ae_if : issue_slots_1_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_xcpt_pf_if = _T_282 ? issue_slots_3_out_uop_xcpt_pf_if : _T_281 ? issue_slots_2_out_uop_xcpt_pf_if : issue_slots_1_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_typ = _T_282 ? issue_slots_3_out_uop_fp_typ : _T_281 ? issue_slots_2_out_uop_fp_typ : issue_slots_1_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_rm = _T_282 ? issue_slots_3_out_uop_fp_rm : _T_281 ? issue_slots_2_out_uop_fp_rm : issue_slots_1_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_val = _T_282 ? issue_slots_3_out_uop_fp_val : _T_281 ? issue_slots_2_out_uop_fp_val : issue_slots_1_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fcn_op = _T_282 ? issue_slots_3_out_uop_fcn_op : _T_281 ? issue_slots_2_out_uop_fcn_op : issue_slots_1_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fcn_dw = _T_282 ? issue_slots_3_out_uop_fcn_dw : _T_281 ? issue_slots_2_out_uop_fcn_dw : issue_slots_1_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_frs3_en = _T_282 ? issue_slots_3_out_uop_frs3_en : _T_281 ? issue_slots_2_out_uop_frs3_en : issue_slots_1_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_lrs2_rtype = _T_282 ? issue_slots_3_out_uop_lrs2_rtype : _T_281 ? issue_slots_2_out_uop_lrs2_rtype : issue_slots_1_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_lrs1_rtype = _T_282 ? issue_slots_3_out_uop_lrs1_rtype : _T_281 ? issue_slots_2_out_uop_lrs1_rtype : issue_slots_1_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_dst_rtype = _T_282 ? issue_slots_3_out_uop_dst_rtype : _T_281 ? issue_slots_2_out_uop_dst_rtype : issue_slots_1_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_lrs3 = _T_282 ? issue_slots_3_out_uop_lrs3 : _T_281 ? issue_slots_2_out_uop_lrs3 : issue_slots_1_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_lrs2 = _T_282 ? issue_slots_3_out_uop_lrs2 : _T_281 ? issue_slots_2_out_uop_lrs2 : issue_slots_1_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_lrs1 = _T_282 ? issue_slots_3_out_uop_lrs1 : _T_281 ? issue_slots_2_out_uop_lrs1 : issue_slots_1_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_ldst = _T_282 ? issue_slots_3_out_uop_ldst : _T_281 ? issue_slots_2_out_uop_ldst : issue_slots_1_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_ldst_is_rs1 = _T_282 ? issue_slots_3_out_uop_ldst_is_rs1 : _T_281 ? issue_slots_2_out_uop_ldst_is_rs1 : issue_slots_1_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_csr_cmd = _T_282 ? issue_slots_3_out_uop_csr_cmd : _T_281 ? issue_slots_2_out_uop_csr_cmd : issue_slots_1_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_flush_on_commit = _T_282 ? issue_slots_3_out_uop_flush_on_commit : _T_281 ? issue_slots_2_out_uop_flush_on_commit : issue_slots_1_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_unique = _T_282 ? issue_slots_3_out_uop_is_unique : _T_281 ? issue_slots_2_out_uop_is_unique : issue_slots_1_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_uses_stq = _T_282 ? issue_slots_3_out_uop_uses_stq : _T_281 ? issue_slots_2_out_uop_uses_stq : issue_slots_1_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_uses_ldq = _T_282 ? issue_slots_3_out_uop_uses_ldq : _T_281 ? issue_slots_2_out_uop_uses_ldq : issue_slots_1_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_mem_signed = _T_282 ? issue_slots_3_out_uop_mem_signed : _T_281 ? issue_slots_2_out_uop_mem_signed : issue_slots_1_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_mem_size = _T_282 ? issue_slots_3_out_uop_mem_size : _T_281 ? issue_slots_2_out_uop_mem_size : issue_slots_1_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_mem_cmd = _T_282 ? issue_slots_3_out_uop_mem_cmd : _T_281 ? issue_slots_2_out_uop_mem_cmd : issue_slots_1_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_exc_cause = _T_282 ? issue_slots_3_out_uop_exc_cause : _T_281 ? issue_slots_2_out_uop_exc_cause : issue_slots_1_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_exception = _T_282 ? issue_slots_3_out_uop_exception : _T_281 ? issue_slots_2_out_uop_exception : issue_slots_1_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_stale_pdst = _T_282 ? issue_slots_3_out_uop_stale_pdst : _T_281 ? issue_slots_2_out_uop_stale_pdst : issue_slots_1_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_ppred_busy = _T_282 ? issue_slots_3_out_uop_ppred_busy : _T_281 ? issue_slots_2_out_uop_ppred_busy : issue_slots_1_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_prs3_busy = _T_282 ? issue_slots_3_out_uop_prs3_busy : _T_281 ? issue_slots_2_out_uop_prs3_busy : issue_slots_1_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_prs2_busy = _T_282 ? issue_slots_3_out_uop_prs2_busy : _T_281 ? issue_slots_2_out_uop_prs2_busy : issue_slots_1_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_prs1_busy = _T_282 ? issue_slots_3_out_uop_prs1_busy : _T_281 ? issue_slots_2_out_uop_prs1_busy : issue_slots_1_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_ppred = _T_282 ? issue_slots_3_out_uop_ppred : _T_281 ? issue_slots_2_out_uop_ppred : issue_slots_1_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_prs3 = _T_282 ? issue_slots_3_out_uop_prs3 : _T_281 ? issue_slots_2_out_uop_prs3 : issue_slots_1_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_prs2 = _T_282 ? issue_slots_3_out_uop_prs2 : _T_281 ? issue_slots_2_out_uop_prs2 : issue_slots_1_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_prs1 = _T_282 ? issue_slots_3_out_uop_prs1 : _T_281 ? issue_slots_2_out_uop_prs1 : issue_slots_1_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_pdst = _T_282 ? issue_slots_3_out_uop_pdst : _T_281 ? issue_slots_2_out_uop_pdst : issue_slots_1_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_rxq_idx = _T_282 ? issue_slots_3_out_uop_rxq_idx : _T_281 ? issue_slots_2_out_uop_rxq_idx : issue_slots_1_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_stq_idx = _T_282 ? issue_slots_3_out_uop_stq_idx : _T_281 ? issue_slots_2_out_uop_stq_idx : issue_slots_1_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_ldq_idx = _T_282 ? issue_slots_3_out_uop_ldq_idx : _T_281 ? issue_slots_2_out_uop_ldq_idx : issue_slots_1_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_rob_idx = _T_282 ? issue_slots_3_out_uop_rob_idx : _T_281 ? issue_slots_2_out_uop_rob_idx : issue_slots_1_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_vec = _T_282 ? issue_slots_3_out_uop_fp_ctrl_vec : _T_281 ? issue_slots_2_out_uop_fp_ctrl_vec : issue_slots_1_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_wflags = _T_282 ? issue_slots_3_out_uop_fp_ctrl_wflags : _T_281 ? issue_slots_2_out_uop_fp_ctrl_wflags : issue_slots_1_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_sqrt = _T_282 ? issue_slots_3_out_uop_fp_ctrl_sqrt : _T_281 ? issue_slots_2_out_uop_fp_ctrl_sqrt : issue_slots_1_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_div = _T_282 ? issue_slots_3_out_uop_fp_ctrl_div : _T_281 ? issue_slots_2_out_uop_fp_ctrl_div : issue_slots_1_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_fma = _T_282 ? issue_slots_3_out_uop_fp_ctrl_fma : _T_281 ? issue_slots_2_out_uop_fp_ctrl_fma : issue_slots_1_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_fastpipe = _T_282 ? issue_slots_3_out_uop_fp_ctrl_fastpipe : _T_281 ? issue_slots_2_out_uop_fp_ctrl_fastpipe : issue_slots_1_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_toint = _T_282 ? issue_slots_3_out_uop_fp_ctrl_toint : _T_281 ? issue_slots_2_out_uop_fp_ctrl_toint : issue_slots_1_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_fromint = _T_282 ? issue_slots_3_out_uop_fp_ctrl_fromint : _T_281 ? issue_slots_2_out_uop_fp_ctrl_fromint : issue_slots_1_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_typeTagOut = _T_282 ? issue_slots_3_out_uop_fp_ctrl_typeTagOut : _T_281 ? issue_slots_2_out_uop_fp_ctrl_typeTagOut : issue_slots_1_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_typeTagIn = _T_282 ? issue_slots_3_out_uop_fp_ctrl_typeTagIn : _T_281 ? issue_slots_2_out_uop_fp_ctrl_typeTagIn : issue_slots_1_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_swap23 = _T_282 ? issue_slots_3_out_uop_fp_ctrl_swap23 : _T_281 ? issue_slots_2_out_uop_fp_ctrl_swap23 : issue_slots_1_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_swap12 = _T_282 ? issue_slots_3_out_uop_fp_ctrl_swap12 : _T_281 ? issue_slots_2_out_uop_fp_ctrl_swap12 : issue_slots_1_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_ren3 = _T_282 ? issue_slots_3_out_uop_fp_ctrl_ren3 : _T_281 ? issue_slots_2_out_uop_fp_ctrl_ren3 : issue_slots_1_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_ren2 = _T_282 ? issue_slots_3_out_uop_fp_ctrl_ren2 : _T_281 ? issue_slots_2_out_uop_fp_ctrl_ren2 : issue_slots_1_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_ren1 = _T_282 ? issue_slots_3_out_uop_fp_ctrl_ren1 : _T_281 ? issue_slots_2_out_uop_fp_ctrl_ren1 : issue_slots_1_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_wen = _T_282 ? issue_slots_3_out_uop_fp_ctrl_wen : _T_281 ? issue_slots_2_out_uop_fp_ctrl_wen : issue_slots_1_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_ldst = _T_282 ? issue_slots_3_out_uop_fp_ctrl_ldst : _T_281 ? issue_slots_2_out_uop_fp_ctrl_ldst : issue_slots_1_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_op2_sel = _T_282 ? issue_slots_3_out_uop_op2_sel : _T_281 ? issue_slots_2_out_uop_op2_sel : issue_slots_1_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_op1_sel = _T_282 ? issue_slots_3_out_uop_op1_sel : _T_281 ? issue_slots_2_out_uop_op1_sel : issue_slots_1_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_imm_packed = _T_282 ? issue_slots_3_out_uop_imm_packed : _T_281 ? issue_slots_2_out_uop_imm_packed : issue_slots_1_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_pimm = _T_282 ? issue_slots_3_out_uop_pimm : _T_281 ? issue_slots_2_out_uop_pimm : issue_slots_1_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_imm_sel = _T_282 ? issue_slots_3_out_uop_imm_sel : _T_281 ? issue_slots_2_out_uop_imm_sel : issue_slots_1_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_imm_rename = _T_282 ? issue_slots_3_out_uop_imm_rename : _T_281 ? issue_slots_2_out_uop_imm_rename : issue_slots_1_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_taken = _T_282 ? issue_slots_3_out_uop_taken : _T_281 ? issue_slots_2_out_uop_taken : issue_slots_1_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_pc_lob = _T_282 ? issue_slots_3_out_uop_pc_lob : _T_281 ? issue_slots_2_out_uop_pc_lob : issue_slots_1_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_edge_inst = _T_282 ? issue_slots_3_out_uop_edge_inst : _T_281 ? issue_slots_2_out_uop_edge_inst : issue_slots_1_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_ftq_idx = _T_282 ? issue_slots_3_out_uop_ftq_idx : _T_281 ? issue_slots_2_out_uop_ftq_idx : issue_slots_1_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_mov = _T_282 ? issue_slots_3_out_uop_is_mov : _T_281 ? issue_slots_2_out_uop_is_mov : issue_slots_1_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_rocc = _T_282 ? issue_slots_3_out_uop_is_rocc : _T_281 ? issue_slots_2_out_uop_is_rocc : issue_slots_1_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_sys_pc2epc = _T_282 ? issue_slots_3_out_uop_is_sys_pc2epc : _T_281 ? issue_slots_2_out_uop_is_sys_pc2epc : issue_slots_1_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_eret = _T_282 ? issue_slots_3_out_uop_is_eret : _T_281 ? issue_slots_2_out_uop_is_eret : issue_slots_1_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_amo = _T_282 ? issue_slots_3_out_uop_is_amo : _T_281 ? issue_slots_2_out_uop_is_amo : issue_slots_1_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_sfence = _T_282 ? issue_slots_3_out_uop_is_sfence : _T_281 ? issue_slots_2_out_uop_is_sfence : issue_slots_1_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_fencei = _T_282 ? issue_slots_3_out_uop_is_fencei : _T_281 ? issue_slots_2_out_uop_is_fencei : issue_slots_1_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_fence = _T_282 ? issue_slots_3_out_uop_is_fence : _T_281 ? issue_slots_2_out_uop_is_fence : issue_slots_1_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_sfb = _T_282 ? issue_slots_3_out_uop_is_sfb : _T_281 ? issue_slots_2_out_uop_is_sfb : issue_slots_1_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_br_type = _T_282 ? issue_slots_3_out_uop_br_type : _T_281 ? issue_slots_2_out_uop_br_type : issue_slots_1_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_br_tag = _T_282 ? issue_slots_3_out_uop_br_tag : _T_281 ? issue_slots_2_out_uop_br_tag : issue_slots_1_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_br_mask = _T_282 ? issue_slots_3_out_uop_br_mask : _T_281 ? issue_slots_2_out_uop_br_mask : issue_slots_1_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_dis_col_sel = _T_282 ? issue_slots_3_out_uop_dis_col_sel : _T_281 ? issue_slots_2_out_uop_dis_col_sel : issue_slots_1_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_iw_p3_bypass_hint = _T_282 ? issue_slots_3_out_uop_iw_p3_bypass_hint : _T_281 ? issue_slots_2_out_uop_iw_p3_bypass_hint : issue_slots_1_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_iw_p2_bypass_hint = _T_282 ? issue_slots_3_out_uop_iw_p2_bypass_hint : _T_281 ? issue_slots_2_out_uop_iw_p2_bypass_hint : issue_slots_1_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_iw_p1_bypass_hint = _T_282 ? issue_slots_3_out_uop_iw_p1_bypass_hint : _T_281 ? issue_slots_2_out_uop_iw_p1_bypass_hint : issue_slots_1_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_iw_p2_speculative_child = _T_282 ? issue_slots_3_out_uop_iw_p2_speculative_child : _T_281 ? issue_slots_2_out_uop_iw_p2_speculative_child : issue_slots_1_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_iw_p1_speculative_child = _T_282 ? issue_slots_3_out_uop_iw_p1_speculative_child : _T_281 ? issue_slots_2_out_uop_iw_p1_speculative_child : issue_slots_1_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_iw_issued_partial_dgen = _T_282 ? issue_slots_3_out_uop_iw_issued_partial_dgen : _T_281 ? issue_slots_2_out_uop_iw_issued_partial_dgen : issue_slots_1_out_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_iw_issued_partial_agen = _T_282 ? issue_slots_3_out_uop_iw_issued_partial_agen : _T_281 ? issue_slots_2_out_uop_iw_issued_partial_agen : issue_slots_1_out_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_iw_issued = _T_282 ? issue_slots_3_out_uop_iw_issued : _T_281 ? issue_slots_2_out_uop_iw_issued : issue_slots_1_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_0 = _T_282 ? issue_slots_3_out_uop_fu_code_0 : _T_281 ? issue_slots_2_out_uop_fu_code_0 : issue_slots_1_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_1 = _T_282 ? issue_slots_3_out_uop_fu_code_1 : _T_281 ? issue_slots_2_out_uop_fu_code_1 : issue_slots_1_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_2 = _T_282 ? issue_slots_3_out_uop_fu_code_2 : _T_281 ? issue_slots_2_out_uop_fu_code_2 : issue_slots_1_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_3 = _T_282 ? issue_slots_3_out_uop_fu_code_3 : _T_281 ? issue_slots_2_out_uop_fu_code_3 : issue_slots_1_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_4 = _T_282 ? issue_slots_3_out_uop_fu_code_4 : _T_281 ? issue_slots_2_out_uop_fu_code_4 : issue_slots_1_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_5 = _T_282 ? issue_slots_3_out_uop_fu_code_5 : _T_281 ? issue_slots_2_out_uop_fu_code_5 : issue_slots_1_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_6 = _T_282 ? issue_slots_3_out_uop_fu_code_6 : _T_281 ? issue_slots_2_out_uop_fu_code_6 : issue_slots_1_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_7 = _T_282 ? issue_slots_3_out_uop_fu_code_7 : _T_281 ? issue_slots_2_out_uop_fu_code_7 : issue_slots_1_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_8 = _T_282 ? issue_slots_3_out_uop_fu_code_8 : _T_281 ? issue_slots_2_out_uop_fu_code_8 : issue_slots_1_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_9 = _T_282 ? issue_slots_3_out_uop_fu_code_9 : _T_281 ? issue_slots_2_out_uop_fu_code_9 : issue_slots_1_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_iq_type_0 = _T_282 ? issue_slots_3_out_uop_iq_type_0 : _T_281 ? issue_slots_2_out_uop_iq_type_0 : issue_slots_1_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_iq_type_1 = _T_282 ? issue_slots_3_out_uop_iq_type_1 : _T_281 ? issue_slots_2_out_uop_iq_type_1 : issue_slots_1_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_iq_type_2 = _T_282 ? issue_slots_3_out_uop_iq_type_2 : _T_281 ? issue_slots_2_out_uop_iq_type_2 : issue_slots_1_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_iq_type_3 = _T_282 ? issue_slots_3_out_uop_iq_type_3 : _T_281 ? issue_slots_2_out_uop_iq_type_3 : issue_slots_1_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_debug_pc = _T_282 ? issue_slots_3_out_uop_debug_pc : _T_281 ? issue_slots_2_out_uop_debug_pc : issue_slots_1_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_rvc = _T_282 ? issue_slots_3_out_uop_is_rvc : _T_281 ? issue_slots_2_out_uop_is_rvc : issue_slots_1_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_debug_inst = _T_282 ? issue_slots_3_out_uop_debug_inst : _T_281 ? issue_slots_2_out_uop_debug_inst : issue_slots_1_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_inst = _T_282 ? issue_slots_3_out_uop_inst : _T_281 ? issue_slots_2_out_uop_inst : issue_slots_1_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] wire _T_284 = shamts_oh_3 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_285 = shamts_oh_4 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_1_in_uop_valid = _T_285 ? issue_slots_4_will_be_valid : _T_284 ? issue_slots_3_will_be_valid : shamts_oh_2 == 3'h1 & issue_slots_2_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_1_in_uop_bits_debug_tsrc = _T_285 ? issue_slots_4_out_uop_debug_tsrc : _T_284 ? issue_slots_3_out_uop_debug_tsrc : issue_slots_2_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_debug_fsrc = _T_285 ? issue_slots_4_out_uop_debug_fsrc : _T_284 ? issue_slots_3_out_uop_debug_fsrc : issue_slots_2_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_bp_xcpt_if = _T_285 ? issue_slots_4_out_uop_bp_xcpt_if : _T_284 ? issue_slots_3_out_uop_bp_xcpt_if : issue_slots_2_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_bp_debug_if = _T_285 ? issue_slots_4_out_uop_bp_debug_if : _T_284 ? issue_slots_3_out_uop_bp_debug_if : issue_slots_2_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_xcpt_ma_if = _T_285 ? issue_slots_4_out_uop_xcpt_ma_if : _T_284 ? issue_slots_3_out_uop_xcpt_ma_if : issue_slots_2_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_xcpt_ae_if = _T_285 ? issue_slots_4_out_uop_xcpt_ae_if : _T_284 ? issue_slots_3_out_uop_xcpt_ae_if : issue_slots_2_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_xcpt_pf_if = _T_285 ? issue_slots_4_out_uop_xcpt_pf_if : _T_284 ? issue_slots_3_out_uop_xcpt_pf_if : issue_slots_2_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_typ = _T_285 ? issue_slots_4_out_uop_fp_typ : _T_284 ? issue_slots_3_out_uop_fp_typ : issue_slots_2_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_rm = _T_285 ? issue_slots_4_out_uop_fp_rm : _T_284 ? issue_slots_3_out_uop_fp_rm : issue_slots_2_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_val = _T_285 ? issue_slots_4_out_uop_fp_val : _T_284 ? issue_slots_3_out_uop_fp_val : issue_slots_2_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fcn_op = _T_285 ? issue_slots_4_out_uop_fcn_op : _T_284 ? issue_slots_3_out_uop_fcn_op : issue_slots_2_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fcn_dw = _T_285 ? issue_slots_4_out_uop_fcn_dw : _T_284 ? issue_slots_3_out_uop_fcn_dw : issue_slots_2_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_frs3_en = _T_285 ? issue_slots_4_out_uop_frs3_en : _T_284 ? issue_slots_3_out_uop_frs3_en : issue_slots_2_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_lrs2_rtype = _T_285 ? issue_slots_4_out_uop_lrs2_rtype : _T_284 ? issue_slots_3_out_uop_lrs2_rtype : issue_slots_2_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_lrs1_rtype = _T_285 ? issue_slots_4_out_uop_lrs1_rtype : _T_284 ? issue_slots_3_out_uop_lrs1_rtype : issue_slots_2_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_dst_rtype = _T_285 ? issue_slots_4_out_uop_dst_rtype : _T_284 ? issue_slots_3_out_uop_dst_rtype : issue_slots_2_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_lrs3 = _T_285 ? issue_slots_4_out_uop_lrs3 : _T_284 ? issue_slots_3_out_uop_lrs3 : issue_slots_2_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_lrs2 = _T_285 ? issue_slots_4_out_uop_lrs2 : _T_284 ? issue_slots_3_out_uop_lrs2 : issue_slots_2_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_lrs1 = _T_285 ? issue_slots_4_out_uop_lrs1 : _T_284 ? issue_slots_3_out_uop_lrs1 : issue_slots_2_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_ldst = _T_285 ? issue_slots_4_out_uop_ldst : _T_284 ? issue_slots_3_out_uop_ldst : issue_slots_2_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_ldst_is_rs1 = _T_285 ? issue_slots_4_out_uop_ldst_is_rs1 : _T_284 ? issue_slots_3_out_uop_ldst_is_rs1 : issue_slots_2_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_csr_cmd = _T_285 ? issue_slots_4_out_uop_csr_cmd : _T_284 ? issue_slots_3_out_uop_csr_cmd : issue_slots_2_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_flush_on_commit = _T_285 ? issue_slots_4_out_uop_flush_on_commit : _T_284 ? issue_slots_3_out_uop_flush_on_commit : issue_slots_2_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_unique = _T_285 ? issue_slots_4_out_uop_is_unique : _T_284 ? issue_slots_3_out_uop_is_unique : issue_slots_2_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_uses_stq = _T_285 ? issue_slots_4_out_uop_uses_stq : _T_284 ? issue_slots_3_out_uop_uses_stq : issue_slots_2_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_uses_ldq = _T_285 ? issue_slots_4_out_uop_uses_ldq : _T_284 ? issue_slots_3_out_uop_uses_ldq : issue_slots_2_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_mem_signed = _T_285 ? issue_slots_4_out_uop_mem_signed : _T_284 ? issue_slots_3_out_uop_mem_signed : issue_slots_2_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_mem_size = _T_285 ? issue_slots_4_out_uop_mem_size : _T_284 ? issue_slots_3_out_uop_mem_size : issue_slots_2_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_mem_cmd = _T_285 ? issue_slots_4_out_uop_mem_cmd : _T_284 ? issue_slots_3_out_uop_mem_cmd : issue_slots_2_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_exc_cause = _T_285 ? issue_slots_4_out_uop_exc_cause : _T_284 ? issue_slots_3_out_uop_exc_cause : issue_slots_2_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_exception = _T_285 ? issue_slots_4_out_uop_exception : _T_284 ? issue_slots_3_out_uop_exception : issue_slots_2_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_stale_pdst = _T_285 ? issue_slots_4_out_uop_stale_pdst : _T_284 ? issue_slots_3_out_uop_stale_pdst : issue_slots_2_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_ppred_busy = _T_285 ? issue_slots_4_out_uop_ppred_busy : _T_284 ? issue_slots_3_out_uop_ppred_busy : issue_slots_2_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_prs3_busy = _T_285 ? issue_slots_4_out_uop_prs3_busy : _T_284 ? issue_slots_3_out_uop_prs3_busy : issue_slots_2_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_prs2_busy = _T_285 ? issue_slots_4_out_uop_prs2_busy : _T_284 ? issue_slots_3_out_uop_prs2_busy : issue_slots_2_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_prs1_busy = _T_285 ? issue_slots_4_out_uop_prs1_busy : _T_284 ? issue_slots_3_out_uop_prs1_busy : issue_slots_2_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_ppred = _T_285 ? issue_slots_4_out_uop_ppred : _T_284 ? issue_slots_3_out_uop_ppred : issue_slots_2_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_prs3 = _T_285 ? issue_slots_4_out_uop_prs3 : _T_284 ? issue_slots_3_out_uop_prs3 : issue_slots_2_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_prs2 = _T_285 ? issue_slots_4_out_uop_prs2 : _T_284 ? issue_slots_3_out_uop_prs2 : issue_slots_2_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_prs1 = _T_285 ? issue_slots_4_out_uop_prs1 : _T_284 ? issue_slots_3_out_uop_prs1 : issue_slots_2_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_pdst = _T_285 ? issue_slots_4_out_uop_pdst : _T_284 ? issue_slots_3_out_uop_pdst : issue_slots_2_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_rxq_idx = _T_285 ? issue_slots_4_out_uop_rxq_idx : _T_284 ? issue_slots_3_out_uop_rxq_idx : issue_slots_2_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_stq_idx = _T_285 ? issue_slots_4_out_uop_stq_idx : _T_284 ? issue_slots_3_out_uop_stq_idx : issue_slots_2_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_ldq_idx = _T_285 ? issue_slots_4_out_uop_ldq_idx : _T_284 ? issue_slots_3_out_uop_ldq_idx : issue_slots_2_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_rob_idx = _T_285 ? issue_slots_4_out_uop_rob_idx : _T_284 ? issue_slots_3_out_uop_rob_idx : issue_slots_2_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_vec = _T_285 ? issue_slots_4_out_uop_fp_ctrl_vec : _T_284 ? issue_slots_3_out_uop_fp_ctrl_vec : issue_slots_2_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_wflags = _T_285 ? issue_slots_4_out_uop_fp_ctrl_wflags : _T_284 ? issue_slots_3_out_uop_fp_ctrl_wflags : issue_slots_2_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_sqrt = _T_285 ? issue_slots_4_out_uop_fp_ctrl_sqrt : _T_284 ? issue_slots_3_out_uop_fp_ctrl_sqrt : issue_slots_2_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_div = _T_285 ? issue_slots_4_out_uop_fp_ctrl_div : _T_284 ? issue_slots_3_out_uop_fp_ctrl_div : issue_slots_2_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_fma = _T_285 ? issue_slots_4_out_uop_fp_ctrl_fma : _T_284 ? issue_slots_3_out_uop_fp_ctrl_fma : issue_slots_2_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_fastpipe = _T_285 ? issue_slots_4_out_uop_fp_ctrl_fastpipe : _T_284 ? issue_slots_3_out_uop_fp_ctrl_fastpipe : issue_slots_2_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_toint = _T_285 ? issue_slots_4_out_uop_fp_ctrl_toint : _T_284 ? issue_slots_3_out_uop_fp_ctrl_toint : issue_slots_2_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_fromint = _T_285 ? issue_slots_4_out_uop_fp_ctrl_fromint : _T_284 ? issue_slots_3_out_uop_fp_ctrl_fromint : issue_slots_2_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_typeTagOut = _T_285 ? issue_slots_4_out_uop_fp_ctrl_typeTagOut : _T_284 ? issue_slots_3_out_uop_fp_ctrl_typeTagOut : issue_slots_2_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_typeTagIn = _T_285 ? issue_slots_4_out_uop_fp_ctrl_typeTagIn : _T_284 ? issue_slots_3_out_uop_fp_ctrl_typeTagIn : issue_slots_2_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_swap23 = _T_285 ? issue_slots_4_out_uop_fp_ctrl_swap23 : _T_284 ? issue_slots_3_out_uop_fp_ctrl_swap23 : issue_slots_2_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_swap12 = _T_285 ? issue_slots_4_out_uop_fp_ctrl_swap12 : _T_284 ? issue_slots_3_out_uop_fp_ctrl_swap12 : issue_slots_2_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_ren3 = _T_285 ? issue_slots_4_out_uop_fp_ctrl_ren3 : _T_284 ? issue_slots_3_out_uop_fp_ctrl_ren3 : issue_slots_2_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_ren2 = _T_285 ? issue_slots_4_out_uop_fp_ctrl_ren2 : _T_284 ? issue_slots_3_out_uop_fp_ctrl_ren2 : issue_slots_2_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_ren1 = _T_285 ? issue_slots_4_out_uop_fp_ctrl_ren1 : _T_284 ? issue_slots_3_out_uop_fp_ctrl_ren1 : issue_slots_2_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_wen = _T_285 ? issue_slots_4_out_uop_fp_ctrl_wen : _T_284 ? issue_slots_3_out_uop_fp_ctrl_wen : issue_slots_2_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_ldst = _T_285 ? issue_slots_4_out_uop_fp_ctrl_ldst : _T_284 ? issue_slots_3_out_uop_fp_ctrl_ldst : issue_slots_2_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_op2_sel = _T_285 ? issue_slots_4_out_uop_op2_sel : _T_284 ? issue_slots_3_out_uop_op2_sel : issue_slots_2_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_op1_sel = _T_285 ? issue_slots_4_out_uop_op1_sel : _T_284 ? issue_slots_3_out_uop_op1_sel : issue_slots_2_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_imm_packed = _T_285 ? issue_slots_4_out_uop_imm_packed : _T_284 ? issue_slots_3_out_uop_imm_packed : issue_slots_2_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_pimm = _T_285 ? issue_slots_4_out_uop_pimm : _T_284 ? issue_slots_3_out_uop_pimm : issue_slots_2_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_imm_sel = _T_285 ? issue_slots_4_out_uop_imm_sel : _T_284 ? issue_slots_3_out_uop_imm_sel : issue_slots_2_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_imm_rename = _T_285 ? issue_slots_4_out_uop_imm_rename : _T_284 ? issue_slots_3_out_uop_imm_rename : issue_slots_2_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_taken = _T_285 ? issue_slots_4_out_uop_taken : _T_284 ? issue_slots_3_out_uop_taken : issue_slots_2_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_pc_lob = _T_285 ? issue_slots_4_out_uop_pc_lob : _T_284 ? issue_slots_3_out_uop_pc_lob : issue_slots_2_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_edge_inst = _T_285 ? issue_slots_4_out_uop_edge_inst : _T_284 ? issue_slots_3_out_uop_edge_inst : issue_slots_2_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_ftq_idx = _T_285 ? issue_slots_4_out_uop_ftq_idx : _T_284 ? issue_slots_3_out_uop_ftq_idx : issue_slots_2_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_mov = _T_285 ? issue_slots_4_out_uop_is_mov : _T_284 ? issue_slots_3_out_uop_is_mov : issue_slots_2_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_rocc = _T_285 ? issue_slots_4_out_uop_is_rocc : _T_284 ? issue_slots_3_out_uop_is_rocc : issue_slots_2_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_sys_pc2epc = _T_285 ? issue_slots_4_out_uop_is_sys_pc2epc : _T_284 ? issue_slots_3_out_uop_is_sys_pc2epc : issue_slots_2_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_eret = _T_285 ? issue_slots_4_out_uop_is_eret : _T_284 ? issue_slots_3_out_uop_is_eret : issue_slots_2_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_amo = _T_285 ? issue_slots_4_out_uop_is_amo : _T_284 ? issue_slots_3_out_uop_is_amo : issue_slots_2_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_sfence = _T_285 ? issue_slots_4_out_uop_is_sfence : _T_284 ? issue_slots_3_out_uop_is_sfence : issue_slots_2_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_fencei = _T_285 ? issue_slots_4_out_uop_is_fencei : _T_284 ? issue_slots_3_out_uop_is_fencei : issue_slots_2_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_fence = _T_285 ? issue_slots_4_out_uop_is_fence : _T_284 ? issue_slots_3_out_uop_is_fence : issue_slots_2_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_sfb = _T_285 ? issue_slots_4_out_uop_is_sfb : _T_284 ? issue_slots_3_out_uop_is_sfb : issue_slots_2_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_br_type = _T_285 ? issue_slots_4_out_uop_br_type : _T_284 ? issue_slots_3_out_uop_br_type : issue_slots_2_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_br_tag = _T_285 ? issue_slots_4_out_uop_br_tag : _T_284 ? issue_slots_3_out_uop_br_tag : issue_slots_2_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_br_mask = _T_285 ? issue_slots_4_out_uop_br_mask : _T_284 ? issue_slots_3_out_uop_br_mask : issue_slots_2_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_dis_col_sel = _T_285 ? issue_slots_4_out_uop_dis_col_sel : _T_284 ? issue_slots_3_out_uop_dis_col_sel : issue_slots_2_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_iw_p3_bypass_hint = _T_285 ? issue_slots_4_out_uop_iw_p3_bypass_hint : _T_284 ? issue_slots_3_out_uop_iw_p3_bypass_hint : issue_slots_2_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_iw_p2_bypass_hint = _T_285 ? issue_slots_4_out_uop_iw_p2_bypass_hint : _T_284 ? issue_slots_3_out_uop_iw_p2_bypass_hint : issue_slots_2_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_iw_p1_bypass_hint = _T_285 ? issue_slots_4_out_uop_iw_p1_bypass_hint : _T_284 ? issue_slots_3_out_uop_iw_p1_bypass_hint : issue_slots_2_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_iw_p2_speculative_child = _T_285 ? issue_slots_4_out_uop_iw_p2_speculative_child : _T_284 ? issue_slots_3_out_uop_iw_p2_speculative_child : issue_slots_2_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_iw_p1_speculative_child = _T_285 ? issue_slots_4_out_uop_iw_p1_speculative_child : _T_284 ? issue_slots_3_out_uop_iw_p1_speculative_child : issue_slots_2_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_iw_issued_partial_dgen = _T_285 ? issue_slots_4_out_uop_iw_issued_partial_dgen : _T_284 ? issue_slots_3_out_uop_iw_issued_partial_dgen : issue_slots_2_out_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_iw_issued_partial_agen = _T_285 ? issue_slots_4_out_uop_iw_issued_partial_agen : _T_284 ? issue_slots_3_out_uop_iw_issued_partial_agen : issue_slots_2_out_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_iw_issued = _T_285 ? issue_slots_4_out_uop_iw_issued : _T_284 ? issue_slots_3_out_uop_iw_issued : issue_slots_2_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_0 = _T_285 ? issue_slots_4_out_uop_fu_code_0 : _T_284 ? issue_slots_3_out_uop_fu_code_0 : issue_slots_2_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_1 = _T_285 ? issue_slots_4_out_uop_fu_code_1 : _T_284 ? issue_slots_3_out_uop_fu_code_1 : issue_slots_2_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_2 = _T_285 ? issue_slots_4_out_uop_fu_code_2 : _T_284 ? issue_slots_3_out_uop_fu_code_2 : issue_slots_2_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_3 = _T_285 ? issue_slots_4_out_uop_fu_code_3 : _T_284 ? issue_slots_3_out_uop_fu_code_3 : issue_slots_2_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_4 = _T_285 ? issue_slots_4_out_uop_fu_code_4 : _T_284 ? issue_slots_3_out_uop_fu_code_4 : issue_slots_2_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_5 = _T_285 ? issue_slots_4_out_uop_fu_code_5 : _T_284 ? issue_slots_3_out_uop_fu_code_5 : issue_slots_2_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_6 = _T_285 ? issue_slots_4_out_uop_fu_code_6 : _T_284 ? issue_slots_3_out_uop_fu_code_6 : issue_slots_2_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_7 = _T_285 ? issue_slots_4_out_uop_fu_code_7 : _T_284 ? issue_slots_3_out_uop_fu_code_7 : issue_slots_2_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_8 = _T_285 ? issue_slots_4_out_uop_fu_code_8 : _T_284 ? issue_slots_3_out_uop_fu_code_8 : issue_slots_2_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_9 = _T_285 ? issue_slots_4_out_uop_fu_code_9 : _T_284 ? issue_slots_3_out_uop_fu_code_9 : issue_slots_2_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_iq_type_0 = _T_285 ? issue_slots_4_out_uop_iq_type_0 : _T_284 ? issue_slots_3_out_uop_iq_type_0 : issue_slots_2_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_iq_type_1 = _T_285 ? issue_slots_4_out_uop_iq_type_1 : _T_284 ? issue_slots_3_out_uop_iq_type_1 : issue_slots_2_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_iq_type_2 = _T_285 ? issue_slots_4_out_uop_iq_type_2 : _T_284 ? issue_slots_3_out_uop_iq_type_2 : issue_slots_2_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_iq_type_3 = _T_285 ? issue_slots_4_out_uop_iq_type_3 : _T_284 ? issue_slots_3_out_uop_iq_type_3 : issue_slots_2_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_debug_pc = _T_285 ? issue_slots_4_out_uop_debug_pc : _T_284 ? issue_slots_3_out_uop_debug_pc : issue_slots_2_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_rvc = _T_285 ? issue_slots_4_out_uop_is_rvc : _T_284 ? issue_slots_3_out_uop_is_rvc : issue_slots_2_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_debug_inst = _T_285 ? issue_slots_4_out_uop_debug_inst : _T_284 ? issue_slots_3_out_uop_debug_inst : issue_slots_2_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_inst = _T_285 ? issue_slots_4_out_uop_inst : _T_284 ? issue_slots_3_out_uop_inst : issue_slots_2_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_1_clear_T = |shamts_oh_1; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_1_clear = _issue_slots_1_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_287 = shamts_oh_4 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_288 = shamts_oh_5 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_2_in_uop_valid = _T_288 ? issue_slots_5_will_be_valid : _T_287 ? issue_slots_4_will_be_valid : shamts_oh_3 == 3'h1 & issue_slots_3_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_2_in_uop_bits_debug_tsrc = _T_288 ? issue_slots_5_out_uop_debug_tsrc : _T_287 ? issue_slots_4_out_uop_debug_tsrc : issue_slots_3_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_debug_fsrc = _T_288 ? issue_slots_5_out_uop_debug_fsrc : _T_287 ? issue_slots_4_out_uop_debug_fsrc : issue_slots_3_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_bp_xcpt_if = _T_288 ? issue_slots_5_out_uop_bp_xcpt_if : _T_287 ? issue_slots_4_out_uop_bp_xcpt_if : issue_slots_3_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_bp_debug_if = _T_288 ? issue_slots_5_out_uop_bp_debug_if : _T_287 ? issue_slots_4_out_uop_bp_debug_if : issue_slots_3_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_xcpt_ma_if = _T_288 ? issue_slots_5_out_uop_xcpt_ma_if : _T_287 ? issue_slots_4_out_uop_xcpt_ma_if : issue_slots_3_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_xcpt_ae_if = _T_288 ? issue_slots_5_out_uop_xcpt_ae_if : _T_287 ? issue_slots_4_out_uop_xcpt_ae_if : issue_slots_3_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_xcpt_pf_if = _T_288 ? issue_slots_5_out_uop_xcpt_pf_if : _T_287 ? issue_slots_4_out_uop_xcpt_pf_if : issue_slots_3_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_typ = _T_288 ? issue_slots_5_out_uop_fp_typ : _T_287 ? issue_slots_4_out_uop_fp_typ : issue_slots_3_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_rm = _T_288 ? issue_slots_5_out_uop_fp_rm : _T_287 ? issue_slots_4_out_uop_fp_rm : issue_slots_3_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_val = _T_288 ? issue_slots_5_out_uop_fp_val : _T_287 ? issue_slots_4_out_uop_fp_val : issue_slots_3_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fcn_op = _T_288 ? issue_slots_5_out_uop_fcn_op : _T_287 ? issue_slots_4_out_uop_fcn_op : issue_slots_3_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fcn_dw = _T_288 ? issue_slots_5_out_uop_fcn_dw : _T_287 ? issue_slots_4_out_uop_fcn_dw : issue_slots_3_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_frs3_en = _T_288 ? issue_slots_5_out_uop_frs3_en : _T_287 ? issue_slots_4_out_uop_frs3_en : issue_slots_3_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_lrs2_rtype = _T_288 ? issue_slots_5_out_uop_lrs2_rtype : _T_287 ? issue_slots_4_out_uop_lrs2_rtype : issue_slots_3_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_lrs1_rtype = _T_288 ? issue_slots_5_out_uop_lrs1_rtype : _T_287 ? issue_slots_4_out_uop_lrs1_rtype : issue_slots_3_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_dst_rtype = _T_288 ? issue_slots_5_out_uop_dst_rtype : _T_287 ? issue_slots_4_out_uop_dst_rtype : issue_slots_3_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_lrs3 = _T_288 ? issue_slots_5_out_uop_lrs3 : _T_287 ? issue_slots_4_out_uop_lrs3 : issue_slots_3_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_lrs2 = _T_288 ? issue_slots_5_out_uop_lrs2 : _T_287 ? issue_slots_4_out_uop_lrs2 : issue_slots_3_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_lrs1 = _T_288 ? issue_slots_5_out_uop_lrs1 : _T_287 ? issue_slots_4_out_uop_lrs1 : issue_slots_3_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_ldst = _T_288 ? issue_slots_5_out_uop_ldst : _T_287 ? issue_slots_4_out_uop_ldst : issue_slots_3_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_ldst_is_rs1 = _T_288 ? issue_slots_5_out_uop_ldst_is_rs1 : _T_287 ? issue_slots_4_out_uop_ldst_is_rs1 : issue_slots_3_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_csr_cmd = _T_288 ? issue_slots_5_out_uop_csr_cmd : _T_287 ? issue_slots_4_out_uop_csr_cmd : issue_slots_3_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_flush_on_commit = _T_288 ? issue_slots_5_out_uop_flush_on_commit : _T_287 ? issue_slots_4_out_uop_flush_on_commit : issue_slots_3_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_unique = _T_288 ? issue_slots_5_out_uop_is_unique : _T_287 ? issue_slots_4_out_uop_is_unique : issue_slots_3_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_uses_stq = _T_288 ? issue_slots_5_out_uop_uses_stq : _T_287 ? issue_slots_4_out_uop_uses_stq : issue_slots_3_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_uses_ldq = _T_288 ? issue_slots_5_out_uop_uses_ldq : _T_287 ? issue_slots_4_out_uop_uses_ldq : issue_slots_3_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_mem_signed = _T_288 ? issue_slots_5_out_uop_mem_signed : _T_287 ? issue_slots_4_out_uop_mem_signed : issue_slots_3_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_mem_size = _T_288 ? issue_slots_5_out_uop_mem_size : _T_287 ? issue_slots_4_out_uop_mem_size : issue_slots_3_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_mem_cmd = _T_288 ? issue_slots_5_out_uop_mem_cmd : _T_287 ? issue_slots_4_out_uop_mem_cmd : issue_slots_3_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_exc_cause = _T_288 ? issue_slots_5_out_uop_exc_cause : _T_287 ? issue_slots_4_out_uop_exc_cause : issue_slots_3_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_exception = _T_288 ? issue_slots_5_out_uop_exception : _T_287 ? issue_slots_4_out_uop_exception : issue_slots_3_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_stale_pdst = _T_288 ? issue_slots_5_out_uop_stale_pdst : _T_287 ? issue_slots_4_out_uop_stale_pdst : issue_slots_3_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_ppred_busy = _T_288 ? issue_slots_5_out_uop_ppred_busy : _T_287 ? issue_slots_4_out_uop_ppred_busy : issue_slots_3_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_prs3_busy = _T_288 ? issue_slots_5_out_uop_prs3_busy : _T_287 ? issue_slots_4_out_uop_prs3_busy : issue_slots_3_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_prs2_busy = _T_288 ? issue_slots_5_out_uop_prs2_busy : _T_287 ? issue_slots_4_out_uop_prs2_busy : issue_slots_3_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_prs1_busy = _T_288 ? issue_slots_5_out_uop_prs1_busy : _T_287 ? issue_slots_4_out_uop_prs1_busy : issue_slots_3_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_ppred = _T_288 ? issue_slots_5_out_uop_ppred : _T_287 ? issue_slots_4_out_uop_ppred : issue_slots_3_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_prs3 = _T_288 ? issue_slots_5_out_uop_prs3 : _T_287 ? issue_slots_4_out_uop_prs3 : issue_slots_3_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_prs2 = _T_288 ? issue_slots_5_out_uop_prs2 : _T_287 ? issue_slots_4_out_uop_prs2 : issue_slots_3_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_prs1 = _T_288 ? issue_slots_5_out_uop_prs1 : _T_287 ? issue_slots_4_out_uop_prs1 : issue_slots_3_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_pdst = _T_288 ? issue_slots_5_out_uop_pdst : _T_287 ? issue_slots_4_out_uop_pdst : issue_slots_3_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_rxq_idx = _T_288 ? issue_slots_5_out_uop_rxq_idx : _T_287 ? issue_slots_4_out_uop_rxq_idx : issue_slots_3_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_stq_idx = _T_288 ? issue_slots_5_out_uop_stq_idx : _T_287 ? issue_slots_4_out_uop_stq_idx : issue_slots_3_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_ldq_idx = _T_288 ? issue_slots_5_out_uop_ldq_idx : _T_287 ? issue_slots_4_out_uop_ldq_idx : issue_slots_3_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_rob_idx = _T_288 ? issue_slots_5_out_uop_rob_idx : _T_287 ? issue_slots_4_out_uop_rob_idx : issue_slots_3_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_vec = _T_288 ? issue_slots_5_out_uop_fp_ctrl_vec : _T_287 ? issue_slots_4_out_uop_fp_ctrl_vec : issue_slots_3_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_wflags = _T_288 ? issue_slots_5_out_uop_fp_ctrl_wflags : _T_287 ? issue_slots_4_out_uop_fp_ctrl_wflags : issue_slots_3_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_sqrt = _T_288 ? issue_slots_5_out_uop_fp_ctrl_sqrt : _T_287 ? issue_slots_4_out_uop_fp_ctrl_sqrt : issue_slots_3_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_div = _T_288 ? issue_slots_5_out_uop_fp_ctrl_div : _T_287 ? issue_slots_4_out_uop_fp_ctrl_div : issue_slots_3_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_fma = _T_288 ? issue_slots_5_out_uop_fp_ctrl_fma : _T_287 ? issue_slots_4_out_uop_fp_ctrl_fma : issue_slots_3_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_fastpipe = _T_288 ? issue_slots_5_out_uop_fp_ctrl_fastpipe : _T_287 ? issue_slots_4_out_uop_fp_ctrl_fastpipe : issue_slots_3_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_toint = _T_288 ? issue_slots_5_out_uop_fp_ctrl_toint : _T_287 ? issue_slots_4_out_uop_fp_ctrl_toint : issue_slots_3_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_fromint = _T_288 ? issue_slots_5_out_uop_fp_ctrl_fromint : _T_287 ? issue_slots_4_out_uop_fp_ctrl_fromint : issue_slots_3_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_typeTagOut = _T_288 ? issue_slots_5_out_uop_fp_ctrl_typeTagOut : _T_287 ? issue_slots_4_out_uop_fp_ctrl_typeTagOut : issue_slots_3_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_typeTagIn = _T_288 ? issue_slots_5_out_uop_fp_ctrl_typeTagIn : _T_287 ? issue_slots_4_out_uop_fp_ctrl_typeTagIn : issue_slots_3_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_swap23 = _T_288 ? issue_slots_5_out_uop_fp_ctrl_swap23 : _T_287 ? issue_slots_4_out_uop_fp_ctrl_swap23 : issue_slots_3_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_swap12 = _T_288 ? issue_slots_5_out_uop_fp_ctrl_swap12 : _T_287 ? issue_slots_4_out_uop_fp_ctrl_swap12 : issue_slots_3_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_ren3 = _T_288 ? issue_slots_5_out_uop_fp_ctrl_ren3 : _T_287 ? issue_slots_4_out_uop_fp_ctrl_ren3 : issue_slots_3_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_ren2 = _T_288 ? issue_slots_5_out_uop_fp_ctrl_ren2 : _T_287 ? issue_slots_4_out_uop_fp_ctrl_ren2 : issue_slots_3_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_ren1 = _T_288 ? issue_slots_5_out_uop_fp_ctrl_ren1 : _T_287 ? issue_slots_4_out_uop_fp_ctrl_ren1 : issue_slots_3_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_wen = _T_288 ? issue_slots_5_out_uop_fp_ctrl_wen : _T_287 ? issue_slots_4_out_uop_fp_ctrl_wen : issue_slots_3_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_ldst = _T_288 ? issue_slots_5_out_uop_fp_ctrl_ldst : _T_287 ? issue_slots_4_out_uop_fp_ctrl_ldst : issue_slots_3_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_op2_sel = _T_288 ? issue_slots_5_out_uop_op2_sel : _T_287 ? issue_slots_4_out_uop_op2_sel : issue_slots_3_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_op1_sel = _T_288 ? issue_slots_5_out_uop_op1_sel : _T_287 ? issue_slots_4_out_uop_op1_sel : issue_slots_3_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_imm_packed = _T_288 ? issue_slots_5_out_uop_imm_packed : _T_287 ? issue_slots_4_out_uop_imm_packed : issue_slots_3_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_pimm = _T_288 ? issue_slots_5_out_uop_pimm : _T_287 ? issue_slots_4_out_uop_pimm : issue_slots_3_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_imm_sel = _T_288 ? issue_slots_5_out_uop_imm_sel : _T_287 ? issue_slots_4_out_uop_imm_sel : issue_slots_3_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_imm_rename = _T_288 ? issue_slots_5_out_uop_imm_rename : _T_287 ? issue_slots_4_out_uop_imm_rename : issue_slots_3_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_taken = _T_288 ? issue_slots_5_out_uop_taken : _T_287 ? issue_slots_4_out_uop_taken : issue_slots_3_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_pc_lob = _T_288 ? issue_slots_5_out_uop_pc_lob : _T_287 ? issue_slots_4_out_uop_pc_lob : issue_slots_3_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_edge_inst = _T_288 ? issue_slots_5_out_uop_edge_inst : _T_287 ? issue_slots_4_out_uop_edge_inst : issue_slots_3_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_ftq_idx = _T_288 ? issue_slots_5_out_uop_ftq_idx : _T_287 ? issue_slots_4_out_uop_ftq_idx : issue_slots_3_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_mov = _T_288 ? issue_slots_5_out_uop_is_mov : _T_287 ? issue_slots_4_out_uop_is_mov : issue_slots_3_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_rocc = _T_288 ? issue_slots_5_out_uop_is_rocc : _T_287 ? issue_slots_4_out_uop_is_rocc : issue_slots_3_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_sys_pc2epc = _T_288 ? issue_slots_5_out_uop_is_sys_pc2epc : _T_287 ? issue_slots_4_out_uop_is_sys_pc2epc : issue_slots_3_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_eret = _T_288 ? issue_slots_5_out_uop_is_eret : _T_287 ? issue_slots_4_out_uop_is_eret : issue_slots_3_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_amo = _T_288 ? issue_slots_5_out_uop_is_amo : _T_287 ? issue_slots_4_out_uop_is_amo : issue_slots_3_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_sfence = _T_288 ? issue_slots_5_out_uop_is_sfence : _T_287 ? issue_slots_4_out_uop_is_sfence : issue_slots_3_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_fencei = _T_288 ? issue_slots_5_out_uop_is_fencei : _T_287 ? issue_slots_4_out_uop_is_fencei : issue_slots_3_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_fence = _T_288 ? issue_slots_5_out_uop_is_fence : _T_287 ? issue_slots_4_out_uop_is_fence : issue_slots_3_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_sfb = _T_288 ? issue_slots_5_out_uop_is_sfb : _T_287 ? issue_slots_4_out_uop_is_sfb : issue_slots_3_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_br_type = _T_288 ? issue_slots_5_out_uop_br_type : _T_287 ? issue_slots_4_out_uop_br_type : issue_slots_3_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_br_tag = _T_288 ? issue_slots_5_out_uop_br_tag : _T_287 ? issue_slots_4_out_uop_br_tag : issue_slots_3_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_br_mask = _T_288 ? issue_slots_5_out_uop_br_mask : _T_287 ? issue_slots_4_out_uop_br_mask : issue_slots_3_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_dis_col_sel = _T_288 ? issue_slots_5_out_uop_dis_col_sel : _T_287 ? issue_slots_4_out_uop_dis_col_sel : issue_slots_3_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_iw_p3_bypass_hint = _T_288 ? issue_slots_5_out_uop_iw_p3_bypass_hint : _T_287 ? issue_slots_4_out_uop_iw_p3_bypass_hint : issue_slots_3_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_iw_p2_bypass_hint = _T_288 ? issue_slots_5_out_uop_iw_p2_bypass_hint : _T_287 ? issue_slots_4_out_uop_iw_p2_bypass_hint : issue_slots_3_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_iw_p1_bypass_hint = _T_288 ? issue_slots_5_out_uop_iw_p1_bypass_hint : _T_287 ? issue_slots_4_out_uop_iw_p1_bypass_hint : issue_slots_3_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_iw_p2_speculative_child = _T_288 ? issue_slots_5_out_uop_iw_p2_speculative_child : _T_287 ? issue_slots_4_out_uop_iw_p2_speculative_child : issue_slots_3_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_iw_p1_speculative_child = _T_288 ? issue_slots_5_out_uop_iw_p1_speculative_child : _T_287 ? issue_slots_4_out_uop_iw_p1_speculative_child : issue_slots_3_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_iw_issued_partial_dgen = _T_288 ? issue_slots_5_out_uop_iw_issued_partial_dgen : _T_287 ? issue_slots_4_out_uop_iw_issued_partial_dgen : issue_slots_3_out_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_iw_issued_partial_agen = _T_288 ? issue_slots_5_out_uop_iw_issued_partial_agen : _T_287 ? issue_slots_4_out_uop_iw_issued_partial_agen : issue_slots_3_out_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_iw_issued = _T_288 ? issue_slots_5_out_uop_iw_issued : _T_287 ? issue_slots_4_out_uop_iw_issued : issue_slots_3_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_0 = _T_288 ? issue_slots_5_out_uop_fu_code_0 : _T_287 ? issue_slots_4_out_uop_fu_code_0 : issue_slots_3_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_1 = _T_288 ? issue_slots_5_out_uop_fu_code_1 : _T_287 ? issue_slots_4_out_uop_fu_code_1 : issue_slots_3_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_2 = _T_288 ? issue_slots_5_out_uop_fu_code_2 : _T_287 ? issue_slots_4_out_uop_fu_code_2 : issue_slots_3_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_3 = _T_288 ? issue_slots_5_out_uop_fu_code_3 : _T_287 ? issue_slots_4_out_uop_fu_code_3 : issue_slots_3_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_4 = _T_288 ? issue_slots_5_out_uop_fu_code_4 : _T_287 ? issue_slots_4_out_uop_fu_code_4 : issue_slots_3_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_5 = _T_288 ? issue_slots_5_out_uop_fu_code_5 : _T_287 ? issue_slots_4_out_uop_fu_code_5 : issue_slots_3_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_6 = _T_288 ? issue_slots_5_out_uop_fu_code_6 : _T_287 ? issue_slots_4_out_uop_fu_code_6 : issue_slots_3_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_7 = _T_288 ? issue_slots_5_out_uop_fu_code_7 : _T_287 ? issue_slots_4_out_uop_fu_code_7 : issue_slots_3_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_8 = _T_288 ? issue_slots_5_out_uop_fu_code_8 : _T_287 ? issue_slots_4_out_uop_fu_code_8 : issue_slots_3_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_9 = _T_288 ? issue_slots_5_out_uop_fu_code_9 : _T_287 ? issue_slots_4_out_uop_fu_code_9 : issue_slots_3_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_iq_type_0 = _T_288 ? issue_slots_5_out_uop_iq_type_0 : _T_287 ? issue_slots_4_out_uop_iq_type_0 : issue_slots_3_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_iq_type_1 = _T_288 ? issue_slots_5_out_uop_iq_type_1 : _T_287 ? issue_slots_4_out_uop_iq_type_1 : issue_slots_3_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_iq_type_2 = _T_288 ? issue_slots_5_out_uop_iq_type_2 : _T_287 ? issue_slots_4_out_uop_iq_type_2 : issue_slots_3_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_iq_type_3 = _T_288 ? issue_slots_5_out_uop_iq_type_3 : _T_287 ? issue_slots_4_out_uop_iq_type_3 : issue_slots_3_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_debug_pc = _T_288 ? issue_slots_5_out_uop_debug_pc : _T_287 ? issue_slots_4_out_uop_debug_pc : issue_slots_3_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_rvc = _T_288 ? issue_slots_5_out_uop_is_rvc : _T_287 ? issue_slots_4_out_uop_is_rvc : issue_slots_3_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_debug_inst = _T_288 ? issue_slots_5_out_uop_debug_inst : _T_287 ? issue_slots_4_out_uop_debug_inst : issue_slots_3_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_inst = _T_288 ? issue_slots_5_out_uop_inst : _T_287 ? issue_slots_4_out_uop_inst : issue_slots_3_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_2_clear_T = |shamts_oh_2; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_2_clear = _issue_slots_2_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_290 = shamts_oh_5 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_291 = shamts_oh_6 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_3_in_uop_valid = _T_291 ? issue_slots_6_will_be_valid : _T_290 ? issue_slots_5_will_be_valid : shamts_oh_4 == 3'h1 & issue_slots_4_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_3_in_uop_bits_debug_tsrc = _T_291 ? issue_slots_6_out_uop_debug_tsrc : _T_290 ? issue_slots_5_out_uop_debug_tsrc : issue_slots_4_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_debug_fsrc = _T_291 ? issue_slots_6_out_uop_debug_fsrc : _T_290 ? issue_slots_5_out_uop_debug_fsrc : issue_slots_4_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_bp_xcpt_if = _T_291 ? issue_slots_6_out_uop_bp_xcpt_if : _T_290 ? issue_slots_5_out_uop_bp_xcpt_if : issue_slots_4_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_bp_debug_if = _T_291 ? issue_slots_6_out_uop_bp_debug_if : _T_290 ? issue_slots_5_out_uop_bp_debug_if : issue_slots_4_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_xcpt_ma_if = _T_291 ? issue_slots_6_out_uop_xcpt_ma_if : _T_290 ? issue_slots_5_out_uop_xcpt_ma_if : issue_slots_4_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_xcpt_ae_if = _T_291 ? issue_slots_6_out_uop_xcpt_ae_if : _T_290 ? issue_slots_5_out_uop_xcpt_ae_if : issue_slots_4_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_xcpt_pf_if = _T_291 ? issue_slots_6_out_uop_xcpt_pf_if : _T_290 ? issue_slots_5_out_uop_xcpt_pf_if : issue_slots_4_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_typ = _T_291 ? issue_slots_6_out_uop_fp_typ : _T_290 ? issue_slots_5_out_uop_fp_typ : issue_slots_4_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_rm = _T_291 ? issue_slots_6_out_uop_fp_rm : _T_290 ? issue_slots_5_out_uop_fp_rm : issue_slots_4_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_val = _T_291 ? issue_slots_6_out_uop_fp_val : _T_290 ? issue_slots_5_out_uop_fp_val : issue_slots_4_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fcn_op = _T_291 ? issue_slots_6_out_uop_fcn_op : _T_290 ? issue_slots_5_out_uop_fcn_op : issue_slots_4_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fcn_dw = _T_291 ? issue_slots_6_out_uop_fcn_dw : _T_290 ? issue_slots_5_out_uop_fcn_dw : issue_slots_4_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_frs3_en = _T_291 ? issue_slots_6_out_uop_frs3_en : _T_290 ? issue_slots_5_out_uop_frs3_en : issue_slots_4_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_lrs2_rtype = _T_291 ? issue_slots_6_out_uop_lrs2_rtype : _T_290 ? issue_slots_5_out_uop_lrs2_rtype : issue_slots_4_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_lrs1_rtype = _T_291 ? issue_slots_6_out_uop_lrs1_rtype : _T_290 ? issue_slots_5_out_uop_lrs1_rtype : issue_slots_4_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_dst_rtype = _T_291 ? issue_slots_6_out_uop_dst_rtype : _T_290 ? issue_slots_5_out_uop_dst_rtype : issue_slots_4_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_lrs3 = _T_291 ? issue_slots_6_out_uop_lrs3 : _T_290 ? issue_slots_5_out_uop_lrs3 : issue_slots_4_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_lrs2 = _T_291 ? issue_slots_6_out_uop_lrs2 : _T_290 ? issue_slots_5_out_uop_lrs2 : issue_slots_4_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_lrs1 = _T_291 ? issue_slots_6_out_uop_lrs1 : _T_290 ? issue_slots_5_out_uop_lrs1 : issue_slots_4_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_ldst = _T_291 ? issue_slots_6_out_uop_ldst : _T_290 ? issue_slots_5_out_uop_ldst : issue_slots_4_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_ldst_is_rs1 = _T_291 ? issue_slots_6_out_uop_ldst_is_rs1 : _T_290 ? issue_slots_5_out_uop_ldst_is_rs1 : issue_slots_4_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_csr_cmd = _T_291 ? issue_slots_6_out_uop_csr_cmd : _T_290 ? issue_slots_5_out_uop_csr_cmd : issue_slots_4_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_flush_on_commit = _T_291 ? issue_slots_6_out_uop_flush_on_commit : _T_290 ? issue_slots_5_out_uop_flush_on_commit : issue_slots_4_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_unique = _T_291 ? issue_slots_6_out_uop_is_unique : _T_290 ? issue_slots_5_out_uop_is_unique : issue_slots_4_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_uses_stq = _T_291 ? issue_slots_6_out_uop_uses_stq : _T_290 ? issue_slots_5_out_uop_uses_stq : issue_slots_4_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_uses_ldq = _T_291 ? issue_slots_6_out_uop_uses_ldq : _T_290 ? issue_slots_5_out_uop_uses_ldq : issue_slots_4_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_mem_signed = _T_291 ? issue_slots_6_out_uop_mem_signed : _T_290 ? issue_slots_5_out_uop_mem_signed : issue_slots_4_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_mem_size = _T_291 ? issue_slots_6_out_uop_mem_size : _T_290 ? issue_slots_5_out_uop_mem_size : issue_slots_4_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_mem_cmd = _T_291 ? issue_slots_6_out_uop_mem_cmd : _T_290 ? issue_slots_5_out_uop_mem_cmd : issue_slots_4_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_exc_cause = _T_291 ? issue_slots_6_out_uop_exc_cause : _T_290 ? issue_slots_5_out_uop_exc_cause : issue_slots_4_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_exception = _T_291 ? issue_slots_6_out_uop_exception : _T_290 ? issue_slots_5_out_uop_exception : issue_slots_4_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_stale_pdst = _T_291 ? issue_slots_6_out_uop_stale_pdst : _T_290 ? issue_slots_5_out_uop_stale_pdst : issue_slots_4_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_ppred_busy = _T_291 ? issue_slots_6_out_uop_ppred_busy : _T_290 ? issue_slots_5_out_uop_ppred_busy : issue_slots_4_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_prs3_busy = _T_291 ? issue_slots_6_out_uop_prs3_busy : _T_290 ? issue_slots_5_out_uop_prs3_busy : issue_slots_4_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_prs2_busy = _T_291 ? issue_slots_6_out_uop_prs2_busy : _T_290 ? issue_slots_5_out_uop_prs2_busy : issue_slots_4_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_prs1_busy = _T_291 ? issue_slots_6_out_uop_prs1_busy : _T_290 ? issue_slots_5_out_uop_prs1_busy : issue_slots_4_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_ppred = _T_291 ? issue_slots_6_out_uop_ppred : _T_290 ? issue_slots_5_out_uop_ppred : issue_slots_4_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_prs3 = _T_291 ? issue_slots_6_out_uop_prs3 : _T_290 ? issue_slots_5_out_uop_prs3 : issue_slots_4_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_prs2 = _T_291 ? issue_slots_6_out_uop_prs2 : _T_290 ? issue_slots_5_out_uop_prs2 : issue_slots_4_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_prs1 = _T_291 ? issue_slots_6_out_uop_prs1 : _T_290 ? issue_slots_5_out_uop_prs1 : issue_slots_4_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_pdst = _T_291 ? issue_slots_6_out_uop_pdst : _T_290 ? issue_slots_5_out_uop_pdst : issue_slots_4_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_rxq_idx = _T_291 ? issue_slots_6_out_uop_rxq_idx : _T_290 ? issue_slots_5_out_uop_rxq_idx : issue_slots_4_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_stq_idx = _T_291 ? issue_slots_6_out_uop_stq_idx : _T_290 ? issue_slots_5_out_uop_stq_idx : issue_slots_4_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_ldq_idx = _T_291 ? issue_slots_6_out_uop_ldq_idx : _T_290 ? issue_slots_5_out_uop_ldq_idx : issue_slots_4_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_rob_idx = _T_291 ? issue_slots_6_out_uop_rob_idx : _T_290 ? issue_slots_5_out_uop_rob_idx : issue_slots_4_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_vec = _T_291 ? issue_slots_6_out_uop_fp_ctrl_vec : _T_290 ? issue_slots_5_out_uop_fp_ctrl_vec : issue_slots_4_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_wflags = _T_291 ? issue_slots_6_out_uop_fp_ctrl_wflags : _T_290 ? issue_slots_5_out_uop_fp_ctrl_wflags : issue_slots_4_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_sqrt = _T_291 ? issue_slots_6_out_uop_fp_ctrl_sqrt : _T_290 ? issue_slots_5_out_uop_fp_ctrl_sqrt : issue_slots_4_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_div = _T_291 ? issue_slots_6_out_uop_fp_ctrl_div : _T_290 ? issue_slots_5_out_uop_fp_ctrl_div : issue_slots_4_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_fma = _T_291 ? issue_slots_6_out_uop_fp_ctrl_fma : _T_290 ? issue_slots_5_out_uop_fp_ctrl_fma : issue_slots_4_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_fastpipe = _T_291 ? issue_slots_6_out_uop_fp_ctrl_fastpipe : _T_290 ? issue_slots_5_out_uop_fp_ctrl_fastpipe : issue_slots_4_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_toint = _T_291 ? issue_slots_6_out_uop_fp_ctrl_toint : _T_290 ? issue_slots_5_out_uop_fp_ctrl_toint : issue_slots_4_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_fromint = _T_291 ? issue_slots_6_out_uop_fp_ctrl_fromint : _T_290 ? issue_slots_5_out_uop_fp_ctrl_fromint : issue_slots_4_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_typeTagOut = _T_291 ? issue_slots_6_out_uop_fp_ctrl_typeTagOut : _T_290 ? issue_slots_5_out_uop_fp_ctrl_typeTagOut : issue_slots_4_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_typeTagIn = _T_291 ? issue_slots_6_out_uop_fp_ctrl_typeTagIn : _T_290 ? issue_slots_5_out_uop_fp_ctrl_typeTagIn : issue_slots_4_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_swap23 = _T_291 ? issue_slots_6_out_uop_fp_ctrl_swap23 : _T_290 ? issue_slots_5_out_uop_fp_ctrl_swap23 : issue_slots_4_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_swap12 = _T_291 ? issue_slots_6_out_uop_fp_ctrl_swap12 : _T_290 ? issue_slots_5_out_uop_fp_ctrl_swap12 : issue_slots_4_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_ren3 = _T_291 ? issue_slots_6_out_uop_fp_ctrl_ren3 : _T_290 ? issue_slots_5_out_uop_fp_ctrl_ren3 : issue_slots_4_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_ren2 = _T_291 ? issue_slots_6_out_uop_fp_ctrl_ren2 : _T_290 ? issue_slots_5_out_uop_fp_ctrl_ren2 : issue_slots_4_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_ren1 = _T_291 ? issue_slots_6_out_uop_fp_ctrl_ren1 : _T_290 ? issue_slots_5_out_uop_fp_ctrl_ren1 : issue_slots_4_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_wen = _T_291 ? issue_slots_6_out_uop_fp_ctrl_wen : _T_290 ? issue_slots_5_out_uop_fp_ctrl_wen : issue_slots_4_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_ldst = _T_291 ? issue_slots_6_out_uop_fp_ctrl_ldst : _T_290 ? issue_slots_5_out_uop_fp_ctrl_ldst : issue_slots_4_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_op2_sel = _T_291 ? issue_slots_6_out_uop_op2_sel : _T_290 ? issue_slots_5_out_uop_op2_sel : issue_slots_4_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_op1_sel = _T_291 ? issue_slots_6_out_uop_op1_sel : _T_290 ? issue_slots_5_out_uop_op1_sel : issue_slots_4_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_imm_packed = _T_291 ? issue_slots_6_out_uop_imm_packed : _T_290 ? issue_slots_5_out_uop_imm_packed : issue_slots_4_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_pimm = _T_291 ? issue_slots_6_out_uop_pimm : _T_290 ? issue_slots_5_out_uop_pimm : issue_slots_4_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_imm_sel = _T_291 ? issue_slots_6_out_uop_imm_sel : _T_290 ? issue_slots_5_out_uop_imm_sel : issue_slots_4_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_imm_rename = _T_291 ? issue_slots_6_out_uop_imm_rename : _T_290 ? issue_slots_5_out_uop_imm_rename : issue_slots_4_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_taken = _T_291 ? issue_slots_6_out_uop_taken : _T_290 ? issue_slots_5_out_uop_taken : issue_slots_4_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_pc_lob = _T_291 ? issue_slots_6_out_uop_pc_lob : _T_290 ? issue_slots_5_out_uop_pc_lob : issue_slots_4_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_edge_inst = _T_291 ? issue_slots_6_out_uop_edge_inst : _T_290 ? issue_slots_5_out_uop_edge_inst : issue_slots_4_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_ftq_idx = _T_291 ? issue_slots_6_out_uop_ftq_idx : _T_290 ? issue_slots_5_out_uop_ftq_idx : issue_slots_4_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_mov = _T_291 ? issue_slots_6_out_uop_is_mov : _T_290 ? issue_slots_5_out_uop_is_mov : issue_slots_4_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_rocc = _T_291 ? issue_slots_6_out_uop_is_rocc : _T_290 ? issue_slots_5_out_uop_is_rocc : issue_slots_4_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_sys_pc2epc = _T_291 ? issue_slots_6_out_uop_is_sys_pc2epc : _T_290 ? issue_slots_5_out_uop_is_sys_pc2epc : issue_slots_4_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_eret = _T_291 ? issue_slots_6_out_uop_is_eret : _T_290 ? issue_slots_5_out_uop_is_eret : issue_slots_4_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_amo = _T_291 ? issue_slots_6_out_uop_is_amo : _T_290 ? issue_slots_5_out_uop_is_amo : issue_slots_4_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_sfence = _T_291 ? issue_slots_6_out_uop_is_sfence : _T_290 ? issue_slots_5_out_uop_is_sfence : issue_slots_4_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_fencei = _T_291 ? issue_slots_6_out_uop_is_fencei : _T_290 ? issue_slots_5_out_uop_is_fencei : issue_slots_4_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_fence = _T_291 ? issue_slots_6_out_uop_is_fence : _T_290 ? issue_slots_5_out_uop_is_fence : issue_slots_4_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_sfb = _T_291 ? issue_slots_6_out_uop_is_sfb : _T_290 ? issue_slots_5_out_uop_is_sfb : issue_slots_4_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_br_type = _T_291 ? issue_slots_6_out_uop_br_type : _T_290 ? issue_slots_5_out_uop_br_type : issue_slots_4_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_br_tag = _T_291 ? issue_slots_6_out_uop_br_tag : _T_290 ? issue_slots_5_out_uop_br_tag : issue_slots_4_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_br_mask = _T_291 ? issue_slots_6_out_uop_br_mask : _T_290 ? issue_slots_5_out_uop_br_mask : issue_slots_4_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_dis_col_sel = _T_291 ? issue_slots_6_out_uop_dis_col_sel : _T_290 ? issue_slots_5_out_uop_dis_col_sel : issue_slots_4_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_iw_p3_bypass_hint = _T_291 ? issue_slots_6_out_uop_iw_p3_bypass_hint : _T_290 ? issue_slots_5_out_uop_iw_p3_bypass_hint : issue_slots_4_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_iw_p2_bypass_hint = _T_291 ? issue_slots_6_out_uop_iw_p2_bypass_hint : _T_290 ? issue_slots_5_out_uop_iw_p2_bypass_hint : issue_slots_4_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_iw_p1_bypass_hint = _T_291 ? issue_slots_6_out_uop_iw_p1_bypass_hint : _T_290 ? issue_slots_5_out_uop_iw_p1_bypass_hint : issue_slots_4_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_iw_p2_speculative_child = _T_291 ? issue_slots_6_out_uop_iw_p2_speculative_child : _T_290 ? issue_slots_5_out_uop_iw_p2_speculative_child : issue_slots_4_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_iw_p1_speculative_child = _T_291 ? issue_slots_6_out_uop_iw_p1_speculative_child : _T_290 ? issue_slots_5_out_uop_iw_p1_speculative_child : issue_slots_4_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_iw_issued_partial_dgen = _T_291 ? issue_slots_6_out_uop_iw_issued_partial_dgen : _T_290 ? issue_slots_5_out_uop_iw_issued_partial_dgen : issue_slots_4_out_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_iw_issued_partial_agen = _T_291 ? issue_slots_6_out_uop_iw_issued_partial_agen : _T_290 ? issue_slots_5_out_uop_iw_issued_partial_agen : issue_slots_4_out_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_iw_issued = _T_291 ? issue_slots_6_out_uop_iw_issued : _T_290 ? issue_slots_5_out_uop_iw_issued : issue_slots_4_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_0 = _T_291 ? issue_slots_6_out_uop_fu_code_0 : _T_290 ? issue_slots_5_out_uop_fu_code_0 : issue_slots_4_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_1 = _T_291 ? issue_slots_6_out_uop_fu_code_1 : _T_290 ? issue_slots_5_out_uop_fu_code_1 : issue_slots_4_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_2 = _T_291 ? issue_slots_6_out_uop_fu_code_2 : _T_290 ? issue_slots_5_out_uop_fu_code_2 : issue_slots_4_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_3 = _T_291 ? issue_slots_6_out_uop_fu_code_3 : _T_290 ? issue_slots_5_out_uop_fu_code_3 : issue_slots_4_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_4 = _T_291 ? issue_slots_6_out_uop_fu_code_4 : _T_290 ? issue_slots_5_out_uop_fu_code_4 : issue_slots_4_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_5 = _T_291 ? issue_slots_6_out_uop_fu_code_5 : _T_290 ? issue_slots_5_out_uop_fu_code_5 : issue_slots_4_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_6 = _T_291 ? issue_slots_6_out_uop_fu_code_6 : _T_290 ? issue_slots_5_out_uop_fu_code_6 : issue_slots_4_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_7 = _T_291 ? issue_slots_6_out_uop_fu_code_7 : _T_290 ? issue_slots_5_out_uop_fu_code_7 : issue_slots_4_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_8 = _T_291 ? issue_slots_6_out_uop_fu_code_8 : _T_290 ? issue_slots_5_out_uop_fu_code_8 : issue_slots_4_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_9 = _T_291 ? issue_slots_6_out_uop_fu_code_9 : _T_290 ? issue_slots_5_out_uop_fu_code_9 : issue_slots_4_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_iq_type_0 = _T_291 ? issue_slots_6_out_uop_iq_type_0 : _T_290 ? issue_slots_5_out_uop_iq_type_0 : issue_slots_4_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_iq_type_1 = _T_291 ? issue_slots_6_out_uop_iq_type_1 : _T_290 ? issue_slots_5_out_uop_iq_type_1 : issue_slots_4_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_iq_type_2 = _T_291 ? issue_slots_6_out_uop_iq_type_2 : _T_290 ? issue_slots_5_out_uop_iq_type_2 : issue_slots_4_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_iq_type_3 = _T_291 ? issue_slots_6_out_uop_iq_type_3 : _T_290 ? issue_slots_5_out_uop_iq_type_3 : issue_slots_4_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_debug_pc = _T_291 ? issue_slots_6_out_uop_debug_pc : _T_290 ? issue_slots_5_out_uop_debug_pc : issue_slots_4_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_rvc = _T_291 ? issue_slots_6_out_uop_is_rvc : _T_290 ? issue_slots_5_out_uop_is_rvc : issue_slots_4_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_debug_inst = _T_291 ? issue_slots_6_out_uop_debug_inst : _T_290 ? issue_slots_5_out_uop_debug_inst : issue_slots_4_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_inst = _T_291 ? issue_slots_6_out_uop_inst : _T_290 ? issue_slots_5_out_uop_inst : issue_slots_4_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_3_clear_T = |shamts_oh_3; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_3_clear = _issue_slots_3_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_293 = shamts_oh_6 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_294 = shamts_oh_7 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_4_in_uop_valid = _T_294 ? issue_slots_7_will_be_valid : _T_293 ? issue_slots_6_will_be_valid : shamts_oh_5 == 3'h1 & issue_slots_5_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_4_in_uop_bits_debug_tsrc = _T_294 ? issue_slots_7_out_uop_debug_tsrc : _T_293 ? issue_slots_6_out_uop_debug_tsrc : issue_slots_5_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_debug_fsrc = _T_294 ? issue_slots_7_out_uop_debug_fsrc : _T_293 ? issue_slots_6_out_uop_debug_fsrc : issue_slots_5_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_bp_xcpt_if = _T_294 ? issue_slots_7_out_uop_bp_xcpt_if : _T_293 ? issue_slots_6_out_uop_bp_xcpt_if : issue_slots_5_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_bp_debug_if = _T_294 ? issue_slots_7_out_uop_bp_debug_if : _T_293 ? issue_slots_6_out_uop_bp_debug_if : issue_slots_5_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_xcpt_ma_if = _T_294 ? issue_slots_7_out_uop_xcpt_ma_if : _T_293 ? issue_slots_6_out_uop_xcpt_ma_if : issue_slots_5_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_xcpt_ae_if = _T_294 ? issue_slots_7_out_uop_xcpt_ae_if : _T_293 ? issue_slots_6_out_uop_xcpt_ae_if : issue_slots_5_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_xcpt_pf_if = _T_294 ? issue_slots_7_out_uop_xcpt_pf_if : _T_293 ? issue_slots_6_out_uop_xcpt_pf_if : issue_slots_5_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_typ = _T_294 ? issue_slots_7_out_uop_fp_typ : _T_293 ? issue_slots_6_out_uop_fp_typ : issue_slots_5_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_rm = _T_294 ? issue_slots_7_out_uop_fp_rm : _T_293 ? issue_slots_6_out_uop_fp_rm : issue_slots_5_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_val = _T_294 ? issue_slots_7_out_uop_fp_val : _T_293 ? issue_slots_6_out_uop_fp_val : issue_slots_5_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fcn_op = _T_294 ? issue_slots_7_out_uop_fcn_op : _T_293 ? issue_slots_6_out_uop_fcn_op : issue_slots_5_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fcn_dw = _T_294 ? issue_slots_7_out_uop_fcn_dw : _T_293 ? issue_slots_6_out_uop_fcn_dw : issue_slots_5_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_frs3_en = _T_294 ? issue_slots_7_out_uop_frs3_en : _T_293 ? issue_slots_6_out_uop_frs3_en : issue_slots_5_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_lrs2_rtype = _T_294 ? issue_slots_7_out_uop_lrs2_rtype : _T_293 ? issue_slots_6_out_uop_lrs2_rtype : issue_slots_5_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_lrs1_rtype = _T_294 ? issue_slots_7_out_uop_lrs1_rtype : _T_293 ? issue_slots_6_out_uop_lrs1_rtype : issue_slots_5_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_dst_rtype = _T_294 ? issue_slots_7_out_uop_dst_rtype : _T_293 ? issue_slots_6_out_uop_dst_rtype : issue_slots_5_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_lrs3 = _T_294 ? issue_slots_7_out_uop_lrs3 : _T_293 ? issue_slots_6_out_uop_lrs3 : issue_slots_5_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_lrs2 = _T_294 ? issue_slots_7_out_uop_lrs2 : _T_293 ? issue_slots_6_out_uop_lrs2 : issue_slots_5_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_lrs1 = _T_294 ? issue_slots_7_out_uop_lrs1 : _T_293 ? issue_slots_6_out_uop_lrs1 : issue_slots_5_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_ldst = _T_294 ? issue_slots_7_out_uop_ldst : _T_293 ? issue_slots_6_out_uop_ldst : issue_slots_5_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_ldst_is_rs1 = _T_294 ? issue_slots_7_out_uop_ldst_is_rs1 : _T_293 ? issue_slots_6_out_uop_ldst_is_rs1 : issue_slots_5_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_csr_cmd = _T_294 ? issue_slots_7_out_uop_csr_cmd : _T_293 ? issue_slots_6_out_uop_csr_cmd : issue_slots_5_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_flush_on_commit = _T_294 ? issue_slots_7_out_uop_flush_on_commit : _T_293 ? issue_slots_6_out_uop_flush_on_commit : issue_slots_5_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_unique = _T_294 ? issue_slots_7_out_uop_is_unique : _T_293 ? issue_slots_6_out_uop_is_unique : issue_slots_5_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_uses_stq = _T_294 ? issue_slots_7_out_uop_uses_stq : _T_293 ? issue_slots_6_out_uop_uses_stq : issue_slots_5_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_uses_ldq = _T_294 ? issue_slots_7_out_uop_uses_ldq : _T_293 ? issue_slots_6_out_uop_uses_ldq : issue_slots_5_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_mem_signed = _T_294 ? issue_slots_7_out_uop_mem_signed : _T_293 ? issue_slots_6_out_uop_mem_signed : issue_slots_5_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_mem_size = _T_294 ? issue_slots_7_out_uop_mem_size : _T_293 ? issue_slots_6_out_uop_mem_size : issue_slots_5_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_mem_cmd = _T_294 ? issue_slots_7_out_uop_mem_cmd : _T_293 ? issue_slots_6_out_uop_mem_cmd : issue_slots_5_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_exc_cause = _T_294 ? issue_slots_7_out_uop_exc_cause : _T_293 ? issue_slots_6_out_uop_exc_cause : issue_slots_5_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_exception = _T_294 ? issue_slots_7_out_uop_exception : _T_293 ? issue_slots_6_out_uop_exception : issue_slots_5_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_stale_pdst = _T_294 ? issue_slots_7_out_uop_stale_pdst : _T_293 ? issue_slots_6_out_uop_stale_pdst : issue_slots_5_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_ppred_busy = _T_294 ? issue_slots_7_out_uop_ppred_busy : _T_293 ? issue_slots_6_out_uop_ppred_busy : issue_slots_5_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_prs3_busy = _T_294 ? issue_slots_7_out_uop_prs3_busy : _T_293 ? issue_slots_6_out_uop_prs3_busy : issue_slots_5_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_prs2_busy = _T_294 ? issue_slots_7_out_uop_prs2_busy : _T_293 ? issue_slots_6_out_uop_prs2_busy : issue_slots_5_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_prs1_busy = _T_294 ? issue_slots_7_out_uop_prs1_busy : _T_293 ? issue_slots_6_out_uop_prs1_busy : issue_slots_5_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_ppred = _T_294 ? issue_slots_7_out_uop_ppred : _T_293 ? issue_slots_6_out_uop_ppred : issue_slots_5_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_prs3 = _T_294 ? issue_slots_7_out_uop_prs3 : _T_293 ? issue_slots_6_out_uop_prs3 : issue_slots_5_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_prs2 = _T_294 ? issue_slots_7_out_uop_prs2 : _T_293 ? issue_slots_6_out_uop_prs2 : issue_slots_5_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_prs1 = _T_294 ? issue_slots_7_out_uop_prs1 : _T_293 ? issue_slots_6_out_uop_prs1 : issue_slots_5_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_pdst = _T_294 ? issue_slots_7_out_uop_pdst : _T_293 ? issue_slots_6_out_uop_pdst : issue_slots_5_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_rxq_idx = _T_294 ? issue_slots_7_out_uop_rxq_idx : _T_293 ? issue_slots_6_out_uop_rxq_idx : issue_slots_5_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_stq_idx = _T_294 ? issue_slots_7_out_uop_stq_idx : _T_293 ? issue_slots_6_out_uop_stq_idx : issue_slots_5_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_ldq_idx = _T_294 ? issue_slots_7_out_uop_ldq_idx : _T_293 ? issue_slots_6_out_uop_ldq_idx : issue_slots_5_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_rob_idx = _T_294 ? issue_slots_7_out_uop_rob_idx : _T_293 ? issue_slots_6_out_uop_rob_idx : issue_slots_5_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_vec = _T_294 ? issue_slots_7_out_uop_fp_ctrl_vec : _T_293 ? issue_slots_6_out_uop_fp_ctrl_vec : issue_slots_5_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_wflags = _T_294 ? issue_slots_7_out_uop_fp_ctrl_wflags : _T_293 ? issue_slots_6_out_uop_fp_ctrl_wflags : issue_slots_5_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_sqrt = _T_294 ? issue_slots_7_out_uop_fp_ctrl_sqrt : _T_293 ? issue_slots_6_out_uop_fp_ctrl_sqrt : issue_slots_5_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_div = _T_294 ? issue_slots_7_out_uop_fp_ctrl_div : _T_293 ? issue_slots_6_out_uop_fp_ctrl_div : issue_slots_5_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_fma = _T_294 ? issue_slots_7_out_uop_fp_ctrl_fma : _T_293 ? issue_slots_6_out_uop_fp_ctrl_fma : issue_slots_5_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_fastpipe = _T_294 ? issue_slots_7_out_uop_fp_ctrl_fastpipe : _T_293 ? issue_slots_6_out_uop_fp_ctrl_fastpipe : issue_slots_5_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_toint = _T_294 ? issue_slots_7_out_uop_fp_ctrl_toint : _T_293 ? issue_slots_6_out_uop_fp_ctrl_toint : issue_slots_5_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_fromint = _T_294 ? issue_slots_7_out_uop_fp_ctrl_fromint : _T_293 ? issue_slots_6_out_uop_fp_ctrl_fromint : issue_slots_5_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_typeTagOut = _T_294 ? issue_slots_7_out_uop_fp_ctrl_typeTagOut : _T_293 ? issue_slots_6_out_uop_fp_ctrl_typeTagOut : issue_slots_5_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_typeTagIn = _T_294 ? issue_slots_7_out_uop_fp_ctrl_typeTagIn : _T_293 ? issue_slots_6_out_uop_fp_ctrl_typeTagIn : issue_slots_5_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_swap23 = _T_294 ? issue_slots_7_out_uop_fp_ctrl_swap23 : _T_293 ? issue_slots_6_out_uop_fp_ctrl_swap23 : issue_slots_5_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_swap12 = _T_294 ? issue_slots_7_out_uop_fp_ctrl_swap12 : _T_293 ? issue_slots_6_out_uop_fp_ctrl_swap12 : issue_slots_5_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_ren3 = _T_294 ? issue_slots_7_out_uop_fp_ctrl_ren3 : _T_293 ? issue_slots_6_out_uop_fp_ctrl_ren3 : issue_slots_5_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_ren2 = _T_294 ? issue_slots_7_out_uop_fp_ctrl_ren2 : _T_293 ? issue_slots_6_out_uop_fp_ctrl_ren2 : issue_slots_5_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_ren1 = _T_294 ? issue_slots_7_out_uop_fp_ctrl_ren1 : _T_293 ? issue_slots_6_out_uop_fp_ctrl_ren1 : issue_slots_5_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_wen = _T_294 ? issue_slots_7_out_uop_fp_ctrl_wen : _T_293 ? issue_slots_6_out_uop_fp_ctrl_wen : issue_slots_5_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_ldst = _T_294 ? issue_slots_7_out_uop_fp_ctrl_ldst : _T_293 ? issue_slots_6_out_uop_fp_ctrl_ldst : issue_slots_5_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_op2_sel = _T_294 ? issue_slots_7_out_uop_op2_sel : _T_293 ? issue_slots_6_out_uop_op2_sel : issue_slots_5_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_op1_sel = _T_294 ? issue_slots_7_out_uop_op1_sel : _T_293 ? issue_slots_6_out_uop_op1_sel : issue_slots_5_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_imm_packed = _T_294 ? issue_slots_7_out_uop_imm_packed : _T_293 ? issue_slots_6_out_uop_imm_packed : issue_slots_5_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_pimm = _T_294 ? issue_slots_7_out_uop_pimm : _T_293 ? issue_slots_6_out_uop_pimm : issue_slots_5_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_imm_sel = _T_294 ? issue_slots_7_out_uop_imm_sel : _T_293 ? issue_slots_6_out_uop_imm_sel : issue_slots_5_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_imm_rename = _T_294 ? issue_slots_7_out_uop_imm_rename : _T_293 ? issue_slots_6_out_uop_imm_rename : issue_slots_5_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_taken = _T_294 ? issue_slots_7_out_uop_taken : _T_293 ? issue_slots_6_out_uop_taken : issue_slots_5_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_pc_lob = _T_294 ? issue_slots_7_out_uop_pc_lob : _T_293 ? issue_slots_6_out_uop_pc_lob : issue_slots_5_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_edge_inst = _T_294 ? issue_slots_7_out_uop_edge_inst : _T_293 ? issue_slots_6_out_uop_edge_inst : issue_slots_5_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_ftq_idx = _T_294 ? issue_slots_7_out_uop_ftq_idx : _T_293 ? issue_slots_6_out_uop_ftq_idx : issue_slots_5_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_mov = _T_294 ? issue_slots_7_out_uop_is_mov : _T_293 ? issue_slots_6_out_uop_is_mov : issue_slots_5_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_rocc = _T_294 ? issue_slots_7_out_uop_is_rocc : _T_293 ? issue_slots_6_out_uop_is_rocc : issue_slots_5_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_sys_pc2epc = _T_294 ? issue_slots_7_out_uop_is_sys_pc2epc : _T_293 ? issue_slots_6_out_uop_is_sys_pc2epc : issue_slots_5_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_eret = _T_294 ? issue_slots_7_out_uop_is_eret : _T_293 ? issue_slots_6_out_uop_is_eret : issue_slots_5_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_amo = _T_294 ? issue_slots_7_out_uop_is_amo : _T_293 ? issue_slots_6_out_uop_is_amo : issue_slots_5_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_sfence = _T_294 ? issue_slots_7_out_uop_is_sfence : _T_293 ? issue_slots_6_out_uop_is_sfence : issue_slots_5_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_fencei = _T_294 ? issue_slots_7_out_uop_is_fencei : _T_293 ? issue_slots_6_out_uop_is_fencei : issue_slots_5_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_fence = _T_294 ? issue_slots_7_out_uop_is_fence : _T_293 ? issue_slots_6_out_uop_is_fence : issue_slots_5_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_sfb = _T_294 ? issue_slots_7_out_uop_is_sfb : _T_293 ? issue_slots_6_out_uop_is_sfb : issue_slots_5_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_br_type = _T_294 ? issue_slots_7_out_uop_br_type : _T_293 ? issue_slots_6_out_uop_br_type : issue_slots_5_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_br_tag = _T_294 ? issue_slots_7_out_uop_br_tag : _T_293 ? issue_slots_6_out_uop_br_tag : issue_slots_5_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_br_mask = _T_294 ? issue_slots_7_out_uop_br_mask : _T_293 ? issue_slots_6_out_uop_br_mask : issue_slots_5_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_dis_col_sel = _T_294 ? issue_slots_7_out_uop_dis_col_sel : _T_293 ? issue_slots_6_out_uop_dis_col_sel : issue_slots_5_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_iw_p3_bypass_hint = _T_294 ? issue_slots_7_out_uop_iw_p3_bypass_hint : _T_293 ? issue_slots_6_out_uop_iw_p3_bypass_hint : issue_slots_5_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_iw_p2_bypass_hint = _T_294 ? issue_slots_7_out_uop_iw_p2_bypass_hint : _T_293 ? issue_slots_6_out_uop_iw_p2_bypass_hint : issue_slots_5_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_iw_p1_bypass_hint = _T_294 ? issue_slots_7_out_uop_iw_p1_bypass_hint : _T_293 ? issue_slots_6_out_uop_iw_p1_bypass_hint : issue_slots_5_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_iw_p2_speculative_child = _T_294 ? issue_slots_7_out_uop_iw_p2_speculative_child : _T_293 ? issue_slots_6_out_uop_iw_p2_speculative_child : issue_slots_5_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_iw_p1_speculative_child = _T_294 ? issue_slots_7_out_uop_iw_p1_speculative_child : _T_293 ? issue_slots_6_out_uop_iw_p1_speculative_child : issue_slots_5_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_iw_issued_partial_dgen = _T_294 ? issue_slots_7_out_uop_iw_issued_partial_dgen : _T_293 ? issue_slots_6_out_uop_iw_issued_partial_dgen : issue_slots_5_out_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_iw_issued_partial_agen = _T_294 ? issue_slots_7_out_uop_iw_issued_partial_agen : _T_293 ? issue_slots_6_out_uop_iw_issued_partial_agen : issue_slots_5_out_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_iw_issued = _T_294 ? issue_slots_7_out_uop_iw_issued : _T_293 ? issue_slots_6_out_uop_iw_issued : issue_slots_5_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_0 = _T_294 ? issue_slots_7_out_uop_fu_code_0 : _T_293 ? issue_slots_6_out_uop_fu_code_0 : issue_slots_5_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_1 = _T_294 ? issue_slots_7_out_uop_fu_code_1 : _T_293 ? issue_slots_6_out_uop_fu_code_1 : issue_slots_5_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_2 = _T_294 ? issue_slots_7_out_uop_fu_code_2 : _T_293 ? issue_slots_6_out_uop_fu_code_2 : issue_slots_5_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_3 = _T_294 ? issue_slots_7_out_uop_fu_code_3 : _T_293 ? issue_slots_6_out_uop_fu_code_3 : issue_slots_5_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_4 = _T_294 ? issue_slots_7_out_uop_fu_code_4 : _T_293 ? issue_slots_6_out_uop_fu_code_4 : issue_slots_5_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_5 = _T_294 ? issue_slots_7_out_uop_fu_code_5 : _T_293 ? issue_slots_6_out_uop_fu_code_5 : issue_slots_5_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_6 = _T_294 ? issue_slots_7_out_uop_fu_code_6 : _T_293 ? issue_slots_6_out_uop_fu_code_6 : issue_slots_5_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_7 = _T_294 ? issue_slots_7_out_uop_fu_code_7 : _T_293 ? issue_slots_6_out_uop_fu_code_7 : issue_slots_5_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_8 = _T_294 ? issue_slots_7_out_uop_fu_code_8 : _T_293 ? issue_slots_6_out_uop_fu_code_8 : issue_slots_5_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_9 = _T_294 ? issue_slots_7_out_uop_fu_code_9 : _T_293 ? issue_slots_6_out_uop_fu_code_9 : issue_slots_5_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_iq_type_0 = _T_294 ? issue_slots_7_out_uop_iq_type_0 : _T_293 ? issue_slots_6_out_uop_iq_type_0 : issue_slots_5_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_iq_type_1 = _T_294 ? issue_slots_7_out_uop_iq_type_1 : _T_293 ? issue_slots_6_out_uop_iq_type_1 : issue_slots_5_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_iq_type_2 = _T_294 ? issue_slots_7_out_uop_iq_type_2 : _T_293 ? issue_slots_6_out_uop_iq_type_2 : issue_slots_5_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_iq_type_3 = _T_294 ? issue_slots_7_out_uop_iq_type_3 : _T_293 ? issue_slots_6_out_uop_iq_type_3 : issue_slots_5_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_debug_pc = _T_294 ? issue_slots_7_out_uop_debug_pc : _T_293 ? issue_slots_6_out_uop_debug_pc : issue_slots_5_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_rvc = _T_294 ? issue_slots_7_out_uop_is_rvc : _T_293 ? issue_slots_6_out_uop_is_rvc : issue_slots_5_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_debug_inst = _T_294 ? issue_slots_7_out_uop_debug_inst : _T_293 ? issue_slots_6_out_uop_debug_inst : issue_slots_5_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_inst = _T_294 ? issue_slots_7_out_uop_inst : _T_293 ? issue_slots_6_out_uop_inst : issue_slots_5_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_4_clear_T = |shamts_oh_4; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_4_clear = _issue_slots_4_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_296 = shamts_oh_7 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_297 = shamts_oh_8 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_5_in_uop_valid = _T_297 ? issue_slots_8_will_be_valid : _T_296 ? issue_slots_7_will_be_valid : shamts_oh_6 == 3'h1 & issue_slots_6_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_5_in_uop_bits_debug_tsrc = _T_297 ? issue_slots_8_out_uop_debug_tsrc : _T_296 ? issue_slots_7_out_uop_debug_tsrc : issue_slots_6_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_debug_fsrc = _T_297 ? issue_slots_8_out_uop_debug_fsrc : _T_296 ? issue_slots_7_out_uop_debug_fsrc : issue_slots_6_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_bp_xcpt_if = _T_297 ? issue_slots_8_out_uop_bp_xcpt_if : _T_296 ? issue_slots_7_out_uop_bp_xcpt_if : issue_slots_6_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_bp_debug_if = _T_297 ? issue_slots_8_out_uop_bp_debug_if : _T_296 ? issue_slots_7_out_uop_bp_debug_if : issue_slots_6_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_xcpt_ma_if = _T_297 ? issue_slots_8_out_uop_xcpt_ma_if : _T_296 ? issue_slots_7_out_uop_xcpt_ma_if : issue_slots_6_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_xcpt_ae_if = _T_297 ? issue_slots_8_out_uop_xcpt_ae_if : _T_296 ? issue_slots_7_out_uop_xcpt_ae_if : issue_slots_6_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_xcpt_pf_if = _T_297 ? issue_slots_8_out_uop_xcpt_pf_if : _T_296 ? issue_slots_7_out_uop_xcpt_pf_if : issue_slots_6_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_typ = _T_297 ? issue_slots_8_out_uop_fp_typ : _T_296 ? issue_slots_7_out_uop_fp_typ : issue_slots_6_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_rm = _T_297 ? issue_slots_8_out_uop_fp_rm : _T_296 ? issue_slots_7_out_uop_fp_rm : issue_slots_6_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_val = _T_297 ? issue_slots_8_out_uop_fp_val : _T_296 ? issue_slots_7_out_uop_fp_val : issue_slots_6_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fcn_op = _T_297 ? issue_slots_8_out_uop_fcn_op : _T_296 ? issue_slots_7_out_uop_fcn_op : issue_slots_6_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fcn_dw = _T_297 ? issue_slots_8_out_uop_fcn_dw : _T_296 ? issue_slots_7_out_uop_fcn_dw : issue_slots_6_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_frs3_en = _T_297 ? issue_slots_8_out_uop_frs3_en : _T_296 ? issue_slots_7_out_uop_frs3_en : issue_slots_6_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_lrs2_rtype = _T_297 ? issue_slots_8_out_uop_lrs2_rtype : _T_296 ? issue_slots_7_out_uop_lrs2_rtype : issue_slots_6_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_lrs1_rtype = _T_297 ? issue_slots_8_out_uop_lrs1_rtype : _T_296 ? issue_slots_7_out_uop_lrs1_rtype : issue_slots_6_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_dst_rtype = _T_297 ? issue_slots_8_out_uop_dst_rtype : _T_296 ? issue_slots_7_out_uop_dst_rtype : issue_slots_6_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_lrs3 = _T_297 ? issue_slots_8_out_uop_lrs3 : _T_296 ? issue_slots_7_out_uop_lrs3 : issue_slots_6_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_lrs2 = _T_297 ? issue_slots_8_out_uop_lrs2 : _T_296 ? issue_slots_7_out_uop_lrs2 : issue_slots_6_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_lrs1 = _T_297 ? issue_slots_8_out_uop_lrs1 : _T_296 ? issue_slots_7_out_uop_lrs1 : issue_slots_6_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_ldst = _T_297 ? issue_slots_8_out_uop_ldst : _T_296 ? issue_slots_7_out_uop_ldst : issue_slots_6_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_ldst_is_rs1 = _T_297 ? issue_slots_8_out_uop_ldst_is_rs1 : _T_296 ? issue_slots_7_out_uop_ldst_is_rs1 : issue_slots_6_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_csr_cmd = _T_297 ? issue_slots_8_out_uop_csr_cmd : _T_296 ? issue_slots_7_out_uop_csr_cmd : issue_slots_6_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_flush_on_commit = _T_297 ? issue_slots_8_out_uop_flush_on_commit : _T_296 ? issue_slots_7_out_uop_flush_on_commit : issue_slots_6_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_unique = _T_297 ? issue_slots_8_out_uop_is_unique : _T_296 ? issue_slots_7_out_uop_is_unique : issue_slots_6_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_uses_stq = _T_297 ? issue_slots_8_out_uop_uses_stq : _T_296 ? issue_slots_7_out_uop_uses_stq : issue_slots_6_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_uses_ldq = _T_297 ? issue_slots_8_out_uop_uses_ldq : _T_296 ? issue_slots_7_out_uop_uses_ldq : issue_slots_6_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_mem_signed = _T_297 ? issue_slots_8_out_uop_mem_signed : _T_296 ? issue_slots_7_out_uop_mem_signed : issue_slots_6_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_mem_size = _T_297 ? issue_slots_8_out_uop_mem_size : _T_296 ? issue_slots_7_out_uop_mem_size : issue_slots_6_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_mem_cmd = _T_297 ? issue_slots_8_out_uop_mem_cmd : _T_296 ? issue_slots_7_out_uop_mem_cmd : issue_slots_6_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_exc_cause = _T_297 ? issue_slots_8_out_uop_exc_cause : _T_296 ? issue_slots_7_out_uop_exc_cause : issue_slots_6_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_exception = _T_297 ? issue_slots_8_out_uop_exception : _T_296 ? issue_slots_7_out_uop_exception : issue_slots_6_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_stale_pdst = _T_297 ? issue_slots_8_out_uop_stale_pdst : _T_296 ? issue_slots_7_out_uop_stale_pdst : issue_slots_6_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_ppred_busy = _T_297 ? issue_slots_8_out_uop_ppred_busy : _T_296 ? issue_slots_7_out_uop_ppred_busy : issue_slots_6_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_prs3_busy = _T_297 ? issue_slots_8_out_uop_prs3_busy : _T_296 ? issue_slots_7_out_uop_prs3_busy : issue_slots_6_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_prs2_busy = _T_297 ? issue_slots_8_out_uop_prs2_busy : _T_296 ? issue_slots_7_out_uop_prs2_busy : issue_slots_6_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_prs1_busy = _T_297 ? issue_slots_8_out_uop_prs1_busy : _T_296 ? issue_slots_7_out_uop_prs1_busy : issue_slots_6_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_ppred = _T_297 ? issue_slots_8_out_uop_ppred : _T_296 ? issue_slots_7_out_uop_ppred : issue_slots_6_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_prs3 = _T_297 ? issue_slots_8_out_uop_prs3 : _T_296 ? issue_slots_7_out_uop_prs3 : issue_slots_6_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_prs2 = _T_297 ? issue_slots_8_out_uop_prs2 : _T_296 ? issue_slots_7_out_uop_prs2 : issue_slots_6_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_prs1 = _T_297 ? issue_slots_8_out_uop_prs1 : _T_296 ? issue_slots_7_out_uop_prs1 : issue_slots_6_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_pdst = _T_297 ? issue_slots_8_out_uop_pdst : _T_296 ? issue_slots_7_out_uop_pdst : issue_slots_6_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_rxq_idx = _T_297 ? issue_slots_8_out_uop_rxq_idx : _T_296 ? issue_slots_7_out_uop_rxq_idx : issue_slots_6_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_stq_idx = _T_297 ? issue_slots_8_out_uop_stq_idx : _T_296 ? issue_slots_7_out_uop_stq_idx : issue_slots_6_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_ldq_idx = _T_297 ? issue_slots_8_out_uop_ldq_idx : _T_296 ? issue_slots_7_out_uop_ldq_idx : issue_slots_6_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_rob_idx = _T_297 ? issue_slots_8_out_uop_rob_idx : _T_296 ? issue_slots_7_out_uop_rob_idx : issue_slots_6_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_vec = _T_297 ? issue_slots_8_out_uop_fp_ctrl_vec : _T_296 ? issue_slots_7_out_uop_fp_ctrl_vec : issue_slots_6_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_wflags = _T_297 ? issue_slots_8_out_uop_fp_ctrl_wflags : _T_296 ? issue_slots_7_out_uop_fp_ctrl_wflags : issue_slots_6_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_sqrt = _T_297 ? issue_slots_8_out_uop_fp_ctrl_sqrt : _T_296 ? issue_slots_7_out_uop_fp_ctrl_sqrt : issue_slots_6_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_div = _T_297 ? issue_slots_8_out_uop_fp_ctrl_div : _T_296 ? issue_slots_7_out_uop_fp_ctrl_div : issue_slots_6_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_fma = _T_297 ? issue_slots_8_out_uop_fp_ctrl_fma : _T_296 ? issue_slots_7_out_uop_fp_ctrl_fma : issue_slots_6_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_fastpipe = _T_297 ? issue_slots_8_out_uop_fp_ctrl_fastpipe : _T_296 ? issue_slots_7_out_uop_fp_ctrl_fastpipe : issue_slots_6_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_toint = _T_297 ? issue_slots_8_out_uop_fp_ctrl_toint : _T_296 ? issue_slots_7_out_uop_fp_ctrl_toint : issue_slots_6_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_fromint = _T_297 ? issue_slots_8_out_uop_fp_ctrl_fromint : _T_296 ? issue_slots_7_out_uop_fp_ctrl_fromint : issue_slots_6_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_typeTagOut = _T_297 ? issue_slots_8_out_uop_fp_ctrl_typeTagOut : _T_296 ? issue_slots_7_out_uop_fp_ctrl_typeTagOut : issue_slots_6_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_typeTagIn = _T_297 ? issue_slots_8_out_uop_fp_ctrl_typeTagIn : _T_296 ? issue_slots_7_out_uop_fp_ctrl_typeTagIn : issue_slots_6_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_swap23 = _T_297 ? issue_slots_8_out_uop_fp_ctrl_swap23 : _T_296 ? issue_slots_7_out_uop_fp_ctrl_swap23 : issue_slots_6_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_swap12 = _T_297 ? issue_slots_8_out_uop_fp_ctrl_swap12 : _T_296 ? issue_slots_7_out_uop_fp_ctrl_swap12 : issue_slots_6_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_ren3 = _T_297 ? issue_slots_8_out_uop_fp_ctrl_ren3 : _T_296 ? issue_slots_7_out_uop_fp_ctrl_ren3 : issue_slots_6_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_ren2 = _T_297 ? issue_slots_8_out_uop_fp_ctrl_ren2 : _T_296 ? issue_slots_7_out_uop_fp_ctrl_ren2 : issue_slots_6_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_ren1 = _T_297 ? issue_slots_8_out_uop_fp_ctrl_ren1 : _T_296 ? issue_slots_7_out_uop_fp_ctrl_ren1 : issue_slots_6_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_wen = _T_297 ? issue_slots_8_out_uop_fp_ctrl_wen : _T_296 ? issue_slots_7_out_uop_fp_ctrl_wen : issue_slots_6_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_ldst = _T_297 ? issue_slots_8_out_uop_fp_ctrl_ldst : _T_296 ? issue_slots_7_out_uop_fp_ctrl_ldst : issue_slots_6_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_op2_sel = _T_297 ? issue_slots_8_out_uop_op2_sel : _T_296 ? issue_slots_7_out_uop_op2_sel : issue_slots_6_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_op1_sel = _T_297 ? issue_slots_8_out_uop_op1_sel : _T_296 ? issue_slots_7_out_uop_op1_sel : issue_slots_6_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_imm_packed = _T_297 ? issue_slots_8_out_uop_imm_packed : _T_296 ? issue_slots_7_out_uop_imm_packed : issue_slots_6_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_pimm = _T_297 ? issue_slots_8_out_uop_pimm : _T_296 ? issue_slots_7_out_uop_pimm : issue_slots_6_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_imm_sel = _T_297 ? issue_slots_8_out_uop_imm_sel : _T_296 ? issue_slots_7_out_uop_imm_sel : issue_slots_6_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_imm_rename = _T_297 ? issue_slots_8_out_uop_imm_rename : _T_296 ? issue_slots_7_out_uop_imm_rename : issue_slots_6_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_taken = _T_297 ? issue_slots_8_out_uop_taken : _T_296 ? issue_slots_7_out_uop_taken : issue_slots_6_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_pc_lob = _T_297 ? issue_slots_8_out_uop_pc_lob : _T_296 ? issue_slots_7_out_uop_pc_lob : issue_slots_6_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_edge_inst = _T_297 ? issue_slots_8_out_uop_edge_inst : _T_296 ? issue_slots_7_out_uop_edge_inst : issue_slots_6_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_ftq_idx = _T_297 ? issue_slots_8_out_uop_ftq_idx : _T_296 ? issue_slots_7_out_uop_ftq_idx : issue_slots_6_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_mov = _T_297 ? issue_slots_8_out_uop_is_mov : _T_296 ? issue_slots_7_out_uop_is_mov : issue_slots_6_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_rocc = _T_297 ? issue_slots_8_out_uop_is_rocc : _T_296 ? issue_slots_7_out_uop_is_rocc : issue_slots_6_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_sys_pc2epc = _T_297 ? issue_slots_8_out_uop_is_sys_pc2epc : _T_296 ? issue_slots_7_out_uop_is_sys_pc2epc : issue_slots_6_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_eret = _T_297 ? issue_slots_8_out_uop_is_eret : _T_296 ? issue_slots_7_out_uop_is_eret : issue_slots_6_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_amo = _T_297 ? issue_slots_8_out_uop_is_amo : _T_296 ? issue_slots_7_out_uop_is_amo : issue_slots_6_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_sfence = _T_297 ? issue_slots_8_out_uop_is_sfence : _T_296 ? issue_slots_7_out_uop_is_sfence : issue_slots_6_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_fencei = _T_297 ? issue_slots_8_out_uop_is_fencei : _T_296 ? issue_slots_7_out_uop_is_fencei : issue_slots_6_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_fence = _T_297 ? issue_slots_8_out_uop_is_fence : _T_296 ? issue_slots_7_out_uop_is_fence : issue_slots_6_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_sfb = _T_297 ? issue_slots_8_out_uop_is_sfb : _T_296 ? issue_slots_7_out_uop_is_sfb : issue_slots_6_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_br_type = _T_297 ? issue_slots_8_out_uop_br_type : _T_296 ? issue_slots_7_out_uop_br_type : issue_slots_6_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_br_tag = _T_297 ? issue_slots_8_out_uop_br_tag : _T_296 ? issue_slots_7_out_uop_br_tag : issue_slots_6_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_br_mask = _T_297 ? issue_slots_8_out_uop_br_mask : _T_296 ? issue_slots_7_out_uop_br_mask : issue_slots_6_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_dis_col_sel = _T_297 ? issue_slots_8_out_uop_dis_col_sel : _T_296 ? issue_slots_7_out_uop_dis_col_sel : issue_slots_6_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_iw_p3_bypass_hint = _T_297 ? issue_slots_8_out_uop_iw_p3_bypass_hint : _T_296 ? issue_slots_7_out_uop_iw_p3_bypass_hint : issue_slots_6_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_iw_p2_bypass_hint = _T_297 ? issue_slots_8_out_uop_iw_p2_bypass_hint : _T_296 ? issue_slots_7_out_uop_iw_p2_bypass_hint : issue_slots_6_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_iw_p1_bypass_hint = _T_297 ? issue_slots_8_out_uop_iw_p1_bypass_hint : _T_296 ? issue_slots_7_out_uop_iw_p1_bypass_hint : issue_slots_6_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_iw_p2_speculative_child = _T_297 ? issue_slots_8_out_uop_iw_p2_speculative_child : _T_296 ? issue_slots_7_out_uop_iw_p2_speculative_child : issue_slots_6_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_iw_p1_speculative_child = _T_297 ? issue_slots_8_out_uop_iw_p1_speculative_child : _T_296 ? issue_slots_7_out_uop_iw_p1_speculative_child : issue_slots_6_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_iw_issued_partial_dgen = _T_297 ? issue_slots_8_out_uop_iw_issued_partial_dgen : _T_296 ? issue_slots_7_out_uop_iw_issued_partial_dgen : issue_slots_6_out_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_iw_issued_partial_agen = _T_297 ? issue_slots_8_out_uop_iw_issued_partial_agen : _T_296 ? issue_slots_7_out_uop_iw_issued_partial_agen : issue_slots_6_out_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_iw_issued = _T_297 ? issue_slots_8_out_uop_iw_issued : _T_296 ? issue_slots_7_out_uop_iw_issued : issue_slots_6_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_0 = _T_297 ? issue_slots_8_out_uop_fu_code_0 : _T_296 ? issue_slots_7_out_uop_fu_code_0 : issue_slots_6_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_1 = _T_297 ? issue_slots_8_out_uop_fu_code_1 : _T_296 ? issue_slots_7_out_uop_fu_code_1 : issue_slots_6_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_2 = _T_297 ? issue_slots_8_out_uop_fu_code_2 : _T_296 ? issue_slots_7_out_uop_fu_code_2 : issue_slots_6_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_3 = _T_297 ? issue_slots_8_out_uop_fu_code_3 : _T_296 ? issue_slots_7_out_uop_fu_code_3 : issue_slots_6_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_4 = _T_297 ? issue_slots_8_out_uop_fu_code_4 : _T_296 ? issue_slots_7_out_uop_fu_code_4 : issue_slots_6_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_5 = _T_297 ? issue_slots_8_out_uop_fu_code_5 : _T_296 ? issue_slots_7_out_uop_fu_code_5 : issue_slots_6_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_6 = _T_297 ? issue_slots_8_out_uop_fu_code_6 : _T_296 ? issue_slots_7_out_uop_fu_code_6 : issue_slots_6_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_7 = _T_297 ? issue_slots_8_out_uop_fu_code_7 : _T_296 ? issue_slots_7_out_uop_fu_code_7 : issue_slots_6_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_8 = _T_297 ? issue_slots_8_out_uop_fu_code_8 : _T_296 ? issue_slots_7_out_uop_fu_code_8 : issue_slots_6_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_9 = _T_297 ? issue_slots_8_out_uop_fu_code_9 : _T_296 ? issue_slots_7_out_uop_fu_code_9 : issue_slots_6_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_iq_type_0 = _T_297 ? issue_slots_8_out_uop_iq_type_0 : _T_296 ? issue_slots_7_out_uop_iq_type_0 : issue_slots_6_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_iq_type_1 = _T_297 ? issue_slots_8_out_uop_iq_type_1 : _T_296 ? issue_slots_7_out_uop_iq_type_1 : issue_slots_6_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_iq_type_2 = _T_297 ? issue_slots_8_out_uop_iq_type_2 : _T_296 ? issue_slots_7_out_uop_iq_type_2 : issue_slots_6_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_iq_type_3 = _T_297 ? issue_slots_8_out_uop_iq_type_3 : _T_296 ? issue_slots_7_out_uop_iq_type_3 : issue_slots_6_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_debug_pc = _T_297 ? issue_slots_8_out_uop_debug_pc : _T_296 ? issue_slots_7_out_uop_debug_pc : issue_slots_6_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_rvc = _T_297 ? issue_slots_8_out_uop_is_rvc : _T_296 ? issue_slots_7_out_uop_is_rvc : issue_slots_6_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_debug_inst = _T_297 ? issue_slots_8_out_uop_debug_inst : _T_296 ? issue_slots_7_out_uop_debug_inst : issue_slots_6_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_inst = _T_297 ? issue_slots_8_out_uop_inst : _T_296 ? issue_slots_7_out_uop_inst : issue_slots_6_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_5_clear_T = |shamts_oh_5; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_5_clear = _issue_slots_5_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_299 = shamts_oh_8 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_300 = shamts_oh_9 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_6_in_uop_valid = _T_300 ? issue_slots_9_will_be_valid : _T_299 ? issue_slots_8_will_be_valid : shamts_oh_7 == 3'h1 & issue_slots_7_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_6_in_uop_bits_debug_tsrc = _T_300 ? issue_slots_9_out_uop_debug_tsrc : _T_299 ? issue_slots_8_out_uop_debug_tsrc : issue_slots_7_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_debug_fsrc = _T_300 ? issue_slots_9_out_uop_debug_fsrc : _T_299 ? issue_slots_8_out_uop_debug_fsrc : issue_slots_7_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_bp_xcpt_if = _T_300 ? issue_slots_9_out_uop_bp_xcpt_if : _T_299 ? issue_slots_8_out_uop_bp_xcpt_if : issue_slots_7_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_bp_debug_if = _T_300 ? issue_slots_9_out_uop_bp_debug_if : _T_299 ? issue_slots_8_out_uop_bp_debug_if : issue_slots_7_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_xcpt_ma_if = _T_300 ? issue_slots_9_out_uop_xcpt_ma_if : _T_299 ? issue_slots_8_out_uop_xcpt_ma_if : issue_slots_7_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_xcpt_ae_if = _T_300 ? issue_slots_9_out_uop_xcpt_ae_if : _T_299 ? issue_slots_8_out_uop_xcpt_ae_if : issue_slots_7_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_xcpt_pf_if = _T_300 ? issue_slots_9_out_uop_xcpt_pf_if : _T_299 ? issue_slots_8_out_uop_xcpt_pf_if : issue_slots_7_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_typ = _T_300 ? issue_slots_9_out_uop_fp_typ : _T_299 ? issue_slots_8_out_uop_fp_typ : issue_slots_7_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_rm = _T_300 ? issue_slots_9_out_uop_fp_rm : _T_299 ? issue_slots_8_out_uop_fp_rm : issue_slots_7_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_val = _T_300 ? issue_slots_9_out_uop_fp_val : _T_299 ? issue_slots_8_out_uop_fp_val : issue_slots_7_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fcn_op = _T_300 ? issue_slots_9_out_uop_fcn_op : _T_299 ? issue_slots_8_out_uop_fcn_op : issue_slots_7_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fcn_dw = _T_300 ? issue_slots_9_out_uop_fcn_dw : _T_299 ? issue_slots_8_out_uop_fcn_dw : issue_slots_7_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_frs3_en = _T_300 ? issue_slots_9_out_uop_frs3_en : _T_299 ? issue_slots_8_out_uop_frs3_en : issue_slots_7_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_lrs2_rtype = _T_300 ? issue_slots_9_out_uop_lrs2_rtype : _T_299 ? issue_slots_8_out_uop_lrs2_rtype : issue_slots_7_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_lrs1_rtype = _T_300 ? issue_slots_9_out_uop_lrs1_rtype : _T_299 ? issue_slots_8_out_uop_lrs1_rtype : issue_slots_7_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_dst_rtype = _T_300 ? issue_slots_9_out_uop_dst_rtype : _T_299 ? issue_slots_8_out_uop_dst_rtype : issue_slots_7_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_lrs3 = _T_300 ? issue_slots_9_out_uop_lrs3 : _T_299 ? issue_slots_8_out_uop_lrs3 : issue_slots_7_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_lrs2 = _T_300 ? issue_slots_9_out_uop_lrs2 : _T_299 ? issue_slots_8_out_uop_lrs2 : issue_slots_7_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_lrs1 = _T_300 ? issue_slots_9_out_uop_lrs1 : _T_299 ? issue_slots_8_out_uop_lrs1 : issue_slots_7_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_ldst = _T_300 ? issue_slots_9_out_uop_ldst : _T_299 ? issue_slots_8_out_uop_ldst : issue_slots_7_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_ldst_is_rs1 = _T_300 ? issue_slots_9_out_uop_ldst_is_rs1 : _T_299 ? issue_slots_8_out_uop_ldst_is_rs1 : issue_slots_7_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_csr_cmd = _T_300 ? issue_slots_9_out_uop_csr_cmd : _T_299 ? issue_slots_8_out_uop_csr_cmd : issue_slots_7_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_flush_on_commit = _T_300 ? issue_slots_9_out_uop_flush_on_commit : _T_299 ? issue_slots_8_out_uop_flush_on_commit : issue_slots_7_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_unique = _T_300 ? issue_slots_9_out_uop_is_unique : _T_299 ? issue_slots_8_out_uop_is_unique : issue_slots_7_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_uses_stq = _T_300 ? issue_slots_9_out_uop_uses_stq : _T_299 ? issue_slots_8_out_uop_uses_stq : issue_slots_7_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_uses_ldq = _T_300 ? issue_slots_9_out_uop_uses_ldq : _T_299 ? issue_slots_8_out_uop_uses_ldq : issue_slots_7_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_mem_signed = _T_300 ? issue_slots_9_out_uop_mem_signed : _T_299 ? issue_slots_8_out_uop_mem_signed : issue_slots_7_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_mem_size = _T_300 ? issue_slots_9_out_uop_mem_size : _T_299 ? issue_slots_8_out_uop_mem_size : issue_slots_7_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_mem_cmd = _T_300 ? issue_slots_9_out_uop_mem_cmd : _T_299 ? issue_slots_8_out_uop_mem_cmd : issue_slots_7_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_exc_cause = _T_300 ? issue_slots_9_out_uop_exc_cause : _T_299 ? issue_slots_8_out_uop_exc_cause : issue_slots_7_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_exception = _T_300 ? issue_slots_9_out_uop_exception : _T_299 ? issue_slots_8_out_uop_exception : issue_slots_7_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_stale_pdst = _T_300 ? issue_slots_9_out_uop_stale_pdst : _T_299 ? issue_slots_8_out_uop_stale_pdst : issue_slots_7_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_ppred_busy = _T_300 ? issue_slots_9_out_uop_ppred_busy : _T_299 ? issue_slots_8_out_uop_ppred_busy : issue_slots_7_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_prs3_busy = _T_300 ? issue_slots_9_out_uop_prs3_busy : _T_299 ? issue_slots_8_out_uop_prs3_busy : issue_slots_7_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_prs2_busy = _T_300 ? issue_slots_9_out_uop_prs2_busy : _T_299 ? issue_slots_8_out_uop_prs2_busy : issue_slots_7_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_prs1_busy = _T_300 ? issue_slots_9_out_uop_prs1_busy : _T_299 ? issue_slots_8_out_uop_prs1_busy : issue_slots_7_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_ppred = _T_300 ? issue_slots_9_out_uop_ppred : _T_299 ? issue_slots_8_out_uop_ppred : issue_slots_7_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_prs3 = _T_300 ? issue_slots_9_out_uop_prs3 : _T_299 ? issue_slots_8_out_uop_prs3 : issue_slots_7_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_prs2 = _T_300 ? issue_slots_9_out_uop_prs2 : _T_299 ? issue_slots_8_out_uop_prs2 : issue_slots_7_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_prs1 = _T_300 ? issue_slots_9_out_uop_prs1 : _T_299 ? issue_slots_8_out_uop_prs1 : issue_slots_7_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_pdst = _T_300 ? issue_slots_9_out_uop_pdst : _T_299 ? issue_slots_8_out_uop_pdst : issue_slots_7_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_rxq_idx = _T_300 ? issue_slots_9_out_uop_rxq_idx : _T_299 ? issue_slots_8_out_uop_rxq_idx : issue_slots_7_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_stq_idx = _T_300 ? issue_slots_9_out_uop_stq_idx : _T_299 ? issue_slots_8_out_uop_stq_idx : issue_slots_7_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_ldq_idx = _T_300 ? issue_slots_9_out_uop_ldq_idx : _T_299 ? issue_slots_8_out_uop_ldq_idx : issue_slots_7_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_rob_idx = _T_300 ? issue_slots_9_out_uop_rob_idx : _T_299 ? issue_slots_8_out_uop_rob_idx : issue_slots_7_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_vec = _T_300 ? issue_slots_9_out_uop_fp_ctrl_vec : _T_299 ? issue_slots_8_out_uop_fp_ctrl_vec : issue_slots_7_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_wflags = _T_300 ? issue_slots_9_out_uop_fp_ctrl_wflags : _T_299 ? issue_slots_8_out_uop_fp_ctrl_wflags : issue_slots_7_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_sqrt = _T_300 ? issue_slots_9_out_uop_fp_ctrl_sqrt : _T_299 ? issue_slots_8_out_uop_fp_ctrl_sqrt : issue_slots_7_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_div = _T_300 ? issue_slots_9_out_uop_fp_ctrl_div : _T_299 ? issue_slots_8_out_uop_fp_ctrl_div : issue_slots_7_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_fma = _T_300 ? issue_slots_9_out_uop_fp_ctrl_fma : _T_299 ? issue_slots_8_out_uop_fp_ctrl_fma : issue_slots_7_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_fastpipe = _T_300 ? issue_slots_9_out_uop_fp_ctrl_fastpipe : _T_299 ? issue_slots_8_out_uop_fp_ctrl_fastpipe : issue_slots_7_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_toint = _T_300 ? issue_slots_9_out_uop_fp_ctrl_toint : _T_299 ? issue_slots_8_out_uop_fp_ctrl_toint : issue_slots_7_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_fromint = _T_300 ? issue_slots_9_out_uop_fp_ctrl_fromint : _T_299 ? issue_slots_8_out_uop_fp_ctrl_fromint : issue_slots_7_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_typeTagOut = _T_300 ? issue_slots_9_out_uop_fp_ctrl_typeTagOut : _T_299 ? issue_slots_8_out_uop_fp_ctrl_typeTagOut : issue_slots_7_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_typeTagIn = _T_300 ? issue_slots_9_out_uop_fp_ctrl_typeTagIn : _T_299 ? issue_slots_8_out_uop_fp_ctrl_typeTagIn : issue_slots_7_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_swap23 = _T_300 ? issue_slots_9_out_uop_fp_ctrl_swap23 : _T_299 ? issue_slots_8_out_uop_fp_ctrl_swap23 : issue_slots_7_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_swap12 = _T_300 ? issue_slots_9_out_uop_fp_ctrl_swap12 : _T_299 ? issue_slots_8_out_uop_fp_ctrl_swap12 : issue_slots_7_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_ren3 = _T_300 ? issue_slots_9_out_uop_fp_ctrl_ren3 : _T_299 ? issue_slots_8_out_uop_fp_ctrl_ren3 : issue_slots_7_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_ren2 = _T_300 ? issue_slots_9_out_uop_fp_ctrl_ren2 : _T_299 ? issue_slots_8_out_uop_fp_ctrl_ren2 : issue_slots_7_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_ren1 = _T_300 ? issue_slots_9_out_uop_fp_ctrl_ren1 : _T_299 ? issue_slots_8_out_uop_fp_ctrl_ren1 : issue_slots_7_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_wen = _T_300 ? issue_slots_9_out_uop_fp_ctrl_wen : _T_299 ? issue_slots_8_out_uop_fp_ctrl_wen : issue_slots_7_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_ldst = _T_300 ? issue_slots_9_out_uop_fp_ctrl_ldst : _T_299 ? issue_slots_8_out_uop_fp_ctrl_ldst : issue_slots_7_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_op2_sel = _T_300 ? issue_slots_9_out_uop_op2_sel : _T_299 ? issue_slots_8_out_uop_op2_sel : issue_slots_7_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_op1_sel = _T_300 ? issue_slots_9_out_uop_op1_sel : _T_299 ? issue_slots_8_out_uop_op1_sel : issue_slots_7_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_imm_packed = _T_300 ? issue_slots_9_out_uop_imm_packed : _T_299 ? issue_slots_8_out_uop_imm_packed : issue_slots_7_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_pimm = _T_300 ? issue_slots_9_out_uop_pimm : _T_299 ? issue_slots_8_out_uop_pimm : issue_slots_7_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_imm_sel = _T_300 ? issue_slots_9_out_uop_imm_sel : _T_299 ? issue_slots_8_out_uop_imm_sel : issue_slots_7_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_imm_rename = _T_300 ? issue_slots_9_out_uop_imm_rename : _T_299 ? issue_slots_8_out_uop_imm_rename : issue_slots_7_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_taken = _T_300 ? issue_slots_9_out_uop_taken : _T_299 ? issue_slots_8_out_uop_taken : issue_slots_7_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_pc_lob = _T_300 ? issue_slots_9_out_uop_pc_lob : _T_299 ? issue_slots_8_out_uop_pc_lob : issue_slots_7_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_edge_inst = _T_300 ? issue_slots_9_out_uop_edge_inst : _T_299 ? issue_slots_8_out_uop_edge_inst : issue_slots_7_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_ftq_idx = _T_300 ? issue_slots_9_out_uop_ftq_idx : _T_299 ? issue_slots_8_out_uop_ftq_idx : issue_slots_7_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_mov = _T_300 ? issue_slots_9_out_uop_is_mov : _T_299 ? issue_slots_8_out_uop_is_mov : issue_slots_7_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_rocc = _T_300 ? issue_slots_9_out_uop_is_rocc : _T_299 ? issue_slots_8_out_uop_is_rocc : issue_slots_7_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_sys_pc2epc = _T_300 ? issue_slots_9_out_uop_is_sys_pc2epc : _T_299 ? issue_slots_8_out_uop_is_sys_pc2epc : issue_slots_7_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_eret = _T_300 ? issue_slots_9_out_uop_is_eret : _T_299 ? issue_slots_8_out_uop_is_eret : issue_slots_7_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_amo = _T_300 ? issue_slots_9_out_uop_is_amo : _T_299 ? issue_slots_8_out_uop_is_amo : issue_slots_7_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_sfence = _T_300 ? issue_slots_9_out_uop_is_sfence : _T_299 ? issue_slots_8_out_uop_is_sfence : issue_slots_7_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_fencei = _T_300 ? issue_slots_9_out_uop_is_fencei : _T_299 ? issue_slots_8_out_uop_is_fencei : issue_slots_7_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_fence = _T_300 ? issue_slots_9_out_uop_is_fence : _T_299 ? issue_slots_8_out_uop_is_fence : issue_slots_7_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_sfb = _T_300 ? issue_slots_9_out_uop_is_sfb : _T_299 ? issue_slots_8_out_uop_is_sfb : issue_slots_7_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_br_type = _T_300 ? issue_slots_9_out_uop_br_type : _T_299 ? issue_slots_8_out_uop_br_type : issue_slots_7_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_br_tag = _T_300 ? issue_slots_9_out_uop_br_tag : _T_299 ? issue_slots_8_out_uop_br_tag : issue_slots_7_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_br_mask = _T_300 ? issue_slots_9_out_uop_br_mask : _T_299 ? issue_slots_8_out_uop_br_mask : issue_slots_7_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_dis_col_sel = _T_300 ? issue_slots_9_out_uop_dis_col_sel : _T_299 ? issue_slots_8_out_uop_dis_col_sel : issue_slots_7_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_iw_p3_bypass_hint = _T_300 ? issue_slots_9_out_uop_iw_p3_bypass_hint : _T_299 ? issue_slots_8_out_uop_iw_p3_bypass_hint : issue_slots_7_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_iw_p2_bypass_hint = _T_300 ? issue_slots_9_out_uop_iw_p2_bypass_hint : _T_299 ? issue_slots_8_out_uop_iw_p2_bypass_hint : issue_slots_7_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_iw_p1_bypass_hint = _T_300 ? issue_slots_9_out_uop_iw_p1_bypass_hint : _T_299 ? issue_slots_8_out_uop_iw_p1_bypass_hint : issue_slots_7_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_iw_p2_speculative_child = _T_300 ? issue_slots_9_out_uop_iw_p2_speculative_child : _T_299 ? issue_slots_8_out_uop_iw_p2_speculative_child : issue_slots_7_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_iw_p1_speculative_child = _T_300 ? issue_slots_9_out_uop_iw_p1_speculative_child : _T_299 ? issue_slots_8_out_uop_iw_p1_speculative_child : issue_slots_7_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_iw_issued_partial_dgen = _T_300 ? issue_slots_9_out_uop_iw_issued_partial_dgen : _T_299 ? issue_slots_8_out_uop_iw_issued_partial_dgen : issue_slots_7_out_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_iw_issued_partial_agen = _T_300 ? issue_slots_9_out_uop_iw_issued_partial_agen : _T_299 ? issue_slots_8_out_uop_iw_issued_partial_agen : issue_slots_7_out_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_iw_issued = _T_300 ? issue_slots_9_out_uop_iw_issued : _T_299 ? issue_slots_8_out_uop_iw_issued : issue_slots_7_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_0 = _T_300 ? issue_slots_9_out_uop_fu_code_0 : _T_299 ? issue_slots_8_out_uop_fu_code_0 : issue_slots_7_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_1 = _T_300 ? issue_slots_9_out_uop_fu_code_1 : _T_299 ? issue_slots_8_out_uop_fu_code_1 : issue_slots_7_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_2 = _T_300 ? issue_slots_9_out_uop_fu_code_2 : _T_299 ? issue_slots_8_out_uop_fu_code_2 : issue_slots_7_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_3 = _T_300 ? issue_slots_9_out_uop_fu_code_3 : _T_299 ? issue_slots_8_out_uop_fu_code_3 : issue_slots_7_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_4 = _T_300 ? issue_slots_9_out_uop_fu_code_4 : _T_299 ? issue_slots_8_out_uop_fu_code_4 : issue_slots_7_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_5 = _T_300 ? issue_slots_9_out_uop_fu_code_5 : _T_299 ? issue_slots_8_out_uop_fu_code_5 : issue_slots_7_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_6 = _T_300 ? issue_slots_9_out_uop_fu_code_6 : _T_299 ? issue_slots_8_out_uop_fu_code_6 : issue_slots_7_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_7 = _T_300 ? issue_slots_9_out_uop_fu_code_7 : _T_299 ? issue_slots_8_out_uop_fu_code_7 : issue_slots_7_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_8 = _T_300 ? issue_slots_9_out_uop_fu_code_8 : _T_299 ? issue_slots_8_out_uop_fu_code_8 : issue_slots_7_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_9 = _T_300 ? issue_slots_9_out_uop_fu_code_9 : _T_299 ? issue_slots_8_out_uop_fu_code_9 : issue_slots_7_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_iq_type_0 = _T_300 ? issue_slots_9_out_uop_iq_type_0 : _T_299 ? issue_slots_8_out_uop_iq_type_0 : issue_slots_7_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_iq_type_1 = _T_300 ? issue_slots_9_out_uop_iq_type_1 : _T_299 ? issue_slots_8_out_uop_iq_type_1 : issue_slots_7_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_iq_type_2 = _T_300 ? issue_slots_9_out_uop_iq_type_2 : _T_299 ? issue_slots_8_out_uop_iq_type_2 : issue_slots_7_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_iq_type_3 = _T_300 ? issue_slots_9_out_uop_iq_type_3 : _T_299 ? issue_slots_8_out_uop_iq_type_3 : issue_slots_7_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_debug_pc = _T_300 ? issue_slots_9_out_uop_debug_pc : _T_299 ? issue_slots_8_out_uop_debug_pc : issue_slots_7_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_rvc = _T_300 ? issue_slots_9_out_uop_is_rvc : _T_299 ? issue_slots_8_out_uop_is_rvc : issue_slots_7_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_debug_inst = _T_300 ? issue_slots_9_out_uop_debug_inst : _T_299 ? issue_slots_8_out_uop_debug_inst : issue_slots_7_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_inst = _T_300 ? issue_slots_9_out_uop_inst : _T_299 ? issue_slots_8_out_uop_inst : issue_slots_7_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_6_clear_T = |shamts_oh_6; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_6_clear = _issue_slots_6_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_302 = shamts_oh_9 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_303 = shamts_oh_10 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_7_in_uop_valid = _T_303 ? issue_slots_10_will_be_valid : _T_302 ? issue_slots_9_will_be_valid : shamts_oh_8 == 3'h1 & issue_slots_8_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_7_in_uop_bits_debug_tsrc = _T_303 ? issue_slots_10_out_uop_debug_tsrc : _T_302 ? issue_slots_9_out_uop_debug_tsrc : issue_slots_8_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_debug_fsrc = _T_303 ? issue_slots_10_out_uop_debug_fsrc : _T_302 ? issue_slots_9_out_uop_debug_fsrc : issue_slots_8_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_bp_xcpt_if = _T_303 ? issue_slots_10_out_uop_bp_xcpt_if : _T_302 ? issue_slots_9_out_uop_bp_xcpt_if : issue_slots_8_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_bp_debug_if = _T_303 ? issue_slots_10_out_uop_bp_debug_if : _T_302 ? issue_slots_9_out_uop_bp_debug_if : issue_slots_8_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_xcpt_ma_if = _T_303 ? issue_slots_10_out_uop_xcpt_ma_if : _T_302 ? issue_slots_9_out_uop_xcpt_ma_if : issue_slots_8_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_xcpt_ae_if = _T_303 ? issue_slots_10_out_uop_xcpt_ae_if : _T_302 ? issue_slots_9_out_uop_xcpt_ae_if : issue_slots_8_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_xcpt_pf_if = _T_303 ? issue_slots_10_out_uop_xcpt_pf_if : _T_302 ? issue_slots_9_out_uop_xcpt_pf_if : issue_slots_8_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_typ = _T_303 ? issue_slots_10_out_uop_fp_typ : _T_302 ? issue_slots_9_out_uop_fp_typ : issue_slots_8_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_rm = _T_303 ? issue_slots_10_out_uop_fp_rm : _T_302 ? issue_slots_9_out_uop_fp_rm : issue_slots_8_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_val = _T_303 ? issue_slots_10_out_uop_fp_val : _T_302 ? issue_slots_9_out_uop_fp_val : issue_slots_8_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fcn_op = _T_303 ? issue_slots_10_out_uop_fcn_op : _T_302 ? issue_slots_9_out_uop_fcn_op : issue_slots_8_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fcn_dw = _T_303 ? issue_slots_10_out_uop_fcn_dw : _T_302 ? issue_slots_9_out_uop_fcn_dw : issue_slots_8_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_frs3_en = _T_303 ? issue_slots_10_out_uop_frs3_en : _T_302 ? issue_slots_9_out_uop_frs3_en : issue_slots_8_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_lrs2_rtype = _T_303 ? issue_slots_10_out_uop_lrs2_rtype : _T_302 ? issue_slots_9_out_uop_lrs2_rtype : issue_slots_8_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_lrs1_rtype = _T_303 ? issue_slots_10_out_uop_lrs1_rtype : _T_302 ? issue_slots_9_out_uop_lrs1_rtype : issue_slots_8_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_dst_rtype = _T_303 ? issue_slots_10_out_uop_dst_rtype : _T_302 ? issue_slots_9_out_uop_dst_rtype : issue_slots_8_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_lrs3 = _T_303 ? issue_slots_10_out_uop_lrs3 : _T_302 ? issue_slots_9_out_uop_lrs3 : issue_slots_8_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_lrs2 = _T_303 ? issue_slots_10_out_uop_lrs2 : _T_302 ? issue_slots_9_out_uop_lrs2 : issue_slots_8_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_lrs1 = _T_303 ? issue_slots_10_out_uop_lrs1 : _T_302 ? issue_slots_9_out_uop_lrs1 : issue_slots_8_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_ldst = _T_303 ? issue_slots_10_out_uop_ldst : _T_302 ? issue_slots_9_out_uop_ldst : issue_slots_8_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_ldst_is_rs1 = _T_303 ? issue_slots_10_out_uop_ldst_is_rs1 : _T_302 ? issue_slots_9_out_uop_ldst_is_rs1 : issue_slots_8_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_csr_cmd = _T_303 ? issue_slots_10_out_uop_csr_cmd : _T_302 ? issue_slots_9_out_uop_csr_cmd : issue_slots_8_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_flush_on_commit = _T_303 ? issue_slots_10_out_uop_flush_on_commit : _T_302 ? issue_slots_9_out_uop_flush_on_commit : issue_slots_8_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_unique = _T_303 ? issue_slots_10_out_uop_is_unique : _T_302 ? issue_slots_9_out_uop_is_unique : issue_slots_8_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_uses_stq = _T_303 ? issue_slots_10_out_uop_uses_stq : _T_302 ? issue_slots_9_out_uop_uses_stq : issue_slots_8_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_uses_ldq = _T_303 ? issue_slots_10_out_uop_uses_ldq : _T_302 ? issue_slots_9_out_uop_uses_ldq : issue_slots_8_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_mem_signed = _T_303 ? issue_slots_10_out_uop_mem_signed : _T_302 ? issue_slots_9_out_uop_mem_signed : issue_slots_8_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_mem_size = _T_303 ? issue_slots_10_out_uop_mem_size : _T_302 ? issue_slots_9_out_uop_mem_size : issue_slots_8_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_mem_cmd = _T_303 ? issue_slots_10_out_uop_mem_cmd : _T_302 ? issue_slots_9_out_uop_mem_cmd : issue_slots_8_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_exc_cause = _T_303 ? issue_slots_10_out_uop_exc_cause : _T_302 ? issue_slots_9_out_uop_exc_cause : issue_slots_8_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_exception = _T_303 ? issue_slots_10_out_uop_exception : _T_302 ? issue_slots_9_out_uop_exception : issue_slots_8_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_stale_pdst = _T_303 ? issue_slots_10_out_uop_stale_pdst : _T_302 ? issue_slots_9_out_uop_stale_pdst : issue_slots_8_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_ppred_busy = _T_303 ? issue_slots_10_out_uop_ppred_busy : _T_302 ? issue_slots_9_out_uop_ppred_busy : issue_slots_8_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_prs3_busy = _T_303 ? issue_slots_10_out_uop_prs3_busy : _T_302 ? issue_slots_9_out_uop_prs3_busy : issue_slots_8_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_prs2_busy = _T_303 ? issue_slots_10_out_uop_prs2_busy : _T_302 ? issue_slots_9_out_uop_prs2_busy : issue_slots_8_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_prs1_busy = _T_303 ? issue_slots_10_out_uop_prs1_busy : _T_302 ? issue_slots_9_out_uop_prs1_busy : issue_slots_8_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_ppred = _T_303 ? issue_slots_10_out_uop_ppred : _T_302 ? issue_slots_9_out_uop_ppred : issue_slots_8_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_prs3 = _T_303 ? issue_slots_10_out_uop_prs3 : _T_302 ? issue_slots_9_out_uop_prs3 : issue_slots_8_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_prs2 = _T_303 ? issue_slots_10_out_uop_prs2 : _T_302 ? issue_slots_9_out_uop_prs2 : issue_slots_8_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_prs1 = _T_303 ? issue_slots_10_out_uop_prs1 : _T_302 ? issue_slots_9_out_uop_prs1 : issue_slots_8_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_pdst = _T_303 ? issue_slots_10_out_uop_pdst : _T_302 ? issue_slots_9_out_uop_pdst : issue_slots_8_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_rxq_idx = _T_303 ? issue_slots_10_out_uop_rxq_idx : _T_302 ? issue_slots_9_out_uop_rxq_idx : issue_slots_8_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_stq_idx = _T_303 ? issue_slots_10_out_uop_stq_idx : _T_302 ? issue_slots_9_out_uop_stq_idx : issue_slots_8_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_ldq_idx = _T_303 ? issue_slots_10_out_uop_ldq_idx : _T_302 ? issue_slots_9_out_uop_ldq_idx : issue_slots_8_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_rob_idx = _T_303 ? issue_slots_10_out_uop_rob_idx : _T_302 ? issue_slots_9_out_uop_rob_idx : issue_slots_8_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_vec = _T_303 ? issue_slots_10_out_uop_fp_ctrl_vec : _T_302 ? issue_slots_9_out_uop_fp_ctrl_vec : issue_slots_8_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_wflags = _T_303 ? issue_slots_10_out_uop_fp_ctrl_wflags : _T_302 ? issue_slots_9_out_uop_fp_ctrl_wflags : issue_slots_8_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_sqrt = _T_303 ? issue_slots_10_out_uop_fp_ctrl_sqrt : _T_302 ? issue_slots_9_out_uop_fp_ctrl_sqrt : issue_slots_8_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_div = _T_303 ? issue_slots_10_out_uop_fp_ctrl_div : _T_302 ? issue_slots_9_out_uop_fp_ctrl_div : issue_slots_8_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_fma = _T_303 ? issue_slots_10_out_uop_fp_ctrl_fma : _T_302 ? issue_slots_9_out_uop_fp_ctrl_fma : issue_slots_8_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_fastpipe = _T_303 ? issue_slots_10_out_uop_fp_ctrl_fastpipe : _T_302 ? issue_slots_9_out_uop_fp_ctrl_fastpipe : issue_slots_8_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_toint = _T_303 ? issue_slots_10_out_uop_fp_ctrl_toint : _T_302 ? issue_slots_9_out_uop_fp_ctrl_toint : issue_slots_8_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_fromint = _T_303 ? issue_slots_10_out_uop_fp_ctrl_fromint : _T_302 ? issue_slots_9_out_uop_fp_ctrl_fromint : issue_slots_8_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_typeTagOut = _T_303 ? issue_slots_10_out_uop_fp_ctrl_typeTagOut : _T_302 ? issue_slots_9_out_uop_fp_ctrl_typeTagOut : issue_slots_8_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_typeTagIn = _T_303 ? issue_slots_10_out_uop_fp_ctrl_typeTagIn : _T_302 ? issue_slots_9_out_uop_fp_ctrl_typeTagIn : issue_slots_8_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_swap23 = _T_303 ? issue_slots_10_out_uop_fp_ctrl_swap23 : _T_302 ? issue_slots_9_out_uop_fp_ctrl_swap23 : issue_slots_8_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_swap12 = _T_303 ? issue_slots_10_out_uop_fp_ctrl_swap12 : _T_302 ? issue_slots_9_out_uop_fp_ctrl_swap12 : issue_slots_8_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_ren3 = _T_303 ? issue_slots_10_out_uop_fp_ctrl_ren3 : _T_302 ? issue_slots_9_out_uop_fp_ctrl_ren3 : issue_slots_8_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_ren2 = _T_303 ? issue_slots_10_out_uop_fp_ctrl_ren2 : _T_302 ? issue_slots_9_out_uop_fp_ctrl_ren2 : issue_slots_8_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_ren1 = _T_303 ? issue_slots_10_out_uop_fp_ctrl_ren1 : _T_302 ? issue_slots_9_out_uop_fp_ctrl_ren1 : issue_slots_8_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_wen = _T_303 ? issue_slots_10_out_uop_fp_ctrl_wen : _T_302 ? issue_slots_9_out_uop_fp_ctrl_wen : issue_slots_8_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_ldst = _T_303 ? issue_slots_10_out_uop_fp_ctrl_ldst : _T_302 ? issue_slots_9_out_uop_fp_ctrl_ldst : issue_slots_8_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_op2_sel = _T_303 ? issue_slots_10_out_uop_op2_sel : _T_302 ? issue_slots_9_out_uop_op2_sel : issue_slots_8_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_op1_sel = _T_303 ? issue_slots_10_out_uop_op1_sel : _T_302 ? issue_slots_9_out_uop_op1_sel : issue_slots_8_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_imm_packed = _T_303 ? issue_slots_10_out_uop_imm_packed : _T_302 ? issue_slots_9_out_uop_imm_packed : issue_slots_8_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_pimm = _T_303 ? issue_slots_10_out_uop_pimm : _T_302 ? issue_slots_9_out_uop_pimm : issue_slots_8_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_imm_sel = _T_303 ? issue_slots_10_out_uop_imm_sel : _T_302 ? issue_slots_9_out_uop_imm_sel : issue_slots_8_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_imm_rename = _T_303 ? issue_slots_10_out_uop_imm_rename : _T_302 ? issue_slots_9_out_uop_imm_rename : issue_slots_8_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_taken = _T_303 ? issue_slots_10_out_uop_taken : _T_302 ? issue_slots_9_out_uop_taken : issue_slots_8_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_pc_lob = _T_303 ? issue_slots_10_out_uop_pc_lob : _T_302 ? issue_slots_9_out_uop_pc_lob : issue_slots_8_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_edge_inst = _T_303 ? issue_slots_10_out_uop_edge_inst : _T_302 ? issue_slots_9_out_uop_edge_inst : issue_slots_8_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_ftq_idx = _T_303 ? issue_slots_10_out_uop_ftq_idx : _T_302 ? issue_slots_9_out_uop_ftq_idx : issue_slots_8_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_mov = _T_303 ? issue_slots_10_out_uop_is_mov : _T_302 ? issue_slots_9_out_uop_is_mov : issue_slots_8_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_rocc = _T_303 ? issue_slots_10_out_uop_is_rocc : _T_302 ? issue_slots_9_out_uop_is_rocc : issue_slots_8_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_sys_pc2epc = _T_303 ? issue_slots_10_out_uop_is_sys_pc2epc : _T_302 ? issue_slots_9_out_uop_is_sys_pc2epc : issue_slots_8_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_eret = _T_303 ? issue_slots_10_out_uop_is_eret : _T_302 ? issue_slots_9_out_uop_is_eret : issue_slots_8_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_amo = _T_303 ? issue_slots_10_out_uop_is_amo : _T_302 ? issue_slots_9_out_uop_is_amo : issue_slots_8_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_sfence = _T_303 ? issue_slots_10_out_uop_is_sfence : _T_302 ? issue_slots_9_out_uop_is_sfence : issue_slots_8_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_fencei = _T_303 ? issue_slots_10_out_uop_is_fencei : _T_302 ? issue_slots_9_out_uop_is_fencei : issue_slots_8_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_fence = _T_303 ? issue_slots_10_out_uop_is_fence : _T_302 ? issue_slots_9_out_uop_is_fence : issue_slots_8_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_sfb = _T_303 ? issue_slots_10_out_uop_is_sfb : _T_302 ? issue_slots_9_out_uop_is_sfb : issue_slots_8_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_br_type = _T_303 ? issue_slots_10_out_uop_br_type : _T_302 ? issue_slots_9_out_uop_br_type : issue_slots_8_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_br_tag = _T_303 ? issue_slots_10_out_uop_br_tag : _T_302 ? issue_slots_9_out_uop_br_tag : issue_slots_8_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_br_mask = _T_303 ? issue_slots_10_out_uop_br_mask : _T_302 ? issue_slots_9_out_uop_br_mask : issue_slots_8_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_dis_col_sel = _T_303 ? issue_slots_10_out_uop_dis_col_sel : _T_302 ? issue_slots_9_out_uop_dis_col_sel : issue_slots_8_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_iw_p3_bypass_hint = _T_303 ? issue_slots_10_out_uop_iw_p3_bypass_hint : _T_302 ? issue_slots_9_out_uop_iw_p3_bypass_hint : issue_slots_8_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_iw_p2_bypass_hint = _T_303 ? issue_slots_10_out_uop_iw_p2_bypass_hint : _T_302 ? issue_slots_9_out_uop_iw_p2_bypass_hint : issue_slots_8_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_iw_p1_bypass_hint = _T_303 ? issue_slots_10_out_uop_iw_p1_bypass_hint : _T_302 ? issue_slots_9_out_uop_iw_p1_bypass_hint : issue_slots_8_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_iw_p2_speculative_child = _T_303 ? issue_slots_10_out_uop_iw_p2_speculative_child : _T_302 ? issue_slots_9_out_uop_iw_p2_speculative_child : issue_slots_8_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_iw_p1_speculative_child = _T_303 ? issue_slots_10_out_uop_iw_p1_speculative_child : _T_302 ? issue_slots_9_out_uop_iw_p1_speculative_child : issue_slots_8_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_iw_issued_partial_dgen = _T_303 ? issue_slots_10_out_uop_iw_issued_partial_dgen : _T_302 ? issue_slots_9_out_uop_iw_issued_partial_dgen : issue_slots_8_out_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_iw_issued_partial_agen = _T_303 ? issue_slots_10_out_uop_iw_issued_partial_agen : _T_302 ? issue_slots_9_out_uop_iw_issued_partial_agen : issue_slots_8_out_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_iw_issued = _T_303 ? issue_slots_10_out_uop_iw_issued : _T_302 ? issue_slots_9_out_uop_iw_issued : issue_slots_8_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_0 = _T_303 ? issue_slots_10_out_uop_fu_code_0 : _T_302 ? issue_slots_9_out_uop_fu_code_0 : issue_slots_8_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_1 = _T_303 ? issue_slots_10_out_uop_fu_code_1 : _T_302 ? issue_slots_9_out_uop_fu_code_1 : issue_slots_8_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_2 = _T_303 ? issue_slots_10_out_uop_fu_code_2 : _T_302 ? issue_slots_9_out_uop_fu_code_2 : issue_slots_8_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_3 = _T_303 ? issue_slots_10_out_uop_fu_code_3 : _T_302 ? issue_slots_9_out_uop_fu_code_3 : issue_slots_8_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_4 = _T_303 ? issue_slots_10_out_uop_fu_code_4 : _T_302 ? issue_slots_9_out_uop_fu_code_4 : issue_slots_8_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_5 = _T_303 ? issue_slots_10_out_uop_fu_code_5 : _T_302 ? issue_slots_9_out_uop_fu_code_5 : issue_slots_8_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_6 = _T_303 ? issue_slots_10_out_uop_fu_code_6 : _T_302 ? issue_slots_9_out_uop_fu_code_6 : issue_slots_8_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_7 = _T_303 ? issue_slots_10_out_uop_fu_code_7 : _T_302 ? issue_slots_9_out_uop_fu_code_7 : issue_slots_8_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_8 = _T_303 ? issue_slots_10_out_uop_fu_code_8 : _T_302 ? issue_slots_9_out_uop_fu_code_8 : issue_slots_8_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_9 = _T_303 ? issue_slots_10_out_uop_fu_code_9 : _T_302 ? issue_slots_9_out_uop_fu_code_9 : issue_slots_8_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_iq_type_0 = _T_303 ? issue_slots_10_out_uop_iq_type_0 : _T_302 ? issue_slots_9_out_uop_iq_type_0 : issue_slots_8_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_iq_type_1 = _T_303 ? issue_slots_10_out_uop_iq_type_1 : _T_302 ? issue_slots_9_out_uop_iq_type_1 : issue_slots_8_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_iq_type_2 = _T_303 ? issue_slots_10_out_uop_iq_type_2 : _T_302 ? issue_slots_9_out_uop_iq_type_2 : issue_slots_8_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_iq_type_3 = _T_303 ? issue_slots_10_out_uop_iq_type_3 : _T_302 ? issue_slots_9_out_uop_iq_type_3 : issue_slots_8_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_debug_pc = _T_303 ? issue_slots_10_out_uop_debug_pc : _T_302 ? issue_slots_9_out_uop_debug_pc : issue_slots_8_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_rvc = _T_303 ? issue_slots_10_out_uop_is_rvc : _T_302 ? issue_slots_9_out_uop_is_rvc : issue_slots_8_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_debug_inst = _T_303 ? issue_slots_10_out_uop_debug_inst : _T_302 ? issue_slots_9_out_uop_debug_inst : issue_slots_8_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_inst = _T_303 ? issue_slots_10_out_uop_inst : _T_302 ? issue_slots_9_out_uop_inst : issue_slots_8_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_7_clear_T = |shamts_oh_7; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_7_clear = _issue_slots_7_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_305 = shamts_oh_10 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_306 = shamts_oh_11 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_8_in_uop_valid = _T_306 ? issue_slots_11_will_be_valid : _T_305 ? issue_slots_10_will_be_valid : shamts_oh_9 == 3'h1 & issue_slots_9_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_8_in_uop_bits_debug_tsrc = _T_306 ? issue_slots_11_out_uop_debug_tsrc : _T_305 ? issue_slots_10_out_uop_debug_tsrc : issue_slots_9_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_debug_fsrc = _T_306 ? issue_slots_11_out_uop_debug_fsrc : _T_305 ? issue_slots_10_out_uop_debug_fsrc : issue_slots_9_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_bp_xcpt_if = _T_306 ? issue_slots_11_out_uop_bp_xcpt_if : _T_305 ? issue_slots_10_out_uop_bp_xcpt_if : issue_slots_9_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_bp_debug_if = _T_306 ? issue_slots_11_out_uop_bp_debug_if : _T_305 ? issue_slots_10_out_uop_bp_debug_if : issue_slots_9_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_xcpt_ma_if = _T_306 ? issue_slots_11_out_uop_xcpt_ma_if : _T_305 ? issue_slots_10_out_uop_xcpt_ma_if : issue_slots_9_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_xcpt_ae_if = _T_306 ? issue_slots_11_out_uop_xcpt_ae_if : _T_305 ? issue_slots_10_out_uop_xcpt_ae_if : issue_slots_9_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_xcpt_pf_if = _T_306 ? issue_slots_11_out_uop_xcpt_pf_if : _T_305 ? issue_slots_10_out_uop_xcpt_pf_if : issue_slots_9_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_typ = _T_306 ? issue_slots_11_out_uop_fp_typ : _T_305 ? issue_slots_10_out_uop_fp_typ : issue_slots_9_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_rm = _T_306 ? issue_slots_11_out_uop_fp_rm : _T_305 ? issue_slots_10_out_uop_fp_rm : issue_slots_9_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_val = _T_306 ? issue_slots_11_out_uop_fp_val : _T_305 ? issue_slots_10_out_uop_fp_val : issue_slots_9_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fcn_op = _T_306 ? issue_slots_11_out_uop_fcn_op : _T_305 ? issue_slots_10_out_uop_fcn_op : issue_slots_9_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fcn_dw = _T_306 ? issue_slots_11_out_uop_fcn_dw : _T_305 ? issue_slots_10_out_uop_fcn_dw : issue_slots_9_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_frs3_en = _T_306 ? issue_slots_11_out_uop_frs3_en : _T_305 ? issue_slots_10_out_uop_frs3_en : issue_slots_9_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_lrs2_rtype = _T_306 ? issue_slots_11_out_uop_lrs2_rtype : _T_305 ? issue_slots_10_out_uop_lrs2_rtype : issue_slots_9_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_lrs1_rtype = _T_306 ? issue_slots_11_out_uop_lrs1_rtype : _T_305 ? issue_slots_10_out_uop_lrs1_rtype : issue_slots_9_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_dst_rtype = _T_306 ? issue_slots_11_out_uop_dst_rtype : _T_305 ? issue_slots_10_out_uop_dst_rtype : issue_slots_9_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_lrs3 = _T_306 ? issue_slots_11_out_uop_lrs3 : _T_305 ? issue_slots_10_out_uop_lrs3 : issue_slots_9_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_lrs2 = _T_306 ? issue_slots_11_out_uop_lrs2 : _T_305 ? issue_slots_10_out_uop_lrs2 : issue_slots_9_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_lrs1 = _T_306 ? issue_slots_11_out_uop_lrs1 : _T_305 ? issue_slots_10_out_uop_lrs1 : issue_slots_9_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_ldst = _T_306 ? issue_slots_11_out_uop_ldst : _T_305 ? issue_slots_10_out_uop_ldst : issue_slots_9_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_ldst_is_rs1 = _T_306 ? issue_slots_11_out_uop_ldst_is_rs1 : _T_305 ? issue_slots_10_out_uop_ldst_is_rs1 : issue_slots_9_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_csr_cmd = _T_306 ? issue_slots_11_out_uop_csr_cmd : _T_305 ? issue_slots_10_out_uop_csr_cmd : issue_slots_9_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_flush_on_commit = _T_306 ? issue_slots_11_out_uop_flush_on_commit : _T_305 ? issue_slots_10_out_uop_flush_on_commit : issue_slots_9_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_unique = _T_306 ? issue_slots_11_out_uop_is_unique : _T_305 ? issue_slots_10_out_uop_is_unique : issue_slots_9_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_uses_stq = _T_306 ? issue_slots_11_out_uop_uses_stq : _T_305 ? issue_slots_10_out_uop_uses_stq : issue_slots_9_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_uses_ldq = _T_306 ? issue_slots_11_out_uop_uses_ldq : _T_305 ? issue_slots_10_out_uop_uses_ldq : issue_slots_9_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_mem_signed = _T_306 ? issue_slots_11_out_uop_mem_signed : _T_305 ? issue_slots_10_out_uop_mem_signed : issue_slots_9_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_mem_size = _T_306 ? issue_slots_11_out_uop_mem_size : _T_305 ? issue_slots_10_out_uop_mem_size : issue_slots_9_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_mem_cmd = _T_306 ? issue_slots_11_out_uop_mem_cmd : _T_305 ? issue_slots_10_out_uop_mem_cmd : issue_slots_9_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_exc_cause = _T_306 ? issue_slots_11_out_uop_exc_cause : _T_305 ? issue_slots_10_out_uop_exc_cause : issue_slots_9_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_exception = _T_306 ? issue_slots_11_out_uop_exception : _T_305 ? issue_slots_10_out_uop_exception : issue_slots_9_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_stale_pdst = _T_306 ? issue_slots_11_out_uop_stale_pdst : _T_305 ? issue_slots_10_out_uop_stale_pdst : issue_slots_9_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_ppred_busy = _T_306 ? issue_slots_11_out_uop_ppred_busy : _T_305 ? issue_slots_10_out_uop_ppred_busy : issue_slots_9_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_prs3_busy = _T_306 ? issue_slots_11_out_uop_prs3_busy : _T_305 ? issue_slots_10_out_uop_prs3_busy : issue_slots_9_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_prs2_busy = _T_306 ? issue_slots_11_out_uop_prs2_busy : _T_305 ? issue_slots_10_out_uop_prs2_busy : issue_slots_9_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_prs1_busy = _T_306 ? issue_slots_11_out_uop_prs1_busy : _T_305 ? issue_slots_10_out_uop_prs1_busy : issue_slots_9_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_ppred = _T_306 ? issue_slots_11_out_uop_ppred : _T_305 ? issue_slots_10_out_uop_ppred : issue_slots_9_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_prs3 = _T_306 ? issue_slots_11_out_uop_prs3 : _T_305 ? issue_slots_10_out_uop_prs3 : issue_slots_9_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_prs2 = _T_306 ? issue_slots_11_out_uop_prs2 : _T_305 ? issue_slots_10_out_uop_prs2 : issue_slots_9_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_prs1 = _T_306 ? issue_slots_11_out_uop_prs1 : _T_305 ? issue_slots_10_out_uop_prs1 : issue_slots_9_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_pdst = _T_306 ? issue_slots_11_out_uop_pdst : _T_305 ? issue_slots_10_out_uop_pdst : issue_slots_9_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_rxq_idx = _T_306 ? issue_slots_11_out_uop_rxq_idx : _T_305 ? issue_slots_10_out_uop_rxq_idx : issue_slots_9_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_stq_idx = _T_306 ? issue_slots_11_out_uop_stq_idx : _T_305 ? issue_slots_10_out_uop_stq_idx : issue_slots_9_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_ldq_idx = _T_306 ? issue_slots_11_out_uop_ldq_idx : _T_305 ? issue_slots_10_out_uop_ldq_idx : issue_slots_9_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_rob_idx = _T_306 ? issue_slots_11_out_uop_rob_idx : _T_305 ? issue_slots_10_out_uop_rob_idx : issue_slots_9_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_vec = _T_306 ? issue_slots_11_out_uop_fp_ctrl_vec : _T_305 ? issue_slots_10_out_uop_fp_ctrl_vec : issue_slots_9_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_wflags = _T_306 ? issue_slots_11_out_uop_fp_ctrl_wflags : _T_305 ? issue_slots_10_out_uop_fp_ctrl_wflags : issue_slots_9_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_sqrt = _T_306 ? issue_slots_11_out_uop_fp_ctrl_sqrt : _T_305 ? issue_slots_10_out_uop_fp_ctrl_sqrt : issue_slots_9_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_div = _T_306 ? issue_slots_11_out_uop_fp_ctrl_div : _T_305 ? issue_slots_10_out_uop_fp_ctrl_div : issue_slots_9_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_fma = _T_306 ? issue_slots_11_out_uop_fp_ctrl_fma : _T_305 ? issue_slots_10_out_uop_fp_ctrl_fma : issue_slots_9_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_fastpipe = _T_306 ? issue_slots_11_out_uop_fp_ctrl_fastpipe : _T_305 ? issue_slots_10_out_uop_fp_ctrl_fastpipe : issue_slots_9_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_toint = _T_306 ? issue_slots_11_out_uop_fp_ctrl_toint : _T_305 ? issue_slots_10_out_uop_fp_ctrl_toint : issue_slots_9_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_fromint = _T_306 ? issue_slots_11_out_uop_fp_ctrl_fromint : _T_305 ? issue_slots_10_out_uop_fp_ctrl_fromint : issue_slots_9_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_typeTagOut = _T_306 ? issue_slots_11_out_uop_fp_ctrl_typeTagOut : _T_305 ? issue_slots_10_out_uop_fp_ctrl_typeTagOut : issue_slots_9_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_typeTagIn = _T_306 ? issue_slots_11_out_uop_fp_ctrl_typeTagIn : _T_305 ? issue_slots_10_out_uop_fp_ctrl_typeTagIn : issue_slots_9_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_swap23 = _T_306 ? issue_slots_11_out_uop_fp_ctrl_swap23 : _T_305 ? issue_slots_10_out_uop_fp_ctrl_swap23 : issue_slots_9_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_swap12 = _T_306 ? issue_slots_11_out_uop_fp_ctrl_swap12 : _T_305 ? issue_slots_10_out_uop_fp_ctrl_swap12 : issue_slots_9_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_ren3 = _T_306 ? issue_slots_11_out_uop_fp_ctrl_ren3 : _T_305 ? issue_slots_10_out_uop_fp_ctrl_ren3 : issue_slots_9_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_ren2 = _T_306 ? issue_slots_11_out_uop_fp_ctrl_ren2 : _T_305 ? issue_slots_10_out_uop_fp_ctrl_ren2 : issue_slots_9_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_ren1 = _T_306 ? issue_slots_11_out_uop_fp_ctrl_ren1 : _T_305 ? issue_slots_10_out_uop_fp_ctrl_ren1 : issue_slots_9_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_wen = _T_306 ? issue_slots_11_out_uop_fp_ctrl_wen : _T_305 ? issue_slots_10_out_uop_fp_ctrl_wen : issue_slots_9_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_ldst = _T_306 ? issue_slots_11_out_uop_fp_ctrl_ldst : _T_305 ? issue_slots_10_out_uop_fp_ctrl_ldst : issue_slots_9_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_op2_sel = _T_306 ? issue_slots_11_out_uop_op2_sel : _T_305 ? issue_slots_10_out_uop_op2_sel : issue_slots_9_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_op1_sel = _T_306 ? issue_slots_11_out_uop_op1_sel : _T_305 ? issue_slots_10_out_uop_op1_sel : issue_slots_9_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_imm_packed = _T_306 ? issue_slots_11_out_uop_imm_packed : _T_305 ? issue_slots_10_out_uop_imm_packed : issue_slots_9_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_pimm = _T_306 ? issue_slots_11_out_uop_pimm : _T_305 ? issue_slots_10_out_uop_pimm : issue_slots_9_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_imm_sel = _T_306 ? issue_slots_11_out_uop_imm_sel : _T_305 ? issue_slots_10_out_uop_imm_sel : issue_slots_9_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_imm_rename = _T_306 ? issue_slots_11_out_uop_imm_rename : _T_305 ? issue_slots_10_out_uop_imm_rename : issue_slots_9_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_taken = _T_306 ? issue_slots_11_out_uop_taken : _T_305 ? issue_slots_10_out_uop_taken : issue_slots_9_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_pc_lob = _T_306 ? issue_slots_11_out_uop_pc_lob : _T_305 ? issue_slots_10_out_uop_pc_lob : issue_slots_9_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_edge_inst = _T_306 ? issue_slots_11_out_uop_edge_inst : _T_305 ? issue_slots_10_out_uop_edge_inst : issue_slots_9_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_ftq_idx = _T_306 ? issue_slots_11_out_uop_ftq_idx : _T_305 ? issue_slots_10_out_uop_ftq_idx : issue_slots_9_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_mov = _T_306 ? issue_slots_11_out_uop_is_mov : _T_305 ? issue_slots_10_out_uop_is_mov : issue_slots_9_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_rocc = _T_306 ? issue_slots_11_out_uop_is_rocc : _T_305 ? issue_slots_10_out_uop_is_rocc : issue_slots_9_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_sys_pc2epc = _T_306 ? issue_slots_11_out_uop_is_sys_pc2epc : _T_305 ? issue_slots_10_out_uop_is_sys_pc2epc : issue_slots_9_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_eret = _T_306 ? issue_slots_11_out_uop_is_eret : _T_305 ? issue_slots_10_out_uop_is_eret : issue_slots_9_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_amo = _T_306 ? issue_slots_11_out_uop_is_amo : _T_305 ? issue_slots_10_out_uop_is_amo : issue_slots_9_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_sfence = _T_306 ? issue_slots_11_out_uop_is_sfence : _T_305 ? issue_slots_10_out_uop_is_sfence : issue_slots_9_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_fencei = _T_306 ? issue_slots_11_out_uop_is_fencei : _T_305 ? issue_slots_10_out_uop_is_fencei : issue_slots_9_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_fence = _T_306 ? issue_slots_11_out_uop_is_fence : _T_305 ? issue_slots_10_out_uop_is_fence : issue_slots_9_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_sfb = _T_306 ? issue_slots_11_out_uop_is_sfb : _T_305 ? issue_slots_10_out_uop_is_sfb : issue_slots_9_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_br_type = _T_306 ? issue_slots_11_out_uop_br_type : _T_305 ? issue_slots_10_out_uop_br_type : issue_slots_9_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_br_tag = _T_306 ? issue_slots_11_out_uop_br_tag : _T_305 ? issue_slots_10_out_uop_br_tag : issue_slots_9_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_br_mask = _T_306 ? issue_slots_11_out_uop_br_mask : _T_305 ? issue_slots_10_out_uop_br_mask : issue_slots_9_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_dis_col_sel = _T_306 ? issue_slots_11_out_uop_dis_col_sel : _T_305 ? issue_slots_10_out_uop_dis_col_sel : issue_slots_9_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_iw_p3_bypass_hint = _T_306 ? issue_slots_11_out_uop_iw_p3_bypass_hint : _T_305 ? issue_slots_10_out_uop_iw_p3_bypass_hint : issue_slots_9_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_iw_p2_bypass_hint = _T_306 ? issue_slots_11_out_uop_iw_p2_bypass_hint : _T_305 ? issue_slots_10_out_uop_iw_p2_bypass_hint : issue_slots_9_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_iw_p1_bypass_hint = _T_306 ? issue_slots_11_out_uop_iw_p1_bypass_hint : _T_305 ? issue_slots_10_out_uop_iw_p1_bypass_hint : issue_slots_9_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_iw_p2_speculative_child = _T_306 ? issue_slots_11_out_uop_iw_p2_speculative_child : _T_305 ? issue_slots_10_out_uop_iw_p2_speculative_child : issue_slots_9_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_iw_p1_speculative_child = _T_306 ? issue_slots_11_out_uop_iw_p1_speculative_child : _T_305 ? issue_slots_10_out_uop_iw_p1_speculative_child : issue_slots_9_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_iw_issued_partial_dgen = _T_306 ? issue_slots_11_out_uop_iw_issued_partial_dgen : _T_305 ? issue_slots_10_out_uop_iw_issued_partial_dgen : issue_slots_9_out_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_iw_issued_partial_agen = _T_306 ? issue_slots_11_out_uop_iw_issued_partial_agen : _T_305 ? issue_slots_10_out_uop_iw_issued_partial_agen : issue_slots_9_out_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_iw_issued = _T_306 ? issue_slots_11_out_uop_iw_issued : _T_305 ? issue_slots_10_out_uop_iw_issued : issue_slots_9_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_0 = _T_306 ? issue_slots_11_out_uop_fu_code_0 : _T_305 ? issue_slots_10_out_uop_fu_code_0 : issue_slots_9_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_1 = _T_306 ? issue_slots_11_out_uop_fu_code_1 : _T_305 ? issue_slots_10_out_uop_fu_code_1 : issue_slots_9_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_2 = _T_306 ? issue_slots_11_out_uop_fu_code_2 : _T_305 ? issue_slots_10_out_uop_fu_code_2 : issue_slots_9_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_3 = _T_306 ? issue_slots_11_out_uop_fu_code_3 : _T_305 ? issue_slots_10_out_uop_fu_code_3 : issue_slots_9_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_4 = _T_306 ? issue_slots_11_out_uop_fu_code_4 : _T_305 ? issue_slots_10_out_uop_fu_code_4 : issue_slots_9_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_5 = _T_306 ? issue_slots_11_out_uop_fu_code_5 : _T_305 ? issue_slots_10_out_uop_fu_code_5 : issue_slots_9_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_6 = _T_306 ? issue_slots_11_out_uop_fu_code_6 : _T_305 ? issue_slots_10_out_uop_fu_code_6 : issue_slots_9_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_7 = _T_306 ? issue_slots_11_out_uop_fu_code_7 : _T_305 ? issue_slots_10_out_uop_fu_code_7 : issue_slots_9_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_8 = _T_306 ? issue_slots_11_out_uop_fu_code_8 : _T_305 ? issue_slots_10_out_uop_fu_code_8 : issue_slots_9_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_9 = _T_306 ? issue_slots_11_out_uop_fu_code_9 : _T_305 ? issue_slots_10_out_uop_fu_code_9 : issue_slots_9_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_iq_type_0 = _T_306 ? issue_slots_11_out_uop_iq_type_0 : _T_305 ? issue_slots_10_out_uop_iq_type_0 : issue_slots_9_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_iq_type_1 = _T_306 ? issue_slots_11_out_uop_iq_type_1 : _T_305 ? issue_slots_10_out_uop_iq_type_1 : issue_slots_9_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_iq_type_2 = _T_306 ? issue_slots_11_out_uop_iq_type_2 : _T_305 ? issue_slots_10_out_uop_iq_type_2 : issue_slots_9_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_iq_type_3 = _T_306 ? issue_slots_11_out_uop_iq_type_3 : _T_305 ? issue_slots_10_out_uop_iq_type_3 : issue_slots_9_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_debug_pc = _T_306 ? issue_slots_11_out_uop_debug_pc : _T_305 ? issue_slots_10_out_uop_debug_pc : issue_slots_9_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_rvc = _T_306 ? issue_slots_11_out_uop_is_rvc : _T_305 ? issue_slots_10_out_uop_is_rvc : issue_slots_9_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_debug_inst = _T_306 ? issue_slots_11_out_uop_debug_inst : _T_305 ? issue_slots_10_out_uop_debug_inst : issue_slots_9_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_inst = _T_306 ? issue_slots_11_out_uop_inst : _T_305 ? issue_slots_10_out_uop_inst : issue_slots_9_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_8_clear_T = |shamts_oh_8; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_8_clear = _issue_slots_8_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_308 = shamts_oh_11 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_309 = shamts_oh_12 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_9_in_uop_valid = _T_309 ? issue_slots_12_will_be_valid : _T_308 ? issue_slots_11_will_be_valid : shamts_oh_10 == 3'h1 & issue_slots_10_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_9_in_uop_bits_debug_tsrc = _T_309 ? issue_slots_12_out_uop_debug_tsrc : _T_308 ? issue_slots_11_out_uop_debug_tsrc : issue_slots_10_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_debug_fsrc = _T_309 ? issue_slots_12_out_uop_debug_fsrc : _T_308 ? issue_slots_11_out_uop_debug_fsrc : issue_slots_10_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_bp_xcpt_if = _T_309 ? issue_slots_12_out_uop_bp_xcpt_if : _T_308 ? issue_slots_11_out_uop_bp_xcpt_if : issue_slots_10_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_bp_debug_if = _T_309 ? issue_slots_12_out_uop_bp_debug_if : _T_308 ? issue_slots_11_out_uop_bp_debug_if : issue_slots_10_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_xcpt_ma_if = _T_309 ? issue_slots_12_out_uop_xcpt_ma_if : _T_308 ? issue_slots_11_out_uop_xcpt_ma_if : issue_slots_10_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_xcpt_ae_if = _T_309 ? issue_slots_12_out_uop_xcpt_ae_if : _T_308 ? issue_slots_11_out_uop_xcpt_ae_if : issue_slots_10_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_xcpt_pf_if = _T_309 ? issue_slots_12_out_uop_xcpt_pf_if : _T_308 ? issue_slots_11_out_uop_xcpt_pf_if : issue_slots_10_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_typ = _T_309 ? issue_slots_12_out_uop_fp_typ : _T_308 ? issue_slots_11_out_uop_fp_typ : issue_slots_10_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_rm = _T_309 ? issue_slots_12_out_uop_fp_rm : _T_308 ? issue_slots_11_out_uop_fp_rm : issue_slots_10_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_val = _T_309 ? issue_slots_12_out_uop_fp_val : _T_308 ? issue_slots_11_out_uop_fp_val : issue_slots_10_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fcn_op = _T_309 ? issue_slots_12_out_uop_fcn_op : _T_308 ? issue_slots_11_out_uop_fcn_op : issue_slots_10_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fcn_dw = _T_309 ? issue_slots_12_out_uop_fcn_dw : _T_308 ? issue_slots_11_out_uop_fcn_dw : issue_slots_10_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_frs3_en = _T_309 ? issue_slots_12_out_uop_frs3_en : _T_308 ? issue_slots_11_out_uop_frs3_en : issue_slots_10_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_lrs2_rtype = _T_309 ? issue_slots_12_out_uop_lrs2_rtype : _T_308 ? issue_slots_11_out_uop_lrs2_rtype : issue_slots_10_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_lrs1_rtype = _T_309 ? issue_slots_12_out_uop_lrs1_rtype : _T_308 ? issue_slots_11_out_uop_lrs1_rtype : issue_slots_10_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_dst_rtype = _T_309 ? issue_slots_12_out_uop_dst_rtype : _T_308 ? issue_slots_11_out_uop_dst_rtype : issue_slots_10_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_lrs3 = _T_309 ? issue_slots_12_out_uop_lrs3 : _T_308 ? issue_slots_11_out_uop_lrs3 : issue_slots_10_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_lrs2 = _T_309 ? issue_slots_12_out_uop_lrs2 : _T_308 ? issue_slots_11_out_uop_lrs2 : issue_slots_10_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_lrs1 = _T_309 ? issue_slots_12_out_uop_lrs1 : _T_308 ? issue_slots_11_out_uop_lrs1 : issue_slots_10_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_ldst = _T_309 ? issue_slots_12_out_uop_ldst : _T_308 ? issue_slots_11_out_uop_ldst : issue_slots_10_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_ldst_is_rs1 = _T_309 ? issue_slots_12_out_uop_ldst_is_rs1 : _T_308 ? issue_slots_11_out_uop_ldst_is_rs1 : issue_slots_10_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_csr_cmd = _T_309 ? issue_slots_12_out_uop_csr_cmd : _T_308 ? issue_slots_11_out_uop_csr_cmd : issue_slots_10_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_flush_on_commit = _T_309 ? issue_slots_12_out_uop_flush_on_commit : _T_308 ? issue_slots_11_out_uop_flush_on_commit : issue_slots_10_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_unique = _T_309 ? issue_slots_12_out_uop_is_unique : _T_308 ? issue_slots_11_out_uop_is_unique : issue_slots_10_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_uses_stq = _T_309 ? issue_slots_12_out_uop_uses_stq : _T_308 ? issue_slots_11_out_uop_uses_stq : issue_slots_10_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_uses_ldq = _T_309 ? issue_slots_12_out_uop_uses_ldq : _T_308 ? issue_slots_11_out_uop_uses_ldq : issue_slots_10_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_mem_signed = _T_309 ? issue_slots_12_out_uop_mem_signed : _T_308 ? issue_slots_11_out_uop_mem_signed : issue_slots_10_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_mem_size = _T_309 ? issue_slots_12_out_uop_mem_size : _T_308 ? issue_slots_11_out_uop_mem_size : issue_slots_10_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_mem_cmd = _T_309 ? issue_slots_12_out_uop_mem_cmd : _T_308 ? issue_slots_11_out_uop_mem_cmd : issue_slots_10_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_exc_cause = _T_309 ? issue_slots_12_out_uop_exc_cause : _T_308 ? issue_slots_11_out_uop_exc_cause : issue_slots_10_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_exception = _T_309 ? issue_slots_12_out_uop_exception : _T_308 ? issue_slots_11_out_uop_exception : issue_slots_10_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_stale_pdst = _T_309 ? issue_slots_12_out_uop_stale_pdst : _T_308 ? issue_slots_11_out_uop_stale_pdst : issue_slots_10_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_ppred_busy = _T_309 ? issue_slots_12_out_uop_ppred_busy : _T_308 ? issue_slots_11_out_uop_ppred_busy : issue_slots_10_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_prs3_busy = _T_309 ? issue_slots_12_out_uop_prs3_busy : _T_308 ? issue_slots_11_out_uop_prs3_busy : issue_slots_10_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_prs2_busy = _T_309 ? issue_slots_12_out_uop_prs2_busy : _T_308 ? issue_slots_11_out_uop_prs2_busy : issue_slots_10_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_prs1_busy = _T_309 ? issue_slots_12_out_uop_prs1_busy : _T_308 ? issue_slots_11_out_uop_prs1_busy : issue_slots_10_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_ppred = _T_309 ? issue_slots_12_out_uop_ppred : _T_308 ? issue_slots_11_out_uop_ppred : issue_slots_10_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_prs3 = _T_309 ? issue_slots_12_out_uop_prs3 : _T_308 ? issue_slots_11_out_uop_prs3 : issue_slots_10_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_prs2 = _T_309 ? issue_slots_12_out_uop_prs2 : _T_308 ? issue_slots_11_out_uop_prs2 : issue_slots_10_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_prs1 = _T_309 ? issue_slots_12_out_uop_prs1 : _T_308 ? issue_slots_11_out_uop_prs1 : issue_slots_10_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_pdst = _T_309 ? issue_slots_12_out_uop_pdst : _T_308 ? issue_slots_11_out_uop_pdst : issue_slots_10_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_rxq_idx = _T_309 ? issue_slots_12_out_uop_rxq_idx : _T_308 ? issue_slots_11_out_uop_rxq_idx : issue_slots_10_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_stq_idx = _T_309 ? issue_slots_12_out_uop_stq_idx : _T_308 ? issue_slots_11_out_uop_stq_idx : issue_slots_10_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_ldq_idx = _T_309 ? issue_slots_12_out_uop_ldq_idx : _T_308 ? issue_slots_11_out_uop_ldq_idx : issue_slots_10_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_rob_idx = _T_309 ? issue_slots_12_out_uop_rob_idx : _T_308 ? issue_slots_11_out_uop_rob_idx : issue_slots_10_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_vec = _T_309 ? issue_slots_12_out_uop_fp_ctrl_vec : _T_308 ? issue_slots_11_out_uop_fp_ctrl_vec : issue_slots_10_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_wflags = _T_309 ? issue_slots_12_out_uop_fp_ctrl_wflags : _T_308 ? issue_slots_11_out_uop_fp_ctrl_wflags : issue_slots_10_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_sqrt = _T_309 ? issue_slots_12_out_uop_fp_ctrl_sqrt : _T_308 ? issue_slots_11_out_uop_fp_ctrl_sqrt : issue_slots_10_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_div = _T_309 ? issue_slots_12_out_uop_fp_ctrl_div : _T_308 ? issue_slots_11_out_uop_fp_ctrl_div : issue_slots_10_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_fma = _T_309 ? issue_slots_12_out_uop_fp_ctrl_fma : _T_308 ? issue_slots_11_out_uop_fp_ctrl_fma : issue_slots_10_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_fastpipe = _T_309 ? issue_slots_12_out_uop_fp_ctrl_fastpipe : _T_308 ? issue_slots_11_out_uop_fp_ctrl_fastpipe : issue_slots_10_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_toint = _T_309 ? issue_slots_12_out_uop_fp_ctrl_toint : _T_308 ? issue_slots_11_out_uop_fp_ctrl_toint : issue_slots_10_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_fromint = _T_309 ? issue_slots_12_out_uop_fp_ctrl_fromint : _T_308 ? issue_slots_11_out_uop_fp_ctrl_fromint : issue_slots_10_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_typeTagOut = _T_309 ? issue_slots_12_out_uop_fp_ctrl_typeTagOut : _T_308 ? issue_slots_11_out_uop_fp_ctrl_typeTagOut : issue_slots_10_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_typeTagIn = _T_309 ? issue_slots_12_out_uop_fp_ctrl_typeTagIn : _T_308 ? issue_slots_11_out_uop_fp_ctrl_typeTagIn : issue_slots_10_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_swap23 = _T_309 ? issue_slots_12_out_uop_fp_ctrl_swap23 : _T_308 ? issue_slots_11_out_uop_fp_ctrl_swap23 : issue_slots_10_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_swap12 = _T_309 ? issue_slots_12_out_uop_fp_ctrl_swap12 : _T_308 ? issue_slots_11_out_uop_fp_ctrl_swap12 : issue_slots_10_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_ren3 = _T_309 ? issue_slots_12_out_uop_fp_ctrl_ren3 : _T_308 ? issue_slots_11_out_uop_fp_ctrl_ren3 : issue_slots_10_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_ren2 = _T_309 ? issue_slots_12_out_uop_fp_ctrl_ren2 : _T_308 ? issue_slots_11_out_uop_fp_ctrl_ren2 : issue_slots_10_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_ren1 = _T_309 ? issue_slots_12_out_uop_fp_ctrl_ren1 : _T_308 ? issue_slots_11_out_uop_fp_ctrl_ren1 : issue_slots_10_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_wen = _T_309 ? issue_slots_12_out_uop_fp_ctrl_wen : _T_308 ? issue_slots_11_out_uop_fp_ctrl_wen : issue_slots_10_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_ldst = _T_309 ? issue_slots_12_out_uop_fp_ctrl_ldst : _T_308 ? issue_slots_11_out_uop_fp_ctrl_ldst : issue_slots_10_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_op2_sel = _T_309 ? issue_slots_12_out_uop_op2_sel : _T_308 ? issue_slots_11_out_uop_op2_sel : issue_slots_10_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_op1_sel = _T_309 ? issue_slots_12_out_uop_op1_sel : _T_308 ? issue_slots_11_out_uop_op1_sel : issue_slots_10_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_imm_packed = _T_309 ? issue_slots_12_out_uop_imm_packed : _T_308 ? issue_slots_11_out_uop_imm_packed : issue_slots_10_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_pimm = _T_309 ? issue_slots_12_out_uop_pimm : _T_308 ? issue_slots_11_out_uop_pimm : issue_slots_10_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_imm_sel = _T_309 ? issue_slots_12_out_uop_imm_sel : _T_308 ? issue_slots_11_out_uop_imm_sel : issue_slots_10_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_imm_rename = _T_309 ? issue_slots_12_out_uop_imm_rename : _T_308 ? issue_slots_11_out_uop_imm_rename : issue_slots_10_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_taken = _T_309 ? issue_slots_12_out_uop_taken : _T_308 ? issue_slots_11_out_uop_taken : issue_slots_10_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_pc_lob = _T_309 ? issue_slots_12_out_uop_pc_lob : _T_308 ? issue_slots_11_out_uop_pc_lob : issue_slots_10_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_edge_inst = _T_309 ? issue_slots_12_out_uop_edge_inst : _T_308 ? issue_slots_11_out_uop_edge_inst : issue_slots_10_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_ftq_idx = _T_309 ? issue_slots_12_out_uop_ftq_idx : _T_308 ? issue_slots_11_out_uop_ftq_idx : issue_slots_10_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_mov = _T_309 ? issue_slots_12_out_uop_is_mov : _T_308 ? issue_slots_11_out_uop_is_mov : issue_slots_10_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_rocc = _T_309 ? issue_slots_12_out_uop_is_rocc : _T_308 ? issue_slots_11_out_uop_is_rocc : issue_slots_10_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_sys_pc2epc = _T_309 ? issue_slots_12_out_uop_is_sys_pc2epc : _T_308 ? issue_slots_11_out_uop_is_sys_pc2epc : issue_slots_10_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_eret = _T_309 ? issue_slots_12_out_uop_is_eret : _T_308 ? issue_slots_11_out_uop_is_eret : issue_slots_10_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_amo = _T_309 ? issue_slots_12_out_uop_is_amo : _T_308 ? issue_slots_11_out_uop_is_amo : issue_slots_10_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_sfence = _T_309 ? issue_slots_12_out_uop_is_sfence : _T_308 ? issue_slots_11_out_uop_is_sfence : issue_slots_10_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_fencei = _T_309 ? issue_slots_12_out_uop_is_fencei : _T_308 ? issue_slots_11_out_uop_is_fencei : issue_slots_10_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_fence = _T_309 ? issue_slots_12_out_uop_is_fence : _T_308 ? issue_slots_11_out_uop_is_fence : issue_slots_10_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_sfb = _T_309 ? issue_slots_12_out_uop_is_sfb : _T_308 ? issue_slots_11_out_uop_is_sfb : issue_slots_10_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_br_type = _T_309 ? issue_slots_12_out_uop_br_type : _T_308 ? issue_slots_11_out_uop_br_type : issue_slots_10_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_br_tag = _T_309 ? issue_slots_12_out_uop_br_tag : _T_308 ? issue_slots_11_out_uop_br_tag : issue_slots_10_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_br_mask = _T_309 ? issue_slots_12_out_uop_br_mask : _T_308 ? issue_slots_11_out_uop_br_mask : issue_slots_10_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_dis_col_sel = _T_309 ? issue_slots_12_out_uop_dis_col_sel : _T_308 ? issue_slots_11_out_uop_dis_col_sel : issue_slots_10_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_iw_p3_bypass_hint = _T_309 ? issue_slots_12_out_uop_iw_p3_bypass_hint : _T_308 ? issue_slots_11_out_uop_iw_p3_bypass_hint : issue_slots_10_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_iw_p2_bypass_hint = _T_309 ? issue_slots_12_out_uop_iw_p2_bypass_hint : _T_308 ? issue_slots_11_out_uop_iw_p2_bypass_hint : issue_slots_10_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_iw_p1_bypass_hint = _T_309 ? issue_slots_12_out_uop_iw_p1_bypass_hint : _T_308 ? issue_slots_11_out_uop_iw_p1_bypass_hint : issue_slots_10_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_iw_p2_speculative_child = _T_309 ? issue_slots_12_out_uop_iw_p2_speculative_child : _T_308 ? issue_slots_11_out_uop_iw_p2_speculative_child : issue_slots_10_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_iw_p1_speculative_child = _T_309 ? issue_slots_12_out_uop_iw_p1_speculative_child : _T_308 ? issue_slots_11_out_uop_iw_p1_speculative_child : issue_slots_10_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_iw_issued_partial_dgen = _T_309 ? issue_slots_12_out_uop_iw_issued_partial_dgen : _T_308 ? issue_slots_11_out_uop_iw_issued_partial_dgen : issue_slots_10_out_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_iw_issued_partial_agen = _T_309 ? issue_slots_12_out_uop_iw_issued_partial_agen : _T_308 ? issue_slots_11_out_uop_iw_issued_partial_agen : issue_slots_10_out_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_iw_issued = _T_309 ? issue_slots_12_out_uop_iw_issued : _T_308 ? issue_slots_11_out_uop_iw_issued : issue_slots_10_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_0 = _T_309 ? issue_slots_12_out_uop_fu_code_0 : _T_308 ? issue_slots_11_out_uop_fu_code_0 : issue_slots_10_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_1 = _T_309 ? issue_slots_12_out_uop_fu_code_1 : _T_308 ? issue_slots_11_out_uop_fu_code_1 : issue_slots_10_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_2 = _T_309 ? issue_slots_12_out_uop_fu_code_2 : _T_308 ? issue_slots_11_out_uop_fu_code_2 : issue_slots_10_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_3 = _T_309 ? issue_slots_12_out_uop_fu_code_3 : _T_308 ? issue_slots_11_out_uop_fu_code_3 : issue_slots_10_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_4 = _T_309 ? issue_slots_12_out_uop_fu_code_4 : _T_308 ? issue_slots_11_out_uop_fu_code_4 : issue_slots_10_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_5 = _T_309 ? issue_slots_12_out_uop_fu_code_5 : _T_308 ? issue_slots_11_out_uop_fu_code_5 : issue_slots_10_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_6 = _T_309 ? issue_slots_12_out_uop_fu_code_6 : _T_308 ? issue_slots_11_out_uop_fu_code_6 : issue_slots_10_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_7 = _T_309 ? issue_slots_12_out_uop_fu_code_7 : _T_308 ? issue_slots_11_out_uop_fu_code_7 : issue_slots_10_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_8 = _T_309 ? issue_slots_12_out_uop_fu_code_8 : _T_308 ? issue_slots_11_out_uop_fu_code_8 : issue_slots_10_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_9 = _T_309 ? issue_slots_12_out_uop_fu_code_9 : _T_308 ? issue_slots_11_out_uop_fu_code_9 : issue_slots_10_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_iq_type_0 = _T_309 ? issue_slots_12_out_uop_iq_type_0 : _T_308 ? issue_slots_11_out_uop_iq_type_0 : issue_slots_10_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_iq_type_1 = _T_309 ? issue_slots_12_out_uop_iq_type_1 : _T_308 ? issue_slots_11_out_uop_iq_type_1 : issue_slots_10_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_iq_type_2 = _T_309 ? issue_slots_12_out_uop_iq_type_2 : _T_308 ? issue_slots_11_out_uop_iq_type_2 : issue_slots_10_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_iq_type_3 = _T_309 ? issue_slots_12_out_uop_iq_type_3 : _T_308 ? issue_slots_11_out_uop_iq_type_3 : issue_slots_10_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_debug_pc = _T_309 ? issue_slots_12_out_uop_debug_pc : _T_308 ? issue_slots_11_out_uop_debug_pc : issue_slots_10_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_rvc = _T_309 ? issue_slots_12_out_uop_is_rvc : _T_308 ? issue_slots_11_out_uop_is_rvc : issue_slots_10_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_debug_inst = _T_309 ? issue_slots_12_out_uop_debug_inst : _T_308 ? issue_slots_11_out_uop_debug_inst : issue_slots_10_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_inst = _T_309 ? issue_slots_12_out_uop_inst : _T_308 ? issue_slots_11_out_uop_inst : issue_slots_10_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_9_clear_T = |shamts_oh_9; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_9_clear = _issue_slots_9_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_311 = shamts_oh_12 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_312 = shamts_oh_13 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_10_in_uop_valid = _T_312 ? issue_slots_13_will_be_valid : _T_311 ? issue_slots_12_will_be_valid : shamts_oh_11 == 3'h1 & issue_slots_11_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_10_in_uop_bits_debug_tsrc = _T_312 ? issue_slots_13_out_uop_debug_tsrc : _T_311 ? issue_slots_12_out_uop_debug_tsrc : issue_slots_11_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_debug_fsrc = _T_312 ? issue_slots_13_out_uop_debug_fsrc : _T_311 ? issue_slots_12_out_uop_debug_fsrc : issue_slots_11_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_bp_xcpt_if = _T_312 ? issue_slots_13_out_uop_bp_xcpt_if : _T_311 ? issue_slots_12_out_uop_bp_xcpt_if : issue_slots_11_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_bp_debug_if = _T_312 ? issue_slots_13_out_uop_bp_debug_if : _T_311 ? issue_slots_12_out_uop_bp_debug_if : issue_slots_11_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_xcpt_ma_if = _T_312 ? issue_slots_13_out_uop_xcpt_ma_if : _T_311 ? issue_slots_12_out_uop_xcpt_ma_if : issue_slots_11_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_xcpt_ae_if = _T_312 ? issue_slots_13_out_uop_xcpt_ae_if : _T_311 ? issue_slots_12_out_uop_xcpt_ae_if : issue_slots_11_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_xcpt_pf_if = _T_312 ? issue_slots_13_out_uop_xcpt_pf_if : _T_311 ? issue_slots_12_out_uop_xcpt_pf_if : issue_slots_11_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_typ = _T_312 ? issue_slots_13_out_uop_fp_typ : _T_311 ? issue_slots_12_out_uop_fp_typ : issue_slots_11_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_rm = _T_312 ? issue_slots_13_out_uop_fp_rm : _T_311 ? issue_slots_12_out_uop_fp_rm : issue_slots_11_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_val = _T_312 ? issue_slots_13_out_uop_fp_val : _T_311 ? issue_slots_12_out_uop_fp_val : issue_slots_11_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fcn_op = _T_312 ? issue_slots_13_out_uop_fcn_op : _T_311 ? issue_slots_12_out_uop_fcn_op : issue_slots_11_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fcn_dw = _T_312 ? issue_slots_13_out_uop_fcn_dw : _T_311 ? issue_slots_12_out_uop_fcn_dw : issue_slots_11_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_frs3_en = _T_312 ? issue_slots_13_out_uop_frs3_en : _T_311 ? issue_slots_12_out_uop_frs3_en : issue_slots_11_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_lrs2_rtype = _T_312 ? issue_slots_13_out_uop_lrs2_rtype : _T_311 ? issue_slots_12_out_uop_lrs2_rtype : issue_slots_11_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_lrs1_rtype = _T_312 ? issue_slots_13_out_uop_lrs1_rtype : _T_311 ? issue_slots_12_out_uop_lrs1_rtype : issue_slots_11_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_dst_rtype = _T_312 ? issue_slots_13_out_uop_dst_rtype : _T_311 ? issue_slots_12_out_uop_dst_rtype : issue_slots_11_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_lrs3 = _T_312 ? issue_slots_13_out_uop_lrs3 : _T_311 ? issue_slots_12_out_uop_lrs3 : issue_slots_11_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_lrs2 = _T_312 ? issue_slots_13_out_uop_lrs2 : _T_311 ? issue_slots_12_out_uop_lrs2 : issue_slots_11_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_lrs1 = _T_312 ? issue_slots_13_out_uop_lrs1 : _T_311 ? issue_slots_12_out_uop_lrs1 : issue_slots_11_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_ldst = _T_312 ? issue_slots_13_out_uop_ldst : _T_311 ? issue_slots_12_out_uop_ldst : issue_slots_11_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_ldst_is_rs1 = _T_312 ? issue_slots_13_out_uop_ldst_is_rs1 : _T_311 ? issue_slots_12_out_uop_ldst_is_rs1 : issue_slots_11_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_csr_cmd = _T_312 ? issue_slots_13_out_uop_csr_cmd : _T_311 ? issue_slots_12_out_uop_csr_cmd : issue_slots_11_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_flush_on_commit = _T_312 ? issue_slots_13_out_uop_flush_on_commit : _T_311 ? issue_slots_12_out_uop_flush_on_commit : issue_slots_11_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_unique = _T_312 ? issue_slots_13_out_uop_is_unique : _T_311 ? issue_slots_12_out_uop_is_unique : issue_slots_11_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_uses_stq = _T_312 ? issue_slots_13_out_uop_uses_stq : _T_311 ? issue_slots_12_out_uop_uses_stq : issue_slots_11_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_uses_ldq = _T_312 ? issue_slots_13_out_uop_uses_ldq : _T_311 ? issue_slots_12_out_uop_uses_ldq : issue_slots_11_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_mem_signed = _T_312 ? issue_slots_13_out_uop_mem_signed : _T_311 ? issue_slots_12_out_uop_mem_signed : issue_slots_11_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_mem_size = _T_312 ? issue_slots_13_out_uop_mem_size : _T_311 ? issue_slots_12_out_uop_mem_size : issue_slots_11_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_mem_cmd = _T_312 ? issue_slots_13_out_uop_mem_cmd : _T_311 ? issue_slots_12_out_uop_mem_cmd : issue_slots_11_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_exc_cause = _T_312 ? issue_slots_13_out_uop_exc_cause : _T_311 ? issue_slots_12_out_uop_exc_cause : issue_slots_11_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_exception = _T_312 ? issue_slots_13_out_uop_exception : _T_311 ? issue_slots_12_out_uop_exception : issue_slots_11_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_stale_pdst = _T_312 ? issue_slots_13_out_uop_stale_pdst : _T_311 ? issue_slots_12_out_uop_stale_pdst : issue_slots_11_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_ppred_busy = _T_312 ? issue_slots_13_out_uop_ppred_busy : _T_311 ? issue_slots_12_out_uop_ppred_busy : issue_slots_11_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_prs3_busy = _T_312 ? issue_slots_13_out_uop_prs3_busy : _T_311 ? issue_slots_12_out_uop_prs3_busy : issue_slots_11_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_prs2_busy = _T_312 ? issue_slots_13_out_uop_prs2_busy : _T_311 ? issue_slots_12_out_uop_prs2_busy : issue_slots_11_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_prs1_busy = _T_312 ? issue_slots_13_out_uop_prs1_busy : _T_311 ? issue_slots_12_out_uop_prs1_busy : issue_slots_11_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_ppred = _T_312 ? issue_slots_13_out_uop_ppred : _T_311 ? issue_slots_12_out_uop_ppred : issue_slots_11_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_prs3 = _T_312 ? issue_slots_13_out_uop_prs3 : _T_311 ? issue_slots_12_out_uop_prs3 : issue_slots_11_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_prs2 = _T_312 ? issue_slots_13_out_uop_prs2 : _T_311 ? issue_slots_12_out_uop_prs2 : issue_slots_11_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_prs1 = _T_312 ? issue_slots_13_out_uop_prs1 : _T_311 ? issue_slots_12_out_uop_prs1 : issue_slots_11_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_pdst = _T_312 ? issue_slots_13_out_uop_pdst : _T_311 ? issue_slots_12_out_uop_pdst : issue_slots_11_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_rxq_idx = _T_312 ? issue_slots_13_out_uop_rxq_idx : _T_311 ? issue_slots_12_out_uop_rxq_idx : issue_slots_11_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_stq_idx = _T_312 ? issue_slots_13_out_uop_stq_idx : _T_311 ? issue_slots_12_out_uop_stq_idx : issue_slots_11_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_ldq_idx = _T_312 ? issue_slots_13_out_uop_ldq_idx : _T_311 ? issue_slots_12_out_uop_ldq_idx : issue_slots_11_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_rob_idx = _T_312 ? issue_slots_13_out_uop_rob_idx : _T_311 ? issue_slots_12_out_uop_rob_idx : issue_slots_11_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_vec = _T_312 ? issue_slots_13_out_uop_fp_ctrl_vec : _T_311 ? issue_slots_12_out_uop_fp_ctrl_vec : issue_slots_11_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_wflags = _T_312 ? issue_slots_13_out_uop_fp_ctrl_wflags : _T_311 ? issue_slots_12_out_uop_fp_ctrl_wflags : issue_slots_11_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_sqrt = _T_312 ? issue_slots_13_out_uop_fp_ctrl_sqrt : _T_311 ? issue_slots_12_out_uop_fp_ctrl_sqrt : issue_slots_11_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_div = _T_312 ? issue_slots_13_out_uop_fp_ctrl_div : _T_311 ? issue_slots_12_out_uop_fp_ctrl_div : issue_slots_11_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_fma = _T_312 ? issue_slots_13_out_uop_fp_ctrl_fma : _T_311 ? issue_slots_12_out_uop_fp_ctrl_fma : issue_slots_11_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_fastpipe = _T_312 ? issue_slots_13_out_uop_fp_ctrl_fastpipe : _T_311 ? issue_slots_12_out_uop_fp_ctrl_fastpipe : issue_slots_11_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_toint = _T_312 ? issue_slots_13_out_uop_fp_ctrl_toint : _T_311 ? issue_slots_12_out_uop_fp_ctrl_toint : issue_slots_11_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_fromint = _T_312 ? issue_slots_13_out_uop_fp_ctrl_fromint : _T_311 ? issue_slots_12_out_uop_fp_ctrl_fromint : issue_slots_11_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_typeTagOut = _T_312 ? issue_slots_13_out_uop_fp_ctrl_typeTagOut : _T_311 ? issue_slots_12_out_uop_fp_ctrl_typeTagOut : issue_slots_11_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_typeTagIn = _T_312 ? issue_slots_13_out_uop_fp_ctrl_typeTagIn : _T_311 ? issue_slots_12_out_uop_fp_ctrl_typeTagIn : issue_slots_11_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_swap23 = _T_312 ? issue_slots_13_out_uop_fp_ctrl_swap23 : _T_311 ? issue_slots_12_out_uop_fp_ctrl_swap23 : issue_slots_11_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_swap12 = _T_312 ? issue_slots_13_out_uop_fp_ctrl_swap12 : _T_311 ? issue_slots_12_out_uop_fp_ctrl_swap12 : issue_slots_11_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_ren3 = _T_312 ? issue_slots_13_out_uop_fp_ctrl_ren3 : _T_311 ? issue_slots_12_out_uop_fp_ctrl_ren3 : issue_slots_11_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_ren2 = _T_312 ? issue_slots_13_out_uop_fp_ctrl_ren2 : _T_311 ? issue_slots_12_out_uop_fp_ctrl_ren2 : issue_slots_11_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_ren1 = _T_312 ? issue_slots_13_out_uop_fp_ctrl_ren1 : _T_311 ? issue_slots_12_out_uop_fp_ctrl_ren1 : issue_slots_11_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_wen = _T_312 ? issue_slots_13_out_uop_fp_ctrl_wen : _T_311 ? issue_slots_12_out_uop_fp_ctrl_wen : issue_slots_11_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_ldst = _T_312 ? issue_slots_13_out_uop_fp_ctrl_ldst : _T_311 ? issue_slots_12_out_uop_fp_ctrl_ldst : issue_slots_11_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_op2_sel = _T_312 ? issue_slots_13_out_uop_op2_sel : _T_311 ? issue_slots_12_out_uop_op2_sel : issue_slots_11_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_op1_sel = _T_312 ? issue_slots_13_out_uop_op1_sel : _T_311 ? issue_slots_12_out_uop_op1_sel : issue_slots_11_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_imm_packed = _T_312 ? issue_slots_13_out_uop_imm_packed : _T_311 ? issue_slots_12_out_uop_imm_packed : issue_slots_11_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_pimm = _T_312 ? issue_slots_13_out_uop_pimm : _T_311 ? issue_slots_12_out_uop_pimm : issue_slots_11_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_imm_sel = _T_312 ? issue_slots_13_out_uop_imm_sel : _T_311 ? issue_slots_12_out_uop_imm_sel : issue_slots_11_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_imm_rename = _T_312 ? issue_slots_13_out_uop_imm_rename : _T_311 ? issue_slots_12_out_uop_imm_rename : issue_slots_11_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_taken = _T_312 ? issue_slots_13_out_uop_taken : _T_311 ? issue_slots_12_out_uop_taken : issue_slots_11_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_pc_lob = _T_312 ? issue_slots_13_out_uop_pc_lob : _T_311 ? issue_slots_12_out_uop_pc_lob : issue_slots_11_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_edge_inst = _T_312 ? issue_slots_13_out_uop_edge_inst : _T_311 ? issue_slots_12_out_uop_edge_inst : issue_slots_11_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_ftq_idx = _T_312 ? issue_slots_13_out_uop_ftq_idx : _T_311 ? issue_slots_12_out_uop_ftq_idx : issue_slots_11_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_mov = _T_312 ? issue_slots_13_out_uop_is_mov : _T_311 ? issue_slots_12_out_uop_is_mov : issue_slots_11_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_rocc = _T_312 ? issue_slots_13_out_uop_is_rocc : _T_311 ? issue_slots_12_out_uop_is_rocc : issue_slots_11_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_sys_pc2epc = _T_312 ? issue_slots_13_out_uop_is_sys_pc2epc : _T_311 ? issue_slots_12_out_uop_is_sys_pc2epc : issue_slots_11_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_eret = _T_312 ? issue_slots_13_out_uop_is_eret : _T_311 ? issue_slots_12_out_uop_is_eret : issue_slots_11_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_amo = _T_312 ? issue_slots_13_out_uop_is_amo : _T_311 ? issue_slots_12_out_uop_is_amo : issue_slots_11_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_sfence = _T_312 ? issue_slots_13_out_uop_is_sfence : _T_311 ? issue_slots_12_out_uop_is_sfence : issue_slots_11_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_fencei = _T_312 ? issue_slots_13_out_uop_is_fencei : _T_311 ? issue_slots_12_out_uop_is_fencei : issue_slots_11_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_fence = _T_312 ? issue_slots_13_out_uop_is_fence : _T_311 ? issue_slots_12_out_uop_is_fence : issue_slots_11_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_sfb = _T_312 ? issue_slots_13_out_uop_is_sfb : _T_311 ? issue_slots_12_out_uop_is_sfb : issue_slots_11_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_br_type = _T_312 ? issue_slots_13_out_uop_br_type : _T_311 ? issue_slots_12_out_uop_br_type : issue_slots_11_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_br_tag = _T_312 ? issue_slots_13_out_uop_br_tag : _T_311 ? issue_slots_12_out_uop_br_tag : issue_slots_11_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_br_mask = _T_312 ? issue_slots_13_out_uop_br_mask : _T_311 ? issue_slots_12_out_uop_br_mask : issue_slots_11_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_dis_col_sel = _T_312 ? issue_slots_13_out_uop_dis_col_sel : _T_311 ? issue_slots_12_out_uop_dis_col_sel : issue_slots_11_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iw_p3_bypass_hint = _T_312 ? issue_slots_13_out_uop_iw_p3_bypass_hint : _T_311 ? issue_slots_12_out_uop_iw_p3_bypass_hint : issue_slots_11_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iw_p2_bypass_hint = _T_312 ? issue_slots_13_out_uop_iw_p2_bypass_hint : _T_311 ? issue_slots_12_out_uop_iw_p2_bypass_hint : issue_slots_11_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iw_p1_bypass_hint = _T_312 ? issue_slots_13_out_uop_iw_p1_bypass_hint : _T_311 ? issue_slots_12_out_uop_iw_p1_bypass_hint : issue_slots_11_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iw_p2_speculative_child = _T_312 ? issue_slots_13_out_uop_iw_p2_speculative_child : _T_311 ? issue_slots_12_out_uop_iw_p2_speculative_child : issue_slots_11_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iw_p1_speculative_child = _T_312 ? issue_slots_13_out_uop_iw_p1_speculative_child : _T_311 ? issue_slots_12_out_uop_iw_p1_speculative_child : issue_slots_11_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iw_issued_partial_dgen = _T_312 ? issue_slots_13_out_uop_iw_issued_partial_dgen : _T_311 ? issue_slots_12_out_uop_iw_issued_partial_dgen : issue_slots_11_out_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iw_issued_partial_agen = _T_312 ? issue_slots_13_out_uop_iw_issued_partial_agen : _T_311 ? issue_slots_12_out_uop_iw_issued_partial_agen : issue_slots_11_out_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iw_issued = _T_312 ? issue_slots_13_out_uop_iw_issued : _T_311 ? issue_slots_12_out_uop_iw_issued : issue_slots_11_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_0 = _T_312 ? issue_slots_13_out_uop_fu_code_0 : _T_311 ? issue_slots_12_out_uop_fu_code_0 : issue_slots_11_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_1 = _T_312 ? issue_slots_13_out_uop_fu_code_1 : _T_311 ? issue_slots_12_out_uop_fu_code_1 : issue_slots_11_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_2 = _T_312 ? issue_slots_13_out_uop_fu_code_2 : _T_311 ? issue_slots_12_out_uop_fu_code_2 : issue_slots_11_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_3 = _T_312 ? issue_slots_13_out_uop_fu_code_3 : _T_311 ? issue_slots_12_out_uop_fu_code_3 : issue_slots_11_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_4 = _T_312 ? issue_slots_13_out_uop_fu_code_4 : _T_311 ? issue_slots_12_out_uop_fu_code_4 : issue_slots_11_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_5 = _T_312 ? issue_slots_13_out_uop_fu_code_5 : _T_311 ? issue_slots_12_out_uop_fu_code_5 : issue_slots_11_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_6 = _T_312 ? issue_slots_13_out_uop_fu_code_6 : _T_311 ? issue_slots_12_out_uop_fu_code_6 : issue_slots_11_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_7 = _T_312 ? issue_slots_13_out_uop_fu_code_7 : _T_311 ? issue_slots_12_out_uop_fu_code_7 : issue_slots_11_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_8 = _T_312 ? issue_slots_13_out_uop_fu_code_8 : _T_311 ? issue_slots_12_out_uop_fu_code_8 : issue_slots_11_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_9 = _T_312 ? issue_slots_13_out_uop_fu_code_9 : _T_311 ? issue_slots_12_out_uop_fu_code_9 : issue_slots_11_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iq_type_0 = _T_312 ? issue_slots_13_out_uop_iq_type_0 : _T_311 ? issue_slots_12_out_uop_iq_type_0 : issue_slots_11_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iq_type_1 = _T_312 ? issue_slots_13_out_uop_iq_type_1 : _T_311 ? issue_slots_12_out_uop_iq_type_1 : issue_slots_11_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iq_type_2 = _T_312 ? issue_slots_13_out_uop_iq_type_2 : _T_311 ? issue_slots_12_out_uop_iq_type_2 : issue_slots_11_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iq_type_3 = _T_312 ? issue_slots_13_out_uop_iq_type_3 : _T_311 ? issue_slots_12_out_uop_iq_type_3 : issue_slots_11_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_debug_pc = _T_312 ? issue_slots_13_out_uop_debug_pc : _T_311 ? issue_slots_12_out_uop_debug_pc : issue_slots_11_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_rvc = _T_312 ? issue_slots_13_out_uop_is_rvc : _T_311 ? issue_slots_12_out_uop_is_rvc : issue_slots_11_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_debug_inst = _T_312 ? issue_slots_13_out_uop_debug_inst : _T_311 ? issue_slots_12_out_uop_debug_inst : issue_slots_11_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_inst = _T_312 ? issue_slots_13_out_uop_inst : _T_311 ? issue_slots_12_out_uop_inst : issue_slots_11_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_10_clear_T = |shamts_oh_10; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_10_clear = _issue_slots_10_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_314 = shamts_oh_13 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_315 = shamts_oh_14 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_11_in_uop_valid = _T_315 ? issue_slots_14_will_be_valid : _T_314 ? issue_slots_13_will_be_valid : shamts_oh_12 == 3'h1 & issue_slots_12_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_11_in_uop_bits_debug_tsrc = _T_315 ? issue_slots_14_out_uop_debug_tsrc : _T_314 ? issue_slots_13_out_uop_debug_tsrc : issue_slots_12_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_debug_fsrc = _T_315 ? issue_slots_14_out_uop_debug_fsrc : _T_314 ? issue_slots_13_out_uop_debug_fsrc : issue_slots_12_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_bp_xcpt_if = _T_315 ? issue_slots_14_out_uop_bp_xcpt_if : _T_314 ? issue_slots_13_out_uop_bp_xcpt_if : issue_slots_12_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_bp_debug_if = _T_315 ? issue_slots_14_out_uop_bp_debug_if : _T_314 ? issue_slots_13_out_uop_bp_debug_if : issue_slots_12_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_xcpt_ma_if = _T_315 ? issue_slots_14_out_uop_xcpt_ma_if : _T_314 ? issue_slots_13_out_uop_xcpt_ma_if : issue_slots_12_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_xcpt_ae_if = _T_315 ? issue_slots_14_out_uop_xcpt_ae_if : _T_314 ? issue_slots_13_out_uop_xcpt_ae_if : issue_slots_12_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_xcpt_pf_if = _T_315 ? issue_slots_14_out_uop_xcpt_pf_if : _T_314 ? issue_slots_13_out_uop_xcpt_pf_if : issue_slots_12_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_typ = _T_315 ? issue_slots_14_out_uop_fp_typ : _T_314 ? issue_slots_13_out_uop_fp_typ : issue_slots_12_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_rm = _T_315 ? issue_slots_14_out_uop_fp_rm : _T_314 ? issue_slots_13_out_uop_fp_rm : issue_slots_12_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_val = _T_315 ? issue_slots_14_out_uop_fp_val : _T_314 ? issue_slots_13_out_uop_fp_val : issue_slots_12_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fcn_op = _T_315 ? issue_slots_14_out_uop_fcn_op : _T_314 ? issue_slots_13_out_uop_fcn_op : issue_slots_12_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fcn_dw = _T_315 ? issue_slots_14_out_uop_fcn_dw : _T_314 ? issue_slots_13_out_uop_fcn_dw : issue_slots_12_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_frs3_en = _T_315 ? issue_slots_14_out_uop_frs3_en : _T_314 ? issue_slots_13_out_uop_frs3_en : issue_slots_12_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_lrs2_rtype = _T_315 ? issue_slots_14_out_uop_lrs2_rtype : _T_314 ? issue_slots_13_out_uop_lrs2_rtype : issue_slots_12_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_lrs1_rtype = _T_315 ? issue_slots_14_out_uop_lrs1_rtype : _T_314 ? issue_slots_13_out_uop_lrs1_rtype : issue_slots_12_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_dst_rtype = _T_315 ? issue_slots_14_out_uop_dst_rtype : _T_314 ? issue_slots_13_out_uop_dst_rtype : issue_slots_12_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_lrs3 = _T_315 ? issue_slots_14_out_uop_lrs3 : _T_314 ? issue_slots_13_out_uop_lrs3 : issue_slots_12_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_lrs2 = _T_315 ? issue_slots_14_out_uop_lrs2 : _T_314 ? issue_slots_13_out_uop_lrs2 : issue_slots_12_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_lrs1 = _T_315 ? issue_slots_14_out_uop_lrs1 : _T_314 ? issue_slots_13_out_uop_lrs1 : issue_slots_12_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_ldst = _T_315 ? issue_slots_14_out_uop_ldst : _T_314 ? issue_slots_13_out_uop_ldst : issue_slots_12_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_ldst_is_rs1 = _T_315 ? issue_slots_14_out_uop_ldst_is_rs1 : _T_314 ? issue_slots_13_out_uop_ldst_is_rs1 : issue_slots_12_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_csr_cmd = _T_315 ? issue_slots_14_out_uop_csr_cmd : _T_314 ? issue_slots_13_out_uop_csr_cmd : issue_slots_12_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_flush_on_commit = _T_315 ? issue_slots_14_out_uop_flush_on_commit : _T_314 ? issue_slots_13_out_uop_flush_on_commit : issue_slots_12_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_unique = _T_315 ? issue_slots_14_out_uop_is_unique : _T_314 ? issue_slots_13_out_uop_is_unique : issue_slots_12_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_uses_stq = _T_315 ? issue_slots_14_out_uop_uses_stq : _T_314 ? issue_slots_13_out_uop_uses_stq : issue_slots_12_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_uses_ldq = _T_315 ? issue_slots_14_out_uop_uses_ldq : _T_314 ? issue_slots_13_out_uop_uses_ldq : issue_slots_12_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_mem_signed = _T_315 ? issue_slots_14_out_uop_mem_signed : _T_314 ? issue_slots_13_out_uop_mem_signed : issue_slots_12_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_mem_size = _T_315 ? issue_slots_14_out_uop_mem_size : _T_314 ? issue_slots_13_out_uop_mem_size : issue_slots_12_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_mem_cmd = _T_315 ? issue_slots_14_out_uop_mem_cmd : _T_314 ? issue_slots_13_out_uop_mem_cmd : issue_slots_12_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_exc_cause = _T_315 ? issue_slots_14_out_uop_exc_cause : _T_314 ? issue_slots_13_out_uop_exc_cause : issue_slots_12_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_exception = _T_315 ? issue_slots_14_out_uop_exception : _T_314 ? issue_slots_13_out_uop_exception : issue_slots_12_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_stale_pdst = _T_315 ? issue_slots_14_out_uop_stale_pdst : _T_314 ? issue_slots_13_out_uop_stale_pdst : issue_slots_12_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_ppred_busy = _T_315 ? issue_slots_14_out_uop_ppred_busy : _T_314 ? issue_slots_13_out_uop_ppred_busy : issue_slots_12_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_prs3_busy = _T_315 ? issue_slots_14_out_uop_prs3_busy : _T_314 ? issue_slots_13_out_uop_prs3_busy : issue_slots_12_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_prs2_busy = _T_315 ? issue_slots_14_out_uop_prs2_busy : _T_314 ? issue_slots_13_out_uop_prs2_busy : issue_slots_12_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_prs1_busy = _T_315 ? issue_slots_14_out_uop_prs1_busy : _T_314 ? issue_slots_13_out_uop_prs1_busy : issue_slots_12_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_ppred = _T_315 ? issue_slots_14_out_uop_ppred : _T_314 ? issue_slots_13_out_uop_ppred : issue_slots_12_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_prs3 = _T_315 ? issue_slots_14_out_uop_prs3 : _T_314 ? issue_slots_13_out_uop_prs3 : issue_slots_12_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_prs2 = _T_315 ? issue_slots_14_out_uop_prs2 : _T_314 ? issue_slots_13_out_uop_prs2 : issue_slots_12_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_prs1 = _T_315 ? issue_slots_14_out_uop_prs1 : _T_314 ? issue_slots_13_out_uop_prs1 : issue_slots_12_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_pdst = _T_315 ? issue_slots_14_out_uop_pdst : _T_314 ? issue_slots_13_out_uop_pdst : issue_slots_12_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_rxq_idx = _T_315 ? issue_slots_14_out_uop_rxq_idx : _T_314 ? issue_slots_13_out_uop_rxq_idx : issue_slots_12_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_stq_idx = _T_315 ? issue_slots_14_out_uop_stq_idx : _T_314 ? issue_slots_13_out_uop_stq_idx : issue_slots_12_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_ldq_idx = _T_315 ? issue_slots_14_out_uop_ldq_idx : _T_314 ? issue_slots_13_out_uop_ldq_idx : issue_slots_12_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_rob_idx = _T_315 ? issue_slots_14_out_uop_rob_idx : _T_314 ? issue_slots_13_out_uop_rob_idx : issue_slots_12_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_vec = _T_315 ? issue_slots_14_out_uop_fp_ctrl_vec : _T_314 ? issue_slots_13_out_uop_fp_ctrl_vec : issue_slots_12_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_wflags = _T_315 ? issue_slots_14_out_uop_fp_ctrl_wflags : _T_314 ? issue_slots_13_out_uop_fp_ctrl_wflags : issue_slots_12_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_sqrt = _T_315 ? issue_slots_14_out_uop_fp_ctrl_sqrt : _T_314 ? issue_slots_13_out_uop_fp_ctrl_sqrt : issue_slots_12_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_div = _T_315 ? issue_slots_14_out_uop_fp_ctrl_div : _T_314 ? issue_slots_13_out_uop_fp_ctrl_div : issue_slots_12_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_fma = _T_315 ? issue_slots_14_out_uop_fp_ctrl_fma : _T_314 ? issue_slots_13_out_uop_fp_ctrl_fma : issue_slots_12_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_fastpipe = _T_315 ? issue_slots_14_out_uop_fp_ctrl_fastpipe : _T_314 ? issue_slots_13_out_uop_fp_ctrl_fastpipe : issue_slots_12_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_toint = _T_315 ? issue_slots_14_out_uop_fp_ctrl_toint : _T_314 ? issue_slots_13_out_uop_fp_ctrl_toint : issue_slots_12_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_fromint = _T_315 ? issue_slots_14_out_uop_fp_ctrl_fromint : _T_314 ? issue_slots_13_out_uop_fp_ctrl_fromint : issue_slots_12_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_typeTagOut = _T_315 ? issue_slots_14_out_uop_fp_ctrl_typeTagOut : _T_314 ? issue_slots_13_out_uop_fp_ctrl_typeTagOut : issue_slots_12_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_typeTagIn = _T_315 ? issue_slots_14_out_uop_fp_ctrl_typeTagIn : _T_314 ? issue_slots_13_out_uop_fp_ctrl_typeTagIn : issue_slots_12_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_swap23 = _T_315 ? issue_slots_14_out_uop_fp_ctrl_swap23 : _T_314 ? issue_slots_13_out_uop_fp_ctrl_swap23 : issue_slots_12_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_swap12 = _T_315 ? issue_slots_14_out_uop_fp_ctrl_swap12 : _T_314 ? issue_slots_13_out_uop_fp_ctrl_swap12 : issue_slots_12_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_ren3 = _T_315 ? issue_slots_14_out_uop_fp_ctrl_ren3 : _T_314 ? issue_slots_13_out_uop_fp_ctrl_ren3 : issue_slots_12_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_ren2 = _T_315 ? issue_slots_14_out_uop_fp_ctrl_ren2 : _T_314 ? issue_slots_13_out_uop_fp_ctrl_ren2 : issue_slots_12_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_ren1 = _T_315 ? issue_slots_14_out_uop_fp_ctrl_ren1 : _T_314 ? issue_slots_13_out_uop_fp_ctrl_ren1 : issue_slots_12_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_wen = _T_315 ? issue_slots_14_out_uop_fp_ctrl_wen : _T_314 ? issue_slots_13_out_uop_fp_ctrl_wen : issue_slots_12_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_ldst = _T_315 ? issue_slots_14_out_uop_fp_ctrl_ldst : _T_314 ? issue_slots_13_out_uop_fp_ctrl_ldst : issue_slots_12_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_op2_sel = _T_315 ? issue_slots_14_out_uop_op2_sel : _T_314 ? issue_slots_13_out_uop_op2_sel : issue_slots_12_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_op1_sel = _T_315 ? issue_slots_14_out_uop_op1_sel : _T_314 ? issue_slots_13_out_uop_op1_sel : issue_slots_12_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_imm_packed = _T_315 ? issue_slots_14_out_uop_imm_packed : _T_314 ? issue_slots_13_out_uop_imm_packed : issue_slots_12_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_pimm = _T_315 ? issue_slots_14_out_uop_pimm : _T_314 ? issue_slots_13_out_uop_pimm : issue_slots_12_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_imm_sel = _T_315 ? issue_slots_14_out_uop_imm_sel : _T_314 ? issue_slots_13_out_uop_imm_sel : issue_slots_12_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_imm_rename = _T_315 ? issue_slots_14_out_uop_imm_rename : _T_314 ? issue_slots_13_out_uop_imm_rename : issue_slots_12_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_taken = _T_315 ? issue_slots_14_out_uop_taken : _T_314 ? issue_slots_13_out_uop_taken : issue_slots_12_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_pc_lob = _T_315 ? issue_slots_14_out_uop_pc_lob : _T_314 ? issue_slots_13_out_uop_pc_lob : issue_slots_12_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_edge_inst = _T_315 ? issue_slots_14_out_uop_edge_inst : _T_314 ? issue_slots_13_out_uop_edge_inst : issue_slots_12_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_ftq_idx = _T_315 ? issue_slots_14_out_uop_ftq_idx : _T_314 ? issue_slots_13_out_uop_ftq_idx : issue_slots_12_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_mov = _T_315 ? issue_slots_14_out_uop_is_mov : _T_314 ? issue_slots_13_out_uop_is_mov : issue_slots_12_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_rocc = _T_315 ? issue_slots_14_out_uop_is_rocc : _T_314 ? issue_slots_13_out_uop_is_rocc : issue_slots_12_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_sys_pc2epc = _T_315 ? issue_slots_14_out_uop_is_sys_pc2epc : _T_314 ? issue_slots_13_out_uop_is_sys_pc2epc : issue_slots_12_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_eret = _T_315 ? issue_slots_14_out_uop_is_eret : _T_314 ? issue_slots_13_out_uop_is_eret : issue_slots_12_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_amo = _T_315 ? issue_slots_14_out_uop_is_amo : _T_314 ? issue_slots_13_out_uop_is_amo : issue_slots_12_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_sfence = _T_315 ? issue_slots_14_out_uop_is_sfence : _T_314 ? issue_slots_13_out_uop_is_sfence : issue_slots_12_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_fencei = _T_315 ? issue_slots_14_out_uop_is_fencei : _T_314 ? issue_slots_13_out_uop_is_fencei : issue_slots_12_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_fence = _T_315 ? issue_slots_14_out_uop_is_fence : _T_314 ? issue_slots_13_out_uop_is_fence : issue_slots_12_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_sfb = _T_315 ? issue_slots_14_out_uop_is_sfb : _T_314 ? issue_slots_13_out_uop_is_sfb : issue_slots_12_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_br_type = _T_315 ? issue_slots_14_out_uop_br_type : _T_314 ? issue_slots_13_out_uop_br_type : issue_slots_12_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_br_tag = _T_315 ? issue_slots_14_out_uop_br_tag : _T_314 ? issue_slots_13_out_uop_br_tag : issue_slots_12_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_br_mask = _T_315 ? issue_slots_14_out_uop_br_mask : _T_314 ? issue_slots_13_out_uop_br_mask : issue_slots_12_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_dis_col_sel = _T_315 ? issue_slots_14_out_uop_dis_col_sel : _T_314 ? issue_slots_13_out_uop_dis_col_sel : issue_slots_12_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_iw_p3_bypass_hint = _T_315 ? issue_slots_14_out_uop_iw_p3_bypass_hint : _T_314 ? issue_slots_13_out_uop_iw_p3_bypass_hint : issue_slots_12_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_iw_p2_bypass_hint = _T_315 ? issue_slots_14_out_uop_iw_p2_bypass_hint : _T_314 ? issue_slots_13_out_uop_iw_p2_bypass_hint : issue_slots_12_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_iw_p1_bypass_hint = _T_315 ? issue_slots_14_out_uop_iw_p1_bypass_hint : _T_314 ? issue_slots_13_out_uop_iw_p1_bypass_hint : issue_slots_12_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_iw_p2_speculative_child = _T_315 ? issue_slots_14_out_uop_iw_p2_speculative_child : _T_314 ? issue_slots_13_out_uop_iw_p2_speculative_child : issue_slots_12_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_iw_p1_speculative_child = _T_315 ? issue_slots_14_out_uop_iw_p1_speculative_child : _T_314 ? issue_slots_13_out_uop_iw_p1_speculative_child : issue_slots_12_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_iw_issued_partial_dgen = _T_315 ? issue_slots_14_out_uop_iw_issued_partial_dgen : _T_314 ? issue_slots_13_out_uop_iw_issued_partial_dgen : issue_slots_12_out_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_iw_issued_partial_agen = _T_315 ? issue_slots_14_out_uop_iw_issued_partial_agen : _T_314 ? issue_slots_13_out_uop_iw_issued_partial_agen : issue_slots_12_out_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_iw_issued = _T_315 ? issue_slots_14_out_uop_iw_issued : _T_314 ? issue_slots_13_out_uop_iw_issued : issue_slots_12_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_0 = _T_315 ? issue_slots_14_out_uop_fu_code_0 : _T_314 ? issue_slots_13_out_uop_fu_code_0 : issue_slots_12_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_1 = _T_315 ? issue_slots_14_out_uop_fu_code_1 : _T_314 ? issue_slots_13_out_uop_fu_code_1 : issue_slots_12_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_2 = _T_315 ? issue_slots_14_out_uop_fu_code_2 : _T_314 ? issue_slots_13_out_uop_fu_code_2 : issue_slots_12_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_3 = _T_315 ? issue_slots_14_out_uop_fu_code_3 : _T_314 ? issue_slots_13_out_uop_fu_code_3 : issue_slots_12_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_4 = _T_315 ? issue_slots_14_out_uop_fu_code_4 : _T_314 ? issue_slots_13_out_uop_fu_code_4 : issue_slots_12_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_5 = _T_315 ? issue_slots_14_out_uop_fu_code_5 : _T_314 ? issue_slots_13_out_uop_fu_code_5 : issue_slots_12_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_6 = _T_315 ? issue_slots_14_out_uop_fu_code_6 : _T_314 ? issue_slots_13_out_uop_fu_code_6 : issue_slots_12_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_7 = _T_315 ? issue_slots_14_out_uop_fu_code_7 : _T_314 ? issue_slots_13_out_uop_fu_code_7 : issue_slots_12_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_8 = _T_315 ? issue_slots_14_out_uop_fu_code_8 : _T_314 ? issue_slots_13_out_uop_fu_code_8 : issue_slots_12_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_9 = _T_315 ? issue_slots_14_out_uop_fu_code_9 : _T_314 ? issue_slots_13_out_uop_fu_code_9 : issue_slots_12_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_iq_type_0 = _T_315 ? issue_slots_14_out_uop_iq_type_0 : _T_314 ? issue_slots_13_out_uop_iq_type_0 : issue_slots_12_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_iq_type_1 = _T_315 ? issue_slots_14_out_uop_iq_type_1 : _T_314 ? issue_slots_13_out_uop_iq_type_1 : issue_slots_12_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_iq_type_2 = _T_315 ? issue_slots_14_out_uop_iq_type_2 : _T_314 ? issue_slots_13_out_uop_iq_type_2 : issue_slots_12_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_iq_type_3 = _T_315 ? issue_slots_14_out_uop_iq_type_3 : _T_314 ? issue_slots_13_out_uop_iq_type_3 : issue_slots_12_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_debug_pc = _T_315 ? issue_slots_14_out_uop_debug_pc : _T_314 ? issue_slots_13_out_uop_debug_pc : issue_slots_12_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_rvc = _T_315 ? issue_slots_14_out_uop_is_rvc : _T_314 ? issue_slots_13_out_uop_is_rvc : issue_slots_12_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_debug_inst = _T_315 ? issue_slots_14_out_uop_debug_inst : _T_314 ? issue_slots_13_out_uop_debug_inst : issue_slots_12_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_inst = _T_315 ? issue_slots_14_out_uop_inst : _T_314 ? issue_slots_13_out_uop_inst : issue_slots_12_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_11_clear_T = |shamts_oh_11; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_11_clear = _issue_slots_11_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_317 = shamts_oh_14 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_318 = shamts_oh_15 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_12_in_uop_valid = _T_318 ? issue_slots_15_will_be_valid : _T_317 ? issue_slots_14_will_be_valid : shamts_oh_13 == 3'h1 & issue_slots_13_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_12_in_uop_bits_debug_tsrc = _T_318 ? issue_slots_15_out_uop_debug_tsrc : _T_317 ? issue_slots_14_out_uop_debug_tsrc : issue_slots_13_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_debug_fsrc = _T_318 ? issue_slots_15_out_uop_debug_fsrc : _T_317 ? issue_slots_14_out_uop_debug_fsrc : issue_slots_13_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_bp_xcpt_if = _T_318 ? issue_slots_15_out_uop_bp_xcpt_if : _T_317 ? issue_slots_14_out_uop_bp_xcpt_if : issue_slots_13_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_bp_debug_if = _T_318 ? issue_slots_15_out_uop_bp_debug_if : _T_317 ? issue_slots_14_out_uop_bp_debug_if : issue_slots_13_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_xcpt_ma_if = _T_318 ? issue_slots_15_out_uop_xcpt_ma_if : _T_317 ? issue_slots_14_out_uop_xcpt_ma_if : issue_slots_13_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_xcpt_ae_if = _T_318 ? issue_slots_15_out_uop_xcpt_ae_if : _T_317 ? issue_slots_14_out_uop_xcpt_ae_if : issue_slots_13_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_xcpt_pf_if = _T_318 ? issue_slots_15_out_uop_xcpt_pf_if : _T_317 ? issue_slots_14_out_uop_xcpt_pf_if : issue_slots_13_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_typ = _T_318 ? issue_slots_15_out_uop_fp_typ : _T_317 ? issue_slots_14_out_uop_fp_typ : issue_slots_13_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_rm = _T_318 ? issue_slots_15_out_uop_fp_rm : _T_317 ? issue_slots_14_out_uop_fp_rm : issue_slots_13_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_val = _T_318 ? issue_slots_15_out_uop_fp_val : _T_317 ? issue_slots_14_out_uop_fp_val : issue_slots_13_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fcn_op = _T_318 ? issue_slots_15_out_uop_fcn_op : _T_317 ? issue_slots_14_out_uop_fcn_op : issue_slots_13_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fcn_dw = _T_318 ? issue_slots_15_out_uop_fcn_dw : _T_317 ? issue_slots_14_out_uop_fcn_dw : issue_slots_13_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_frs3_en = _T_318 ? issue_slots_15_out_uop_frs3_en : _T_317 ? issue_slots_14_out_uop_frs3_en : issue_slots_13_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_lrs2_rtype = _T_318 ? issue_slots_15_out_uop_lrs2_rtype : _T_317 ? issue_slots_14_out_uop_lrs2_rtype : issue_slots_13_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_lrs1_rtype = _T_318 ? issue_slots_15_out_uop_lrs1_rtype : _T_317 ? issue_slots_14_out_uop_lrs1_rtype : issue_slots_13_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_dst_rtype = _T_318 ? issue_slots_15_out_uop_dst_rtype : _T_317 ? issue_slots_14_out_uop_dst_rtype : issue_slots_13_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_lrs3 = _T_318 ? issue_slots_15_out_uop_lrs3 : _T_317 ? issue_slots_14_out_uop_lrs3 : issue_slots_13_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_lrs2 = _T_318 ? issue_slots_15_out_uop_lrs2 : _T_317 ? issue_slots_14_out_uop_lrs2 : issue_slots_13_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_lrs1 = _T_318 ? issue_slots_15_out_uop_lrs1 : _T_317 ? issue_slots_14_out_uop_lrs1 : issue_slots_13_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_ldst = _T_318 ? issue_slots_15_out_uop_ldst : _T_317 ? issue_slots_14_out_uop_ldst : issue_slots_13_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_ldst_is_rs1 = _T_318 ? issue_slots_15_out_uop_ldst_is_rs1 : _T_317 ? issue_slots_14_out_uop_ldst_is_rs1 : issue_slots_13_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_csr_cmd = _T_318 ? issue_slots_15_out_uop_csr_cmd : _T_317 ? issue_slots_14_out_uop_csr_cmd : issue_slots_13_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_flush_on_commit = _T_318 ? issue_slots_15_out_uop_flush_on_commit : _T_317 ? issue_slots_14_out_uop_flush_on_commit : issue_slots_13_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_is_unique = _T_318 ? issue_slots_15_out_uop_is_unique : _T_317 ? issue_slots_14_out_uop_is_unique : issue_slots_13_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_uses_stq = _T_318 ? issue_slots_15_out_uop_uses_stq : _T_317 ? issue_slots_14_out_uop_uses_stq : issue_slots_13_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_uses_ldq = _T_318 ? issue_slots_15_out_uop_uses_ldq : _T_317 ? issue_slots_14_out_uop_uses_ldq : issue_slots_13_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_mem_signed = _T_318 ? issue_slots_15_out_uop_mem_signed : _T_317 ? issue_slots_14_out_uop_mem_signed : issue_slots_13_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_mem_size = _T_318 ? issue_slots_15_out_uop_mem_size : _T_317 ? issue_slots_14_out_uop_mem_size : issue_slots_13_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_mem_cmd = _T_318 ? issue_slots_15_out_uop_mem_cmd : _T_317 ? issue_slots_14_out_uop_mem_cmd : issue_slots_13_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_exc_cause = _T_318 ? issue_slots_15_out_uop_exc_cause : _T_317 ? issue_slots_14_out_uop_exc_cause : issue_slots_13_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_exception = _T_318 ? issue_slots_15_out_uop_exception : _T_317 ? issue_slots_14_out_uop_exception : issue_slots_13_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_stale_pdst = _T_318 ? issue_slots_15_out_uop_stale_pdst : _T_317 ? issue_slots_14_out_uop_stale_pdst : issue_slots_13_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_ppred_busy = _T_318 ? issue_slots_15_out_uop_ppred_busy : _T_317 ? issue_slots_14_out_uop_ppred_busy : issue_slots_13_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_prs3_busy = _T_318 ? issue_slots_15_out_uop_prs3_busy : _T_317 ? issue_slots_14_out_uop_prs3_busy : issue_slots_13_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_prs2_busy = _T_318 ? issue_slots_15_out_uop_prs2_busy : _T_317 ? issue_slots_14_out_uop_prs2_busy : issue_slots_13_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_prs1_busy = _T_318 ? issue_slots_15_out_uop_prs1_busy : _T_317 ? issue_slots_14_out_uop_prs1_busy : issue_slots_13_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_ppred = _T_318 ? issue_slots_15_out_uop_ppred : _T_317 ? issue_slots_14_out_uop_ppred : issue_slots_13_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_prs3 = _T_318 ? issue_slots_15_out_uop_prs3 : _T_317 ? issue_slots_14_out_uop_prs3 : issue_slots_13_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_prs2 = _T_318 ? issue_slots_15_out_uop_prs2 : _T_317 ? issue_slots_14_out_uop_prs2 : issue_slots_13_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_prs1 = _T_318 ? issue_slots_15_out_uop_prs1 : _T_317 ? issue_slots_14_out_uop_prs1 : issue_slots_13_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_pdst = _T_318 ? issue_slots_15_out_uop_pdst : _T_317 ? issue_slots_14_out_uop_pdst : issue_slots_13_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_rxq_idx = _T_318 ? issue_slots_15_out_uop_rxq_idx : _T_317 ? issue_slots_14_out_uop_rxq_idx : issue_slots_13_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_stq_idx = _T_318 ? issue_slots_15_out_uop_stq_idx : _T_317 ? issue_slots_14_out_uop_stq_idx : issue_slots_13_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_ldq_idx = _T_318 ? issue_slots_15_out_uop_ldq_idx : _T_317 ? issue_slots_14_out_uop_ldq_idx : issue_slots_13_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_rob_idx = _T_318 ? issue_slots_15_out_uop_rob_idx : _T_317 ? issue_slots_14_out_uop_rob_idx : issue_slots_13_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_vec = _T_318 ? issue_slots_15_out_uop_fp_ctrl_vec : _T_317 ? issue_slots_14_out_uop_fp_ctrl_vec : issue_slots_13_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_wflags = _T_318 ? issue_slots_15_out_uop_fp_ctrl_wflags : _T_317 ? issue_slots_14_out_uop_fp_ctrl_wflags : issue_slots_13_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_sqrt = _T_318 ? issue_slots_15_out_uop_fp_ctrl_sqrt : _T_317 ? issue_slots_14_out_uop_fp_ctrl_sqrt : issue_slots_13_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_div = _T_318 ? issue_slots_15_out_uop_fp_ctrl_div : _T_317 ? issue_slots_14_out_uop_fp_ctrl_div : issue_slots_13_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_fma = _T_318 ? issue_slots_15_out_uop_fp_ctrl_fma : _T_317 ? issue_slots_14_out_uop_fp_ctrl_fma : issue_slots_13_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_fastpipe = _T_318 ? issue_slots_15_out_uop_fp_ctrl_fastpipe : _T_317 ? issue_slots_14_out_uop_fp_ctrl_fastpipe : issue_slots_13_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_toint = _T_318 ? issue_slots_15_out_uop_fp_ctrl_toint : _T_317 ? issue_slots_14_out_uop_fp_ctrl_toint : issue_slots_13_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_fromint = _T_318 ? issue_slots_15_out_uop_fp_ctrl_fromint : _T_317 ? issue_slots_14_out_uop_fp_ctrl_fromint : issue_slots_13_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_typeTagOut = _T_318 ? issue_slots_15_out_uop_fp_ctrl_typeTagOut : _T_317 ? issue_slots_14_out_uop_fp_ctrl_typeTagOut : issue_slots_13_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_typeTagIn = _T_318 ? issue_slots_15_out_uop_fp_ctrl_typeTagIn : _T_317 ? issue_slots_14_out_uop_fp_ctrl_typeTagIn : issue_slots_13_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_swap23 = _T_318 ? issue_slots_15_out_uop_fp_ctrl_swap23 : _T_317 ? issue_slots_14_out_uop_fp_ctrl_swap23 : issue_slots_13_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_swap12 = _T_318 ? issue_slots_15_out_uop_fp_ctrl_swap12 : _T_317 ? issue_slots_14_out_uop_fp_ctrl_swap12 : issue_slots_13_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_ren3 = _T_318 ? issue_slots_15_out_uop_fp_ctrl_ren3 : _T_317 ? issue_slots_14_out_uop_fp_ctrl_ren3 : issue_slots_13_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_ren2 = _T_318 ? issue_slots_15_out_uop_fp_ctrl_ren2 : _T_317 ? issue_slots_14_out_uop_fp_ctrl_ren2 : issue_slots_13_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_ren1 = _T_318 ? issue_slots_15_out_uop_fp_ctrl_ren1 : _T_317 ? issue_slots_14_out_uop_fp_ctrl_ren1 : issue_slots_13_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_wen = _T_318 ? issue_slots_15_out_uop_fp_ctrl_wen : _T_317 ? issue_slots_14_out_uop_fp_ctrl_wen : issue_slots_13_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_ldst = _T_318 ? issue_slots_15_out_uop_fp_ctrl_ldst : _T_317 ? issue_slots_14_out_uop_fp_ctrl_ldst : issue_slots_13_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_op2_sel = _T_318 ? issue_slots_15_out_uop_op2_sel : _T_317 ? issue_slots_14_out_uop_op2_sel : issue_slots_13_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_op1_sel = _T_318 ? issue_slots_15_out_uop_op1_sel : _T_317 ? issue_slots_14_out_uop_op1_sel : issue_slots_13_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_imm_packed = _T_318 ? issue_slots_15_out_uop_imm_packed : _T_317 ? issue_slots_14_out_uop_imm_packed : issue_slots_13_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_pimm = _T_318 ? issue_slots_15_out_uop_pimm : _T_317 ? issue_slots_14_out_uop_pimm : issue_slots_13_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_imm_sel = _T_318 ? issue_slots_15_out_uop_imm_sel : _T_317 ? issue_slots_14_out_uop_imm_sel : issue_slots_13_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_imm_rename = _T_318 ? issue_slots_15_out_uop_imm_rename : _T_317 ? issue_slots_14_out_uop_imm_rename : issue_slots_13_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_taken = _T_318 ? issue_slots_15_out_uop_taken : _T_317 ? issue_slots_14_out_uop_taken : issue_slots_13_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_pc_lob = _T_318 ? issue_slots_15_out_uop_pc_lob : _T_317 ? issue_slots_14_out_uop_pc_lob : issue_slots_13_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_edge_inst = _T_318 ? issue_slots_15_out_uop_edge_inst : _T_317 ? issue_slots_14_out_uop_edge_inst : issue_slots_13_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_ftq_idx = _T_318 ? issue_slots_15_out_uop_ftq_idx : _T_317 ? issue_slots_14_out_uop_ftq_idx : issue_slots_13_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_is_mov = _T_318 ? issue_slots_15_out_uop_is_mov : _T_317 ? issue_slots_14_out_uop_is_mov : issue_slots_13_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_is_rocc = _T_318 ? issue_slots_15_out_uop_is_rocc : _T_317 ? issue_slots_14_out_uop_is_rocc : issue_slots_13_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_is_sys_pc2epc = _T_318 ? issue_slots_15_out_uop_is_sys_pc2epc : _T_317 ? issue_slots_14_out_uop_is_sys_pc2epc : issue_slots_13_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_is_eret = _T_318 ? issue_slots_15_out_uop_is_eret : _T_317 ? issue_slots_14_out_uop_is_eret : issue_slots_13_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_is_amo = _T_318 ? issue_slots_15_out_uop_is_amo : _T_317 ? issue_slots_14_out_uop_is_amo : issue_slots_13_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_is_sfence = _T_318 ? issue_slots_15_out_uop_is_sfence : _T_317 ? issue_slots_14_out_uop_is_sfence : issue_slots_13_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_is_fencei = _T_318 ? issue_slots_15_out_uop_is_fencei : _T_317 ? issue_slots_14_out_uop_is_fencei : issue_slots_13_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_is_fence = _T_318 ? issue_slots_15_out_uop_is_fence : _T_317 ? issue_slots_14_out_uop_is_fence : issue_slots_13_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_is_sfb = _T_318 ? issue_slots_15_out_uop_is_sfb : _T_317 ? issue_slots_14_out_uop_is_sfb : issue_slots_13_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_br_type = _T_318 ? issue_slots_15_out_uop_br_type : _T_317 ? issue_slots_14_out_uop_br_type : issue_slots_13_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_br_tag = _T_318 ? issue_slots_15_out_uop_br_tag : _T_317 ? issue_slots_14_out_uop_br_tag : issue_slots_13_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_br_mask = _T_318 ? issue_slots_15_out_uop_br_mask : _T_317 ? issue_slots_14_out_uop_br_mask : issue_slots_13_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_dis_col_sel = _T_318 ? issue_slots_15_out_uop_dis_col_sel : _T_317 ? issue_slots_14_out_uop_dis_col_sel : issue_slots_13_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_iw_p3_bypass_hint = _T_318 ? issue_slots_15_out_uop_iw_p3_bypass_hint : _T_317 ? issue_slots_14_out_uop_iw_p3_bypass_hint : issue_slots_13_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_iw_p2_bypass_hint = _T_318 ? issue_slots_15_out_uop_iw_p2_bypass_hint : _T_317 ? issue_slots_14_out_uop_iw_p2_bypass_hint : issue_slots_13_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_iw_p1_bypass_hint = _T_318 ? issue_slots_15_out_uop_iw_p1_bypass_hint : _T_317 ? issue_slots_14_out_uop_iw_p1_bypass_hint : issue_slots_13_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_iw_p2_speculative_child = _T_318 ? issue_slots_15_out_uop_iw_p2_speculative_child : _T_317 ? issue_slots_14_out_uop_iw_p2_speculative_child : issue_slots_13_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_iw_p1_speculative_child = _T_318 ? issue_slots_15_out_uop_iw_p1_speculative_child : _T_317 ? issue_slots_14_out_uop_iw_p1_speculative_child : issue_slots_13_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_iw_issued_partial_dgen = _T_318 ? issue_slots_15_out_uop_iw_issued_partial_dgen : _T_317 ? issue_slots_14_out_uop_iw_issued_partial_dgen : issue_slots_13_out_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_iw_issued_partial_agen = _T_318 ? issue_slots_15_out_uop_iw_issued_partial_agen : _T_317 ? issue_slots_14_out_uop_iw_issued_partial_agen : issue_slots_13_out_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_iw_issued = _T_318 ? issue_slots_15_out_uop_iw_issued : _T_317 ? issue_slots_14_out_uop_iw_issued : issue_slots_13_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fu_code_0 = _T_318 ? issue_slots_15_out_uop_fu_code_0 : _T_317 ? issue_slots_14_out_uop_fu_code_0 : issue_slots_13_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fu_code_1 = _T_318 ? issue_slots_15_out_uop_fu_code_1 : _T_317 ? issue_slots_14_out_uop_fu_code_1 : issue_slots_13_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fu_code_2 = _T_318 ? issue_slots_15_out_uop_fu_code_2 : _T_317 ? issue_slots_14_out_uop_fu_code_2 : issue_slots_13_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fu_code_3 = _T_318 ? issue_slots_15_out_uop_fu_code_3 : _T_317 ? issue_slots_14_out_uop_fu_code_3 : issue_slots_13_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fu_code_4 = _T_318 ? issue_slots_15_out_uop_fu_code_4 : _T_317 ? issue_slots_14_out_uop_fu_code_4 : issue_slots_13_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fu_code_5 = _T_318 ? issue_slots_15_out_uop_fu_code_5 : _T_317 ? issue_slots_14_out_uop_fu_code_5 : issue_slots_13_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fu_code_6 = _T_318 ? issue_slots_15_out_uop_fu_code_6 : _T_317 ? issue_slots_14_out_uop_fu_code_6 : issue_slots_13_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fu_code_7 = _T_318 ? issue_slots_15_out_uop_fu_code_7 : _T_317 ? issue_slots_14_out_uop_fu_code_7 : issue_slots_13_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fu_code_8 = _T_318 ? issue_slots_15_out_uop_fu_code_8 : _T_317 ? issue_slots_14_out_uop_fu_code_8 : issue_slots_13_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fu_code_9 = _T_318 ? issue_slots_15_out_uop_fu_code_9 : _T_317 ? issue_slots_14_out_uop_fu_code_9 : issue_slots_13_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_iq_type_0 = _T_318 ? issue_slots_15_out_uop_iq_type_0 : _T_317 ? issue_slots_14_out_uop_iq_type_0 : issue_slots_13_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_iq_type_1 = _T_318 ? issue_slots_15_out_uop_iq_type_1 : _T_317 ? issue_slots_14_out_uop_iq_type_1 : issue_slots_13_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_iq_type_2 = _T_318 ? issue_slots_15_out_uop_iq_type_2 : _T_317 ? issue_slots_14_out_uop_iq_type_2 : issue_slots_13_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_iq_type_3 = _T_318 ? issue_slots_15_out_uop_iq_type_3 : _T_317 ? issue_slots_14_out_uop_iq_type_3 : issue_slots_13_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_debug_pc = _T_318 ? issue_slots_15_out_uop_debug_pc : _T_317 ? issue_slots_14_out_uop_debug_pc : issue_slots_13_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_is_rvc = _T_318 ? issue_slots_15_out_uop_is_rvc : _T_317 ? issue_slots_14_out_uop_is_rvc : issue_slots_13_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_debug_inst = _T_318 ? issue_slots_15_out_uop_debug_inst : _T_317 ? issue_slots_14_out_uop_debug_inst : issue_slots_13_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_inst = _T_318 ? issue_slots_15_out_uop_inst : _T_317 ? issue_slots_14_out_uop_inst : issue_slots_13_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_12_clear_T = |shamts_oh_12; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_12_clear = _issue_slots_12_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_320 = shamts_oh_15 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_321 = shamts_oh_16 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_13_in_uop_valid = _T_321 ? will_be_valid_16 : _T_320 ? issue_slots_15_will_be_valid : shamts_oh_14 == 3'h1 & issue_slots_14_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :186:79, :191:33, :194:{28,48}, :195:37] assign issue_slots_13_in_uop_bits_debug_tsrc = _T_321 ? io_dis_uops_0_bits_debug_tsrc_0 : _T_320 ? issue_slots_15_out_uop_debug_tsrc : issue_slots_14_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_debug_fsrc = _T_321 ? io_dis_uops_0_bits_debug_fsrc_0 : _T_320 ? issue_slots_15_out_uop_debug_fsrc : issue_slots_14_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_bp_xcpt_if = _T_321 ? io_dis_uops_0_bits_bp_xcpt_if_0 : _T_320 ? issue_slots_15_out_uop_bp_xcpt_if : issue_slots_14_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_bp_debug_if = _T_321 ? io_dis_uops_0_bits_bp_debug_if_0 : _T_320 ? issue_slots_15_out_uop_bp_debug_if : issue_slots_14_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_xcpt_ma_if = _T_321 ? io_dis_uops_0_bits_xcpt_ma_if_0 : _T_320 ? issue_slots_15_out_uop_xcpt_ma_if : issue_slots_14_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_xcpt_ae_if = _T_321 ? io_dis_uops_0_bits_xcpt_ae_if_0 : _T_320 ? issue_slots_15_out_uop_xcpt_ae_if : issue_slots_14_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_xcpt_pf_if = _T_321 ? io_dis_uops_0_bits_xcpt_pf_if_0 : _T_320 ? issue_slots_15_out_uop_xcpt_pf_if : issue_slots_14_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_typ = _T_321 ? io_dis_uops_0_bits_fp_typ_0 : _T_320 ? issue_slots_15_out_uop_fp_typ : issue_slots_14_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_rm = _T_321 ? io_dis_uops_0_bits_fp_rm_0 : _T_320 ? issue_slots_15_out_uop_fp_rm : issue_slots_14_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_val = _T_321 ? io_dis_uops_0_bits_fp_val_0 : _T_320 ? issue_slots_15_out_uop_fp_val : issue_slots_14_out_uop_fp_val; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fcn_op = _T_321 ? io_dis_uops_0_bits_fcn_op_0 : _T_320 ? issue_slots_15_out_uop_fcn_op : issue_slots_14_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fcn_dw = _T_321 ? io_dis_uops_0_bits_fcn_dw_0 : _T_320 ? issue_slots_15_out_uop_fcn_dw : issue_slots_14_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_frs3_en = _T_321 ? io_dis_uops_0_bits_frs3_en_0 : _T_320 ? issue_slots_15_out_uop_frs3_en : issue_slots_14_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_lrs2_rtype = _T_321 ? _WIRE_lrs2_rtype : _T_320 ? issue_slots_15_out_uop_lrs2_rtype : issue_slots_14_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:35:17, :96:88, :97:32, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_lrs1_rtype = _T_321 ? io_dis_uops_0_bits_lrs1_rtype_0 : _T_320 ? issue_slots_15_out_uop_lrs1_rtype : issue_slots_14_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_dst_rtype = _T_321 ? io_dis_uops_0_bits_dst_rtype_0 : _T_320 ? issue_slots_15_out_uop_dst_rtype : issue_slots_14_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_lrs3 = _T_321 ? io_dis_uops_0_bits_lrs3_0 : _T_320 ? issue_slots_15_out_uop_lrs3 : issue_slots_14_out_uop_lrs3; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_lrs2 = _T_321 ? io_dis_uops_0_bits_lrs2_0 : _T_320 ? issue_slots_15_out_uop_lrs2 : issue_slots_14_out_uop_lrs2; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_lrs1 = _T_321 ? io_dis_uops_0_bits_lrs1_0 : _T_320 ? issue_slots_15_out_uop_lrs1 : issue_slots_14_out_uop_lrs1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_ldst = _T_321 ? io_dis_uops_0_bits_ldst_0 : _T_320 ? issue_slots_15_out_uop_ldst : issue_slots_14_out_uop_ldst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_ldst_is_rs1 = _T_321 ? io_dis_uops_0_bits_ldst_is_rs1_0 : _T_320 ? issue_slots_15_out_uop_ldst_is_rs1 : issue_slots_14_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_csr_cmd = _T_321 ? io_dis_uops_0_bits_csr_cmd_0 : _T_320 ? issue_slots_15_out_uop_csr_cmd : issue_slots_14_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_flush_on_commit = _T_321 ? io_dis_uops_0_bits_flush_on_commit_0 : _T_320 ? issue_slots_15_out_uop_flush_on_commit : issue_slots_14_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_is_unique = _T_321 ? io_dis_uops_0_bits_is_unique_0 : _T_320 ? issue_slots_15_out_uop_is_unique : issue_slots_14_out_uop_is_unique; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_uses_stq = _T_321 ? io_dis_uops_0_bits_uses_stq_0 : _T_320 ? issue_slots_15_out_uop_uses_stq : issue_slots_14_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_uses_ldq = _T_321 ? io_dis_uops_0_bits_uses_ldq_0 : _T_320 ? issue_slots_15_out_uop_uses_ldq : issue_slots_14_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_mem_signed = _T_321 ? io_dis_uops_0_bits_mem_signed_0 : _T_320 ? issue_slots_15_out_uop_mem_signed : issue_slots_14_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_mem_size = _T_321 ? io_dis_uops_0_bits_mem_size_0 : _T_320 ? issue_slots_15_out_uop_mem_size : issue_slots_14_out_uop_mem_size; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_mem_cmd = _T_321 ? io_dis_uops_0_bits_mem_cmd_0 : _T_320 ? issue_slots_15_out_uop_mem_cmd : issue_slots_14_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_exc_cause = _T_321 ? io_dis_uops_0_bits_exc_cause_0 : _T_320 ? issue_slots_15_out_uop_exc_cause : issue_slots_14_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_exception = _T_321 ? io_dis_uops_0_bits_exception_0 : _T_320 ? issue_slots_15_out_uop_exception : issue_slots_14_out_uop_exception; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_stale_pdst = _T_321 ? io_dis_uops_0_bits_stale_pdst_0 : _T_320 ? issue_slots_15_out_uop_stale_pdst : issue_slots_14_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_ppred_busy = ~_T_321 & (_T_320 ? issue_slots_15_out_uop_ppred_busy : issue_slots_14_out_uop_ppred_busy); // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_prs3_busy = ~_T_321 & (_T_320 ? issue_slots_15_out_uop_prs3_busy : issue_slots_14_out_uop_prs3_busy); // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_prs2_busy = _T_321 ? _WIRE_prs2_busy : _T_320 ? issue_slots_15_out_uop_prs2_busy : issue_slots_14_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:71:116, :96:88, :98:32, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_prs1_busy = _T_321 ? _WIRE_prs1_busy : _T_320 ? issue_slots_15_out_uop_prs1_busy : issue_slots_14_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:57:38, :62:116, :63:29, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_ppred = _T_321 ? io_dis_uops_0_bits_ppred_0 : _T_320 ? issue_slots_15_out_uop_ppred : issue_slots_14_out_uop_ppred; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_prs3 = _T_321 ? io_dis_uops_0_bits_prs3_0 : _T_320 ? issue_slots_15_out_uop_prs3 : issue_slots_14_out_uop_prs3; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_prs2 = _T_321 ? io_dis_uops_0_bits_prs2_0 : _T_320 ? issue_slots_15_out_uop_prs2 : issue_slots_14_out_uop_prs2; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_prs1 = _T_321 ? io_dis_uops_0_bits_prs1_0 : _T_320 ? issue_slots_15_out_uop_prs1 : issue_slots_14_out_uop_prs1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_pdst = _T_321 ? io_dis_uops_0_bits_pdst_0 : _T_320 ? issue_slots_15_out_uop_pdst : issue_slots_14_out_uop_pdst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_rxq_idx = _T_321 ? io_dis_uops_0_bits_rxq_idx_0 : _T_320 ? issue_slots_15_out_uop_rxq_idx : issue_slots_14_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_stq_idx = _T_321 ? io_dis_uops_0_bits_stq_idx_0 : _T_320 ? issue_slots_15_out_uop_stq_idx : issue_slots_14_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_ldq_idx = _T_321 ? io_dis_uops_0_bits_ldq_idx_0 : _T_320 ? issue_slots_15_out_uop_ldq_idx : issue_slots_14_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_rob_idx = _T_321 ? io_dis_uops_0_bits_rob_idx_0 : _T_320 ? issue_slots_15_out_uop_rob_idx : issue_slots_14_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_vec = _T_321 ? io_dis_uops_0_bits_fp_ctrl_vec_0 : _T_320 ? issue_slots_15_out_uop_fp_ctrl_vec : issue_slots_14_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_wflags = _T_321 ? io_dis_uops_0_bits_fp_ctrl_wflags_0 : _T_320 ? issue_slots_15_out_uop_fp_ctrl_wflags : issue_slots_14_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_sqrt = _T_321 ? io_dis_uops_0_bits_fp_ctrl_sqrt_0 : _T_320 ? issue_slots_15_out_uop_fp_ctrl_sqrt : issue_slots_14_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_div = _T_321 ? io_dis_uops_0_bits_fp_ctrl_div_0 : _T_320 ? issue_slots_15_out_uop_fp_ctrl_div : issue_slots_14_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_fma = _T_321 ? io_dis_uops_0_bits_fp_ctrl_fma_0 : _T_320 ? issue_slots_15_out_uop_fp_ctrl_fma : issue_slots_14_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_fastpipe = _T_321 ? io_dis_uops_0_bits_fp_ctrl_fastpipe_0 : _T_320 ? issue_slots_15_out_uop_fp_ctrl_fastpipe : issue_slots_14_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_toint = _T_321 ? io_dis_uops_0_bits_fp_ctrl_toint_0 : _T_320 ? issue_slots_15_out_uop_fp_ctrl_toint : issue_slots_14_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_fromint = _T_321 ? io_dis_uops_0_bits_fp_ctrl_fromint_0 : _T_320 ? issue_slots_15_out_uop_fp_ctrl_fromint : issue_slots_14_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_typeTagOut = _T_321 ? io_dis_uops_0_bits_fp_ctrl_typeTagOut_0 : _T_320 ? issue_slots_15_out_uop_fp_ctrl_typeTagOut : issue_slots_14_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_typeTagIn = _T_321 ? io_dis_uops_0_bits_fp_ctrl_typeTagIn_0 : _T_320 ? issue_slots_15_out_uop_fp_ctrl_typeTagIn : issue_slots_14_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_swap23 = _T_321 ? io_dis_uops_0_bits_fp_ctrl_swap23_0 : _T_320 ? issue_slots_15_out_uop_fp_ctrl_swap23 : issue_slots_14_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_swap12 = _T_321 ? io_dis_uops_0_bits_fp_ctrl_swap12_0 : _T_320 ? issue_slots_15_out_uop_fp_ctrl_swap12 : issue_slots_14_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_ren3 = _T_321 ? io_dis_uops_0_bits_fp_ctrl_ren3_0 : _T_320 ? issue_slots_15_out_uop_fp_ctrl_ren3 : issue_slots_14_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_ren2 = _T_321 ? io_dis_uops_0_bits_fp_ctrl_ren2_0 : _T_320 ? issue_slots_15_out_uop_fp_ctrl_ren2 : issue_slots_14_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_ren1 = _T_321 ? io_dis_uops_0_bits_fp_ctrl_ren1_0 : _T_320 ? issue_slots_15_out_uop_fp_ctrl_ren1 : issue_slots_14_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_wen = _T_321 ? io_dis_uops_0_bits_fp_ctrl_wen_0 : _T_320 ? issue_slots_15_out_uop_fp_ctrl_wen : issue_slots_14_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_ldst = _T_321 ? io_dis_uops_0_bits_fp_ctrl_ldst_0 : _T_320 ? issue_slots_15_out_uop_fp_ctrl_ldst : issue_slots_14_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_op2_sel = _T_321 ? io_dis_uops_0_bits_op2_sel_0 : _T_320 ? issue_slots_15_out_uop_op2_sel : issue_slots_14_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_op1_sel = _T_321 ? io_dis_uops_0_bits_op1_sel_0 : _T_320 ? issue_slots_15_out_uop_op1_sel : issue_slots_14_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_imm_packed = _T_321 ? io_dis_uops_0_bits_imm_packed_0 : _T_320 ? issue_slots_15_out_uop_imm_packed : issue_slots_14_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_pimm = _T_321 ? io_dis_uops_0_bits_pimm_0 : _T_320 ? issue_slots_15_out_uop_pimm : issue_slots_14_out_uop_pimm; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_imm_sel = _T_321 ? io_dis_uops_0_bits_imm_sel_0 : _T_320 ? issue_slots_15_out_uop_imm_sel : issue_slots_14_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_imm_rename = _T_321 ? io_dis_uops_0_bits_imm_rename_0 : _T_320 ? issue_slots_15_out_uop_imm_rename : issue_slots_14_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_taken = _T_321 ? io_dis_uops_0_bits_taken_0 : _T_320 ? issue_slots_15_out_uop_taken : issue_slots_14_out_uop_taken; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_pc_lob = _T_321 ? io_dis_uops_0_bits_pc_lob_0 : _T_320 ? issue_slots_15_out_uop_pc_lob : issue_slots_14_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_edge_inst = _T_321 ? io_dis_uops_0_bits_edge_inst_0 : _T_320 ? issue_slots_15_out_uop_edge_inst : issue_slots_14_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_ftq_idx = _T_321 ? io_dis_uops_0_bits_ftq_idx_0 : _T_320 ? issue_slots_15_out_uop_ftq_idx : issue_slots_14_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_is_mov = _T_321 ? io_dis_uops_0_bits_is_mov_0 : _T_320 ? issue_slots_15_out_uop_is_mov : issue_slots_14_out_uop_is_mov; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_is_rocc = _T_321 ? io_dis_uops_0_bits_is_rocc_0 : _T_320 ? issue_slots_15_out_uop_is_rocc : issue_slots_14_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_is_sys_pc2epc = _T_321 ? io_dis_uops_0_bits_is_sys_pc2epc_0 : _T_320 ? issue_slots_15_out_uop_is_sys_pc2epc : issue_slots_14_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_is_eret = _T_321 ? io_dis_uops_0_bits_is_eret_0 : _T_320 ? issue_slots_15_out_uop_is_eret : issue_slots_14_out_uop_is_eret; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_is_amo = _T_321 ? io_dis_uops_0_bits_is_amo_0 : _T_320 ? issue_slots_15_out_uop_is_amo : issue_slots_14_out_uop_is_amo; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_is_sfence = _T_321 ? io_dis_uops_0_bits_is_sfence_0 : _T_320 ? issue_slots_15_out_uop_is_sfence : issue_slots_14_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_is_fencei = _T_321 ? io_dis_uops_0_bits_is_fencei_0 : _T_320 ? issue_slots_15_out_uop_is_fencei : issue_slots_14_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_is_fence = _T_321 ? io_dis_uops_0_bits_is_fence_0 : _T_320 ? issue_slots_15_out_uop_is_fence : issue_slots_14_out_uop_is_fence; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_is_sfb = _T_321 ? io_dis_uops_0_bits_is_sfb_0 : _T_320 ? issue_slots_15_out_uop_is_sfb : issue_slots_14_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_br_type = _T_321 ? io_dis_uops_0_bits_br_type_0 : _T_320 ? issue_slots_15_out_uop_br_type : issue_slots_14_out_uop_br_type; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_br_tag = _T_321 ? io_dis_uops_0_bits_br_tag_0 : _T_320 ? issue_slots_15_out_uop_br_tag : issue_slots_14_out_uop_br_tag; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_br_mask = _T_321 ? io_dis_uops_0_bits_br_mask_0 : _T_320 ? issue_slots_15_out_uop_br_mask : issue_slots_14_out_uop_br_mask; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_dis_col_sel = _T_321 ? io_dis_uops_0_bits_dis_col_sel_0 : _T_320 ? issue_slots_15_out_uop_dis_col_sel : issue_slots_14_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_iw_p3_bypass_hint = _T_321 ? _WIRE_iw_p3_bypass_hint : _T_320 ? issue_slots_15_out_uop_iw_p3_bypass_hint : issue_slots_14_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:41:35, :76:38, :78:37, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_iw_p2_bypass_hint = _T_321 ? _WIRE_iw_p2_bypass_hint : _T_320 ? issue_slots_15_out_uop_iw_p2_bypass_hint : issue_slots_14_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:40:35, :65:38, :68:37, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_iw_p1_bypass_hint = _T_321 ? _WIRE_iw_p1_bypass_hint : _T_320 ? issue_slots_15_out_uop_iw_p1_bypass_hint : issue_slots_14_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:39:35, :57:38, :60:37, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_iw_p2_speculative_child = _T_321 ? _WIRE_iw_p2_speculative_child : _T_320 ? issue_slots_15_out_uop_iw_p2_speculative_child : issue_slots_14_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:35:17, :65:38, :67:43, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_iw_p1_speculative_child = _T_321 ? _WIRE_iw_p1_speculative_child : _T_320 ? issue_slots_15_out_uop_iw_p1_speculative_child : issue_slots_14_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:35:17, :57:38, :59:43, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_iw_issued_partial_dgen = ~_T_321 & (_T_320 ? issue_slots_15_out_uop_iw_issued_partial_dgen : issue_slots_14_out_uop_iw_issued_partial_dgen); // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_iw_issued_partial_agen = ~_T_321 & (_T_320 ? issue_slots_15_out_uop_iw_issued_partial_agen : issue_slots_14_out_uop_iw_issued_partial_agen); // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_iw_issued = ~_T_321 & (_T_320 ? issue_slots_15_out_uop_iw_issued : issue_slots_14_out_uop_iw_issued); // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fu_code_0 = _T_321 ? io_dis_uops_0_bits_fu_code_0_0 : _T_320 ? issue_slots_15_out_uop_fu_code_0 : issue_slots_14_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fu_code_1 = _T_321 ? io_dis_uops_0_bits_fu_code_1_0 : _T_320 ? issue_slots_15_out_uop_fu_code_1 : issue_slots_14_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fu_code_2 = _T_321 ? io_dis_uops_0_bits_fu_code_2_0 : _T_320 ? issue_slots_15_out_uop_fu_code_2 : issue_slots_14_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fu_code_3 = _T_321 ? io_dis_uops_0_bits_fu_code_3_0 : _T_320 ? issue_slots_15_out_uop_fu_code_3 : issue_slots_14_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fu_code_4 = _T_321 ? io_dis_uops_0_bits_fu_code_4_0 : _T_320 ? issue_slots_15_out_uop_fu_code_4 : issue_slots_14_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fu_code_5 = _T_321 ? io_dis_uops_0_bits_fu_code_5_0 : _T_320 ? issue_slots_15_out_uop_fu_code_5 : issue_slots_14_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fu_code_6 = _T_321 ? io_dis_uops_0_bits_fu_code_6_0 : _T_320 ? issue_slots_15_out_uop_fu_code_6 : issue_slots_14_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fu_code_7 = _T_321 ? io_dis_uops_0_bits_fu_code_7_0 : _T_320 ? issue_slots_15_out_uop_fu_code_7 : issue_slots_14_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fu_code_8 = _T_321 ? io_dis_uops_0_bits_fu_code_8_0 : _T_320 ? issue_slots_15_out_uop_fu_code_8 : issue_slots_14_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fu_code_9 = _T_321 ? io_dis_uops_0_bits_fu_code_9_0 : _T_320 ? issue_slots_15_out_uop_fu_code_9 : issue_slots_14_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_iq_type_0 = _T_321 ? io_dis_uops_0_bits_iq_type_0_0 : _T_320 ? issue_slots_15_out_uop_iq_type_0 : issue_slots_14_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_iq_type_1 = _T_321 ? io_dis_uops_0_bits_iq_type_1_0 : _T_320 ? issue_slots_15_out_uop_iq_type_1 : issue_slots_14_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_iq_type_2 = _T_321 ? io_dis_uops_0_bits_iq_type_2_0 : _T_320 ? issue_slots_15_out_uop_iq_type_2 : issue_slots_14_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_iq_type_3 = _T_321 ? io_dis_uops_0_bits_iq_type_3_0 : _T_320 ? issue_slots_15_out_uop_iq_type_3 : issue_slots_14_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_debug_pc = _T_321 ? io_dis_uops_0_bits_debug_pc_0 : _T_320 ? issue_slots_15_out_uop_debug_pc : issue_slots_14_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_is_rvc = _T_321 ? io_dis_uops_0_bits_is_rvc_0 : _T_320 ? issue_slots_15_out_uop_is_rvc : issue_slots_14_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_debug_inst = _T_321 ? io_dis_uops_0_bits_debug_inst_0 : _T_320 ? issue_slots_15_out_uop_debug_inst : issue_slots_14_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_inst = _T_321 ? io_dis_uops_0_bits_inst_0 : _T_320 ? issue_slots_15_out_uop_inst : issue_slots_14_out_uop_inst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign _issue_slots_13_clear_T = |shamts_oh_13; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_13_clear = _issue_slots_13_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_323 = shamts_oh_16 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_324 = shamts_oh_17 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_14_in_uop_valid = _T_324 ? will_be_valid_17 : _T_323 ? will_be_valid_16 : shamts_oh_15 == 3'h1 & issue_slots_15_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :186:79, :191:33, :194:{28,48}, :195:37] assign issue_slots_14_in_uop_bits_debug_tsrc = _T_324 ? io_dis_uops_1_bits_debug_tsrc_0 : _T_323 ? io_dis_uops_0_bits_debug_tsrc_0 : issue_slots_15_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_debug_fsrc = _T_324 ? io_dis_uops_1_bits_debug_fsrc_0 : _T_323 ? io_dis_uops_0_bits_debug_fsrc_0 : issue_slots_15_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_bp_xcpt_if = _T_324 ? io_dis_uops_1_bits_bp_xcpt_if_0 : _T_323 ? io_dis_uops_0_bits_bp_xcpt_if_0 : issue_slots_15_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_bp_debug_if = _T_324 ? io_dis_uops_1_bits_bp_debug_if_0 : _T_323 ? io_dis_uops_0_bits_bp_debug_if_0 : issue_slots_15_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_xcpt_ma_if = _T_324 ? io_dis_uops_1_bits_xcpt_ma_if_0 : _T_323 ? io_dis_uops_0_bits_xcpt_ma_if_0 : issue_slots_15_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_xcpt_ae_if = _T_324 ? io_dis_uops_1_bits_xcpt_ae_if_0 : _T_323 ? io_dis_uops_0_bits_xcpt_ae_if_0 : issue_slots_15_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_xcpt_pf_if = _T_324 ? io_dis_uops_1_bits_xcpt_pf_if_0 : _T_323 ? io_dis_uops_0_bits_xcpt_pf_if_0 : issue_slots_15_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_typ = _T_324 ? io_dis_uops_1_bits_fp_typ_0 : _T_323 ? io_dis_uops_0_bits_fp_typ_0 : issue_slots_15_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_rm = _T_324 ? io_dis_uops_1_bits_fp_rm_0 : _T_323 ? io_dis_uops_0_bits_fp_rm_0 : issue_slots_15_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_val = _T_324 ? io_dis_uops_1_bits_fp_val_0 : _T_323 ? io_dis_uops_0_bits_fp_val_0 : issue_slots_15_out_uop_fp_val; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fcn_op = _T_324 ? io_dis_uops_1_bits_fcn_op_0 : _T_323 ? io_dis_uops_0_bits_fcn_op_0 : issue_slots_15_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fcn_dw = _T_324 ? io_dis_uops_1_bits_fcn_dw_0 : _T_323 ? io_dis_uops_0_bits_fcn_dw_0 : issue_slots_15_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_frs3_en = _T_324 ? io_dis_uops_1_bits_frs3_en_0 : _T_323 ? io_dis_uops_0_bits_frs3_en_0 : issue_slots_15_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_lrs2_rtype = _T_324 ? _WIRE_1_lrs2_rtype : _T_323 ? _WIRE_lrs2_rtype : issue_slots_15_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:35:17, :96:88, :97:32, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_lrs1_rtype = _T_324 ? io_dis_uops_1_bits_lrs1_rtype_0 : _T_323 ? io_dis_uops_0_bits_lrs1_rtype_0 : issue_slots_15_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_dst_rtype = _T_324 ? io_dis_uops_1_bits_dst_rtype_0 : _T_323 ? io_dis_uops_0_bits_dst_rtype_0 : issue_slots_15_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_lrs3 = _T_324 ? io_dis_uops_1_bits_lrs3_0 : _T_323 ? io_dis_uops_0_bits_lrs3_0 : issue_slots_15_out_uop_lrs3; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_lrs2 = _T_324 ? io_dis_uops_1_bits_lrs2_0 : _T_323 ? io_dis_uops_0_bits_lrs2_0 : issue_slots_15_out_uop_lrs2; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_lrs1 = _T_324 ? io_dis_uops_1_bits_lrs1_0 : _T_323 ? io_dis_uops_0_bits_lrs1_0 : issue_slots_15_out_uop_lrs1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_ldst = _T_324 ? io_dis_uops_1_bits_ldst_0 : _T_323 ? io_dis_uops_0_bits_ldst_0 : issue_slots_15_out_uop_ldst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_ldst_is_rs1 = _T_324 ? io_dis_uops_1_bits_ldst_is_rs1_0 : _T_323 ? io_dis_uops_0_bits_ldst_is_rs1_0 : issue_slots_15_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_csr_cmd = _T_324 ? io_dis_uops_1_bits_csr_cmd_0 : _T_323 ? io_dis_uops_0_bits_csr_cmd_0 : issue_slots_15_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_flush_on_commit = _T_324 ? io_dis_uops_1_bits_flush_on_commit_0 : _T_323 ? io_dis_uops_0_bits_flush_on_commit_0 : issue_slots_15_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_is_unique = _T_324 ? io_dis_uops_1_bits_is_unique_0 : _T_323 ? io_dis_uops_0_bits_is_unique_0 : issue_slots_15_out_uop_is_unique; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_uses_stq = _T_324 ? io_dis_uops_1_bits_uses_stq_0 : _T_323 ? io_dis_uops_0_bits_uses_stq_0 : issue_slots_15_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_uses_ldq = _T_324 ? io_dis_uops_1_bits_uses_ldq_0 : _T_323 ? io_dis_uops_0_bits_uses_ldq_0 : issue_slots_15_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_mem_signed = _T_324 ? io_dis_uops_1_bits_mem_signed_0 : _T_323 ? io_dis_uops_0_bits_mem_signed_0 : issue_slots_15_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_mem_size = _T_324 ? io_dis_uops_1_bits_mem_size_0 : _T_323 ? io_dis_uops_0_bits_mem_size_0 : issue_slots_15_out_uop_mem_size; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_mem_cmd = _T_324 ? io_dis_uops_1_bits_mem_cmd_0 : _T_323 ? io_dis_uops_0_bits_mem_cmd_0 : issue_slots_15_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_exc_cause = _T_324 ? io_dis_uops_1_bits_exc_cause_0 : _T_323 ? io_dis_uops_0_bits_exc_cause_0 : issue_slots_15_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_exception = _T_324 ? io_dis_uops_1_bits_exception_0 : _T_323 ? io_dis_uops_0_bits_exception_0 : issue_slots_15_out_uop_exception; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_stale_pdst = _T_324 ? io_dis_uops_1_bits_stale_pdst_0 : _T_323 ? io_dis_uops_0_bits_stale_pdst_0 : issue_slots_15_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] wire _GEN = _T_324 | _T_323; // @[issue-unit-age-ordered.scala:194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_ppred_busy = ~_GEN & issue_slots_15_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:48, :196:37] assign issue_slots_14_in_uop_bits_prs3_busy = ~_GEN & issue_slots_15_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:48, :196:37] assign issue_slots_14_in_uop_bits_prs2_busy = _T_324 ? _WIRE_1_prs2_busy : _T_323 ? _WIRE_prs2_busy : issue_slots_15_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:71:116, :96:88, :98:32, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_prs1_busy = _T_324 ? _WIRE_1_prs1_busy : _T_323 ? _WIRE_prs1_busy : issue_slots_15_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:57:38, :62:116, :63:29, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_ppred = _T_324 ? io_dis_uops_1_bits_ppred_0 : _T_323 ? io_dis_uops_0_bits_ppred_0 : issue_slots_15_out_uop_ppred; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_prs3 = _T_324 ? io_dis_uops_1_bits_prs3_0 : _T_323 ? io_dis_uops_0_bits_prs3_0 : issue_slots_15_out_uop_prs3; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_prs2 = _T_324 ? io_dis_uops_1_bits_prs2_0 : _T_323 ? io_dis_uops_0_bits_prs2_0 : issue_slots_15_out_uop_prs2; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_prs1 = _T_324 ? io_dis_uops_1_bits_prs1_0 : _T_323 ? io_dis_uops_0_bits_prs1_0 : issue_slots_15_out_uop_prs1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_pdst = _T_324 ? io_dis_uops_1_bits_pdst_0 : _T_323 ? io_dis_uops_0_bits_pdst_0 : issue_slots_15_out_uop_pdst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_rxq_idx = _T_324 ? io_dis_uops_1_bits_rxq_idx_0 : _T_323 ? io_dis_uops_0_bits_rxq_idx_0 : issue_slots_15_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_stq_idx = _T_324 ? io_dis_uops_1_bits_stq_idx_0 : _T_323 ? io_dis_uops_0_bits_stq_idx_0 : issue_slots_15_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_ldq_idx = _T_324 ? io_dis_uops_1_bits_ldq_idx_0 : _T_323 ? io_dis_uops_0_bits_ldq_idx_0 : issue_slots_15_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_rob_idx = _T_324 ? io_dis_uops_1_bits_rob_idx_0 : _T_323 ? io_dis_uops_0_bits_rob_idx_0 : issue_slots_15_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_vec = _T_324 ? io_dis_uops_1_bits_fp_ctrl_vec_0 : _T_323 ? io_dis_uops_0_bits_fp_ctrl_vec_0 : issue_slots_15_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_wflags = _T_324 ? io_dis_uops_1_bits_fp_ctrl_wflags_0 : _T_323 ? io_dis_uops_0_bits_fp_ctrl_wflags_0 : issue_slots_15_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_sqrt = _T_324 ? io_dis_uops_1_bits_fp_ctrl_sqrt_0 : _T_323 ? io_dis_uops_0_bits_fp_ctrl_sqrt_0 : issue_slots_15_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_div = _T_324 ? io_dis_uops_1_bits_fp_ctrl_div_0 : _T_323 ? io_dis_uops_0_bits_fp_ctrl_div_0 : issue_slots_15_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_fma = _T_324 ? io_dis_uops_1_bits_fp_ctrl_fma_0 : _T_323 ? io_dis_uops_0_bits_fp_ctrl_fma_0 : issue_slots_15_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_fastpipe = _T_324 ? io_dis_uops_1_bits_fp_ctrl_fastpipe_0 : _T_323 ? io_dis_uops_0_bits_fp_ctrl_fastpipe_0 : issue_slots_15_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_toint = _T_324 ? io_dis_uops_1_bits_fp_ctrl_toint_0 : _T_323 ? io_dis_uops_0_bits_fp_ctrl_toint_0 : issue_slots_15_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_fromint = _T_324 ? io_dis_uops_1_bits_fp_ctrl_fromint_0 : _T_323 ? io_dis_uops_0_bits_fp_ctrl_fromint_0 : issue_slots_15_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_typeTagOut = _T_324 ? io_dis_uops_1_bits_fp_ctrl_typeTagOut_0 : _T_323 ? io_dis_uops_0_bits_fp_ctrl_typeTagOut_0 : issue_slots_15_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_typeTagIn = _T_324 ? io_dis_uops_1_bits_fp_ctrl_typeTagIn_0 : _T_323 ? io_dis_uops_0_bits_fp_ctrl_typeTagIn_0 : issue_slots_15_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_swap23 = _T_324 ? io_dis_uops_1_bits_fp_ctrl_swap23_0 : _T_323 ? io_dis_uops_0_bits_fp_ctrl_swap23_0 : issue_slots_15_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_swap12 = _T_324 ? io_dis_uops_1_bits_fp_ctrl_swap12_0 : _T_323 ? io_dis_uops_0_bits_fp_ctrl_swap12_0 : issue_slots_15_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_ren3 = _T_324 ? io_dis_uops_1_bits_fp_ctrl_ren3_0 : _T_323 ? io_dis_uops_0_bits_fp_ctrl_ren3_0 : issue_slots_15_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_ren2 = _T_324 ? io_dis_uops_1_bits_fp_ctrl_ren2_0 : _T_323 ? io_dis_uops_0_bits_fp_ctrl_ren2_0 : issue_slots_15_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_ren1 = _T_324 ? io_dis_uops_1_bits_fp_ctrl_ren1_0 : _T_323 ? io_dis_uops_0_bits_fp_ctrl_ren1_0 : issue_slots_15_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_wen = _T_324 ? io_dis_uops_1_bits_fp_ctrl_wen_0 : _T_323 ? io_dis_uops_0_bits_fp_ctrl_wen_0 : issue_slots_15_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_ldst = _T_324 ? io_dis_uops_1_bits_fp_ctrl_ldst_0 : _T_323 ? io_dis_uops_0_bits_fp_ctrl_ldst_0 : issue_slots_15_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_op2_sel = _T_324 ? io_dis_uops_1_bits_op2_sel_0 : _T_323 ? io_dis_uops_0_bits_op2_sel_0 : issue_slots_15_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_op1_sel = _T_324 ? io_dis_uops_1_bits_op1_sel_0 : _T_323 ? io_dis_uops_0_bits_op1_sel_0 : issue_slots_15_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_imm_packed = _T_324 ? io_dis_uops_1_bits_imm_packed_0 : _T_323 ? io_dis_uops_0_bits_imm_packed_0 : issue_slots_15_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_pimm = _T_324 ? io_dis_uops_1_bits_pimm_0 : _T_323 ? io_dis_uops_0_bits_pimm_0 : issue_slots_15_out_uop_pimm; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_imm_sel = _T_324 ? io_dis_uops_1_bits_imm_sel_0 : _T_323 ? io_dis_uops_0_bits_imm_sel_0 : issue_slots_15_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_imm_rename = _T_324 ? io_dis_uops_1_bits_imm_rename_0 : _T_323 ? io_dis_uops_0_bits_imm_rename_0 : issue_slots_15_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_taken = _T_324 ? io_dis_uops_1_bits_taken_0 : _T_323 ? io_dis_uops_0_bits_taken_0 : issue_slots_15_out_uop_taken; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_pc_lob = _T_324 ? io_dis_uops_1_bits_pc_lob_0 : _T_323 ? io_dis_uops_0_bits_pc_lob_0 : issue_slots_15_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_edge_inst = _T_324 ? io_dis_uops_1_bits_edge_inst_0 : _T_323 ? io_dis_uops_0_bits_edge_inst_0 : issue_slots_15_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_ftq_idx = _T_324 ? io_dis_uops_1_bits_ftq_idx_0 : _T_323 ? io_dis_uops_0_bits_ftq_idx_0 : issue_slots_15_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_is_mov = _T_324 ? io_dis_uops_1_bits_is_mov_0 : _T_323 ? io_dis_uops_0_bits_is_mov_0 : issue_slots_15_out_uop_is_mov; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_is_rocc = _T_324 ? io_dis_uops_1_bits_is_rocc_0 : _T_323 ? io_dis_uops_0_bits_is_rocc_0 : issue_slots_15_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_is_sys_pc2epc = _T_324 ? io_dis_uops_1_bits_is_sys_pc2epc_0 : _T_323 ? io_dis_uops_0_bits_is_sys_pc2epc_0 : issue_slots_15_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_is_eret = _T_324 ? io_dis_uops_1_bits_is_eret_0 : _T_323 ? io_dis_uops_0_bits_is_eret_0 : issue_slots_15_out_uop_is_eret; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_is_amo = _T_324 ? io_dis_uops_1_bits_is_amo_0 : _T_323 ? io_dis_uops_0_bits_is_amo_0 : issue_slots_15_out_uop_is_amo; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_is_sfence = _T_324 ? io_dis_uops_1_bits_is_sfence_0 : _T_323 ? io_dis_uops_0_bits_is_sfence_0 : issue_slots_15_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_is_fencei = _T_324 ? io_dis_uops_1_bits_is_fencei_0 : _T_323 ? io_dis_uops_0_bits_is_fencei_0 : issue_slots_15_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_is_fence = _T_324 ? io_dis_uops_1_bits_is_fence_0 : _T_323 ? io_dis_uops_0_bits_is_fence_0 : issue_slots_15_out_uop_is_fence; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_is_sfb = _T_324 ? io_dis_uops_1_bits_is_sfb_0 : _T_323 ? io_dis_uops_0_bits_is_sfb_0 : issue_slots_15_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_br_type = _T_324 ? io_dis_uops_1_bits_br_type_0 : _T_323 ? io_dis_uops_0_bits_br_type_0 : issue_slots_15_out_uop_br_type; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_br_tag = _T_324 ? io_dis_uops_1_bits_br_tag_0 : _T_323 ? io_dis_uops_0_bits_br_tag_0 : issue_slots_15_out_uop_br_tag; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_br_mask = _T_324 ? io_dis_uops_1_bits_br_mask_0 : _T_323 ? io_dis_uops_0_bits_br_mask_0 : issue_slots_15_out_uop_br_mask; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_dis_col_sel = _T_324 ? io_dis_uops_1_bits_dis_col_sel_0 : _T_323 ? io_dis_uops_0_bits_dis_col_sel_0 : issue_slots_15_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_iw_p3_bypass_hint = _T_324 ? _WIRE_1_iw_p3_bypass_hint : _T_323 ? _WIRE_iw_p3_bypass_hint : issue_slots_15_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:41:35, :76:38, :78:37, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_iw_p2_bypass_hint = _T_324 ? _WIRE_1_iw_p2_bypass_hint : _T_323 ? _WIRE_iw_p2_bypass_hint : issue_slots_15_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:40:35, :65:38, :68:37, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_iw_p1_bypass_hint = _T_324 ? _WIRE_1_iw_p1_bypass_hint : _T_323 ? _WIRE_iw_p1_bypass_hint : issue_slots_15_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:39:35, :57:38, :60:37, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_iw_p2_speculative_child = _T_324 ? _WIRE_1_iw_p2_speculative_child : _T_323 ? _WIRE_iw_p2_speculative_child : issue_slots_15_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:35:17, :65:38, :67:43, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_iw_p1_speculative_child = _T_324 ? _WIRE_1_iw_p1_speculative_child : _T_323 ? _WIRE_iw_p1_speculative_child : issue_slots_15_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:35:17, :57:38, :59:43, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_iw_issued_partial_dgen = ~_GEN & issue_slots_15_out_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:122:28, :194:48, :196:37] assign issue_slots_14_in_uop_bits_iw_issued_partial_agen = ~_GEN & issue_slots_15_out_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:122:28, :194:48, :196:37] assign issue_slots_14_in_uop_bits_iw_issued = ~_GEN & issue_slots_15_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:48, :196:37] assign issue_slots_14_in_uop_bits_fu_code_0 = _T_324 ? io_dis_uops_1_bits_fu_code_0_0 : _T_323 ? io_dis_uops_0_bits_fu_code_0_0 : issue_slots_15_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fu_code_1 = _T_324 ? io_dis_uops_1_bits_fu_code_1_0 : _T_323 ? io_dis_uops_0_bits_fu_code_1_0 : issue_slots_15_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fu_code_2 = _T_324 ? io_dis_uops_1_bits_fu_code_2_0 : _T_323 ? io_dis_uops_0_bits_fu_code_2_0 : issue_slots_15_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fu_code_3 = _T_324 ? io_dis_uops_1_bits_fu_code_3_0 : _T_323 ? io_dis_uops_0_bits_fu_code_3_0 : issue_slots_15_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fu_code_4 = _T_324 ? io_dis_uops_1_bits_fu_code_4_0 : _T_323 ? io_dis_uops_0_bits_fu_code_4_0 : issue_slots_15_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fu_code_5 = _T_324 ? io_dis_uops_1_bits_fu_code_5_0 : _T_323 ? io_dis_uops_0_bits_fu_code_5_0 : issue_slots_15_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fu_code_6 = _T_324 ? io_dis_uops_1_bits_fu_code_6_0 : _T_323 ? io_dis_uops_0_bits_fu_code_6_0 : issue_slots_15_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fu_code_7 = _T_324 ? io_dis_uops_1_bits_fu_code_7_0 : _T_323 ? io_dis_uops_0_bits_fu_code_7_0 : issue_slots_15_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fu_code_8 = _T_324 ? io_dis_uops_1_bits_fu_code_8_0 : _T_323 ? io_dis_uops_0_bits_fu_code_8_0 : issue_slots_15_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fu_code_9 = _T_324 ? io_dis_uops_1_bits_fu_code_9_0 : _T_323 ? io_dis_uops_0_bits_fu_code_9_0 : issue_slots_15_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_iq_type_0 = _T_324 ? io_dis_uops_1_bits_iq_type_0_0 : _T_323 ? io_dis_uops_0_bits_iq_type_0_0 : issue_slots_15_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_iq_type_1 = _T_324 ? io_dis_uops_1_bits_iq_type_1_0 : _T_323 ? io_dis_uops_0_bits_iq_type_1_0 : issue_slots_15_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_iq_type_2 = _T_324 ? io_dis_uops_1_bits_iq_type_2_0 : _T_323 ? io_dis_uops_0_bits_iq_type_2_0 : issue_slots_15_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_iq_type_3 = _T_324 ? io_dis_uops_1_bits_iq_type_3_0 : _T_323 ? io_dis_uops_0_bits_iq_type_3_0 : issue_slots_15_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_debug_pc = _T_324 ? io_dis_uops_1_bits_debug_pc_0 : _T_323 ? io_dis_uops_0_bits_debug_pc_0 : issue_slots_15_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_is_rvc = _T_324 ? io_dis_uops_1_bits_is_rvc_0 : _T_323 ? io_dis_uops_0_bits_is_rvc_0 : issue_slots_15_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_debug_inst = _T_324 ? io_dis_uops_1_bits_debug_inst_0 : _T_323 ? io_dis_uops_0_bits_debug_inst_0 : issue_slots_15_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_inst = _T_324 ? io_dis_uops_1_bits_inst_0 : _T_323 ? io_dis_uops_0_bits_inst_0 : issue_slots_15_out_uop_inst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign _issue_slots_14_clear_T = |shamts_oh_14; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_14_clear = _issue_slots_14_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_326 = shamts_oh_17 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_327 = shamts_oh_18 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_15_in_uop_valid = _T_327 ? will_be_valid_18 : _T_326 ? will_be_valid_17 : shamts_oh_16 == 3'h1 & will_be_valid_16; // @[issue-unit-age-ordered.scala:122:28, :158:23, :186:79, :191:33, :194:{28,48}, :195:37] assign issue_slots_15_in_uop_bits_debug_tsrc = _T_327 ? io_dis_uops_2_bits_debug_tsrc_0 : _T_326 ? io_dis_uops_1_bits_debug_tsrc_0 : io_dis_uops_0_bits_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_debug_fsrc = _T_327 ? io_dis_uops_2_bits_debug_fsrc_0 : _T_326 ? io_dis_uops_1_bits_debug_fsrc_0 : io_dis_uops_0_bits_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_bp_xcpt_if = _T_327 ? io_dis_uops_2_bits_bp_xcpt_if_0 : _T_326 ? io_dis_uops_1_bits_bp_xcpt_if_0 : io_dis_uops_0_bits_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_bp_debug_if = _T_327 ? io_dis_uops_2_bits_bp_debug_if_0 : _T_326 ? io_dis_uops_1_bits_bp_debug_if_0 : io_dis_uops_0_bits_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_xcpt_ma_if = _T_327 ? io_dis_uops_2_bits_xcpt_ma_if_0 : _T_326 ? io_dis_uops_1_bits_xcpt_ma_if_0 : io_dis_uops_0_bits_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_xcpt_ae_if = _T_327 ? io_dis_uops_2_bits_xcpt_ae_if_0 : _T_326 ? io_dis_uops_1_bits_xcpt_ae_if_0 : io_dis_uops_0_bits_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_xcpt_pf_if = _T_327 ? io_dis_uops_2_bits_xcpt_pf_if_0 : _T_326 ? io_dis_uops_1_bits_xcpt_pf_if_0 : io_dis_uops_0_bits_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_typ = _T_327 ? io_dis_uops_2_bits_fp_typ_0 : _T_326 ? io_dis_uops_1_bits_fp_typ_0 : io_dis_uops_0_bits_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_rm = _T_327 ? io_dis_uops_2_bits_fp_rm_0 : _T_326 ? io_dis_uops_1_bits_fp_rm_0 : io_dis_uops_0_bits_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_val = _T_327 ? io_dis_uops_2_bits_fp_val_0 : _T_326 ? io_dis_uops_1_bits_fp_val_0 : io_dis_uops_0_bits_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fcn_op = _T_327 ? io_dis_uops_2_bits_fcn_op_0 : _T_326 ? io_dis_uops_1_bits_fcn_op_0 : io_dis_uops_0_bits_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fcn_dw = _T_327 ? io_dis_uops_2_bits_fcn_dw_0 : _T_326 ? io_dis_uops_1_bits_fcn_dw_0 : io_dis_uops_0_bits_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_frs3_en = _T_327 ? io_dis_uops_2_bits_frs3_en_0 : _T_326 ? io_dis_uops_1_bits_frs3_en_0 : io_dis_uops_0_bits_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_lrs2_rtype = _T_327 ? (_T_240 ? 2'h2 : io_dis_uops_2_bits_lrs2_rtype_0) : _T_326 ? _WIRE_1_lrs2_rtype : _WIRE_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7, :35:17, :96:{42,88}, :97:32, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_lrs1_rtype = _T_327 ? io_dis_uops_2_bits_lrs1_rtype_0 : _T_326 ? io_dis_uops_1_bits_lrs1_rtype_0 : io_dis_uops_0_bits_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_dst_rtype = _T_327 ? io_dis_uops_2_bits_dst_rtype_0 : _T_326 ? io_dis_uops_1_bits_dst_rtype_0 : io_dis_uops_0_bits_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_lrs3 = _T_327 ? io_dis_uops_2_bits_lrs3_0 : _T_326 ? io_dis_uops_1_bits_lrs3_0 : io_dis_uops_0_bits_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_lrs2 = _T_327 ? io_dis_uops_2_bits_lrs2_0 : _T_326 ? io_dis_uops_1_bits_lrs2_0 : io_dis_uops_0_bits_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_lrs1 = _T_327 ? io_dis_uops_2_bits_lrs1_0 : _T_326 ? io_dis_uops_1_bits_lrs1_0 : io_dis_uops_0_bits_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_ldst = _T_327 ? io_dis_uops_2_bits_ldst_0 : _T_326 ? io_dis_uops_1_bits_ldst_0 : io_dis_uops_0_bits_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_ldst_is_rs1 = _T_327 ? io_dis_uops_2_bits_ldst_is_rs1_0 : _T_326 ? io_dis_uops_1_bits_ldst_is_rs1_0 : io_dis_uops_0_bits_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_csr_cmd = _T_327 ? io_dis_uops_2_bits_csr_cmd_0 : _T_326 ? io_dis_uops_1_bits_csr_cmd_0 : io_dis_uops_0_bits_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_flush_on_commit = _T_327 ? io_dis_uops_2_bits_flush_on_commit_0 : _T_326 ? io_dis_uops_1_bits_flush_on_commit_0 : io_dis_uops_0_bits_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_is_unique = _T_327 ? io_dis_uops_2_bits_is_unique_0 : _T_326 ? io_dis_uops_1_bits_is_unique_0 : io_dis_uops_0_bits_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_uses_stq = _T_327 ? io_dis_uops_2_bits_uses_stq_0 : _T_326 ? io_dis_uops_1_bits_uses_stq_0 : io_dis_uops_0_bits_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_uses_ldq = _T_327 ? io_dis_uops_2_bits_uses_ldq_0 : _T_326 ? io_dis_uops_1_bits_uses_ldq_0 : io_dis_uops_0_bits_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_mem_signed = _T_327 ? io_dis_uops_2_bits_mem_signed_0 : _T_326 ? io_dis_uops_1_bits_mem_signed_0 : io_dis_uops_0_bits_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_mem_size = _T_327 ? io_dis_uops_2_bits_mem_size_0 : _T_326 ? io_dis_uops_1_bits_mem_size_0 : io_dis_uops_0_bits_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_mem_cmd = _T_327 ? io_dis_uops_2_bits_mem_cmd_0 : _T_326 ? io_dis_uops_1_bits_mem_cmd_0 : io_dis_uops_0_bits_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_exc_cause = _T_327 ? io_dis_uops_2_bits_exc_cause_0 : _T_326 ? io_dis_uops_1_bits_exc_cause_0 : io_dis_uops_0_bits_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_exception = _T_327 ? io_dis_uops_2_bits_exception_0 : _T_326 ? io_dis_uops_1_bits_exception_0 : io_dis_uops_0_bits_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_stale_pdst = _T_327 ? io_dis_uops_2_bits_stale_pdst_0 : _T_326 ? io_dis_uops_1_bits_stale_pdst_0 : io_dis_uops_0_bits_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_prs2_busy = _T_327 ? ~_T_240 & ((|{prs2_rebusys_0_2, io_child_rebusys_0 & io_dis_uops_2_bits_iw_p2_speculative_child_0}) ? io_dis_uops_2_bits_lrs2_rtype_0 == 2'h0 : ~_T_197 & io_dis_uops_2_bits_prs2_busy_0) : _T_326 ? _WIRE_1_prs2_busy : _WIRE_prs2_busy; // @[issue-unit-age-ordered.scala:22:7, :35:17, :51:95, :65:{32,38}, :66:29, :71:{37,59,106,116}, :72:{29,63}, :96:{42,88}, :98:32, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_prs1_busy = _T_327 ? ((|{prs1_rebusys_0_2, io_child_rebusys_0 & io_dis_uops_2_bits_iw_p1_speculative_child_0}) ? io_dis_uops_2_bits_lrs1_rtype_0 == 2'h0 : ~_T_167 & io_dis_uops_2_bits_prs1_busy_0) : _T_326 ? _WIRE_1_prs1_busy : _WIRE_prs1_busy; // @[issue-unit-age-ordered.scala:22:7, :35:17, :50:95, :57:{32,38}, :58:29, :62:{37,59,106,116}, :63:{29,63}, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_ppred = _T_327 ? io_dis_uops_2_bits_ppred_0 : _T_326 ? io_dis_uops_1_bits_ppred_0 : io_dis_uops_0_bits_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_prs3 = _T_327 ? io_dis_uops_2_bits_prs3_0 : _T_326 ? io_dis_uops_1_bits_prs3_0 : io_dis_uops_0_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_prs2 = _T_327 ? io_dis_uops_2_bits_prs2_0 : _T_326 ? io_dis_uops_1_bits_prs2_0 : io_dis_uops_0_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_prs1 = _T_327 ? io_dis_uops_2_bits_prs1_0 : _T_326 ? io_dis_uops_1_bits_prs1_0 : io_dis_uops_0_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_pdst = _T_327 ? io_dis_uops_2_bits_pdst_0 : _T_326 ? io_dis_uops_1_bits_pdst_0 : io_dis_uops_0_bits_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_rxq_idx = _T_327 ? io_dis_uops_2_bits_rxq_idx_0 : _T_326 ? io_dis_uops_1_bits_rxq_idx_0 : io_dis_uops_0_bits_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_stq_idx = _T_327 ? io_dis_uops_2_bits_stq_idx_0 : _T_326 ? io_dis_uops_1_bits_stq_idx_0 : io_dis_uops_0_bits_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_ldq_idx = _T_327 ? io_dis_uops_2_bits_ldq_idx_0 : _T_326 ? io_dis_uops_1_bits_ldq_idx_0 : io_dis_uops_0_bits_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_rob_idx = _T_327 ? io_dis_uops_2_bits_rob_idx_0 : _T_326 ? io_dis_uops_1_bits_rob_idx_0 : io_dis_uops_0_bits_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_vec = _T_327 ? io_dis_uops_2_bits_fp_ctrl_vec_0 : _T_326 ? io_dis_uops_1_bits_fp_ctrl_vec_0 : io_dis_uops_0_bits_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_wflags = _T_327 ? io_dis_uops_2_bits_fp_ctrl_wflags_0 : _T_326 ? io_dis_uops_1_bits_fp_ctrl_wflags_0 : io_dis_uops_0_bits_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_sqrt = _T_327 ? io_dis_uops_2_bits_fp_ctrl_sqrt_0 : _T_326 ? io_dis_uops_1_bits_fp_ctrl_sqrt_0 : io_dis_uops_0_bits_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_div = _T_327 ? io_dis_uops_2_bits_fp_ctrl_div_0 : _T_326 ? io_dis_uops_1_bits_fp_ctrl_div_0 : io_dis_uops_0_bits_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_fma = _T_327 ? io_dis_uops_2_bits_fp_ctrl_fma_0 : _T_326 ? io_dis_uops_1_bits_fp_ctrl_fma_0 : io_dis_uops_0_bits_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_fastpipe = _T_327 ? io_dis_uops_2_bits_fp_ctrl_fastpipe_0 : _T_326 ? io_dis_uops_1_bits_fp_ctrl_fastpipe_0 : io_dis_uops_0_bits_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_toint = _T_327 ? io_dis_uops_2_bits_fp_ctrl_toint_0 : _T_326 ? io_dis_uops_1_bits_fp_ctrl_toint_0 : io_dis_uops_0_bits_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_fromint = _T_327 ? io_dis_uops_2_bits_fp_ctrl_fromint_0 : _T_326 ? io_dis_uops_1_bits_fp_ctrl_fromint_0 : io_dis_uops_0_bits_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_typeTagOut = _T_327 ? io_dis_uops_2_bits_fp_ctrl_typeTagOut_0 : _T_326 ? io_dis_uops_1_bits_fp_ctrl_typeTagOut_0 : io_dis_uops_0_bits_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_typeTagIn = _T_327 ? io_dis_uops_2_bits_fp_ctrl_typeTagIn_0 : _T_326 ? io_dis_uops_1_bits_fp_ctrl_typeTagIn_0 : io_dis_uops_0_bits_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_swap23 = _T_327 ? io_dis_uops_2_bits_fp_ctrl_swap23_0 : _T_326 ? io_dis_uops_1_bits_fp_ctrl_swap23_0 : io_dis_uops_0_bits_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_swap12 = _T_327 ? io_dis_uops_2_bits_fp_ctrl_swap12_0 : _T_326 ? io_dis_uops_1_bits_fp_ctrl_swap12_0 : io_dis_uops_0_bits_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_ren3 = _T_327 ? io_dis_uops_2_bits_fp_ctrl_ren3_0 : _T_326 ? io_dis_uops_1_bits_fp_ctrl_ren3_0 : io_dis_uops_0_bits_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_ren2 = _T_327 ? io_dis_uops_2_bits_fp_ctrl_ren2_0 : _T_326 ? io_dis_uops_1_bits_fp_ctrl_ren2_0 : io_dis_uops_0_bits_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_ren1 = _T_327 ? io_dis_uops_2_bits_fp_ctrl_ren1_0 : _T_326 ? io_dis_uops_1_bits_fp_ctrl_ren1_0 : io_dis_uops_0_bits_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_wen = _T_327 ? io_dis_uops_2_bits_fp_ctrl_wen_0 : _T_326 ? io_dis_uops_1_bits_fp_ctrl_wen_0 : io_dis_uops_0_bits_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_ldst = _T_327 ? io_dis_uops_2_bits_fp_ctrl_ldst_0 : _T_326 ? io_dis_uops_1_bits_fp_ctrl_ldst_0 : io_dis_uops_0_bits_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_op2_sel = _T_327 ? io_dis_uops_2_bits_op2_sel_0 : _T_326 ? io_dis_uops_1_bits_op2_sel_0 : io_dis_uops_0_bits_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_op1_sel = _T_327 ? io_dis_uops_2_bits_op1_sel_0 : _T_326 ? io_dis_uops_1_bits_op1_sel_0 : io_dis_uops_0_bits_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_imm_packed = _T_327 ? io_dis_uops_2_bits_imm_packed_0 : _T_326 ? io_dis_uops_1_bits_imm_packed_0 : io_dis_uops_0_bits_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_pimm = _T_327 ? io_dis_uops_2_bits_pimm_0 : _T_326 ? io_dis_uops_1_bits_pimm_0 : io_dis_uops_0_bits_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_imm_sel = _T_327 ? io_dis_uops_2_bits_imm_sel_0 : _T_326 ? io_dis_uops_1_bits_imm_sel_0 : io_dis_uops_0_bits_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_imm_rename = _T_327 ? io_dis_uops_2_bits_imm_rename_0 : _T_326 ? io_dis_uops_1_bits_imm_rename_0 : io_dis_uops_0_bits_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_taken = _T_327 ? io_dis_uops_2_bits_taken_0 : _T_326 ? io_dis_uops_1_bits_taken_0 : io_dis_uops_0_bits_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_pc_lob = _T_327 ? io_dis_uops_2_bits_pc_lob_0 : _T_326 ? io_dis_uops_1_bits_pc_lob_0 : io_dis_uops_0_bits_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_edge_inst = _T_327 ? io_dis_uops_2_bits_edge_inst_0 : _T_326 ? io_dis_uops_1_bits_edge_inst_0 : io_dis_uops_0_bits_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_ftq_idx = _T_327 ? io_dis_uops_2_bits_ftq_idx_0 : _T_326 ? io_dis_uops_1_bits_ftq_idx_0 : io_dis_uops_0_bits_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_is_mov = _T_327 ? io_dis_uops_2_bits_is_mov_0 : _T_326 ? io_dis_uops_1_bits_is_mov_0 : io_dis_uops_0_bits_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_is_rocc = _T_327 ? io_dis_uops_2_bits_is_rocc_0 : _T_326 ? io_dis_uops_1_bits_is_rocc_0 : io_dis_uops_0_bits_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_is_sys_pc2epc = _T_327 ? io_dis_uops_2_bits_is_sys_pc2epc_0 : _T_326 ? io_dis_uops_1_bits_is_sys_pc2epc_0 : io_dis_uops_0_bits_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_is_eret = _T_327 ? io_dis_uops_2_bits_is_eret_0 : _T_326 ? io_dis_uops_1_bits_is_eret_0 : io_dis_uops_0_bits_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_is_amo = _T_327 ? io_dis_uops_2_bits_is_amo_0 : _T_326 ? io_dis_uops_1_bits_is_amo_0 : io_dis_uops_0_bits_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_is_sfence = _T_327 ? io_dis_uops_2_bits_is_sfence_0 : _T_326 ? io_dis_uops_1_bits_is_sfence_0 : io_dis_uops_0_bits_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_is_fencei = _T_327 ? io_dis_uops_2_bits_is_fencei_0 : _T_326 ? io_dis_uops_1_bits_is_fencei_0 : io_dis_uops_0_bits_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_is_fence = _T_327 ? io_dis_uops_2_bits_is_fence_0 : _T_326 ? io_dis_uops_1_bits_is_fence_0 : io_dis_uops_0_bits_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_is_sfb = _T_327 ? io_dis_uops_2_bits_is_sfb_0 : _T_326 ? io_dis_uops_1_bits_is_sfb_0 : io_dis_uops_0_bits_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_br_type = _T_327 ? io_dis_uops_2_bits_br_type_0 : _T_326 ? io_dis_uops_1_bits_br_type_0 : io_dis_uops_0_bits_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_br_tag = _T_327 ? io_dis_uops_2_bits_br_tag_0 : _T_326 ? io_dis_uops_1_bits_br_tag_0 : io_dis_uops_0_bits_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_br_mask = _T_327 ? io_dis_uops_2_bits_br_mask_0 : _T_326 ? io_dis_uops_1_bits_br_mask_0 : io_dis_uops_0_bits_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_dis_col_sel = _T_327 ? io_dis_uops_2_bits_dis_col_sel_0 : _T_326 ? io_dis_uops_1_bits_dis_col_sel_0 : io_dis_uops_0_bits_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_iw_p3_bypass_hint = _T_327 ? (prs3_wakeups_0_2 | prs3_wakeups_1_2 | prs3_wakeups_2_2 | prs3_wakeups_3_2 | prs3_wakeups_4_2) & (prs3_wakeups_0_2 & io_wakeup_ports_0_bits_bypassable_0 | prs3_wakeups_2_2 | prs3_wakeups_3_2 | prs3_wakeups_4_2) : _T_326 ? _WIRE_1_iw_p3_bypass_hint : _WIRE_iw_p3_bypass_hint; // @[Mux.scala:30:73] assign issue_slots_15_in_uop_bits_iw_p2_bypass_hint = _T_327 ? _T_197 & (prs2_wakeups_0_2 & io_wakeup_ports_0_bits_bypassable_0 | prs2_wakeups_2_2 | prs2_wakeups_3_2 | prs2_wakeups_4_2) : _T_326 ? _WIRE_1_iw_p2_bypass_hint : _WIRE_iw_p2_bypass_hint; // @[Mux.scala:30:73] assign issue_slots_15_in_uop_bits_iw_p1_bypass_hint = _T_327 ? _T_167 & (prs1_wakeups_0_2 & io_wakeup_ports_0_bits_bypassable_0 | prs1_wakeups_2_2 | prs1_wakeups_3_2 | prs1_wakeups_4_2) : _T_326 ? _WIRE_1_iw_p1_bypass_hint : _WIRE_iw_p1_bypass_hint; // @[Mux.scala:30:73] assign issue_slots_15_in_uop_bits_iw_p2_speculative_child = _T_327 ? (_T_197 ? (prs2_wakeups_0_2 ? io_wakeup_ports_0_bits_speculative_mask_0 : 3'h0) | {prs2_wakeups_4_2, prs2_wakeups_3_2, prs2_wakeups_2_2} : io_dis_uops_2_bits_iw_p2_speculative_child_0) : _T_326 ? _WIRE_1_iw_p2_speculative_child : _WIRE_iw_p2_speculative_child; // @[Mux.scala:30:73] assign issue_slots_15_in_uop_bits_iw_p1_speculative_child = _T_327 ? (_T_167 ? (prs1_wakeups_0_2 ? io_wakeup_ports_0_bits_speculative_mask_0 : 3'h0) | {prs1_wakeups_4_2, prs1_wakeups_3_2, prs1_wakeups_2_2} : io_dis_uops_2_bits_iw_p1_speculative_child_0) : _T_326 ? _WIRE_1_iw_p1_speculative_child : _WIRE_iw_p1_speculative_child; // @[Mux.scala:30:73] assign issue_slots_15_in_uop_bits_fu_code_0 = _T_327 ? io_dis_uops_2_bits_fu_code_0_0 : _T_326 ? io_dis_uops_1_bits_fu_code_0_0 : io_dis_uops_0_bits_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fu_code_1 = _T_327 ? io_dis_uops_2_bits_fu_code_1_0 : _T_326 ? io_dis_uops_1_bits_fu_code_1_0 : io_dis_uops_0_bits_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fu_code_2 = _T_327 ? io_dis_uops_2_bits_fu_code_2_0 : _T_326 ? io_dis_uops_1_bits_fu_code_2_0 : io_dis_uops_0_bits_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fu_code_3 = _T_327 ? io_dis_uops_2_bits_fu_code_3_0 : _T_326 ? io_dis_uops_1_bits_fu_code_3_0 : io_dis_uops_0_bits_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fu_code_4 = _T_327 ? io_dis_uops_2_bits_fu_code_4_0 : _T_326 ? io_dis_uops_1_bits_fu_code_4_0 : io_dis_uops_0_bits_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fu_code_5 = _T_327 ? io_dis_uops_2_bits_fu_code_5_0 : _T_326 ? io_dis_uops_1_bits_fu_code_5_0 : io_dis_uops_0_bits_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fu_code_6 = _T_327 ? io_dis_uops_2_bits_fu_code_6_0 : _T_326 ? io_dis_uops_1_bits_fu_code_6_0 : io_dis_uops_0_bits_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fu_code_7 = _T_327 ? io_dis_uops_2_bits_fu_code_7_0 : _T_326 ? io_dis_uops_1_bits_fu_code_7_0 : io_dis_uops_0_bits_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fu_code_8 = _T_327 ? io_dis_uops_2_bits_fu_code_8_0 : _T_326 ? io_dis_uops_1_bits_fu_code_8_0 : io_dis_uops_0_bits_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fu_code_9 = _T_327 ? io_dis_uops_2_bits_fu_code_9_0 : _T_326 ? io_dis_uops_1_bits_fu_code_9_0 : io_dis_uops_0_bits_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_iq_type_0 = _T_327 ? io_dis_uops_2_bits_iq_type_0_0 : _T_326 ? io_dis_uops_1_bits_iq_type_0_0 : io_dis_uops_0_bits_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_iq_type_1 = _T_327 ? io_dis_uops_2_bits_iq_type_1_0 : _T_326 ? io_dis_uops_1_bits_iq_type_1_0 : io_dis_uops_0_bits_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_iq_type_2 = _T_327 ? io_dis_uops_2_bits_iq_type_2_0 : _T_326 ? io_dis_uops_1_bits_iq_type_2_0 : io_dis_uops_0_bits_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_iq_type_3 = _T_327 ? io_dis_uops_2_bits_iq_type_3_0 : _T_326 ? io_dis_uops_1_bits_iq_type_3_0 : io_dis_uops_0_bits_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_debug_pc = _T_327 ? io_dis_uops_2_bits_debug_pc_0 : _T_326 ? io_dis_uops_1_bits_debug_pc_0 : io_dis_uops_0_bits_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_is_rvc = _T_327 ? io_dis_uops_2_bits_is_rvc_0 : _T_326 ? io_dis_uops_1_bits_is_rvc_0 : io_dis_uops_0_bits_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_debug_inst = _T_327 ? io_dis_uops_2_bits_debug_inst_0 : _T_326 ? io_dis_uops_1_bits_debug_inst_0 : io_dis_uops_0_bits_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_inst = _T_327 ? io_dis_uops_2_bits_inst_0 : _T_326 ? io_dis_uops_1_bits_inst_0 : io_dis_uops_0_bits_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign _issue_slots_15_clear_T = |shamts_oh_15; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_15_clear = _issue_slots_15_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] reg is_available_0; // @[issue-unit-age-ordered.scala:208:25] reg is_available_1; // @[issue-unit-age-ordered.scala:208:25] reg is_available_2; // @[issue-unit-age-ordered.scala:208:25] reg is_available_3; // @[issue-unit-age-ordered.scala:208:25] reg is_available_4; // @[issue-unit-age-ordered.scala:208:25] reg is_available_5; // @[issue-unit-age-ordered.scala:208:25] reg is_available_6; // @[issue-unit-age-ordered.scala:208:25] reg is_available_7; // @[issue-unit-age-ordered.scala:208:25] reg is_available_8; // @[issue-unit-age-ordered.scala:208:25] reg is_available_9; // @[issue-unit-age-ordered.scala:208:25] reg is_available_10; // @[issue-unit-age-ordered.scala:208:25] reg is_available_11; // @[issue-unit-age-ordered.scala:208:25] reg is_available_12; // @[issue-unit-age-ordered.scala:208:25] reg is_available_13; // @[issue-unit-age-ordered.scala:208:25] reg is_available_14; // @[issue-unit-age-ordered.scala:208:25] reg is_available_15; // @[issue-unit-age-ordered.scala:208:25] wire [1:0] _GEN_0 = {1'h0, is_available_0} + {1'h0, is_available_1}; // @[issue-unit-age-ordered.scala:208:25, :212:45] wire [1:0] _io_dis_uops_0_ready_T; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_0_ready_T = _GEN_0; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_1_ready_T = _GEN_0; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_2_ready_T; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_2_ready_T = _GEN_0; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_0_ready_T_1 = _io_dis_uops_0_ready_T; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _GEN_1 = {1'h0, is_available_2} + {1'h0, is_available_3}; // @[issue-unit-age-ordered.scala:208:25, :212:45] wire [1:0] _io_dis_uops_0_ready_T_2; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_0_ready_T_2 = _GEN_1; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_2; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_1_ready_T_2 = _GEN_1; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_2_ready_T_2; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_2_ready_T_2 = _GEN_1; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_0_ready_T_3 = _io_dis_uops_0_ready_T_2; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_0_ready_T_4 = {1'h0, _io_dis_uops_0_ready_T_1} + {1'h0, _io_dis_uops_0_ready_T_3}; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_0_ready_T_5 = _io_dis_uops_0_ready_T_4; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _GEN_2 = {1'h0, is_available_4} + {1'h0, is_available_5}; // @[issue-unit-age-ordered.scala:208:25, :212:45] wire [1:0] _io_dis_uops_0_ready_T_6; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_0_ready_T_6 = _GEN_2; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_6; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_1_ready_T_6 = _GEN_2; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_2_ready_T_6; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_2_ready_T_6 = _GEN_2; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_0_ready_T_7 = _io_dis_uops_0_ready_T_6; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _GEN_3 = {1'h0, is_available_6} + {1'h0, is_available_7}; // @[issue-unit-age-ordered.scala:208:25, :212:45] wire [1:0] _io_dis_uops_0_ready_T_8; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_0_ready_T_8 = _GEN_3; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_8; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_1_ready_T_8 = _GEN_3; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_2_ready_T_8; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_2_ready_T_8 = _GEN_3; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_0_ready_T_9 = _io_dis_uops_0_ready_T_8; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_0_ready_T_10 = {1'h0, _io_dis_uops_0_ready_T_7} + {1'h0, _io_dis_uops_0_ready_T_9}; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_0_ready_T_11 = _io_dis_uops_0_ready_T_10; // @[issue-unit-age-ordered.scala:212:45] wire [3:0] _io_dis_uops_0_ready_T_12 = {1'h0, _io_dis_uops_0_ready_T_5} + {1'h0, _io_dis_uops_0_ready_T_11}; // @[issue-unit-age-ordered.scala:212:45] wire [3:0] _io_dis_uops_0_ready_T_13 = _io_dis_uops_0_ready_T_12; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _GEN_4 = {1'h0, is_available_8} + {1'h0, is_available_9}; // @[issue-unit-age-ordered.scala:208:25, :212:45] wire [1:0] _io_dis_uops_0_ready_T_14; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_0_ready_T_14 = _GEN_4; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_14; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_1_ready_T_14 = _GEN_4; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_2_ready_T_14; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_2_ready_T_14 = _GEN_4; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_0_ready_T_15 = _io_dis_uops_0_ready_T_14; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _GEN_5 = {1'h0, is_available_10} + {1'h0, is_available_11}; // @[issue-unit-age-ordered.scala:208:25, :212:45] wire [1:0] _io_dis_uops_0_ready_T_16; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_0_ready_T_16 = _GEN_5; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_16; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_1_ready_T_16 = _GEN_5; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_2_ready_T_16; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_2_ready_T_16 = _GEN_5; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_0_ready_T_17 = _io_dis_uops_0_ready_T_16; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_0_ready_T_18 = {1'h0, _io_dis_uops_0_ready_T_15} + {1'h0, _io_dis_uops_0_ready_T_17}; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_0_ready_T_19 = _io_dis_uops_0_ready_T_18; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _GEN_6 = {1'h0, is_available_12} + {1'h0, is_available_13}; // @[issue-unit-age-ordered.scala:208:25, :212:45] wire [1:0] _io_dis_uops_0_ready_T_20; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_0_ready_T_20 = _GEN_6; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_20; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_1_ready_T_20 = _GEN_6; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_2_ready_T_20; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_2_ready_T_20 = _GEN_6; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_0_ready_T_21 = _io_dis_uops_0_ready_T_20; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _GEN_7 = {1'h0, is_available_14} + {1'h0, is_available_15}; // @[issue-unit-age-ordered.scala:208:25, :212:45] wire [1:0] _io_dis_uops_0_ready_T_22; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_0_ready_T_22 = _GEN_7; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_22; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_1_ready_T_22 = _GEN_7; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_2_ready_T_22; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_2_ready_T_22 = _GEN_7; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_0_ready_T_23 = _io_dis_uops_0_ready_T_22; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_0_ready_T_24 = {1'h0, _io_dis_uops_0_ready_T_21} + {1'h0, _io_dis_uops_0_ready_T_23}; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_0_ready_T_25 = _io_dis_uops_0_ready_T_24; // @[issue-unit-age-ordered.scala:212:45] wire [3:0] _io_dis_uops_0_ready_T_26 = {1'h0, _io_dis_uops_0_ready_T_19} + {1'h0, _io_dis_uops_0_ready_T_25}; // @[issue-unit-age-ordered.scala:212:45] wire [3:0] _io_dis_uops_0_ready_T_27 = _io_dis_uops_0_ready_T_26; // @[issue-unit-age-ordered.scala:212:45] wire [4:0] _io_dis_uops_0_ready_T_28 = {1'h0, _io_dis_uops_0_ready_T_13} + {1'h0, _io_dis_uops_0_ready_T_27}; // @[issue-unit-age-ordered.scala:212:45] wire [4:0] _io_dis_uops_0_ready_T_29 = _io_dis_uops_0_ready_T_28; // @[issue-unit-age-ordered.scala:212:45] wire _GEN_8 = io_dis_uops_0_ready_0 & io_dis_uops_0_valid_0; // @[Decoupled.scala:51:35] wire _io_dis_uops_0_ready_T_30; // @[Decoupled.scala:51:35] assign _io_dis_uops_0_ready_T_30 = _GEN_8; // @[Decoupled.scala:51:35] wire _io_dis_uops_1_ready_T_30; // @[Decoupled.scala:51:35] assign _io_dis_uops_1_ready_T_30 = _GEN_8; // @[Decoupled.scala:51:35] wire _io_dis_uops_2_ready_T_30; // @[Decoupled.scala:51:35] assign _io_dis_uops_2_ready_T_30 = _GEN_8; // @[Decoupled.scala:51:35] wire _GEN_9 = io_dis_uops_1_ready_0 & io_dis_uops_1_valid_0; // @[Decoupled.scala:51:35] wire _io_dis_uops_0_ready_T_31; // @[Decoupled.scala:51:35] assign _io_dis_uops_0_ready_T_31 = _GEN_9; // @[Decoupled.scala:51:35] wire _io_dis_uops_1_ready_T_31; // @[Decoupled.scala:51:35] assign _io_dis_uops_1_ready_T_31 = _GEN_9; // @[Decoupled.scala:51:35] wire _io_dis_uops_2_ready_T_31; // @[Decoupled.scala:51:35] assign _io_dis_uops_2_ready_T_31 = _GEN_9; // @[Decoupled.scala:51:35] wire _GEN_10 = io_dis_uops_2_ready_0 & io_dis_uops_2_valid_0; // @[Decoupled.scala:51:35] wire _io_dis_uops_0_ready_T_32; // @[Decoupled.scala:51:35] assign _io_dis_uops_0_ready_T_32 = _GEN_10; // @[Decoupled.scala:51:35] wire _io_dis_uops_1_ready_T_32; // @[Decoupled.scala:51:35] assign _io_dis_uops_1_ready_T_32 = _GEN_10; // @[Decoupled.scala:51:35] wire _io_dis_uops_2_ready_T_32; // @[Decoupled.scala:51:35] assign _io_dis_uops_2_ready_T_32 = _GEN_10; // @[Decoupled.scala:51:35] wire [1:0] _io_dis_uops_0_ready_T_33 = {1'h0, _io_dis_uops_0_ready_T_31} + {1'h0, _io_dis_uops_0_ready_T_32}; // @[Decoupled.scala:51:35] wire [1:0] _io_dis_uops_0_ready_T_34 = _io_dis_uops_0_ready_T_33; // @[issue-unit-age-ordered.scala:212:100] wire [2:0] _io_dis_uops_0_ready_T_35 = {2'h0, _io_dis_uops_0_ready_T_30} + {1'h0, _io_dis_uops_0_ready_T_34}; // @[Decoupled.scala:51:35] wire [1:0] _io_dis_uops_0_ready_T_36 = _io_dis_uops_0_ready_T_35[1:0]; // @[issue-unit-age-ordered.scala:212:100] wire [4:0] _io_dis_uops_0_ready_T_37 = {3'h0, _io_dis_uops_0_ready_T_36}; // @[issue-unit-age-ordered.scala:212:{90,100}] wire [3:0] _io_dis_uops_0_ready_T_38 = _io_dis_uops_0_ready_T_37[3:0]; // @[issue-unit-age-ordered.scala:212:90] wire _io_dis_uops_0_ready_T_39 = _io_dis_uops_0_ready_T_29 > {1'h0, _io_dis_uops_0_ready_T_38}; // @[issue-unit-age-ordered.scala:212:{45,60,90}] reg io_dis_uops_0_ready_REG; // @[issue-unit-age-ordered.scala:212:36] assign io_dis_uops_0_ready_0 = io_dis_uops_0_ready_REG; // @[issue-unit-age-ordered.scala:22:7, :212:36] wire [1:0] _io_dis_uops_1_ready_T_1 = _io_dis_uops_1_ready_T; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_3 = _io_dis_uops_1_ready_T_2; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_1_ready_T_4 = {1'h0, _io_dis_uops_1_ready_T_1} + {1'h0, _io_dis_uops_1_ready_T_3}; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_1_ready_T_5 = _io_dis_uops_1_ready_T_4; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_7 = _io_dis_uops_1_ready_T_6; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_9 = _io_dis_uops_1_ready_T_8; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_1_ready_T_10 = {1'h0, _io_dis_uops_1_ready_T_7} + {1'h0, _io_dis_uops_1_ready_T_9}; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_1_ready_T_11 = _io_dis_uops_1_ready_T_10; // @[issue-unit-age-ordered.scala:212:45] wire [3:0] _io_dis_uops_1_ready_T_12 = {1'h0, _io_dis_uops_1_ready_T_5} + {1'h0, _io_dis_uops_1_ready_T_11}; // @[issue-unit-age-ordered.scala:212:45] wire [3:0] _io_dis_uops_1_ready_T_13 = _io_dis_uops_1_ready_T_12; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_15 = _io_dis_uops_1_ready_T_14; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_17 = _io_dis_uops_1_ready_T_16; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_1_ready_T_18 = {1'h0, _io_dis_uops_1_ready_T_15} + {1'h0, _io_dis_uops_1_ready_T_17}; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_1_ready_T_19 = _io_dis_uops_1_ready_T_18; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_21 = _io_dis_uops_1_ready_T_20; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_23 = _io_dis_uops_1_ready_T_22; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_1_ready_T_24 = {1'h0, _io_dis_uops_1_ready_T_21} + {1'h0, _io_dis_uops_1_ready_T_23}; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_1_ready_T_25 = _io_dis_uops_1_ready_T_24; // @[issue-unit-age-ordered.scala:212:45] wire [3:0] _io_dis_uops_1_ready_T_26 = {1'h0, _io_dis_uops_1_ready_T_19} + {1'h0, _io_dis_uops_1_ready_T_25}; // @[issue-unit-age-ordered.scala:212:45] wire [3:0] _io_dis_uops_1_ready_T_27 = _io_dis_uops_1_ready_T_26; // @[issue-unit-age-ordered.scala:212:45] wire [4:0] _io_dis_uops_1_ready_T_28 = {1'h0, _io_dis_uops_1_ready_T_13} + {1'h0, _io_dis_uops_1_ready_T_27}; // @[issue-unit-age-ordered.scala:212:45] wire [4:0] _io_dis_uops_1_ready_T_29 = _io_dis_uops_1_ready_T_28; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_33 = {1'h0, _io_dis_uops_1_ready_T_31} + {1'h0, _io_dis_uops_1_ready_T_32}; // @[Decoupled.scala:51:35] wire [1:0] _io_dis_uops_1_ready_T_34 = _io_dis_uops_1_ready_T_33; // @[issue-unit-age-ordered.scala:212:100] wire [2:0] _io_dis_uops_1_ready_T_35 = {2'h0, _io_dis_uops_1_ready_T_30} + {1'h0, _io_dis_uops_1_ready_T_34}; // @[Decoupled.scala:51:35] wire [1:0] _io_dis_uops_1_ready_T_36 = _io_dis_uops_1_ready_T_35[1:0]; // @[issue-unit-age-ordered.scala:212:100] wire [4:0] _io_dis_uops_1_ready_T_37 = {3'h0, _io_dis_uops_1_ready_T_36} + 5'h1; // @[issue-unit-age-ordered.scala:212:{90,100}] wire [3:0] _io_dis_uops_1_ready_T_38 = _io_dis_uops_1_ready_T_37[3:0]; // @[issue-unit-age-ordered.scala:212:90] wire _io_dis_uops_1_ready_T_39 = _io_dis_uops_1_ready_T_29 > {1'h0, _io_dis_uops_1_ready_T_38}; // @[issue-unit-age-ordered.scala:212:{45,60,90}] reg io_dis_uops_1_ready_REG; // @[issue-unit-age-ordered.scala:212:36] assign io_dis_uops_1_ready_0 = io_dis_uops_1_ready_REG; // @[issue-unit-age-ordered.scala:22:7, :212:36] wire [1:0] _io_dis_uops_2_ready_T_1 = _io_dis_uops_2_ready_T; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_2_ready_T_3 = _io_dis_uops_2_ready_T_2; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_2_ready_T_4 = {1'h0, _io_dis_uops_2_ready_T_1} + {1'h0, _io_dis_uops_2_ready_T_3}; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_2_ready_T_5 = _io_dis_uops_2_ready_T_4; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_2_ready_T_7 = _io_dis_uops_2_ready_T_6; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_2_ready_T_9 = _io_dis_uops_2_ready_T_8; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_2_ready_T_10 = {1'h0, _io_dis_uops_2_ready_T_7} + {1'h0, _io_dis_uops_2_ready_T_9}; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_2_ready_T_11 = _io_dis_uops_2_ready_T_10; // @[issue-unit-age-ordered.scala:212:45] wire [3:0] _io_dis_uops_2_ready_T_12 = {1'h0, _io_dis_uops_2_ready_T_5} + {1'h0, _io_dis_uops_2_ready_T_11}; // @[issue-unit-age-ordered.scala:212:45] wire [3:0] _io_dis_uops_2_ready_T_13 = _io_dis_uops_2_ready_T_12; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_2_ready_T_15 = _io_dis_uops_2_ready_T_14; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_2_ready_T_17 = _io_dis_uops_2_ready_T_16; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_2_ready_T_18 = {1'h0, _io_dis_uops_2_ready_T_15} + {1'h0, _io_dis_uops_2_ready_T_17}; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_2_ready_T_19 = _io_dis_uops_2_ready_T_18; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_2_ready_T_21 = _io_dis_uops_2_ready_T_20; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_2_ready_T_23 = _io_dis_uops_2_ready_T_22; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_2_ready_T_24 = {1'h0, _io_dis_uops_2_ready_T_21} + {1'h0, _io_dis_uops_2_ready_T_23}; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_2_ready_T_25 = _io_dis_uops_2_ready_T_24; // @[issue-unit-age-ordered.scala:212:45] wire [3:0] _io_dis_uops_2_ready_T_26 = {1'h0, _io_dis_uops_2_ready_T_19} + {1'h0, _io_dis_uops_2_ready_T_25}; // @[issue-unit-age-ordered.scala:212:45] wire [3:0] _io_dis_uops_2_ready_T_27 = _io_dis_uops_2_ready_T_26; // @[issue-unit-age-ordered.scala:212:45] wire [4:0] _io_dis_uops_2_ready_T_28 = {1'h0, _io_dis_uops_2_ready_T_13} + {1'h0, _io_dis_uops_2_ready_T_27}; // @[issue-unit-age-ordered.scala:212:45] wire [4:0] _io_dis_uops_2_ready_T_29 = _io_dis_uops_2_ready_T_28; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_2_ready_T_33 = {1'h0, _io_dis_uops_2_ready_T_31} + {1'h0, _io_dis_uops_2_ready_T_32}; // @[Decoupled.scala:51:35] wire [1:0] _io_dis_uops_2_ready_T_34 = _io_dis_uops_2_ready_T_33; // @[issue-unit-age-ordered.scala:212:100] wire [2:0] _io_dis_uops_2_ready_T_35 = {2'h0, _io_dis_uops_2_ready_T_30} + {1'h0, _io_dis_uops_2_ready_T_34}; // @[Decoupled.scala:51:35] wire [1:0] _io_dis_uops_2_ready_T_36 = _io_dis_uops_2_ready_T_35[1:0]; // @[issue-unit-age-ordered.scala:212:100] wire [4:0] _io_dis_uops_2_ready_T_37 = {3'h0, _io_dis_uops_2_ready_T_36} + 5'h2; // @[issue-unit-age-ordered.scala:212:{90,100}] wire [3:0] _io_dis_uops_2_ready_T_38 = _io_dis_uops_2_ready_T_37[3:0]; // @[issue-unit-age-ordered.scala:212:90] wire _io_dis_uops_2_ready_T_39 = _io_dis_uops_2_ready_T_29 > {1'h0, _io_dis_uops_2_ready_T_38}; // @[issue-unit-age-ordered.scala:212:{45,60,90}] reg io_dis_uops_2_ready_REG; // @[issue-unit-age-ordered.scala:212:36] assign io_dis_uops_2_ready_0 = io_dis_uops_2_ready_REG; // @[issue-unit-age-ordered.scala:22:7, :212:36]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }
module AsyncResetSynchronizerShiftReg_w1_d3_i0_47( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_55 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File Util.scala: package compressacc import chisel3._ import chisel3.util._ import chisel3.{Printable} import freechips.rocketchip.tile._ import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.rocket.{TLBConfig} import freechips.rocketchip.util.DecoupledHelper import freechips.rocketchip.rocket.constants.MemoryOpConstants object CompressAccelLogger { def logInfo(format: String, args: Bits*)(implicit p: Parameters) { val loginfo_cycles = RegInit(0.U(64.W)) loginfo_cycles := loginfo_cycles + 1.U printf("cy: %d, ", loginfo_cycles) printf(Printable.pack(format, args:_*)) } def logCritical(format: String, args: Bits*)(implicit p: Parameters) { val loginfo_cycles = RegInit(0.U(64.W)) loginfo_cycles := loginfo_cycles + 1.U if (p(CompressAccelPrintfEnable)) { printf(midas.targetutils.SynthesizePrintf("cy: %d, ", loginfo_cycles)) printf(midas.targetutils.SynthesizePrintf(format, args:_*)) } else { printf("cy: %d, ", loginfo_cycles) printf(Printable.pack(format, args:_*)) } } def logWaveStyle(format: String, args: Bits*)(implicit p: Parameters) { } } object CompressAccelParams { } File ZstdLitRotBuf.scala: package compressacc import chisel3._ import chisel3.util._ import chisel3.util._ import chisel3.{Printable} import freechips.rocketchip.tile._ import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.rocket.{TLBConfig} import freechips.rocketchip.util.DecoupledHelper import freechips.rocketchip.rocket.constants.MemoryOpConstants class ZstdCompressorReverseLitRotBuf(implicit val p: Parameters) extends Module { val io = IO(new Bundle { val memwrites_in = Flipped(Decoupled(new WriterBundle)) val consumer = new MemLoaderConsumerBundle }) /* * memwrites_in.bits.data * 0 1 2 3 4 5 6 7 * o o o o o o x x * 5 4 3 2 1 0 x x * * consumer * 0 1 2 3 4 5 6 7 * x x 0 1 2 3 4 5 */ val incoming_writes_Q = Module(new Queue(new WriterBundle, 4)) incoming_writes_Q.io.enq <> io.memwrites_in when (incoming_writes_Q.io.deq.fire) { CompressAccelLogger.logInfo("[lit-rot-buf] dat: 0x%x, bytes: 0x%x, EOM: %d\n", incoming_writes_Q.io.deq.bits.data, incoming_writes_Q.io.deq.bits.validbytes, incoming_writes_Q.io.deq.bits.end_of_message ) } val NUM_QUEUES = 32 val QUEUE_DEPTHS = 10 val write_start_index = RegInit(0.U(log2Up(NUM_QUEUES+1).W)) val mem_resp_queues = Seq.fill(NUM_QUEUES)(Module(new Queue(UInt(8.W), QUEUE_DEPTHS)).io) val len_to_write = incoming_writes_Q.io.deq.bits.validbytes for ( queueno <- 0 until NUM_QUEUES ) { mem_resp_queues(queueno).enq.bits := DontCare } for ( queueno <- 0 until NUM_QUEUES ) { val idx = (write_start_index +& queueno.U) % NUM_QUEUES.U for (j <- 0 until NUM_QUEUES) { when (j.U === idx) { mem_resp_queues(j).enq.bits := incoming_writes_Q.io.deq.bits.data >> ((queueno.U) << 3) } } } val wrap_len_index_wide = write_start_index +& len_to_write val wrap_len_index_end = wrap_len_index_wide % NUM_QUEUES.U val wrapped = wrap_len_index_wide >= NUM_QUEUES.U val all_queues_ready = mem_resp_queues.map(_.enq.ready).reduce(_ && _) val input_fire_allqueues = DecoupledHelper( incoming_writes_Q.io.deq.valid, all_queues_ready, ) incoming_writes_Q.io.deq.ready := input_fire_allqueues.fire(incoming_writes_Q.io.deq.valid) when (input_fire_allqueues.fire) { write_start_index := wrap_len_index_end } for ( queueno <- 0 until NUM_QUEUES ) { val use_this_queue = Mux(wrapped, (queueno.U >= write_start_index) || (queueno.U < wrap_len_index_end), (queueno.U >= write_start_index) && (queueno.U < wrap_len_index_end) ) mem_resp_queues(queueno).enq.valid := input_fire_allqueues.fire && use_this_queue } for ( queueno <- 0 until NUM_QUEUES ) { when (mem_resp_queues(queueno).deq.valid) { CompressAccelLogger.logInfo("lrb: qi%d,0x%x\n", queueno.U, mem_resp_queues(queueno).deq.bits) } } val read_start_index = RegInit(0.U(log2Up(NUM_QUEUES+1).W)) val remapVecData = Wire(Vec(NUM_QUEUES, UInt(8.W))) val remapVecValids = Wire(Vec(NUM_QUEUES, Bool())) val remapVecReadys = Wire(Vec(NUM_QUEUES, Bool())) for (queueno <- 0 until NUM_QUEUES) { remapVecData(queueno) := 0.U remapVecValids(queueno) := false.B mem_resp_queues(queueno).deq.ready := false.B } for (queueno <- 0 until NUM_QUEUES) { val remapindex = (queueno.U +& read_start_index) % NUM_QUEUES.U for (j <- 0 until NUM_QUEUES) { when (j.U === remapindex) { remapVecData(queueno) := mem_resp_queues(j).deq.bits remapVecValids(queueno) := mem_resp_queues(j).deq.valid mem_resp_queues(j).deq.ready := remapVecReadys(queueno) } } } // io.consumer.output_data := Cat(remapVecData.reverse) io.consumer.output_data := Cat(remapVecData) val count_valids = remapVecValids.map(_.asUInt).reduce(_ +& _) val enough_data = count_valids =/= 0.U io.consumer.available_output_bytes := count_valids io.consumer.output_last_chunk := false.B // in this module, we don't actualy care about driving this. val read_fire = DecoupledHelper( io.consumer.output_ready, enough_data ) when (read_fire.fire) { CompressAccelLogger.logInfo("lrb READ: bytesread %d\n", io.consumer.user_consumed_bytes) CompressAccelLogger.logInfo("lrb read data: 0x%x\n", io.consumer.output_data) } io.consumer.output_valid := read_fire.fire(io.consumer.output_ready) for (queueno <- 0 until NUM_QUEUES) { remapVecReadys(queueno) := (queueno.U < io.consumer.user_consumed_bytes) && read_fire.fire } when (read_fire.fire) { read_start_index := (read_start_index +& io.consumer.user_consumed_bytes) % NUM_QUEUES.U } } class ZstdCompressorLitRotBuf(implicit val p: Parameters) extends Module { val io = IO(new Bundle { val memwrites_in = Flipped(Decoupled(new WriterBundle)) val consumer = new MemLoaderConsumerBundle }) val incoming_writes_Q = Module(new Queue(new WriterBundle, 4)) incoming_writes_Q.io.enq <> io.memwrites_in when (incoming_writes_Q.io.deq.fire) { CompressAccelLogger.logInfo("[lit-rot-buf] dat: 0x%x, bytes: 0x%x, EOM: %d\n", incoming_writes_Q.io.deq.bits.data, incoming_writes_Q.io.deq.bits.validbytes, incoming_writes_Q.io.deq.bits.end_of_message ) } val NUM_QUEUES = 32 val QUEUE_DEPTHS = 10 val write_start_index = RegInit(0.U(log2Up(NUM_QUEUES+1).W)) val mem_resp_queues = Seq.fill(NUM_QUEUES)(Module(new Queue(UInt(8.W), QUEUE_DEPTHS)).io) val len_to_write = incoming_writes_Q.io.deq.bits.validbytes for ( queueno <- 0 until NUM_QUEUES ) { mem_resp_queues(queueno).enq.bits := 0.U } for ( queueno <- 0 until NUM_QUEUES ) { val idx = (write_start_index +& queueno.U) % NUM_QUEUES.U for (j <- 0 until NUM_QUEUES) { when (j.U === idx) { mem_resp_queues(j).enq.bits := incoming_writes_Q.io.deq.bits.data >> ((queueno.U) << 3) } } } val wrap_len_index_wide = write_start_index +& len_to_write val wrap_len_index_end = wrap_len_index_wide % NUM_QUEUES.U val wrapped = wrap_len_index_wide >= NUM_QUEUES.U val all_queues_ready = mem_resp_queues.map(_.enq.ready).reduce(_ && _) val input_fire_allqueues = DecoupledHelper( incoming_writes_Q.io.deq.valid, all_queues_ready, ) incoming_writes_Q.io.deq.ready := input_fire_allqueues.fire(incoming_writes_Q.io.deq.valid) when (input_fire_allqueues.fire) { write_start_index := wrap_len_index_end } for ( queueno <- 0 until NUM_QUEUES ) { val use_this_queue = Mux(wrapped, (queueno.U >= write_start_index) || (queueno.U < wrap_len_index_end), (queueno.U >= write_start_index) && (queueno.U < wrap_len_index_end) ) mem_resp_queues(queueno).enq.valid := input_fire_allqueues.fire && use_this_queue } for ( queueno <- 0 until NUM_QUEUES ) { when (mem_resp_queues(queueno).deq.valid) { CompressAccelLogger.logInfo("lrb: qi%d,0x%x\n", queueno.U, mem_resp_queues(queueno).deq.bits) } } val read_start_index = RegInit(0.U(log2Up(NUM_QUEUES+1).W)) val remapVecData = Wire(Vec(NUM_QUEUES, UInt(8.W))) val remapVecValids = Wire(Vec(NUM_QUEUES, Bool())) val remapVecReadys = Wire(Vec(NUM_QUEUES, Bool())) for (queueno <- 0 until NUM_QUEUES) { remapVecData(queueno) := 0.U remapVecValids(queueno) := false.B mem_resp_queues(queueno).deq.ready := false.B } for (queueno <- 0 until NUM_QUEUES) { val remapindex = (queueno.U +& read_start_index) % NUM_QUEUES.U for (j <- 0 until NUM_QUEUES) { when (j.U === remapindex) { remapVecData(queueno) := mem_resp_queues(j).deq.bits remapVecValids(queueno) := mem_resp_queues(j).deq.valid mem_resp_queues(j).deq.ready := remapVecReadys(queueno) } } } io.consumer.output_data := Cat(remapVecData.reverse) val count_valids = remapVecValids.map(_.asUInt).reduce(_ +& _) val enough_data = count_valids =/= 0.U io.consumer.available_output_bytes := count_valids io.consumer.output_last_chunk := false.B // in this module, we don't actualy care about driving this. val read_fire = DecoupledHelper( io.consumer.output_ready, enough_data ) when (read_fire.fire) { CompressAccelLogger.logInfo("lrb READ: bytesread %d\n", io.consumer.user_consumed_bytes) CompressAccelLogger.logInfo("lrb read data: 0x%x\n", io.consumer.output_data) } io.consumer.output_valid := read_fire.fire(io.consumer.output_ready) for (queueno <- 0 until NUM_QUEUES) { remapVecReadys(queueno) := (queueno.U < io.consumer.user_consumed_bytes) && read_fire.fire } when (read_fire.fire) { read_start_index := (read_start_index +& io.consumer.user_consumed_bytes) % NUM_QUEUES.U } }
module ZstdCompressorLitRotBuf_1( // @[ZstdLitRotBuf.scala:152:7] input clock, // @[ZstdLitRotBuf.scala:152:7] input reset, // @[ZstdLitRotBuf.scala:152:7] output io_memwrites_in_ready, // @[ZstdLitRotBuf.scala:153:14] input io_memwrites_in_valid, // @[ZstdLitRotBuf.scala:153:14] input [255:0] io_memwrites_in_bits_data, // @[ZstdLitRotBuf.scala:153:14] input io_memwrites_in_bits_end_of_message, // @[ZstdLitRotBuf.scala:153:14] input [5:0] io_consumer_user_consumed_bytes, // @[ZstdLitRotBuf.scala:153:14] output [5:0] io_consumer_available_output_bytes, // @[ZstdLitRotBuf.scala:153:14] output io_consumer_output_valid, // @[ZstdLitRotBuf.scala:153:14] input io_consumer_output_ready, // @[ZstdLitRotBuf.scala:153:14] output [255:0] io_consumer_output_data // @[ZstdLitRotBuf.scala:153:14] ); wire _Queue10_UInt8_31_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_31_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_31_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_30_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_30_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_30_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_29_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_29_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_29_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_28_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_28_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_28_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_27_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_27_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_27_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_26_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_26_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_26_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_25_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_25_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_25_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_24_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_24_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_24_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_23_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_23_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_23_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_22_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_22_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_22_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_21_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_21_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_21_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_20_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_20_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_20_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_19_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_19_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_19_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_18_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_18_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_18_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_17_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_17_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_17_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_16_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_16_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_16_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_15_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_15_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_15_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_14_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_14_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_14_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_13_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_13_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_13_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_12_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_12_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_12_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_11_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_11_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_11_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_10_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_10_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_10_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_9_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_9_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_9_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_8_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_8_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_7_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_7_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_7_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_6_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_6_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_6_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_5_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_5_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_5_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_4_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_4_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_4_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_3_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_3_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_3_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_2_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_2_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_2_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_1_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_1_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_1_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _incoming_writes_Q_io_deq_valid; // @[ZstdLitRotBuf.scala:158:33] wire [255:0] _incoming_writes_Q_io_deq_bits_data; // @[ZstdLitRotBuf.scala:158:33] wire [5:0] _incoming_writes_Q_io_deq_bits_validbytes; // @[ZstdLitRotBuf.scala:158:33] wire _incoming_writes_Q_io_deq_bits_end_of_message; // @[ZstdLitRotBuf.scala:158:33] wire io_memwrites_in_valid_0 = io_memwrites_in_valid; // @[ZstdLitRotBuf.scala:152:7] wire [255:0] io_memwrites_in_bits_data_0 = io_memwrites_in_bits_data; // @[ZstdLitRotBuf.scala:152:7] wire io_memwrites_in_bits_end_of_message_0 = io_memwrites_in_bits_end_of_message; // @[ZstdLitRotBuf.scala:152:7] wire [5:0] io_consumer_user_consumed_bytes_0 = io_consumer_user_consumed_bytes; // @[ZstdLitRotBuf.scala:152:7] wire io_consumer_output_ready_0 = io_consumer_output_ready; // @[ZstdLitRotBuf.scala:152:7] wire [5:0] io_memwrites_in_bits_validbytes = 6'h1; // @[ZstdLitRotBuf.scala:152:7] wire io_consumer_output_last_chunk = 1'h0; // @[ZstdLitRotBuf.scala:152:7] wire enough_data; // @[ZstdLitRotBuf.scala:251:34] wire [255:0] _io_consumer_output_data_T; // @[ZstdLitRotBuf.scala:246:33] wire io_memwrites_in_ready_0; // @[ZstdLitRotBuf.scala:152:7] wire [5:0] io_consumer_available_output_bytes_0; // @[ZstdLitRotBuf.scala:152:7] wire io_consumer_output_valid_0; // @[ZstdLitRotBuf.scala:152:7] wire [255:0] io_consumer_output_data_0; // @[ZstdLitRotBuf.scala:152:7] reg [63:0] loginfo_cycles; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T = {1'h0, loginfo_cycles} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1 = _loginfo_cycles_T[63:0]; // @[Util.scala:19:38] reg [5:0] write_start_index; // @[ZstdLitRotBuf.scala:172:34] wire [6:0] _idx_T = {1'h0, write_start_index}; // @[ZstdLitRotBuf.scala:172:34, :182:34] wire [6:0] _GEN = _idx_T % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx = _GEN[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_1 = _idx_T + 7'h1; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_0 = _idx_T_1 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_1 = _GEN_0[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_2 = _idx_T + 7'h2; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_1 = _idx_T_2 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_2 = _GEN_1[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_3 = _idx_T + 7'h3; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_2 = _idx_T_3 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_3 = _GEN_2[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_4 = _idx_T + 7'h4; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_3 = _idx_T_4 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_4 = _GEN_3[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_5 = _idx_T + 7'h5; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_4 = _idx_T_5 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_5 = _GEN_4[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_6 = _idx_T + 7'h6; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_5 = _idx_T_6 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_6 = _GEN_5[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_7 = _idx_T + 7'h7; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_6 = _idx_T_7 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_7 = _GEN_6[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_8 = _idx_T + 7'h8; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_7 = _idx_T_8 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_8 = _GEN_7[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_9 = _idx_T + 7'h9; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_8 = _idx_T_9 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_9 = _GEN_8[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_10 = _idx_T + 7'hA; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_9 = _idx_T_10 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_10 = _GEN_9[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_11 = _idx_T + 7'hB; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_10 = _idx_T_11 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_11 = _GEN_10[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_12 = _idx_T + 7'hC; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_11 = _idx_T_12 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_12 = _GEN_11[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_13 = _idx_T + 7'hD; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_12 = _idx_T_13 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_13 = _GEN_12[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_14 = _idx_T + 7'hE; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_13 = _idx_T_14 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_14 = _GEN_13[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_15 = _idx_T + 7'hF; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_14 = _idx_T_15 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_15 = _GEN_14[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_16 = _idx_T + 7'h10; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_15 = _idx_T_16 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_16 = _GEN_15[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_17 = _idx_T + 7'h11; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_16 = _idx_T_17 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_17 = _GEN_16[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_18 = _idx_T + 7'h12; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_17 = _idx_T_18 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_18 = _GEN_17[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_19 = _idx_T + 7'h13; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_18 = _idx_T_19 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_19 = _GEN_18[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_20 = _idx_T + 7'h14; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_19 = _idx_T_20 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_20 = _GEN_19[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_21 = _idx_T + 7'h15; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_20 = _idx_T_21 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_21 = _GEN_20[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_22 = _idx_T + 7'h16; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_21 = _idx_T_22 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_22 = _GEN_21[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_23 = _idx_T + 7'h17; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_22 = _idx_T_23 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_23 = _GEN_22[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_24 = _idx_T + 7'h18; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_23 = _idx_T_24 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_24 = _GEN_23[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_25 = _idx_T + 7'h19; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_24 = _idx_T_25 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_25 = _GEN_24[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_26 = _idx_T + 7'h1A; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_25 = _idx_T_26 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_26 = _GEN_25[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_27 = _idx_T + 7'h1B; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_26 = _idx_T_27 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_27 = _GEN_26[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_28 = _idx_T + 7'h1C; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_27 = _idx_T_28 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_28 = _GEN_27[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_29 = _idx_T + 7'h1D; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_28 = _idx_T_29 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_29 = _GEN_28[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_30 = _idx_T + 7'h1E; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_29 = _idx_T_30 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_30 = _GEN_29[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_31 = _idx_T + 7'h1F; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_30 = _idx_T_31 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_31 = _GEN_30[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] wrap_len_index_wide = _idx_T + {1'h0, _incoming_writes_Q_io_deq_bits_validbytes}; // @[ZstdLitRotBuf.scala:158:33, :182:34, :190:47] wire [6:0] _GEN_31 = wrap_len_index_wide % 7'h20; // @[ZstdLitRotBuf.scala:190:47, :191:48] wire [5:0] wrap_len_index_end = _GEN_31[5:0]; // @[ZstdLitRotBuf.scala:191:48] wire wrapped = |(wrap_len_index_wide[6:5]); // @[ZstdLitRotBuf.scala:190:47, :192:37] wire _all_queues_ready_T = _Queue10_UInt8_io_enq_ready & _Queue10_UInt8_1_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_1 = _all_queues_ready_T & _Queue10_UInt8_2_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_2 = _all_queues_ready_T_1 & _Queue10_UInt8_3_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_3 = _all_queues_ready_T_2 & _Queue10_UInt8_4_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_4 = _all_queues_ready_T_3 & _Queue10_UInt8_5_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_5 = _all_queues_ready_T_4 & _Queue10_UInt8_6_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_6 = _all_queues_ready_T_5 & _Queue10_UInt8_7_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_7 = _all_queues_ready_T_6 & _Queue10_UInt8_8_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_8 = _all_queues_ready_T_7 & _Queue10_UInt8_9_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_9 = _all_queues_ready_T_8 & _Queue10_UInt8_10_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_10 = _all_queues_ready_T_9 & _Queue10_UInt8_11_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_11 = _all_queues_ready_T_10 & _Queue10_UInt8_12_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_12 = _all_queues_ready_T_11 & _Queue10_UInt8_13_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_13 = _all_queues_ready_T_12 & _Queue10_UInt8_14_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_14 = _all_queues_ready_T_13 & _Queue10_UInt8_15_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_15 = _all_queues_ready_T_14 & _Queue10_UInt8_16_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_16 = _all_queues_ready_T_15 & _Queue10_UInt8_17_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_17 = _all_queues_ready_T_16 & _Queue10_UInt8_18_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_18 = _all_queues_ready_T_17 & _Queue10_UInt8_19_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_19 = _all_queues_ready_T_18 & _Queue10_UInt8_20_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_20 = _all_queues_ready_T_19 & _Queue10_UInt8_21_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_21 = _all_queues_ready_T_20 & _Queue10_UInt8_22_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_22 = _all_queues_ready_T_21 & _Queue10_UInt8_23_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_23 = _all_queues_ready_T_22 & _Queue10_UInt8_24_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_24 = _all_queues_ready_T_23 & _Queue10_UInt8_25_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_25 = _all_queues_ready_T_24 & _Queue10_UInt8_26_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_26 = _all_queues_ready_T_25 & _Queue10_UInt8_27_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_27 = _all_queues_ready_T_26 & _Queue10_UInt8_28_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_28 = _all_queues_ready_T_27 & _Queue10_UInt8_29_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_29 = _all_queues_ready_T_28 & _Queue10_UInt8_30_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire all_queues_ready = _all_queues_ready_T_29 & _Queue10_UInt8_31_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _T_3140 = _incoming_writes_Q_io_deq_valid & all_queues_ready; // @[Misc.scala:29:18] wire _GEN_32 = write_start_index == 6'h0; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T = _GEN_32; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_3; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_3 = _GEN_32; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _use_this_queue_T_1 = |wrap_len_index_end; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_2 = _use_this_queue_T | _use_this_queue_T_1; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_4 = |wrap_len_index_end; // @[ZstdLitRotBuf.scala:191:48, :210:77, :211:77] wire _use_this_queue_T_5 = _use_this_queue_T_3 & _use_this_queue_T_4; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue = wrapped ? _use_this_queue_T_2 : _use_this_queue_T_5; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_33 = write_start_index < 6'h2; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_6; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_6 = _GEN_33; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_9; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_9 = _GEN_33; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _use_this_queue_T_7 = |(wrap_len_index_end[5:1]); // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_8 = _use_this_queue_T_6 | _use_this_queue_T_7; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_10 = |(wrap_len_index_end[5:1]); // @[ZstdLitRotBuf.scala:191:48, :210:77, :211:77] wire _use_this_queue_T_11 = _use_this_queue_T_9 & _use_this_queue_T_10; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_1 = wrapped ? _use_this_queue_T_8 : _use_this_queue_T_11; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_34 = write_start_index < 6'h3; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_12; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_12 = _GEN_34; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_15; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_15 = _GEN_34; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_35 = wrap_len_index_end > 6'h2; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_13; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_13 = _GEN_35; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_16; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_16 = _GEN_35; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_14 = _use_this_queue_T_12 | _use_this_queue_T_13; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_17 = _use_this_queue_T_15 & _use_this_queue_T_16; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_2 = wrapped ? _use_this_queue_T_14 : _use_this_queue_T_17; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_36 = write_start_index < 6'h4; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_18; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_18 = _GEN_36; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_21; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_21 = _GEN_36; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _use_this_queue_T_19 = |(wrap_len_index_end[5:2]); // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_20 = _use_this_queue_T_18 | _use_this_queue_T_19; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_22 = |(wrap_len_index_end[5:2]); // @[ZstdLitRotBuf.scala:191:48, :210:77, :211:77] wire _use_this_queue_T_23 = _use_this_queue_T_21 & _use_this_queue_T_22; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_3 = wrapped ? _use_this_queue_T_20 : _use_this_queue_T_23; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_37 = write_start_index < 6'h5; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_24; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_24 = _GEN_37; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_27; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_27 = _GEN_37; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_38 = wrap_len_index_end > 6'h4; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_25; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_25 = _GEN_38; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_28; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_28 = _GEN_38; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_26 = _use_this_queue_T_24 | _use_this_queue_T_25; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_29 = _use_this_queue_T_27 & _use_this_queue_T_28; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_4 = wrapped ? _use_this_queue_T_26 : _use_this_queue_T_29; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_39 = write_start_index < 6'h6; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_30; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_30 = _GEN_39; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_33; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_33 = _GEN_39; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_40 = wrap_len_index_end > 6'h5; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_31; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_31 = _GEN_40; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_34; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_34 = _GEN_40; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_32 = _use_this_queue_T_30 | _use_this_queue_T_31; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_35 = _use_this_queue_T_33 & _use_this_queue_T_34; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_5 = wrapped ? _use_this_queue_T_32 : _use_this_queue_T_35; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_41 = write_start_index < 6'h7; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_36; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_36 = _GEN_41; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_39; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_39 = _GEN_41; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_42 = wrap_len_index_end > 6'h6; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_37; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_37 = _GEN_42; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_40; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_40 = _GEN_42; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_38 = _use_this_queue_T_36 | _use_this_queue_T_37; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_41 = _use_this_queue_T_39 & _use_this_queue_T_40; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_6 = wrapped ? _use_this_queue_T_38 : _use_this_queue_T_41; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_43 = write_start_index < 6'h8; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_42; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_42 = _GEN_43; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_45; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_45 = _GEN_43; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _use_this_queue_T_43 = |(wrap_len_index_end[5:3]); // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_44 = _use_this_queue_T_42 | _use_this_queue_T_43; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_46 = |(wrap_len_index_end[5:3]); // @[ZstdLitRotBuf.scala:191:48, :210:77, :211:77] wire _use_this_queue_T_47 = _use_this_queue_T_45 & _use_this_queue_T_46; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_7 = wrapped ? _use_this_queue_T_44 : _use_this_queue_T_47; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_44 = write_start_index < 6'h9; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_48; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_48 = _GEN_44; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_51; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_51 = _GEN_44; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_45 = wrap_len_index_end > 6'h8; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_49; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_49 = _GEN_45; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_52; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_52 = _GEN_45; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_50 = _use_this_queue_T_48 | _use_this_queue_T_49; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_53 = _use_this_queue_T_51 & _use_this_queue_T_52; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_8 = wrapped ? _use_this_queue_T_50 : _use_this_queue_T_53; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_46 = write_start_index < 6'hA; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_54; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_54 = _GEN_46; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_57; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_57 = _GEN_46; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_47 = wrap_len_index_end > 6'h9; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_55; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_55 = _GEN_47; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_58; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_58 = _GEN_47; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_56 = _use_this_queue_T_54 | _use_this_queue_T_55; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_59 = _use_this_queue_T_57 & _use_this_queue_T_58; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_9 = wrapped ? _use_this_queue_T_56 : _use_this_queue_T_59; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_48 = write_start_index < 6'hB; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_60; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_60 = _GEN_48; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_63; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_63 = _GEN_48; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_49 = wrap_len_index_end > 6'hA; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_61; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_61 = _GEN_49; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_64; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_64 = _GEN_49; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_62 = _use_this_queue_T_60 | _use_this_queue_T_61; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_65 = _use_this_queue_T_63 & _use_this_queue_T_64; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_10 = wrapped ? _use_this_queue_T_62 : _use_this_queue_T_65; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_50 = write_start_index < 6'hC; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_66; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_66 = _GEN_50; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_69; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_69 = _GEN_50; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_51 = wrap_len_index_end > 6'hB; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_67; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_67 = _GEN_51; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_70; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_70 = _GEN_51; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_68 = _use_this_queue_T_66 | _use_this_queue_T_67; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_71 = _use_this_queue_T_69 & _use_this_queue_T_70; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_11 = wrapped ? _use_this_queue_T_68 : _use_this_queue_T_71; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_52 = write_start_index < 6'hD; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_72; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_72 = _GEN_52; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_75; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_75 = _GEN_52; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_53 = wrap_len_index_end > 6'hC; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_73; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_73 = _GEN_53; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_76; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_76 = _GEN_53; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_74 = _use_this_queue_T_72 | _use_this_queue_T_73; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_77 = _use_this_queue_T_75 & _use_this_queue_T_76; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_12 = wrapped ? _use_this_queue_T_74 : _use_this_queue_T_77; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_54 = write_start_index < 6'hE; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_78; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_78 = _GEN_54; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_81; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_81 = _GEN_54; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_55 = wrap_len_index_end > 6'hD; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_79; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_79 = _GEN_55; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_82; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_82 = _GEN_55; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_80 = _use_this_queue_T_78 | _use_this_queue_T_79; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_83 = _use_this_queue_T_81 & _use_this_queue_T_82; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_13 = wrapped ? _use_this_queue_T_80 : _use_this_queue_T_83; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_56 = write_start_index < 6'hF; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_84; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_84 = _GEN_56; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_87; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_87 = _GEN_56; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_57 = wrap_len_index_end > 6'hE; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_85; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_85 = _GEN_57; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_88; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_88 = _GEN_57; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_86 = _use_this_queue_T_84 | _use_this_queue_T_85; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_89 = _use_this_queue_T_87 & _use_this_queue_T_88; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_14 = wrapped ? _use_this_queue_T_86 : _use_this_queue_T_89; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_58 = write_start_index < 6'h10; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_90; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_90 = _GEN_58; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_93; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_93 = _GEN_58; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _use_this_queue_T_91 = |(wrap_len_index_end[5:4]); // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_92 = _use_this_queue_T_90 | _use_this_queue_T_91; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_94 = |(wrap_len_index_end[5:4]); // @[ZstdLitRotBuf.scala:191:48, :210:77, :211:77] wire _use_this_queue_T_95 = _use_this_queue_T_93 & _use_this_queue_T_94; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_15 = wrapped ? _use_this_queue_T_92 : _use_this_queue_T_95; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_59 = write_start_index < 6'h11; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_96; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_96 = _GEN_59; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_99; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_99 = _GEN_59; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_60 = wrap_len_index_end > 6'h10; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_97; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_97 = _GEN_60; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_100; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_100 = _GEN_60; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_98 = _use_this_queue_T_96 | _use_this_queue_T_97; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_101 = _use_this_queue_T_99 & _use_this_queue_T_100; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_16 = wrapped ? _use_this_queue_T_98 : _use_this_queue_T_101; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_61 = write_start_index < 6'h12; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_102; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_102 = _GEN_61; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_105; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_105 = _GEN_61; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_62 = wrap_len_index_end > 6'h11; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_103; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_103 = _GEN_62; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_106; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_106 = _GEN_62; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_104 = _use_this_queue_T_102 | _use_this_queue_T_103; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_107 = _use_this_queue_T_105 & _use_this_queue_T_106; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_17 = wrapped ? _use_this_queue_T_104 : _use_this_queue_T_107; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_63 = write_start_index < 6'h13; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_108; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_108 = _GEN_63; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_111; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_111 = _GEN_63; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_64 = wrap_len_index_end > 6'h12; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_109; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_109 = _GEN_64; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_112; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_112 = _GEN_64; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_110 = _use_this_queue_T_108 | _use_this_queue_T_109; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_113 = _use_this_queue_T_111 & _use_this_queue_T_112; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_18 = wrapped ? _use_this_queue_T_110 : _use_this_queue_T_113; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_65 = write_start_index < 6'h14; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_114; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_114 = _GEN_65; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_117; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_117 = _GEN_65; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_66 = wrap_len_index_end > 6'h13; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_115; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_115 = _GEN_66; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_118; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_118 = _GEN_66; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_116 = _use_this_queue_T_114 | _use_this_queue_T_115; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_119 = _use_this_queue_T_117 & _use_this_queue_T_118; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_19 = wrapped ? _use_this_queue_T_116 : _use_this_queue_T_119; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_67 = write_start_index < 6'h15; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_120; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_120 = _GEN_67; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_123; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_123 = _GEN_67; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_68 = wrap_len_index_end > 6'h14; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_121; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_121 = _GEN_68; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_124; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_124 = _GEN_68; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_122 = _use_this_queue_T_120 | _use_this_queue_T_121; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_125 = _use_this_queue_T_123 & _use_this_queue_T_124; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_20 = wrapped ? _use_this_queue_T_122 : _use_this_queue_T_125; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_69 = write_start_index < 6'h16; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_126; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_126 = _GEN_69; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_129; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_129 = _GEN_69; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_70 = wrap_len_index_end > 6'h15; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_127; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_127 = _GEN_70; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_130; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_130 = _GEN_70; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_128 = _use_this_queue_T_126 | _use_this_queue_T_127; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_131 = _use_this_queue_T_129 & _use_this_queue_T_130; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_21 = wrapped ? _use_this_queue_T_128 : _use_this_queue_T_131; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_71 = write_start_index < 6'h17; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_132; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_132 = _GEN_71; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_135; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_135 = _GEN_71; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_72 = wrap_len_index_end > 6'h16; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_133; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_133 = _GEN_72; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_136; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_136 = _GEN_72; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_134 = _use_this_queue_T_132 | _use_this_queue_T_133; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_137 = _use_this_queue_T_135 & _use_this_queue_T_136; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_22 = wrapped ? _use_this_queue_T_134 : _use_this_queue_T_137; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_73 = write_start_index < 6'h18; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_138; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_138 = _GEN_73; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_141; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_141 = _GEN_73; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_74 = wrap_len_index_end > 6'h17; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_139; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_139 = _GEN_74; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_142; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_142 = _GEN_74; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_140 = _use_this_queue_T_138 | _use_this_queue_T_139; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_143 = _use_this_queue_T_141 & _use_this_queue_T_142; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_23 = wrapped ? _use_this_queue_T_140 : _use_this_queue_T_143; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_75 = write_start_index < 6'h19; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_144; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_144 = _GEN_75; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_147; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_147 = _GEN_75; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_76 = wrap_len_index_end > 6'h18; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_145; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_145 = _GEN_76; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_148; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_148 = _GEN_76; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_146 = _use_this_queue_T_144 | _use_this_queue_T_145; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_149 = _use_this_queue_T_147 & _use_this_queue_T_148; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_24 = wrapped ? _use_this_queue_T_146 : _use_this_queue_T_149; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_77 = write_start_index < 6'h1A; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_150; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_150 = _GEN_77; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_153; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_153 = _GEN_77; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_78 = wrap_len_index_end > 6'h19; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_151; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_151 = _GEN_78; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_154; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_154 = _GEN_78; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_152 = _use_this_queue_T_150 | _use_this_queue_T_151; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_155 = _use_this_queue_T_153 & _use_this_queue_T_154; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_25 = wrapped ? _use_this_queue_T_152 : _use_this_queue_T_155; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_79 = write_start_index < 6'h1B; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_156; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_156 = _GEN_79; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_159; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_159 = _GEN_79; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_80 = wrap_len_index_end > 6'h1A; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_157; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_157 = _GEN_80; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_160; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_160 = _GEN_80; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_158 = _use_this_queue_T_156 | _use_this_queue_T_157; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_161 = _use_this_queue_T_159 & _use_this_queue_T_160; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_26 = wrapped ? _use_this_queue_T_158 : _use_this_queue_T_161; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_81 = write_start_index < 6'h1C; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_162; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_162 = _GEN_81; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_165; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_165 = _GEN_81; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_82 = wrap_len_index_end > 6'h1B; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_163; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_163 = _GEN_82; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_166; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_166 = _GEN_82; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_164 = _use_this_queue_T_162 | _use_this_queue_T_163; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_167 = _use_this_queue_T_165 & _use_this_queue_T_166; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_27 = wrapped ? _use_this_queue_T_164 : _use_this_queue_T_167; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_83 = write_start_index < 6'h1D; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_168; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_168 = _GEN_83; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_171; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_171 = _GEN_83; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_84 = wrap_len_index_end > 6'h1C; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_169; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_169 = _GEN_84; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_172; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_172 = _GEN_84; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_170 = _use_this_queue_T_168 | _use_this_queue_T_169; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_173 = _use_this_queue_T_171 & _use_this_queue_T_172; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_28 = wrapped ? _use_this_queue_T_170 : _use_this_queue_T_173; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_85 = write_start_index < 6'h1E; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_174; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_174 = _GEN_85; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_177; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_177 = _GEN_85; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_86 = wrap_len_index_end > 6'h1D; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_175; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_175 = _GEN_86; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_178; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_178 = _GEN_86; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_176 = _use_this_queue_T_174 | _use_this_queue_T_175; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_179 = _use_this_queue_T_177 & _use_this_queue_T_178; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_29 = wrapped ? _use_this_queue_T_176 : _use_this_queue_T_179; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_87 = write_start_index < 6'h1F; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_180; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_180 = _GEN_87; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_183; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_183 = _GEN_87; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_88 = wrap_len_index_end > 6'h1E; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_181; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_181 = _GEN_88; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_184; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_184 = _GEN_88; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_182 = _use_this_queue_T_180 | _use_this_queue_T_181; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_185 = _use_this_queue_T_183 & _use_this_queue_T_184; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_30 = wrapped ? _use_this_queue_T_182 : _use_this_queue_T_185; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _use_this_queue_T_186 = ~(write_start_index[5]); // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_187 = wrap_len_index_end[5]; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_190 = wrap_len_index_end[5]; // @[ZstdLitRotBuf.scala:191:48, :210:77, :211:77] wire _use_this_queue_T_188 = _use_this_queue_T_186 | _use_this_queue_T_187; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_189 = ~(write_start_index[5]); // @[ZstdLitRotBuf.scala:172:34, :210:41, :211:41] wire _use_this_queue_T_191 = _use_this_queue_T_189 & _use_this_queue_T_190; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_31 = wrapped ? _use_this_queue_T_188 : _use_this_queue_T_191; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] reg [63:0] loginfo_cycles_1; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_2 = {1'h0, loginfo_cycles_1} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_3 = _loginfo_cycles_T_2[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_2; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_4 = {1'h0, loginfo_cycles_2} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_5 = _loginfo_cycles_T_4[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_3; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_6 = {1'h0, loginfo_cycles_3} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_7 = _loginfo_cycles_T_6[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_4; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_8 = {1'h0, loginfo_cycles_4} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_9 = _loginfo_cycles_T_8[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_5; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_10 = {1'h0, loginfo_cycles_5} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_11 = _loginfo_cycles_T_10[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_6; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_12 = {1'h0, loginfo_cycles_6} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_13 = _loginfo_cycles_T_12[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_7; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_14 = {1'h0, loginfo_cycles_7} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_15 = _loginfo_cycles_T_14[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_8; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_16 = {1'h0, loginfo_cycles_8} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_17 = _loginfo_cycles_T_16[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_9; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_18 = {1'h0, loginfo_cycles_9} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_19 = _loginfo_cycles_T_18[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_10; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_20 = {1'h0, loginfo_cycles_10} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_21 = _loginfo_cycles_T_20[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_11; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_22 = {1'h0, loginfo_cycles_11} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_23 = _loginfo_cycles_T_22[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_12; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_24 = {1'h0, loginfo_cycles_12} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_25 = _loginfo_cycles_T_24[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_13; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_26 = {1'h0, loginfo_cycles_13} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_27 = _loginfo_cycles_T_26[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_14; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_28 = {1'h0, loginfo_cycles_14} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_29 = _loginfo_cycles_T_28[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_15; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_30 = {1'h0, loginfo_cycles_15} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_31 = _loginfo_cycles_T_30[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_16; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_32 = {1'h0, loginfo_cycles_16} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_33 = _loginfo_cycles_T_32[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_17; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_34 = {1'h0, loginfo_cycles_17} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_35 = _loginfo_cycles_T_34[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_18; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_36 = {1'h0, loginfo_cycles_18} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_37 = _loginfo_cycles_T_36[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_19; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_38 = {1'h0, loginfo_cycles_19} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_39 = _loginfo_cycles_T_38[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_20; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_40 = {1'h0, loginfo_cycles_20} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_41 = _loginfo_cycles_T_40[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_21; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_42 = {1'h0, loginfo_cycles_21} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_43 = _loginfo_cycles_T_42[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_22; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_44 = {1'h0, loginfo_cycles_22} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_45 = _loginfo_cycles_T_44[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_23; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_46 = {1'h0, loginfo_cycles_23} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_47 = _loginfo_cycles_T_46[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_24; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_48 = {1'h0, loginfo_cycles_24} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_49 = _loginfo_cycles_T_48[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_25; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_50 = {1'h0, loginfo_cycles_25} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_51 = _loginfo_cycles_T_50[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_26; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_52 = {1'h0, loginfo_cycles_26} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_53 = _loginfo_cycles_T_52[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_27; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_54 = {1'h0, loginfo_cycles_27} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_55 = _loginfo_cycles_T_54[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_28; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_56 = {1'h0, loginfo_cycles_28} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_57 = _loginfo_cycles_T_56[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_29; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_58 = {1'h0, loginfo_cycles_29} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_59 = _loginfo_cycles_T_58[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_30; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_60 = {1'h0, loginfo_cycles_30} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_61 = _loginfo_cycles_T_60[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_31; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_62 = {1'h0, loginfo_cycles_31} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_63 = _loginfo_cycles_T_62[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_32; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_64 = {1'h0, loginfo_cycles_32} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_65 = _loginfo_cycles_T_64[63:0]; // @[Util.scala:19:38] reg [5:0] read_start_index; // @[ZstdLitRotBuf.scala:222:33] wire [7:0] remapVecData_0; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_1; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_2; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_3; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_4; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_5; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_6; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_7; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_8; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_9; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_10; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_11; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_12; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_13; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_14; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_15; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_16; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_17; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_18; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_19; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_20; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_21; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_22; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_23; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_24; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_25; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_26; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_27; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_28; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_29; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_30; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_31; // @[ZstdLitRotBuf.scala:225:26] wire remapVecValids_0; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_1; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_2; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_3; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_4; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_5; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_6; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_7; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_8; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_9; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_10; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_11; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_12; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_13; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_14; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_15; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_16; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_17; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_18; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_19; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_20; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_21; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_22; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_23; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_24; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_25; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_26; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_27; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_28; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_29; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_30; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_31; // @[ZstdLitRotBuf.scala:226:28] wire _remapVecReadys_0_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_1_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_2_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_3_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_4_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_5_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_6_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_7_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_8_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_9_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_10_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_11_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_12_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_13_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_14_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_15_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_16_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_17_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_18_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_19_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_20_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_21_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_22_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_23_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_24_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_25_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_26_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_27_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_28_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_29_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_30_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_31_T_2; // @[ZstdLitRotBuf.scala:270:78] wire remapVecReadys_0; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_1; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_2; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_3; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_4; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_5; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_6; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_7; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_8; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_9; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_10; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_11; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_12; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_13; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_14; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_15; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_16; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_17; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_18; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_19; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_20; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_21; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_22; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_23; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_24; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_25; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_26; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_27; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_28; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_29; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_30; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_31; // @[ZstdLitRotBuf.scala:227:28] wire [6:0] _remapindex_T = {1'h0, read_start_index}; // @[ZstdLitRotBuf.scala:222:33, :237:33] wire [6:0] _GEN_89 = _remapindex_T % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex = _GEN_89[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3270 = remapindex == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3271 = remapindex == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3272 = remapindex == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3273 = remapindex == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3274 = remapindex == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3275 = remapindex == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3276 = remapindex == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3277 = remapindex == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3278 = remapindex == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3279 = remapindex == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3280 = remapindex == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3281 = remapindex == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3282 = remapindex == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3283 = remapindex == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3284 = remapindex == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3285 = remapindex == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3286 = remapindex == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3287 = remapindex == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3288 = remapindex == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3289 = remapindex == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3290 = remapindex == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3291 = remapindex == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3292 = remapindex == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3293 = remapindex == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3294 = remapindex == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3295 = remapindex == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3296 = remapindex == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3297 = remapindex == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3298 = remapindex == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3299 = remapindex == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3300 = remapindex == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3301 = remapindex == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_0 = _T_3301 ? _Queue10_UInt8_31_io_deq_bits : _T_3300 ? _Queue10_UInt8_30_io_deq_bits : _T_3299 ? _Queue10_UInt8_29_io_deq_bits : _T_3298 ? _Queue10_UInt8_28_io_deq_bits : _T_3297 ? _Queue10_UInt8_27_io_deq_bits : _T_3296 ? _Queue10_UInt8_26_io_deq_bits : _T_3295 ? _Queue10_UInt8_25_io_deq_bits : _T_3294 ? _Queue10_UInt8_24_io_deq_bits : _T_3293 ? _Queue10_UInt8_23_io_deq_bits : _T_3292 ? _Queue10_UInt8_22_io_deq_bits : _T_3291 ? _Queue10_UInt8_21_io_deq_bits : _T_3290 ? _Queue10_UInt8_20_io_deq_bits : _T_3289 ? _Queue10_UInt8_19_io_deq_bits : _T_3288 ? _Queue10_UInt8_18_io_deq_bits : _T_3287 ? _Queue10_UInt8_17_io_deq_bits : _T_3286 ? _Queue10_UInt8_16_io_deq_bits : _T_3285 ? _Queue10_UInt8_15_io_deq_bits : _T_3284 ? _Queue10_UInt8_14_io_deq_bits : _T_3283 ? _Queue10_UInt8_13_io_deq_bits : _T_3282 ? _Queue10_UInt8_12_io_deq_bits : _T_3281 ? _Queue10_UInt8_11_io_deq_bits : _T_3280 ? _Queue10_UInt8_10_io_deq_bits : _T_3279 ? _Queue10_UInt8_9_io_deq_bits : _T_3278 ? _Queue10_UInt8_8_io_deq_bits : _T_3277 ? _Queue10_UInt8_7_io_deq_bits : _T_3276 ? _Queue10_UInt8_6_io_deq_bits : _T_3275 ? _Queue10_UInt8_5_io_deq_bits : _T_3274 ? _Queue10_UInt8_4_io_deq_bits : _T_3273 ? _Queue10_UInt8_3_io_deq_bits : _T_3272 ? _Queue10_UInt8_2_io_deq_bits : _T_3271 ? _Queue10_UInt8_1_io_deq_bits : _T_3270 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_0 = _T_3301 ? _Queue10_UInt8_31_io_deq_valid : _T_3300 ? _Queue10_UInt8_30_io_deq_valid : _T_3299 ? _Queue10_UInt8_29_io_deq_valid : _T_3298 ? _Queue10_UInt8_28_io_deq_valid : _T_3297 ? _Queue10_UInt8_27_io_deq_valid : _T_3296 ? _Queue10_UInt8_26_io_deq_valid : _T_3295 ? _Queue10_UInt8_25_io_deq_valid : _T_3294 ? _Queue10_UInt8_24_io_deq_valid : _T_3293 ? _Queue10_UInt8_23_io_deq_valid : _T_3292 ? _Queue10_UInt8_22_io_deq_valid : _T_3291 ? _Queue10_UInt8_21_io_deq_valid : _T_3290 ? _Queue10_UInt8_20_io_deq_valid : _T_3289 ? _Queue10_UInt8_19_io_deq_valid : _T_3288 ? _Queue10_UInt8_18_io_deq_valid : _T_3287 ? _Queue10_UInt8_17_io_deq_valid : _T_3286 ? _Queue10_UInt8_16_io_deq_valid : _T_3285 ? _Queue10_UInt8_15_io_deq_valid : _T_3284 ? _Queue10_UInt8_14_io_deq_valid : _T_3283 ? _Queue10_UInt8_13_io_deq_valid : _T_3282 ? _Queue10_UInt8_12_io_deq_valid : _T_3281 ? _Queue10_UInt8_11_io_deq_valid : _T_3280 ? _Queue10_UInt8_10_io_deq_valid : _T_3279 ? _Queue10_UInt8_9_io_deq_valid : _T_3278 ? _Queue10_UInt8_8_io_deq_valid : _T_3277 ? _Queue10_UInt8_7_io_deq_valid : _T_3276 ? _Queue10_UInt8_6_io_deq_valid : _T_3275 ? _Queue10_UInt8_5_io_deq_valid : _T_3274 ? _Queue10_UInt8_4_io_deq_valid : _T_3273 ? _Queue10_UInt8_3_io_deq_valid : _T_3272 ? _Queue10_UInt8_2_io_deq_valid : _T_3271 ? _Queue10_UInt8_1_io_deq_valid : _T_3270 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_1 = _remapindex_T + 7'h1; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_90 = _remapindex_T_1 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_1 = _GEN_90[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3302 = remapindex_1 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3303 = remapindex_1 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3304 = remapindex_1 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3305 = remapindex_1 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3306 = remapindex_1 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3307 = remapindex_1 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3308 = remapindex_1 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3309 = remapindex_1 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3310 = remapindex_1 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3311 = remapindex_1 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3312 = remapindex_1 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3313 = remapindex_1 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3314 = remapindex_1 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3315 = remapindex_1 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3316 = remapindex_1 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3317 = remapindex_1 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3318 = remapindex_1 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3319 = remapindex_1 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3320 = remapindex_1 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3321 = remapindex_1 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3322 = remapindex_1 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3323 = remapindex_1 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3324 = remapindex_1 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3325 = remapindex_1 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3326 = remapindex_1 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3327 = remapindex_1 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3328 = remapindex_1 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3329 = remapindex_1 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3330 = remapindex_1 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3331 = remapindex_1 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3332 = remapindex_1 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3333 = remapindex_1 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_1 = _T_3333 ? _Queue10_UInt8_31_io_deq_bits : _T_3332 ? _Queue10_UInt8_30_io_deq_bits : _T_3331 ? _Queue10_UInt8_29_io_deq_bits : _T_3330 ? _Queue10_UInt8_28_io_deq_bits : _T_3329 ? _Queue10_UInt8_27_io_deq_bits : _T_3328 ? _Queue10_UInt8_26_io_deq_bits : _T_3327 ? _Queue10_UInt8_25_io_deq_bits : _T_3326 ? _Queue10_UInt8_24_io_deq_bits : _T_3325 ? _Queue10_UInt8_23_io_deq_bits : _T_3324 ? _Queue10_UInt8_22_io_deq_bits : _T_3323 ? _Queue10_UInt8_21_io_deq_bits : _T_3322 ? _Queue10_UInt8_20_io_deq_bits : _T_3321 ? _Queue10_UInt8_19_io_deq_bits : _T_3320 ? _Queue10_UInt8_18_io_deq_bits : _T_3319 ? _Queue10_UInt8_17_io_deq_bits : _T_3318 ? _Queue10_UInt8_16_io_deq_bits : _T_3317 ? _Queue10_UInt8_15_io_deq_bits : _T_3316 ? _Queue10_UInt8_14_io_deq_bits : _T_3315 ? _Queue10_UInt8_13_io_deq_bits : _T_3314 ? _Queue10_UInt8_12_io_deq_bits : _T_3313 ? _Queue10_UInt8_11_io_deq_bits : _T_3312 ? _Queue10_UInt8_10_io_deq_bits : _T_3311 ? _Queue10_UInt8_9_io_deq_bits : _T_3310 ? _Queue10_UInt8_8_io_deq_bits : _T_3309 ? _Queue10_UInt8_7_io_deq_bits : _T_3308 ? _Queue10_UInt8_6_io_deq_bits : _T_3307 ? _Queue10_UInt8_5_io_deq_bits : _T_3306 ? _Queue10_UInt8_4_io_deq_bits : _T_3305 ? _Queue10_UInt8_3_io_deq_bits : _T_3304 ? _Queue10_UInt8_2_io_deq_bits : _T_3303 ? _Queue10_UInt8_1_io_deq_bits : _T_3302 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_1 = _T_3333 ? _Queue10_UInt8_31_io_deq_valid : _T_3332 ? _Queue10_UInt8_30_io_deq_valid : _T_3331 ? _Queue10_UInt8_29_io_deq_valid : _T_3330 ? _Queue10_UInt8_28_io_deq_valid : _T_3329 ? _Queue10_UInt8_27_io_deq_valid : _T_3328 ? _Queue10_UInt8_26_io_deq_valid : _T_3327 ? _Queue10_UInt8_25_io_deq_valid : _T_3326 ? _Queue10_UInt8_24_io_deq_valid : _T_3325 ? _Queue10_UInt8_23_io_deq_valid : _T_3324 ? _Queue10_UInt8_22_io_deq_valid : _T_3323 ? _Queue10_UInt8_21_io_deq_valid : _T_3322 ? _Queue10_UInt8_20_io_deq_valid : _T_3321 ? _Queue10_UInt8_19_io_deq_valid : _T_3320 ? _Queue10_UInt8_18_io_deq_valid : _T_3319 ? _Queue10_UInt8_17_io_deq_valid : _T_3318 ? _Queue10_UInt8_16_io_deq_valid : _T_3317 ? _Queue10_UInt8_15_io_deq_valid : _T_3316 ? _Queue10_UInt8_14_io_deq_valid : _T_3315 ? _Queue10_UInt8_13_io_deq_valid : _T_3314 ? _Queue10_UInt8_12_io_deq_valid : _T_3313 ? _Queue10_UInt8_11_io_deq_valid : _T_3312 ? _Queue10_UInt8_10_io_deq_valid : _T_3311 ? _Queue10_UInt8_9_io_deq_valid : _T_3310 ? _Queue10_UInt8_8_io_deq_valid : _T_3309 ? _Queue10_UInt8_7_io_deq_valid : _T_3308 ? _Queue10_UInt8_6_io_deq_valid : _T_3307 ? _Queue10_UInt8_5_io_deq_valid : _T_3306 ? _Queue10_UInt8_4_io_deq_valid : _T_3305 ? _Queue10_UInt8_3_io_deq_valid : _T_3304 ? _Queue10_UInt8_2_io_deq_valid : _T_3303 ? _Queue10_UInt8_1_io_deq_valid : _T_3302 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_2 = _remapindex_T + 7'h2; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_91 = _remapindex_T_2 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_2 = _GEN_91[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3334 = remapindex_2 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3335 = remapindex_2 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3336 = remapindex_2 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3337 = remapindex_2 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3338 = remapindex_2 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3339 = remapindex_2 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3340 = remapindex_2 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3341 = remapindex_2 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3342 = remapindex_2 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3343 = remapindex_2 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3344 = remapindex_2 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3345 = remapindex_2 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3346 = remapindex_2 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3347 = remapindex_2 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3348 = remapindex_2 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3349 = remapindex_2 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3350 = remapindex_2 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3351 = remapindex_2 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3352 = remapindex_2 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3353 = remapindex_2 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3354 = remapindex_2 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3355 = remapindex_2 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3356 = remapindex_2 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3357 = remapindex_2 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3358 = remapindex_2 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3359 = remapindex_2 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3360 = remapindex_2 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3361 = remapindex_2 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3362 = remapindex_2 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3363 = remapindex_2 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3364 = remapindex_2 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3365 = remapindex_2 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_2 = _T_3365 ? _Queue10_UInt8_31_io_deq_bits : _T_3364 ? _Queue10_UInt8_30_io_deq_bits : _T_3363 ? _Queue10_UInt8_29_io_deq_bits : _T_3362 ? _Queue10_UInt8_28_io_deq_bits : _T_3361 ? _Queue10_UInt8_27_io_deq_bits : _T_3360 ? _Queue10_UInt8_26_io_deq_bits : _T_3359 ? _Queue10_UInt8_25_io_deq_bits : _T_3358 ? _Queue10_UInt8_24_io_deq_bits : _T_3357 ? _Queue10_UInt8_23_io_deq_bits : _T_3356 ? _Queue10_UInt8_22_io_deq_bits : _T_3355 ? _Queue10_UInt8_21_io_deq_bits : _T_3354 ? _Queue10_UInt8_20_io_deq_bits : _T_3353 ? _Queue10_UInt8_19_io_deq_bits : _T_3352 ? _Queue10_UInt8_18_io_deq_bits : _T_3351 ? _Queue10_UInt8_17_io_deq_bits : _T_3350 ? _Queue10_UInt8_16_io_deq_bits : _T_3349 ? _Queue10_UInt8_15_io_deq_bits : _T_3348 ? _Queue10_UInt8_14_io_deq_bits : _T_3347 ? _Queue10_UInt8_13_io_deq_bits : _T_3346 ? _Queue10_UInt8_12_io_deq_bits : _T_3345 ? _Queue10_UInt8_11_io_deq_bits : _T_3344 ? _Queue10_UInt8_10_io_deq_bits : _T_3343 ? _Queue10_UInt8_9_io_deq_bits : _T_3342 ? _Queue10_UInt8_8_io_deq_bits : _T_3341 ? _Queue10_UInt8_7_io_deq_bits : _T_3340 ? _Queue10_UInt8_6_io_deq_bits : _T_3339 ? _Queue10_UInt8_5_io_deq_bits : _T_3338 ? _Queue10_UInt8_4_io_deq_bits : _T_3337 ? _Queue10_UInt8_3_io_deq_bits : _T_3336 ? _Queue10_UInt8_2_io_deq_bits : _T_3335 ? _Queue10_UInt8_1_io_deq_bits : _T_3334 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_2 = _T_3365 ? _Queue10_UInt8_31_io_deq_valid : _T_3364 ? _Queue10_UInt8_30_io_deq_valid : _T_3363 ? _Queue10_UInt8_29_io_deq_valid : _T_3362 ? _Queue10_UInt8_28_io_deq_valid : _T_3361 ? _Queue10_UInt8_27_io_deq_valid : _T_3360 ? _Queue10_UInt8_26_io_deq_valid : _T_3359 ? _Queue10_UInt8_25_io_deq_valid : _T_3358 ? _Queue10_UInt8_24_io_deq_valid : _T_3357 ? _Queue10_UInt8_23_io_deq_valid : _T_3356 ? _Queue10_UInt8_22_io_deq_valid : _T_3355 ? _Queue10_UInt8_21_io_deq_valid : _T_3354 ? _Queue10_UInt8_20_io_deq_valid : _T_3353 ? _Queue10_UInt8_19_io_deq_valid : _T_3352 ? _Queue10_UInt8_18_io_deq_valid : _T_3351 ? _Queue10_UInt8_17_io_deq_valid : _T_3350 ? _Queue10_UInt8_16_io_deq_valid : _T_3349 ? _Queue10_UInt8_15_io_deq_valid : _T_3348 ? _Queue10_UInt8_14_io_deq_valid : _T_3347 ? _Queue10_UInt8_13_io_deq_valid : _T_3346 ? _Queue10_UInt8_12_io_deq_valid : _T_3345 ? _Queue10_UInt8_11_io_deq_valid : _T_3344 ? _Queue10_UInt8_10_io_deq_valid : _T_3343 ? _Queue10_UInt8_9_io_deq_valid : _T_3342 ? _Queue10_UInt8_8_io_deq_valid : _T_3341 ? _Queue10_UInt8_7_io_deq_valid : _T_3340 ? _Queue10_UInt8_6_io_deq_valid : _T_3339 ? _Queue10_UInt8_5_io_deq_valid : _T_3338 ? _Queue10_UInt8_4_io_deq_valid : _T_3337 ? _Queue10_UInt8_3_io_deq_valid : _T_3336 ? _Queue10_UInt8_2_io_deq_valid : _T_3335 ? _Queue10_UInt8_1_io_deq_valid : _T_3334 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_3 = _remapindex_T + 7'h3; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_92 = _remapindex_T_3 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_3 = _GEN_92[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3366 = remapindex_3 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3367 = remapindex_3 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3368 = remapindex_3 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3369 = remapindex_3 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3370 = remapindex_3 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3371 = remapindex_3 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3372 = remapindex_3 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3373 = remapindex_3 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3374 = remapindex_3 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3375 = remapindex_3 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3376 = remapindex_3 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3377 = remapindex_3 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3378 = remapindex_3 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3379 = remapindex_3 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3380 = remapindex_3 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3381 = remapindex_3 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3382 = remapindex_3 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3383 = remapindex_3 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3384 = remapindex_3 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3385 = remapindex_3 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3386 = remapindex_3 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3387 = remapindex_3 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3388 = remapindex_3 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3389 = remapindex_3 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3390 = remapindex_3 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3391 = remapindex_3 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3392 = remapindex_3 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3393 = remapindex_3 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3394 = remapindex_3 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3395 = remapindex_3 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3396 = remapindex_3 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3397 = remapindex_3 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_3 = _T_3397 ? _Queue10_UInt8_31_io_deq_bits : _T_3396 ? _Queue10_UInt8_30_io_deq_bits : _T_3395 ? _Queue10_UInt8_29_io_deq_bits : _T_3394 ? _Queue10_UInt8_28_io_deq_bits : _T_3393 ? _Queue10_UInt8_27_io_deq_bits : _T_3392 ? _Queue10_UInt8_26_io_deq_bits : _T_3391 ? _Queue10_UInt8_25_io_deq_bits : _T_3390 ? _Queue10_UInt8_24_io_deq_bits : _T_3389 ? _Queue10_UInt8_23_io_deq_bits : _T_3388 ? _Queue10_UInt8_22_io_deq_bits : _T_3387 ? _Queue10_UInt8_21_io_deq_bits : _T_3386 ? _Queue10_UInt8_20_io_deq_bits : _T_3385 ? _Queue10_UInt8_19_io_deq_bits : _T_3384 ? _Queue10_UInt8_18_io_deq_bits : _T_3383 ? _Queue10_UInt8_17_io_deq_bits : _T_3382 ? _Queue10_UInt8_16_io_deq_bits : _T_3381 ? _Queue10_UInt8_15_io_deq_bits : _T_3380 ? _Queue10_UInt8_14_io_deq_bits : _T_3379 ? _Queue10_UInt8_13_io_deq_bits : _T_3378 ? _Queue10_UInt8_12_io_deq_bits : _T_3377 ? _Queue10_UInt8_11_io_deq_bits : _T_3376 ? _Queue10_UInt8_10_io_deq_bits : _T_3375 ? _Queue10_UInt8_9_io_deq_bits : _T_3374 ? _Queue10_UInt8_8_io_deq_bits : _T_3373 ? _Queue10_UInt8_7_io_deq_bits : _T_3372 ? _Queue10_UInt8_6_io_deq_bits : _T_3371 ? _Queue10_UInt8_5_io_deq_bits : _T_3370 ? _Queue10_UInt8_4_io_deq_bits : _T_3369 ? _Queue10_UInt8_3_io_deq_bits : _T_3368 ? _Queue10_UInt8_2_io_deq_bits : _T_3367 ? _Queue10_UInt8_1_io_deq_bits : _T_3366 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_3 = _T_3397 ? _Queue10_UInt8_31_io_deq_valid : _T_3396 ? _Queue10_UInt8_30_io_deq_valid : _T_3395 ? _Queue10_UInt8_29_io_deq_valid : _T_3394 ? _Queue10_UInt8_28_io_deq_valid : _T_3393 ? _Queue10_UInt8_27_io_deq_valid : _T_3392 ? _Queue10_UInt8_26_io_deq_valid : _T_3391 ? _Queue10_UInt8_25_io_deq_valid : _T_3390 ? _Queue10_UInt8_24_io_deq_valid : _T_3389 ? _Queue10_UInt8_23_io_deq_valid : _T_3388 ? _Queue10_UInt8_22_io_deq_valid : _T_3387 ? _Queue10_UInt8_21_io_deq_valid : _T_3386 ? _Queue10_UInt8_20_io_deq_valid : _T_3385 ? _Queue10_UInt8_19_io_deq_valid : _T_3384 ? _Queue10_UInt8_18_io_deq_valid : _T_3383 ? _Queue10_UInt8_17_io_deq_valid : _T_3382 ? _Queue10_UInt8_16_io_deq_valid : _T_3381 ? _Queue10_UInt8_15_io_deq_valid : _T_3380 ? _Queue10_UInt8_14_io_deq_valid : _T_3379 ? _Queue10_UInt8_13_io_deq_valid : _T_3378 ? _Queue10_UInt8_12_io_deq_valid : _T_3377 ? _Queue10_UInt8_11_io_deq_valid : _T_3376 ? _Queue10_UInt8_10_io_deq_valid : _T_3375 ? _Queue10_UInt8_9_io_deq_valid : _T_3374 ? _Queue10_UInt8_8_io_deq_valid : _T_3373 ? _Queue10_UInt8_7_io_deq_valid : _T_3372 ? _Queue10_UInt8_6_io_deq_valid : _T_3371 ? _Queue10_UInt8_5_io_deq_valid : _T_3370 ? _Queue10_UInt8_4_io_deq_valid : _T_3369 ? _Queue10_UInt8_3_io_deq_valid : _T_3368 ? _Queue10_UInt8_2_io_deq_valid : _T_3367 ? _Queue10_UInt8_1_io_deq_valid : _T_3366 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_4 = _remapindex_T + 7'h4; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_93 = _remapindex_T_4 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_4 = _GEN_93[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3398 = remapindex_4 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3399 = remapindex_4 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3400 = remapindex_4 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3401 = remapindex_4 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3402 = remapindex_4 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3403 = remapindex_4 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3404 = remapindex_4 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3405 = remapindex_4 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3406 = remapindex_4 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3407 = remapindex_4 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3408 = remapindex_4 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3409 = remapindex_4 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3410 = remapindex_4 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3411 = remapindex_4 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3412 = remapindex_4 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3413 = remapindex_4 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3414 = remapindex_4 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3415 = remapindex_4 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3416 = remapindex_4 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3417 = remapindex_4 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3418 = remapindex_4 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3419 = remapindex_4 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3420 = remapindex_4 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3421 = remapindex_4 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3422 = remapindex_4 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3423 = remapindex_4 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3424 = remapindex_4 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3425 = remapindex_4 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3426 = remapindex_4 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3427 = remapindex_4 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3428 = remapindex_4 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3429 = remapindex_4 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_4 = _T_3429 ? _Queue10_UInt8_31_io_deq_bits : _T_3428 ? _Queue10_UInt8_30_io_deq_bits : _T_3427 ? _Queue10_UInt8_29_io_deq_bits : _T_3426 ? _Queue10_UInt8_28_io_deq_bits : _T_3425 ? _Queue10_UInt8_27_io_deq_bits : _T_3424 ? _Queue10_UInt8_26_io_deq_bits : _T_3423 ? _Queue10_UInt8_25_io_deq_bits : _T_3422 ? _Queue10_UInt8_24_io_deq_bits : _T_3421 ? _Queue10_UInt8_23_io_deq_bits : _T_3420 ? _Queue10_UInt8_22_io_deq_bits : _T_3419 ? _Queue10_UInt8_21_io_deq_bits : _T_3418 ? _Queue10_UInt8_20_io_deq_bits : _T_3417 ? _Queue10_UInt8_19_io_deq_bits : _T_3416 ? _Queue10_UInt8_18_io_deq_bits : _T_3415 ? _Queue10_UInt8_17_io_deq_bits : _T_3414 ? _Queue10_UInt8_16_io_deq_bits : _T_3413 ? _Queue10_UInt8_15_io_deq_bits : _T_3412 ? _Queue10_UInt8_14_io_deq_bits : _T_3411 ? _Queue10_UInt8_13_io_deq_bits : _T_3410 ? _Queue10_UInt8_12_io_deq_bits : _T_3409 ? _Queue10_UInt8_11_io_deq_bits : _T_3408 ? _Queue10_UInt8_10_io_deq_bits : _T_3407 ? _Queue10_UInt8_9_io_deq_bits : _T_3406 ? _Queue10_UInt8_8_io_deq_bits : _T_3405 ? _Queue10_UInt8_7_io_deq_bits : _T_3404 ? _Queue10_UInt8_6_io_deq_bits : _T_3403 ? _Queue10_UInt8_5_io_deq_bits : _T_3402 ? _Queue10_UInt8_4_io_deq_bits : _T_3401 ? _Queue10_UInt8_3_io_deq_bits : _T_3400 ? _Queue10_UInt8_2_io_deq_bits : _T_3399 ? _Queue10_UInt8_1_io_deq_bits : _T_3398 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_4 = _T_3429 ? _Queue10_UInt8_31_io_deq_valid : _T_3428 ? _Queue10_UInt8_30_io_deq_valid : _T_3427 ? _Queue10_UInt8_29_io_deq_valid : _T_3426 ? _Queue10_UInt8_28_io_deq_valid : _T_3425 ? _Queue10_UInt8_27_io_deq_valid : _T_3424 ? _Queue10_UInt8_26_io_deq_valid : _T_3423 ? _Queue10_UInt8_25_io_deq_valid : _T_3422 ? _Queue10_UInt8_24_io_deq_valid : _T_3421 ? _Queue10_UInt8_23_io_deq_valid : _T_3420 ? _Queue10_UInt8_22_io_deq_valid : _T_3419 ? _Queue10_UInt8_21_io_deq_valid : _T_3418 ? _Queue10_UInt8_20_io_deq_valid : _T_3417 ? _Queue10_UInt8_19_io_deq_valid : _T_3416 ? _Queue10_UInt8_18_io_deq_valid : _T_3415 ? _Queue10_UInt8_17_io_deq_valid : _T_3414 ? _Queue10_UInt8_16_io_deq_valid : _T_3413 ? _Queue10_UInt8_15_io_deq_valid : _T_3412 ? _Queue10_UInt8_14_io_deq_valid : _T_3411 ? _Queue10_UInt8_13_io_deq_valid : _T_3410 ? _Queue10_UInt8_12_io_deq_valid : _T_3409 ? _Queue10_UInt8_11_io_deq_valid : _T_3408 ? _Queue10_UInt8_10_io_deq_valid : _T_3407 ? _Queue10_UInt8_9_io_deq_valid : _T_3406 ? _Queue10_UInt8_8_io_deq_valid : _T_3405 ? _Queue10_UInt8_7_io_deq_valid : _T_3404 ? _Queue10_UInt8_6_io_deq_valid : _T_3403 ? _Queue10_UInt8_5_io_deq_valid : _T_3402 ? _Queue10_UInt8_4_io_deq_valid : _T_3401 ? _Queue10_UInt8_3_io_deq_valid : _T_3400 ? _Queue10_UInt8_2_io_deq_valid : _T_3399 ? _Queue10_UInt8_1_io_deq_valid : _T_3398 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_5 = _remapindex_T + 7'h5; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_94 = _remapindex_T_5 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_5 = _GEN_94[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3430 = remapindex_5 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3431 = remapindex_5 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3432 = remapindex_5 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3433 = remapindex_5 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3434 = remapindex_5 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3435 = remapindex_5 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3436 = remapindex_5 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3437 = remapindex_5 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3438 = remapindex_5 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3439 = remapindex_5 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3440 = remapindex_5 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3441 = remapindex_5 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3442 = remapindex_5 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3443 = remapindex_5 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3444 = remapindex_5 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3445 = remapindex_5 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3446 = remapindex_5 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3447 = remapindex_5 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3448 = remapindex_5 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3449 = remapindex_5 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3450 = remapindex_5 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3451 = remapindex_5 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3452 = remapindex_5 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3453 = remapindex_5 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3454 = remapindex_5 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3455 = remapindex_5 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3456 = remapindex_5 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3457 = remapindex_5 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3458 = remapindex_5 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3459 = remapindex_5 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3460 = remapindex_5 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3461 = remapindex_5 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_5 = _T_3461 ? _Queue10_UInt8_31_io_deq_bits : _T_3460 ? _Queue10_UInt8_30_io_deq_bits : _T_3459 ? _Queue10_UInt8_29_io_deq_bits : _T_3458 ? _Queue10_UInt8_28_io_deq_bits : _T_3457 ? _Queue10_UInt8_27_io_deq_bits : _T_3456 ? _Queue10_UInt8_26_io_deq_bits : _T_3455 ? _Queue10_UInt8_25_io_deq_bits : _T_3454 ? _Queue10_UInt8_24_io_deq_bits : _T_3453 ? _Queue10_UInt8_23_io_deq_bits : _T_3452 ? _Queue10_UInt8_22_io_deq_bits : _T_3451 ? _Queue10_UInt8_21_io_deq_bits : _T_3450 ? _Queue10_UInt8_20_io_deq_bits : _T_3449 ? _Queue10_UInt8_19_io_deq_bits : _T_3448 ? _Queue10_UInt8_18_io_deq_bits : _T_3447 ? _Queue10_UInt8_17_io_deq_bits : _T_3446 ? _Queue10_UInt8_16_io_deq_bits : _T_3445 ? _Queue10_UInt8_15_io_deq_bits : _T_3444 ? _Queue10_UInt8_14_io_deq_bits : _T_3443 ? _Queue10_UInt8_13_io_deq_bits : _T_3442 ? _Queue10_UInt8_12_io_deq_bits : _T_3441 ? _Queue10_UInt8_11_io_deq_bits : _T_3440 ? _Queue10_UInt8_10_io_deq_bits : _T_3439 ? _Queue10_UInt8_9_io_deq_bits : _T_3438 ? _Queue10_UInt8_8_io_deq_bits : _T_3437 ? _Queue10_UInt8_7_io_deq_bits : _T_3436 ? _Queue10_UInt8_6_io_deq_bits : _T_3435 ? _Queue10_UInt8_5_io_deq_bits : _T_3434 ? _Queue10_UInt8_4_io_deq_bits : _T_3433 ? _Queue10_UInt8_3_io_deq_bits : _T_3432 ? _Queue10_UInt8_2_io_deq_bits : _T_3431 ? _Queue10_UInt8_1_io_deq_bits : _T_3430 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_5 = _T_3461 ? _Queue10_UInt8_31_io_deq_valid : _T_3460 ? _Queue10_UInt8_30_io_deq_valid : _T_3459 ? _Queue10_UInt8_29_io_deq_valid : _T_3458 ? _Queue10_UInt8_28_io_deq_valid : _T_3457 ? _Queue10_UInt8_27_io_deq_valid : _T_3456 ? _Queue10_UInt8_26_io_deq_valid : _T_3455 ? _Queue10_UInt8_25_io_deq_valid : _T_3454 ? _Queue10_UInt8_24_io_deq_valid : _T_3453 ? _Queue10_UInt8_23_io_deq_valid : _T_3452 ? _Queue10_UInt8_22_io_deq_valid : _T_3451 ? _Queue10_UInt8_21_io_deq_valid : _T_3450 ? _Queue10_UInt8_20_io_deq_valid : _T_3449 ? _Queue10_UInt8_19_io_deq_valid : _T_3448 ? _Queue10_UInt8_18_io_deq_valid : _T_3447 ? _Queue10_UInt8_17_io_deq_valid : _T_3446 ? _Queue10_UInt8_16_io_deq_valid : _T_3445 ? _Queue10_UInt8_15_io_deq_valid : _T_3444 ? _Queue10_UInt8_14_io_deq_valid : _T_3443 ? _Queue10_UInt8_13_io_deq_valid : _T_3442 ? _Queue10_UInt8_12_io_deq_valid : _T_3441 ? _Queue10_UInt8_11_io_deq_valid : _T_3440 ? _Queue10_UInt8_10_io_deq_valid : _T_3439 ? _Queue10_UInt8_9_io_deq_valid : _T_3438 ? _Queue10_UInt8_8_io_deq_valid : _T_3437 ? _Queue10_UInt8_7_io_deq_valid : _T_3436 ? _Queue10_UInt8_6_io_deq_valid : _T_3435 ? _Queue10_UInt8_5_io_deq_valid : _T_3434 ? _Queue10_UInt8_4_io_deq_valid : _T_3433 ? _Queue10_UInt8_3_io_deq_valid : _T_3432 ? _Queue10_UInt8_2_io_deq_valid : _T_3431 ? _Queue10_UInt8_1_io_deq_valid : _T_3430 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_6 = _remapindex_T + 7'h6; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_95 = _remapindex_T_6 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_6 = _GEN_95[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3462 = remapindex_6 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3463 = remapindex_6 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3464 = remapindex_6 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3465 = remapindex_6 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3466 = remapindex_6 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3467 = remapindex_6 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3468 = remapindex_6 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3469 = remapindex_6 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3470 = remapindex_6 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3471 = remapindex_6 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3472 = remapindex_6 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3473 = remapindex_6 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3474 = remapindex_6 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3475 = remapindex_6 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3476 = remapindex_6 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3477 = remapindex_6 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3478 = remapindex_6 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3479 = remapindex_6 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3480 = remapindex_6 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3481 = remapindex_6 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3482 = remapindex_6 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3483 = remapindex_6 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3484 = remapindex_6 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3485 = remapindex_6 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3486 = remapindex_6 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3487 = remapindex_6 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3488 = remapindex_6 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3489 = remapindex_6 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3490 = remapindex_6 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3491 = remapindex_6 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3492 = remapindex_6 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3493 = remapindex_6 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_6 = _T_3493 ? _Queue10_UInt8_31_io_deq_bits : _T_3492 ? _Queue10_UInt8_30_io_deq_bits : _T_3491 ? _Queue10_UInt8_29_io_deq_bits : _T_3490 ? _Queue10_UInt8_28_io_deq_bits : _T_3489 ? _Queue10_UInt8_27_io_deq_bits : _T_3488 ? _Queue10_UInt8_26_io_deq_bits : _T_3487 ? _Queue10_UInt8_25_io_deq_bits : _T_3486 ? _Queue10_UInt8_24_io_deq_bits : _T_3485 ? _Queue10_UInt8_23_io_deq_bits : _T_3484 ? _Queue10_UInt8_22_io_deq_bits : _T_3483 ? _Queue10_UInt8_21_io_deq_bits : _T_3482 ? _Queue10_UInt8_20_io_deq_bits : _T_3481 ? _Queue10_UInt8_19_io_deq_bits : _T_3480 ? _Queue10_UInt8_18_io_deq_bits : _T_3479 ? _Queue10_UInt8_17_io_deq_bits : _T_3478 ? _Queue10_UInt8_16_io_deq_bits : _T_3477 ? _Queue10_UInt8_15_io_deq_bits : _T_3476 ? _Queue10_UInt8_14_io_deq_bits : _T_3475 ? _Queue10_UInt8_13_io_deq_bits : _T_3474 ? _Queue10_UInt8_12_io_deq_bits : _T_3473 ? _Queue10_UInt8_11_io_deq_bits : _T_3472 ? _Queue10_UInt8_10_io_deq_bits : _T_3471 ? _Queue10_UInt8_9_io_deq_bits : _T_3470 ? _Queue10_UInt8_8_io_deq_bits : _T_3469 ? _Queue10_UInt8_7_io_deq_bits : _T_3468 ? _Queue10_UInt8_6_io_deq_bits : _T_3467 ? _Queue10_UInt8_5_io_deq_bits : _T_3466 ? _Queue10_UInt8_4_io_deq_bits : _T_3465 ? _Queue10_UInt8_3_io_deq_bits : _T_3464 ? _Queue10_UInt8_2_io_deq_bits : _T_3463 ? _Queue10_UInt8_1_io_deq_bits : _T_3462 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_6 = _T_3493 ? _Queue10_UInt8_31_io_deq_valid : _T_3492 ? _Queue10_UInt8_30_io_deq_valid : _T_3491 ? _Queue10_UInt8_29_io_deq_valid : _T_3490 ? _Queue10_UInt8_28_io_deq_valid : _T_3489 ? _Queue10_UInt8_27_io_deq_valid : _T_3488 ? _Queue10_UInt8_26_io_deq_valid : _T_3487 ? _Queue10_UInt8_25_io_deq_valid : _T_3486 ? _Queue10_UInt8_24_io_deq_valid : _T_3485 ? _Queue10_UInt8_23_io_deq_valid : _T_3484 ? _Queue10_UInt8_22_io_deq_valid : _T_3483 ? _Queue10_UInt8_21_io_deq_valid : _T_3482 ? _Queue10_UInt8_20_io_deq_valid : _T_3481 ? _Queue10_UInt8_19_io_deq_valid : _T_3480 ? _Queue10_UInt8_18_io_deq_valid : _T_3479 ? _Queue10_UInt8_17_io_deq_valid : _T_3478 ? _Queue10_UInt8_16_io_deq_valid : _T_3477 ? _Queue10_UInt8_15_io_deq_valid : _T_3476 ? _Queue10_UInt8_14_io_deq_valid : _T_3475 ? _Queue10_UInt8_13_io_deq_valid : _T_3474 ? _Queue10_UInt8_12_io_deq_valid : _T_3473 ? _Queue10_UInt8_11_io_deq_valid : _T_3472 ? _Queue10_UInt8_10_io_deq_valid : _T_3471 ? _Queue10_UInt8_9_io_deq_valid : _T_3470 ? _Queue10_UInt8_8_io_deq_valid : _T_3469 ? _Queue10_UInt8_7_io_deq_valid : _T_3468 ? _Queue10_UInt8_6_io_deq_valid : _T_3467 ? _Queue10_UInt8_5_io_deq_valid : _T_3466 ? _Queue10_UInt8_4_io_deq_valid : _T_3465 ? _Queue10_UInt8_3_io_deq_valid : _T_3464 ? _Queue10_UInt8_2_io_deq_valid : _T_3463 ? _Queue10_UInt8_1_io_deq_valid : _T_3462 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_7 = _remapindex_T + 7'h7; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_96 = _remapindex_T_7 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_7 = _GEN_96[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3494 = remapindex_7 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3495 = remapindex_7 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3496 = remapindex_7 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3497 = remapindex_7 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3498 = remapindex_7 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3499 = remapindex_7 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3500 = remapindex_7 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3501 = remapindex_7 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3502 = remapindex_7 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3503 = remapindex_7 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3504 = remapindex_7 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3505 = remapindex_7 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3506 = remapindex_7 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3507 = remapindex_7 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3508 = remapindex_7 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3509 = remapindex_7 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3510 = remapindex_7 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3511 = remapindex_7 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3512 = remapindex_7 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3513 = remapindex_7 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3514 = remapindex_7 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3515 = remapindex_7 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3516 = remapindex_7 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3517 = remapindex_7 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3518 = remapindex_7 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3519 = remapindex_7 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3520 = remapindex_7 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3521 = remapindex_7 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3522 = remapindex_7 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3523 = remapindex_7 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3524 = remapindex_7 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3525 = remapindex_7 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_7 = _T_3525 ? _Queue10_UInt8_31_io_deq_bits : _T_3524 ? _Queue10_UInt8_30_io_deq_bits : _T_3523 ? _Queue10_UInt8_29_io_deq_bits : _T_3522 ? _Queue10_UInt8_28_io_deq_bits : _T_3521 ? _Queue10_UInt8_27_io_deq_bits : _T_3520 ? _Queue10_UInt8_26_io_deq_bits : _T_3519 ? _Queue10_UInt8_25_io_deq_bits : _T_3518 ? _Queue10_UInt8_24_io_deq_bits : _T_3517 ? _Queue10_UInt8_23_io_deq_bits : _T_3516 ? _Queue10_UInt8_22_io_deq_bits : _T_3515 ? _Queue10_UInt8_21_io_deq_bits : _T_3514 ? _Queue10_UInt8_20_io_deq_bits : _T_3513 ? _Queue10_UInt8_19_io_deq_bits : _T_3512 ? _Queue10_UInt8_18_io_deq_bits : _T_3511 ? _Queue10_UInt8_17_io_deq_bits : _T_3510 ? _Queue10_UInt8_16_io_deq_bits : _T_3509 ? _Queue10_UInt8_15_io_deq_bits : _T_3508 ? _Queue10_UInt8_14_io_deq_bits : _T_3507 ? _Queue10_UInt8_13_io_deq_bits : _T_3506 ? _Queue10_UInt8_12_io_deq_bits : _T_3505 ? _Queue10_UInt8_11_io_deq_bits : _T_3504 ? _Queue10_UInt8_10_io_deq_bits : _T_3503 ? _Queue10_UInt8_9_io_deq_bits : _T_3502 ? _Queue10_UInt8_8_io_deq_bits : _T_3501 ? _Queue10_UInt8_7_io_deq_bits : _T_3500 ? _Queue10_UInt8_6_io_deq_bits : _T_3499 ? _Queue10_UInt8_5_io_deq_bits : _T_3498 ? _Queue10_UInt8_4_io_deq_bits : _T_3497 ? _Queue10_UInt8_3_io_deq_bits : _T_3496 ? _Queue10_UInt8_2_io_deq_bits : _T_3495 ? _Queue10_UInt8_1_io_deq_bits : _T_3494 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_7 = _T_3525 ? _Queue10_UInt8_31_io_deq_valid : _T_3524 ? _Queue10_UInt8_30_io_deq_valid : _T_3523 ? _Queue10_UInt8_29_io_deq_valid : _T_3522 ? _Queue10_UInt8_28_io_deq_valid : _T_3521 ? _Queue10_UInt8_27_io_deq_valid : _T_3520 ? _Queue10_UInt8_26_io_deq_valid : _T_3519 ? _Queue10_UInt8_25_io_deq_valid : _T_3518 ? _Queue10_UInt8_24_io_deq_valid : _T_3517 ? _Queue10_UInt8_23_io_deq_valid : _T_3516 ? _Queue10_UInt8_22_io_deq_valid : _T_3515 ? _Queue10_UInt8_21_io_deq_valid : _T_3514 ? _Queue10_UInt8_20_io_deq_valid : _T_3513 ? _Queue10_UInt8_19_io_deq_valid : _T_3512 ? _Queue10_UInt8_18_io_deq_valid : _T_3511 ? _Queue10_UInt8_17_io_deq_valid : _T_3510 ? _Queue10_UInt8_16_io_deq_valid : _T_3509 ? _Queue10_UInt8_15_io_deq_valid : _T_3508 ? _Queue10_UInt8_14_io_deq_valid : _T_3507 ? _Queue10_UInt8_13_io_deq_valid : _T_3506 ? _Queue10_UInt8_12_io_deq_valid : _T_3505 ? _Queue10_UInt8_11_io_deq_valid : _T_3504 ? _Queue10_UInt8_10_io_deq_valid : _T_3503 ? _Queue10_UInt8_9_io_deq_valid : _T_3502 ? _Queue10_UInt8_8_io_deq_valid : _T_3501 ? _Queue10_UInt8_7_io_deq_valid : _T_3500 ? _Queue10_UInt8_6_io_deq_valid : _T_3499 ? _Queue10_UInt8_5_io_deq_valid : _T_3498 ? _Queue10_UInt8_4_io_deq_valid : _T_3497 ? _Queue10_UInt8_3_io_deq_valid : _T_3496 ? _Queue10_UInt8_2_io_deq_valid : _T_3495 ? _Queue10_UInt8_1_io_deq_valid : _T_3494 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_8 = _remapindex_T + 7'h8; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_97 = _remapindex_T_8 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_8 = _GEN_97[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3526 = remapindex_8 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3527 = remapindex_8 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3528 = remapindex_8 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3529 = remapindex_8 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3530 = remapindex_8 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3531 = remapindex_8 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3532 = remapindex_8 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3533 = remapindex_8 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3534 = remapindex_8 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3535 = remapindex_8 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3536 = remapindex_8 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3537 = remapindex_8 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3538 = remapindex_8 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3539 = remapindex_8 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3540 = remapindex_8 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3541 = remapindex_8 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3542 = remapindex_8 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3543 = remapindex_8 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3544 = remapindex_8 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3545 = remapindex_8 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3546 = remapindex_8 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3547 = remapindex_8 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3548 = remapindex_8 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3549 = remapindex_8 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3550 = remapindex_8 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3551 = remapindex_8 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3552 = remapindex_8 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3553 = remapindex_8 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3554 = remapindex_8 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3555 = remapindex_8 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3556 = remapindex_8 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3557 = remapindex_8 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_8 = _T_3557 ? _Queue10_UInt8_31_io_deq_bits : _T_3556 ? _Queue10_UInt8_30_io_deq_bits : _T_3555 ? _Queue10_UInt8_29_io_deq_bits : _T_3554 ? _Queue10_UInt8_28_io_deq_bits : _T_3553 ? _Queue10_UInt8_27_io_deq_bits : _T_3552 ? _Queue10_UInt8_26_io_deq_bits : _T_3551 ? _Queue10_UInt8_25_io_deq_bits : _T_3550 ? _Queue10_UInt8_24_io_deq_bits : _T_3549 ? _Queue10_UInt8_23_io_deq_bits : _T_3548 ? _Queue10_UInt8_22_io_deq_bits : _T_3547 ? _Queue10_UInt8_21_io_deq_bits : _T_3546 ? _Queue10_UInt8_20_io_deq_bits : _T_3545 ? _Queue10_UInt8_19_io_deq_bits : _T_3544 ? _Queue10_UInt8_18_io_deq_bits : _T_3543 ? _Queue10_UInt8_17_io_deq_bits : _T_3542 ? _Queue10_UInt8_16_io_deq_bits : _T_3541 ? _Queue10_UInt8_15_io_deq_bits : _T_3540 ? _Queue10_UInt8_14_io_deq_bits : _T_3539 ? _Queue10_UInt8_13_io_deq_bits : _T_3538 ? _Queue10_UInt8_12_io_deq_bits : _T_3537 ? _Queue10_UInt8_11_io_deq_bits : _T_3536 ? _Queue10_UInt8_10_io_deq_bits : _T_3535 ? _Queue10_UInt8_9_io_deq_bits : _T_3534 ? _Queue10_UInt8_8_io_deq_bits : _T_3533 ? _Queue10_UInt8_7_io_deq_bits : _T_3532 ? _Queue10_UInt8_6_io_deq_bits : _T_3531 ? _Queue10_UInt8_5_io_deq_bits : _T_3530 ? _Queue10_UInt8_4_io_deq_bits : _T_3529 ? _Queue10_UInt8_3_io_deq_bits : _T_3528 ? _Queue10_UInt8_2_io_deq_bits : _T_3527 ? _Queue10_UInt8_1_io_deq_bits : _T_3526 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_8 = _T_3557 ? _Queue10_UInt8_31_io_deq_valid : _T_3556 ? _Queue10_UInt8_30_io_deq_valid : _T_3555 ? _Queue10_UInt8_29_io_deq_valid : _T_3554 ? _Queue10_UInt8_28_io_deq_valid : _T_3553 ? _Queue10_UInt8_27_io_deq_valid : _T_3552 ? _Queue10_UInt8_26_io_deq_valid : _T_3551 ? _Queue10_UInt8_25_io_deq_valid : _T_3550 ? _Queue10_UInt8_24_io_deq_valid : _T_3549 ? _Queue10_UInt8_23_io_deq_valid : _T_3548 ? _Queue10_UInt8_22_io_deq_valid : _T_3547 ? _Queue10_UInt8_21_io_deq_valid : _T_3546 ? _Queue10_UInt8_20_io_deq_valid : _T_3545 ? _Queue10_UInt8_19_io_deq_valid : _T_3544 ? _Queue10_UInt8_18_io_deq_valid : _T_3543 ? _Queue10_UInt8_17_io_deq_valid : _T_3542 ? _Queue10_UInt8_16_io_deq_valid : _T_3541 ? _Queue10_UInt8_15_io_deq_valid : _T_3540 ? _Queue10_UInt8_14_io_deq_valid : _T_3539 ? _Queue10_UInt8_13_io_deq_valid : _T_3538 ? _Queue10_UInt8_12_io_deq_valid : _T_3537 ? _Queue10_UInt8_11_io_deq_valid : _T_3536 ? _Queue10_UInt8_10_io_deq_valid : _T_3535 ? _Queue10_UInt8_9_io_deq_valid : _T_3534 ? _Queue10_UInt8_8_io_deq_valid : _T_3533 ? _Queue10_UInt8_7_io_deq_valid : _T_3532 ? _Queue10_UInt8_6_io_deq_valid : _T_3531 ? _Queue10_UInt8_5_io_deq_valid : _T_3530 ? _Queue10_UInt8_4_io_deq_valid : _T_3529 ? _Queue10_UInt8_3_io_deq_valid : _T_3528 ? _Queue10_UInt8_2_io_deq_valid : _T_3527 ? _Queue10_UInt8_1_io_deq_valid : _T_3526 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_9 = _remapindex_T + 7'h9; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_98 = _remapindex_T_9 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_9 = _GEN_98[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3558 = remapindex_9 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3559 = remapindex_9 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3560 = remapindex_9 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3561 = remapindex_9 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3562 = remapindex_9 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3563 = remapindex_9 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3564 = remapindex_9 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3565 = remapindex_9 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3566 = remapindex_9 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3567 = remapindex_9 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3568 = remapindex_9 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3569 = remapindex_9 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3570 = remapindex_9 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3571 = remapindex_9 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3572 = remapindex_9 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3573 = remapindex_9 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3574 = remapindex_9 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3575 = remapindex_9 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3576 = remapindex_9 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3577 = remapindex_9 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3578 = remapindex_9 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3579 = remapindex_9 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3580 = remapindex_9 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3581 = remapindex_9 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3582 = remapindex_9 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3583 = remapindex_9 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3584 = remapindex_9 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3585 = remapindex_9 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3586 = remapindex_9 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3587 = remapindex_9 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3588 = remapindex_9 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3589 = remapindex_9 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_9 = _T_3589 ? _Queue10_UInt8_31_io_deq_bits : _T_3588 ? _Queue10_UInt8_30_io_deq_bits : _T_3587 ? _Queue10_UInt8_29_io_deq_bits : _T_3586 ? _Queue10_UInt8_28_io_deq_bits : _T_3585 ? _Queue10_UInt8_27_io_deq_bits : _T_3584 ? _Queue10_UInt8_26_io_deq_bits : _T_3583 ? _Queue10_UInt8_25_io_deq_bits : _T_3582 ? _Queue10_UInt8_24_io_deq_bits : _T_3581 ? _Queue10_UInt8_23_io_deq_bits : _T_3580 ? _Queue10_UInt8_22_io_deq_bits : _T_3579 ? _Queue10_UInt8_21_io_deq_bits : _T_3578 ? _Queue10_UInt8_20_io_deq_bits : _T_3577 ? _Queue10_UInt8_19_io_deq_bits : _T_3576 ? _Queue10_UInt8_18_io_deq_bits : _T_3575 ? _Queue10_UInt8_17_io_deq_bits : _T_3574 ? _Queue10_UInt8_16_io_deq_bits : _T_3573 ? _Queue10_UInt8_15_io_deq_bits : _T_3572 ? _Queue10_UInt8_14_io_deq_bits : _T_3571 ? _Queue10_UInt8_13_io_deq_bits : _T_3570 ? _Queue10_UInt8_12_io_deq_bits : _T_3569 ? _Queue10_UInt8_11_io_deq_bits : _T_3568 ? _Queue10_UInt8_10_io_deq_bits : _T_3567 ? _Queue10_UInt8_9_io_deq_bits : _T_3566 ? _Queue10_UInt8_8_io_deq_bits : _T_3565 ? _Queue10_UInt8_7_io_deq_bits : _T_3564 ? _Queue10_UInt8_6_io_deq_bits : _T_3563 ? _Queue10_UInt8_5_io_deq_bits : _T_3562 ? _Queue10_UInt8_4_io_deq_bits : _T_3561 ? _Queue10_UInt8_3_io_deq_bits : _T_3560 ? _Queue10_UInt8_2_io_deq_bits : _T_3559 ? _Queue10_UInt8_1_io_deq_bits : _T_3558 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_9 = _T_3589 ? _Queue10_UInt8_31_io_deq_valid : _T_3588 ? _Queue10_UInt8_30_io_deq_valid : _T_3587 ? _Queue10_UInt8_29_io_deq_valid : _T_3586 ? _Queue10_UInt8_28_io_deq_valid : _T_3585 ? _Queue10_UInt8_27_io_deq_valid : _T_3584 ? _Queue10_UInt8_26_io_deq_valid : _T_3583 ? _Queue10_UInt8_25_io_deq_valid : _T_3582 ? _Queue10_UInt8_24_io_deq_valid : _T_3581 ? _Queue10_UInt8_23_io_deq_valid : _T_3580 ? _Queue10_UInt8_22_io_deq_valid : _T_3579 ? _Queue10_UInt8_21_io_deq_valid : _T_3578 ? _Queue10_UInt8_20_io_deq_valid : _T_3577 ? _Queue10_UInt8_19_io_deq_valid : _T_3576 ? _Queue10_UInt8_18_io_deq_valid : _T_3575 ? _Queue10_UInt8_17_io_deq_valid : _T_3574 ? _Queue10_UInt8_16_io_deq_valid : _T_3573 ? _Queue10_UInt8_15_io_deq_valid : _T_3572 ? _Queue10_UInt8_14_io_deq_valid : _T_3571 ? _Queue10_UInt8_13_io_deq_valid : _T_3570 ? _Queue10_UInt8_12_io_deq_valid : _T_3569 ? _Queue10_UInt8_11_io_deq_valid : _T_3568 ? _Queue10_UInt8_10_io_deq_valid : _T_3567 ? _Queue10_UInt8_9_io_deq_valid : _T_3566 ? _Queue10_UInt8_8_io_deq_valid : _T_3565 ? _Queue10_UInt8_7_io_deq_valid : _T_3564 ? _Queue10_UInt8_6_io_deq_valid : _T_3563 ? _Queue10_UInt8_5_io_deq_valid : _T_3562 ? _Queue10_UInt8_4_io_deq_valid : _T_3561 ? _Queue10_UInt8_3_io_deq_valid : _T_3560 ? _Queue10_UInt8_2_io_deq_valid : _T_3559 ? _Queue10_UInt8_1_io_deq_valid : _T_3558 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_10 = _remapindex_T + 7'hA; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_99 = _remapindex_T_10 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_10 = _GEN_99[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3590 = remapindex_10 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3591 = remapindex_10 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3592 = remapindex_10 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3593 = remapindex_10 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3594 = remapindex_10 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3595 = remapindex_10 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3596 = remapindex_10 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3597 = remapindex_10 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3598 = remapindex_10 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3599 = remapindex_10 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3600 = remapindex_10 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3601 = remapindex_10 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3602 = remapindex_10 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3603 = remapindex_10 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3604 = remapindex_10 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3605 = remapindex_10 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3606 = remapindex_10 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3607 = remapindex_10 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3608 = remapindex_10 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3609 = remapindex_10 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3610 = remapindex_10 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3611 = remapindex_10 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3612 = remapindex_10 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3613 = remapindex_10 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3614 = remapindex_10 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3615 = remapindex_10 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3616 = remapindex_10 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3617 = remapindex_10 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3618 = remapindex_10 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3619 = remapindex_10 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3620 = remapindex_10 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3621 = remapindex_10 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_10 = _T_3621 ? _Queue10_UInt8_31_io_deq_bits : _T_3620 ? _Queue10_UInt8_30_io_deq_bits : _T_3619 ? _Queue10_UInt8_29_io_deq_bits : _T_3618 ? _Queue10_UInt8_28_io_deq_bits : _T_3617 ? _Queue10_UInt8_27_io_deq_bits : _T_3616 ? _Queue10_UInt8_26_io_deq_bits : _T_3615 ? _Queue10_UInt8_25_io_deq_bits : _T_3614 ? _Queue10_UInt8_24_io_deq_bits : _T_3613 ? _Queue10_UInt8_23_io_deq_bits : _T_3612 ? _Queue10_UInt8_22_io_deq_bits : _T_3611 ? _Queue10_UInt8_21_io_deq_bits : _T_3610 ? _Queue10_UInt8_20_io_deq_bits : _T_3609 ? _Queue10_UInt8_19_io_deq_bits : _T_3608 ? _Queue10_UInt8_18_io_deq_bits : _T_3607 ? _Queue10_UInt8_17_io_deq_bits : _T_3606 ? _Queue10_UInt8_16_io_deq_bits : _T_3605 ? _Queue10_UInt8_15_io_deq_bits : _T_3604 ? _Queue10_UInt8_14_io_deq_bits : _T_3603 ? _Queue10_UInt8_13_io_deq_bits : _T_3602 ? _Queue10_UInt8_12_io_deq_bits : _T_3601 ? _Queue10_UInt8_11_io_deq_bits : _T_3600 ? _Queue10_UInt8_10_io_deq_bits : _T_3599 ? _Queue10_UInt8_9_io_deq_bits : _T_3598 ? _Queue10_UInt8_8_io_deq_bits : _T_3597 ? _Queue10_UInt8_7_io_deq_bits : _T_3596 ? _Queue10_UInt8_6_io_deq_bits : _T_3595 ? _Queue10_UInt8_5_io_deq_bits : _T_3594 ? _Queue10_UInt8_4_io_deq_bits : _T_3593 ? _Queue10_UInt8_3_io_deq_bits : _T_3592 ? _Queue10_UInt8_2_io_deq_bits : _T_3591 ? _Queue10_UInt8_1_io_deq_bits : _T_3590 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_10 = _T_3621 ? _Queue10_UInt8_31_io_deq_valid : _T_3620 ? _Queue10_UInt8_30_io_deq_valid : _T_3619 ? _Queue10_UInt8_29_io_deq_valid : _T_3618 ? _Queue10_UInt8_28_io_deq_valid : _T_3617 ? _Queue10_UInt8_27_io_deq_valid : _T_3616 ? _Queue10_UInt8_26_io_deq_valid : _T_3615 ? _Queue10_UInt8_25_io_deq_valid : _T_3614 ? _Queue10_UInt8_24_io_deq_valid : _T_3613 ? _Queue10_UInt8_23_io_deq_valid : _T_3612 ? _Queue10_UInt8_22_io_deq_valid : _T_3611 ? _Queue10_UInt8_21_io_deq_valid : _T_3610 ? _Queue10_UInt8_20_io_deq_valid : _T_3609 ? _Queue10_UInt8_19_io_deq_valid : _T_3608 ? _Queue10_UInt8_18_io_deq_valid : _T_3607 ? _Queue10_UInt8_17_io_deq_valid : _T_3606 ? _Queue10_UInt8_16_io_deq_valid : _T_3605 ? _Queue10_UInt8_15_io_deq_valid : _T_3604 ? _Queue10_UInt8_14_io_deq_valid : _T_3603 ? _Queue10_UInt8_13_io_deq_valid : _T_3602 ? _Queue10_UInt8_12_io_deq_valid : _T_3601 ? _Queue10_UInt8_11_io_deq_valid : _T_3600 ? _Queue10_UInt8_10_io_deq_valid : _T_3599 ? _Queue10_UInt8_9_io_deq_valid : _T_3598 ? _Queue10_UInt8_8_io_deq_valid : _T_3597 ? _Queue10_UInt8_7_io_deq_valid : _T_3596 ? _Queue10_UInt8_6_io_deq_valid : _T_3595 ? _Queue10_UInt8_5_io_deq_valid : _T_3594 ? _Queue10_UInt8_4_io_deq_valid : _T_3593 ? _Queue10_UInt8_3_io_deq_valid : _T_3592 ? _Queue10_UInt8_2_io_deq_valid : _T_3591 ? _Queue10_UInt8_1_io_deq_valid : _T_3590 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_11 = _remapindex_T + 7'hB; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_100 = _remapindex_T_11 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_11 = _GEN_100[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3622 = remapindex_11 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3623 = remapindex_11 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3624 = remapindex_11 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3625 = remapindex_11 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3626 = remapindex_11 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3627 = remapindex_11 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3628 = remapindex_11 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3629 = remapindex_11 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3630 = remapindex_11 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3631 = remapindex_11 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3632 = remapindex_11 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3633 = remapindex_11 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3634 = remapindex_11 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3635 = remapindex_11 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3636 = remapindex_11 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3637 = remapindex_11 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3638 = remapindex_11 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3639 = remapindex_11 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3640 = remapindex_11 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3641 = remapindex_11 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3642 = remapindex_11 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3643 = remapindex_11 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3644 = remapindex_11 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3645 = remapindex_11 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3646 = remapindex_11 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3647 = remapindex_11 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3648 = remapindex_11 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3649 = remapindex_11 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3650 = remapindex_11 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3651 = remapindex_11 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3652 = remapindex_11 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3653 = remapindex_11 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_11 = _T_3653 ? _Queue10_UInt8_31_io_deq_bits : _T_3652 ? _Queue10_UInt8_30_io_deq_bits : _T_3651 ? _Queue10_UInt8_29_io_deq_bits : _T_3650 ? _Queue10_UInt8_28_io_deq_bits : _T_3649 ? _Queue10_UInt8_27_io_deq_bits : _T_3648 ? _Queue10_UInt8_26_io_deq_bits : _T_3647 ? _Queue10_UInt8_25_io_deq_bits : _T_3646 ? _Queue10_UInt8_24_io_deq_bits : _T_3645 ? _Queue10_UInt8_23_io_deq_bits : _T_3644 ? _Queue10_UInt8_22_io_deq_bits : _T_3643 ? _Queue10_UInt8_21_io_deq_bits : _T_3642 ? _Queue10_UInt8_20_io_deq_bits : _T_3641 ? _Queue10_UInt8_19_io_deq_bits : _T_3640 ? _Queue10_UInt8_18_io_deq_bits : _T_3639 ? _Queue10_UInt8_17_io_deq_bits : _T_3638 ? _Queue10_UInt8_16_io_deq_bits : _T_3637 ? _Queue10_UInt8_15_io_deq_bits : _T_3636 ? _Queue10_UInt8_14_io_deq_bits : _T_3635 ? _Queue10_UInt8_13_io_deq_bits : _T_3634 ? _Queue10_UInt8_12_io_deq_bits : _T_3633 ? _Queue10_UInt8_11_io_deq_bits : _T_3632 ? _Queue10_UInt8_10_io_deq_bits : _T_3631 ? _Queue10_UInt8_9_io_deq_bits : _T_3630 ? _Queue10_UInt8_8_io_deq_bits : _T_3629 ? _Queue10_UInt8_7_io_deq_bits : _T_3628 ? _Queue10_UInt8_6_io_deq_bits : _T_3627 ? _Queue10_UInt8_5_io_deq_bits : _T_3626 ? _Queue10_UInt8_4_io_deq_bits : _T_3625 ? _Queue10_UInt8_3_io_deq_bits : _T_3624 ? _Queue10_UInt8_2_io_deq_bits : _T_3623 ? _Queue10_UInt8_1_io_deq_bits : _T_3622 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_11 = _T_3653 ? _Queue10_UInt8_31_io_deq_valid : _T_3652 ? _Queue10_UInt8_30_io_deq_valid : _T_3651 ? _Queue10_UInt8_29_io_deq_valid : _T_3650 ? _Queue10_UInt8_28_io_deq_valid : _T_3649 ? _Queue10_UInt8_27_io_deq_valid : _T_3648 ? _Queue10_UInt8_26_io_deq_valid : _T_3647 ? _Queue10_UInt8_25_io_deq_valid : _T_3646 ? _Queue10_UInt8_24_io_deq_valid : _T_3645 ? _Queue10_UInt8_23_io_deq_valid : _T_3644 ? _Queue10_UInt8_22_io_deq_valid : _T_3643 ? _Queue10_UInt8_21_io_deq_valid : _T_3642 ? _Queue10_UInt8_20_io_deq_valid : _T_3641 ? _Queue10_UInt8_19_io_deq_valid : _T_3640 ? _Queue10_UInt8_18_io_deq_valid : _T_3639 ? _Queue10_UInt8_17_io_deq_valid : _T_3638 ? _Queue10_UInt8_16_io_deq_valid : _T_3637 ? _Queue10_UInt8_15_io_deq_valid : _T_3636 ? _Queue10_UInt8_14_io_deq_valid : _T_3635 ? _Queue10_UInt8_13_io_deq_valid : _T_3634 ? _Queue10_UInt8_12_io_deq_valid : _T_3633 ? _Queue10_UInt8_11_io_deq_valid : _T_3632 ? _Queue10_UInt8_10_io_deq_valid : _T_3631 ? _Queue10_UInt8_9_io_deq_valid : _T_3630 ? _Queue10_UInt8_8_io_deq_valid : _T_3629 ? _Queue10_UInt8_7_io_deq_valid : _T_3628 ? _Queue10_UInt8_6_io_deq_valid : _T_3627 ? _Queue10_UInt8_5_io_deq_valid : _T_3626 ? _Queue10_UInt8_4_io_deq_valid : _T_3625 ? _Queue10_UInt8_3_io_deq_valid : _T_3624 ? _Queue10_UInt8_2_io_deq_valid : _T_3623 ? _Queue10_UInt8_1_io_deq_valid : _T_3622 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_12 = _remapindex_T + 7'hC; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_101 = _remapindex_T_12 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_12 = _GEN_101[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3654 = remapindex_12 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3655 = remapindex_12 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3656 = remapindex_12 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3657 = remapindex_12 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3658 = remapindex_12 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3659 = remapindex_12 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3660 = remapindex_12 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3661 = remapindex_12 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3662 = remapindex_12 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3663 = remapindex_12 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3664 = remapindex_12 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3665 = remapindex_12 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3666 = remapindex_12 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3667 = remapindex_12 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3668 = remapindex_12 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3669 = remapindex_12 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3670 = remapindex_12 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3671 = remapindex_12 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3672 = remapindex_12 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3673 = remapindex_12 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3674 = remapindex_12 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3675 = remapindex_12 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3676 = remapindex_12 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3677 = remapindex_12 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3678 = remapindex_12 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3679 = remapindex_12 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3680 = remapindex_12 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3681 = remapindex_12 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3682 = remapindex_12 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3683 = remapindex_12 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3684 = remapindex_12 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3685 = remapindex_12 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_12 = _T_3685 ? _Queue10_UInt8_31_io_deq_bits : _T_3684 ? _Queue10_UInt8_30_io_deq_bits : _T_3683 ? _Queue10_UInt8_29_io_deq_bits : _T_3682 ? _Queue10_UInt8_28_io_deq_bits : _T_3681 ? _Queue10_UInt8_27_io_deq_bits : _T_3680 ? _Queue10_UInt8_26_io_deq_bits : _T_3679 ? _Queue10_UInt8_25_io_deq_bits : _T_3678 ? _Queue10_UInt8_24_io_deq_bits : _T_3677 ? _Queue10_UInt8_23_io_deq_bits : _T_3676 ? _Queue10_UInt8_22_io_deq_bits : _T_3675 ? _Queue10_UInt8_21_io_deq_bits : _T_3674 ? _Queue10_UInt8_20_io_deq_bits : _T_3673 ? _Queue10_UInt8_19_io_deq_bits : _T_3672 ? _Queue10_UInt8_18_io_deq_bits : _T_3671 ? _Queue10_UInt8_17_io_deq_bits : _T_3670 ? _Queue10_UInt8_16_io_deq_bits : _T_3669 ? _Queue10_UInt8_15_io_deq_bits : _T_3668 ? _Queue10_UInt8_14_io_deq_bits : _T_3667 ? _Queue10_UInt8_13_io_deq_bits : _T_3666 ? _Queue10_UInt8_12_io_deq_bits : _T_3665 ? _Queue10_UInt8_11_io_deq_bits : _T_3664 ? _Queue10_UInt8_10_io_deq_bits : _T_3663 ? _Queue10_UInt8_9_io_deq_bits : _T_3662 ? _Queue10_UInt8_8_io_deq_bits : _T_3661 ? _Queue10_UInt8_7_io_deq_bits : _T_3660 ? _Queue10_UInt8_6_io_deq_bits : _T_3659 ? _Queue10_UInt8_5_io_deq_bits : _T_3658 ? _Queue10_UInt8_4_io_deq_bits : _T_3657 ? _Queue10_UInt8_3_io_deq_bits : _T_3656 ? _Queue10_UInt8_2_io_deq_bits : _T_3655 ? _Queue10_UInt8_1_io_deq_bits : _T_3654 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_12 = _T_3685 ? _Queue10_UInt8_31_io_deq_valid : _T_3684 ? _Queue10_UInt8_30_io_deq_valid : _T_3683 ? _Queue10_UInt8_29_io_deq_valid : _T_3682 ? _Queue10_UInt8_28_io_deq_valid : _T_3681 ? _Queue10_UInt8_27_io_deq_valid : _T_3680 ? _Queue10_UInt8_26_io_deq_valid : _T_3679 ? _Queue10_UInt8_25_io_deq_valid : _T_3678 ? _Queue10_UInt8_24_io_deq_valid : _T_3677 ? _Queue10_UInt8_23_io_deq_valid : _T_3676 ? _Queue10_UInt8_22_io_deq_valid : _T_3675 ? _Queue10_UInt8_21_io_deq_valid : _T_3674 ? _Queue10_UInt8_20_io_deq_valid : _T_3673 ? _Queue10_UInt8_19_io_deq_valid : _T_3672 ? _Queue10_UInt8_18_io_deq_valid : _T_3671 ? _Queue10_UInt8_17_io_deq_valid : _T_3670 ? _Queue10_UInt8_16_io_deq_valid : _T_3669 ? _Queue10_UInt8_15_io_deq_valid : _T_3668 ? _Queue10_UInt8_14_io_deq_valid : _T_3667 ? _Queue10_UInt8_13_io_deq_valid : _T_3666 ? _Queue10_UInt8_12_io_deq_valid : _T_3665 ? _Queue10_UInt8_11_io_deq_valid : _T_3664 ? _Queue10_UInt8_10_io_deq_valid : _T_3663 ? _Queue10_UInt8_9_io_deq_valid : _T_3662 ? _Queue10_UInt8_8_io_deq_valid : _T_3661 ? _Queue10_UInt8_7_io_deq_valid : _T_3660 ? _Queue10_UInt8_6_io_deq_valid : _T_3659 ? _Queue10_UInt8_5_io_deq_valid : _T_3658 ? _Queue10_UInt8_4_io_deq_valid : _T_3657 ? _Queue10_UInt8_3_io_deq_valid : _T_3656 ? _Queue10_UInt8_2_io_deq_valid : _T_3655 ? _Queue10_UInt8_1_io_deq_valid : _T_3654 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_13 = _remapindex_T + 7'hD; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_102 = _remapindex_T_13 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_13 = _GEN_102[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3686 = remapindex_13 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3687 = remapindex_13 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3688 = remapindex_13 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3689 = remapindex_13 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3690 = remapindex_13 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3691 = remapindex_13 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3692 = remapindex_13 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3693 = remapindex_13 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3694 = remapindex_13 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3695 = remapindex_13 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3696 = remapindex_13 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3697 = remapindex_13 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3698 = remapindex_13 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3699 = remapindex_13 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3700 = remapindex_13 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3701 = remapindex_13 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3702 = remapindex_13 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3703 = remapindex_13 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3704 = remapindex_13 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3705 = remapindex_13 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3706 = remapindex_13 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3707 = remapindex_13 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3708 = remapindex_13 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3709 = remapindex_13 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3710 = remapindex_13 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3711 = remapindex_13 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3712 = remapindex_13 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3713 = remapindex_13 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3714 = remapindex_13 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3715 = remapindex_13 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3716 = remapindex_13 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3717 = remapindex_13 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_13 = _T_3717 ? _Queue10_UInt8_31_io_deq_bits : _T_3716 ? _Queue10_UInt8_30_io_deq_bits : _T_3715 ? _Queue10_UInt8_29_io_deq_bits : _T_3714 ? _Queue10_UInt8_28_io_deq_bits : _T_3713 ? _Queue10_UInt8_27_io_deq_bits : _T_3712 ? _Queue10_UInt8_26_io_deq_bits : _T_3711 ? _Queue10_UInt8_25_io_deq_bits : _T_3710 ? _Queue10_UInt8_24_io_deq_bits : _T_3709 ? _Queue10_UInt8_23_io_deq_bits : _T_3708 ? _Queue10_UInt8_22_io_deq_bits : _T_3707 ? _Queue10_UInt8_21_io_deq_bits : _T_3706 ? _Queue10_UInt8_20_io_deq_bits : _T_3705 ? _Queue10_UInt8_19_io_deq_bits : _T_3704 ? _Queue10_UInt8_18_io_deq_bits : _T_3703 ? _Queue10_UInt8_17_io_deq_bits : _T_3702 ? _Queue10_UInt8_16_io_deq_bits : _T_3701 ? _Queue10_UInt8_15_io_deq_bits : _T_3700 ? _Queue10_UInt8_14_io_deq_bits : _T_3699 ? _Queue10_UInt8_13_io_deq_bits : _T_3698 ? _Queue10_UInt8_12_io_deq_bits : _T_3697 ? _Queue10_UInt8_11_io_deq_bits : _T_3696 ? _Queue10_UInt8_10_io_deq_bits : _T_3695 ? _Queue10_UInt8_9_io_deq_bits : _T_3694 ? _Queue10_UInt8_8_io_deq_bits : _T_3693 ? _Queue10_UInt8_7_io_deq_bits : _T_3692 ? _Queue10_UInt8_6_io_deq_bits : _T_3691 ? _Queue10_UInt8_5_io_deq_bits : _T_3690 ? _Queue10_UInt8_4_io_deq_bits : _T_3689 ? _Queue10_UInt8_3_io_deq_bits : _T_3688 ? _Queue10_UInt8_2_io_deq_bits : _T_3687 ? _Queue10_UInt8_1_io_deq_bits : _T_3686 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_13 = _T_3717 ? _Queue10_UInt8_31_io_deq_valid : _T_3716 ? _Queue10_UInt8_30_io_deq_valid : _T_3715 ? _Queue10_UInt8_29_io_deq_valid : _T_3714 ? _Queue10_UInt8_28_io_deq_valid : _T_3713 ? _Queue10_UInt8_27_io_deq_valid : _T_3712 ? _Queue10_UInt8_26_io_deq_valid : _T_3711 ? _Queue10_UInt8_25_io_deq_valid : _T_3710 ? _Queue10_UInt8_24_io_deq_valid : _T_3709 ? _Queue10_UInt8_23_io_deq_valid : _T_3708 ? _Queue10_UInt8_22_io_deq_valid : _T_3707 ? _Queue10_UInt8_21_io_deq_valid : _T_3706 ? _Queue10_UInt8_20_io_deq_valid : _T_3705 ? _Queue10_UInt8_19_io_deq_valid : _T_3704 ? _Queue10_UInt8_18_io_deq_valid : _T_3703 ? _Queue10_UInt8_17_io_deq_valid : _T_3702 ? _Queue10_UInt8_16_io_deq_valid : _T_3701 ? _Queue10_UInt8_15_io_deq_valid : _T_3700 ? _Queue10_UInt8_14_io_deq_valid : _T_3699 ? _Queue10_UInt8_13_io_deq_valid : _T_3698 ? _Queue10_UInt8_12_io_deq_valid : _T_3697 ? _Queue10_UInt8_11_io_deq_valid : _T_3696 ? _Queue10_UInt8_10_io_deq_valid : _T_3695 ? _Queue10_UInt8_9_io_deq_valid : _T_3694 ? _Queue10_UInt8_8_io_deq_valid : _T_3693 ? _Queue10_UInt8_7_io_deq_valid : _T_3692 ? _Queue10_UInt8_6_io_deq_valid : _T_3691 ? _Queue10_UInt8_5_io_deq_valid : _T_3690 ? _Queue10_UInt8_4_io_deq_valid : _T_3689 ? _Queue10_UInt8_3_io_deq_valid : _T_3688 ? _Queue10_UInt8_2_io_deq_valid : _T_3687 ? _Queue10_UInt8_1_io_deq_valid : _T_3686 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_14 = _remapindex_T + 7'hE; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_103 = _remapindex_T_14 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_14 = _GEN_103[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3718 = remapindex_14 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3719 = remapindex_14 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3720 = remapindex_14 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3721 = remapindex_14 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3722 = remapindex_14 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3723 = remapindex_14 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3724 = remapindex_14 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3725 = remapindex_14 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3726 = remapindex_14 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3727 = remapindex_14 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3728 = remapindex_14 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3729 = remapindex_14 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3730 = remapindex_14 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3731 = remapindex_14 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3732 = remapindex_14 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3733 = remapindex_14 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3734 = remapindex_14 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3735 = remapindex_14 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3736 = remapindex_14 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3737 = remapindex_14 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3738 = remapindex_14 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3739 = remapindex_14 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3740 = remapindex_14 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3741 = remapindex_14 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3742 = remapindex_14 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3743 = remapindex_14 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3744 = remapindex_14 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3745 = remapindex_14 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3746 = remapindex_14 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3747 = remapindex_14 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3748 = remapindex_14 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3749 = remapindex_14 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_14 = _T_3749 ? _Queue10_UInt8_31_io_deq_bits : _T_3748 ? _Queue10_UInt8_30_io_deq_bits : _T_3747 ? _Queue10_UInt8_29_io_deq_bits : _T_3746 ? _Queue10_UInt8_28_io_deq_bits : _T_3745 ? _Queue10_UInt8_27_io_deq_bits : _T_3744 ? _Queue10_UInt8_26_io_deq_bits : _T_3743 ? _Queue10_UInt8_25_io_deq_bits : _T_3742 ? _Queue10_UInt8_24_io_deq_bits : _T_3741 ? _Queue10_UInt8_23_io_deq_bits : _T_3740 ? _Queue10_UInt8_22_io_deq_bits : _T_3739 ? _Queue10_UInt8_21_io_deq_bits : _T_3738 ? _Queue10_UInt8_20_io_deq_bits : _T_3737 ? _Queue10_UInt8_19_io_deq_bits : _T_3736 ? _Queue10_UInt8_18_io_deq_bits : _T_3735 ? _Queue10_UInt8_17_io_deq_bits : _T_3734 ? _Queue10_UInt8_16_io_deq_bits : _T_3733 ? _Queue10_UInt8_15_io_deq_bits : _T_3732 ? _Queue10_UInt8_14_io_deq_bits : _T_3731 ? _Queue10_UInt8_13_io_deq_bits : _T_3730 ? _Queue10_UInt8_12_io_deq_bits : _T_3729 ? _Queue10_UInt8_11_io_deq_bits : _T_3728 ? _Queue10_UInt8_10_io_deq_bits : _T_3727 ? _Queue10_UInt8_9_io_deq_bits : _T_3726 ? _Queue10_UInt8_8_io_deq_bits : _T_3725 ? _Queue10_UInt8_7_io_deq_bits : _T_3724 ? _Queue10_UInt8_6_io_deq_bits : _T_3723 ? _Queue10_UInt8_5_io_deq_bits : _T_3722 ? _Queue10_UInt8_4_io_deq_bits : _T_3721 ? _Queue10_UInt8_3_io_deq_bits : _T_3720 ? _Queue10_UInt8_2_io_deq_bits : _T_3719 ? _Queue10_UInt8_1_io_deq_bits : _T_3718 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_14 = _T_3749 ? _Queue10_UInt8_31_io_deq_valid : _T_3748 ? _Queue10_UInt8_30_io_deq_valid : _T_3747 ? _Queue10_UInt8_29_io_deq_valid : _T_3746 ? _Queue10_UInt8_28_io_deq_valid : _T_3745 ? _Queue10_UInt8_27_io_deq_valid : _T_3744 ? _Queue10_UInt8_26_io_deq_valid : _T_3743 ? _Queue10_UInt8_25_io_deq_valid : _T_3742 ? _Queue10_UInt8_24_io_deq_valid : _T_3741 ? _Queue10_UInt8_23_io_deq_valid : _T_3740 ? _Queue10_UInt8_22_io_deq_valid : _T_3739 ? _Queue10_UInt8_21_io_deq_valid : _T_3738 ? _Queue10_UInt8_20_io_deq_valid : _T_3737 ? _Queue10_UInt8_19_io_deq_valid : _T_3736 ? _Queue10_UInt8_18_io_deq_valid : _T_3735 ? _Queue10_UInt8_17_io_deq_valid : _T_3734 ? _Queue10_UInt8_16_io_deq_valid : _T_3733 ? _Queue10_UInt8_15_io_deq_valid : _T_3732 ? _Queue10_UInt8_14_io_deq_valid : _T_3731 ? _Queue10_UInt8_13_io_deq_valid : _T_3730 ? _Queue10_UInt8_12_io_deq_valid : _T_3729 ? _Queue10_UInt8_11_io_deq_valid : _T_3728 ? _Queue10_UInt8_10_io_deq_valid : _T_3727 ? _Queue10_UInt8_9_io_deq_valid : _T_3726 ? _Queue10_UInt8_8_io_deq_valid : _T_3725 ? _Queue10_UInt8_7_io_deq_valid : _T_3724 ? _Queue10_UInt8_6_io_deq_valid : _T_3723 ? _Queue10_UInt8_5_io_deq_valid : _T_3722 ? _Queue10_UInt8_4_io_deq_valid : _T_3721 ? _Queue10_UInt8_3_io_deq_valid : _T_3720 ? _Queue10_UInt8_2_io_deq_valid : _T_3719 ? _Queue10_UInt8_1_io_deq_valid : _T_3718 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_15 = _remapindex_T + 7'hF; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_104 = _remapindex_T_15 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_15 = _GEN_104[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3750 = remapindex_15 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3751 = remapindex_15 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3752 = remapindex_15 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3753 = remapindex_15 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3754 = remapindex_15 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3755 = remapindex_15 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3756 = remapindex_15 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3757 = remapindex_15 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3758 = remapindex_15 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3759 = remapindex_15 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3760 = remapindex_15 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3761 = remapindex_15 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3762 = remapindex_15 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3763 = remapindex_15 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3764 = remapindex_15 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3765 = remapindex_15 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3766 = remapindex_15 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3767 = remapindex_15 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3768 = remapindex_15 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3769 = remapindex_15 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3770 = remapindex_15 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3771 = remapindex_15 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3772 = remapindex_15 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3773 = remapindex_15 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3774 = remapindex_15 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3775 = remapindex_15 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3776 = remapindex_15 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3777 = remapindex_15 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3778 = remapindex_15 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3779 = remapindex_15 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3780 = remapindex_15 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3781 = remapindex_15 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_15 = _T_3781 ? _Queue10_UInt8_31_io_deq_bits : _T_3780 ? _Queue10_UInt8_30_io_deq_bits : _T_3779 ? _Queue10_UInt8_29_io_deq_bits : _T_3778 ? _Queue10_UInt8_28_io_deq_bits : _T_3777 ? _Queue10_UInt8_27_io_deq_bits : _T_3776 ? _Queue10_UInt8_26_io_deq_bits : _T_3775 ? _Queue10_UInt8_25_io_deq_bits : _T_3774 ? _Queue10_UInt8_24_io_deq_bits : _T_3773 ? _Queue10_UInt8_23_io_deq_bits : _T_3772 ? _Queue10_UInt8_22_io_deq_bits : _T_3771 ? _Queue10_UInt8_21_io_deq_bits : _T_3770 ? _Queue10_UInt8_20_io_deq_bits : _T_3769 ? _Queue10_UInt8_19_io_deq_bits : _T_3768 ? _Queue10_UInt8_18_io_deq_bits : _T_3767 ? _Queue10_UInt8_17_io_deq_bits : _T_3766 ? _Queue10_UInt8_16_io_deq_bits : _T_3765 ? _Queue10_UInt8_15_io_deq_bits : _T_3764 ? _Queue10_UInt8_14_io_deq_bits : _T_3763 ? _Queue10_UInt8_13_io_deq_bits : _T_3762 ? _Queue10_UInt8_12_io_deq_bits : _T_3761 ? _Queue10_UInt8_11_io_deq_bits : _T_3760 ? _Queue10_UInt8_10_io_deq_bits : _T_3759 ? _Queue10_UInt8_9_io_deq_bits : _T_3758 ? _Queue10_UInt8_8_io_deq_bits : _T_3757 ? _Queue10_UInt8_7_io_deq_bits : _T_3756 ? _Queue10_UInt8_6_io_deq_bits : _T_3755 ? _Queue10_UInt8_5_io_deq_bits : _T_3754 ? _Queue10_UInt8_4_io_deq_bits : _T_3753 ? _Queue10_UInt8_3_io_deq_bits : _T_3752 ? _Queue10_UInt8_2_io_deq_bits : _T_3751 ? _Queue10_UInt8_1_io_deq_bits : _T_3750 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_15 = _T_3781 ? _Queue10_UInt8_31_io_deq_valid : _T_3780 ? _Queue10_UInt8_30_io_deq_valid : _T_3779 ? _Queue10_UInt8_29_io_deq_valid : _T_3778 ? _Queue10_UInt8_28_io_deq_valid : _T_3777 ? _Queue10_UInt8_27_io_deq_valid : _T_3776 ? _Queue10_UInt8_26_io_deq_valid : _T_3775 ? _Queue10_UInt8_25_io_deq_valid : _T_3774 ? _Queue10_UInt8_24_io_deq_valid : _T_3773 ? _Queue10_UInt8_23_io_deq_valid : _T_3772 ? _Queue10_UInt8_22_io_deq_valid : _T_3771 ? _Queue10_UInt8_21_io_deq_valid : _T_3770 ? _Queue10_UInt8_20_io_deq_valid : _T_3769 ? _Queue10_UInt8_19_io_deq_valid : _T_3768 ? _Queue10_UInt8_18_io_deq_valid : _T_3767 ? _Queue10_UInt8_17_io_deq_valid : _T_3766 ? _Queue10_UInt8_16_io_deq_valid : _T_3765 ? _Queue10_UInt8_15_io_deq_valid : _T_3764 ? _Queue10_UInt8_14_io_deq_valid : _T_3763 ? _Queue10_UInt8_13_io_deq_valid : _T_3762 ? _Queue10_UInt8_12_io_deq_valid : _T_3761 ? _Queue10_UInt8_11_io_deq_valid : _T_3760 ? _Queue10_UInt8_10_io_deq_valid : _T_3759 ? _Queue10_UInt8_9_io_deq_valid : _T_3758 ? _Queue10_UInt8_8_io_deq_valid : _T_3757 ? _Queue10_UInt8_7_io_deq_valid : _T_3756 ? _Queue10_UInt8_6_io_deq_valid : _T_3755 ? _Queue10_UInt8_5_io_deq_valid : _T_3754 ? _Queue10_UInt8_4_io_deq_valid : _T_3753 ? _Queue10_UInt8_3_io_deq_valid : _T_3752 ? _Queue10_UInt8_2_io_deq_valid : _T_3751 ? _Queue10_UInt8_1_io_deq_valid : _T_3750 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_16 = _remapindex_T + 7'h10; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_105 = _remapindex_T_16 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_16 = _GEN_105[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3782 = remapindex_16 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3783 = remapindex_16 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3784 = remapindex_16 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3785 = remapindex_16 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3786 = remapindex_16 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3787 = remapindex_16 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3788 = remapindex_16 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3789 = remapindex_16 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3790 = remapindex_16 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3791 = remapindex_16 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3792 = remapindex_16 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3793 = remapindex_16 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3794 = remapindex_16 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3795 = remapindex_16 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3796 = remapindex_16 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3797 = remapindex_16 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3798 = remapindex_16 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3799 = remapindex_16 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3800 = remapindex_16 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3801 = remapindex_16 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3802 = remapindex_16 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3803 = remapindex_16 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3804 = remapindex_16 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3805 = remapindex_16 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3806 = remapindex_16 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3807 = remapindex_16 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3808 = remapindex_16 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3809 = remapindex_16 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3810 = remapindex_16 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3811 = remapindex_16 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3812 = remapindex_16 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3813 = remapindex_16 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_16 = _T_3813 ? _Queue10_UInt8_31_io_deq_bits : _T_3812 ? _Queue10_UInt8_30_io_deq_bits : _T_3811 ? _Queue10_UInt8_29_io_deq_bits : _T_3810 ? _Queue10_UInt8_28_io_deq_bits : _T_3809 ? _Queue10_UInt8_27_io_deq_bits : _T_3808 ? _Queue10_UInt8_26_io_deq_bits : _T_3807 ? _Queue10_UInt8_25_io_deq_bits : _T_3806 ? _Queue10_UInt8_24_io_deq_bits : _T_3805 ? _Queue10_UInt8_23_io_deq_bits : _T_3804 ? _Queue10_UInt8_22_io_deq_bits : _T_3803 ? _Queue10_UInt8_21_io_deq_bits : _T_3802 ? _Queue10_UInt8_20_io_deq_bits : _T_3801 ? _Queue10_UInt8_19_io_deq_bits : _T_3800 ? _Queue10_UInt8_18_io_deq_bits : _T_3799 ? _Queue10_UInt8_17_io_deq_bits : _T_3798 ? _Queue10_UInt8_16_io_deq_bits : _T_3797 ? _Queue10_UInt8_15_io_deq_bits : _T_3796 ? _Queue10_UInt8_14_io_deq_bits : _T_3795 ? _Queue10_UInt8_13_io_deq_bits : _T_3794 ? _Queue10_UInt8_12_io_deq_bits : _T_3793 ? _Queue10_UInt8_11_io_deq_bits : _T_3792 ? _Queue10_UInt8_10_io_deq_bits : _T_3791 ? _Queue10_UInt8_9_io_deq_bits : _T_3790 ? _Queue10_UInt8_8_io_deq_bits : _T_3789 ? _Queue10_UInt8_7_io_deq_bits : _T_3788 ? _Queue10_UInt8_6_io_deq_bits : _T_3787 ? _Queue10_UInt8_5_io_deq_bits : _T_3786 ? _Queue10_UInt8_4_io_deq_bits : _T_3785 ? _Queue10_UInt8_3_io_deq_bits : _T_3784 ? _Queue10_UInt8_2_io_deq_bits : _T_3783 ? _Queue10_UInt8_1_io_deq_bits : _T_3782 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_16 = _T_3813 ? _Queue10_UInt8_31_io_deq_valid : _T_3812 ? _Queue10_UInt8_30_io_deq_valid : _T_3811 ? _Queue10_UInt8_29_io_deq_valid : _T_3810 ? _Queue10_UInt8_28_io_deq_valid : _T_3809 ? _Queue10_UInt8_27_io_deq_valid : _T_3808 ? _Queue10_UInt8_26_io_deq_valid : _T_3807 ? _Queue10_UInt8_25_io_deq_valid : _T_3806 ? _Queue10_UInt8_24_io_deq_valid : _T_3805 ? _Queue10_UInt8_23_io_deq_valid : _T_3804 ? _Queue10_UInt8_22_io_deq_valid : _T_3803 ? _Queue10_UInt8_21_io_deq_valid : _T_3802 ? _Queue10_UInt8_20_io_deq_valid : _T_3801 ? _Queue10_UInt8_19_io_deq_valid : _T_3800 ? _Queue10_UInt8_18_io_deq_valid : _T_3799 ? _Queue10_UInt8_17_io_deq_valid : _T_3798 ? _Queue10_UInt8_16_io_deq_valid : _T_3797 ? _Queue10_UInt8_15_io_deq_valid : _T_3796 ? _Queue10_UInt8_14_io_deq_valid : _T_3795 ? _Queue10_UInt8_13_io_deq_valid : _T_3794 ? _Queue10_UInt8_12_io_deq_valid : _T_3793 ? _Queue10_UInt8_11_io_deq_valid : _T_3792 ? _Queue10_UInt8_10_io_deq_valid : _T_3791 ? _Queue10_UInt8_9_io_deq_valid : _T_3790 ? _Queue10_UInt8_8_io_deq_valid : _T_3789 ? _Queue10_UInt8_7_io_deq_valid : _T_3788 ? _Queue10_UInt8_6_io_deq_valid : _T_3787 ? _Queue10_UInt8_5_io_deq_valid : _T_3786 ? _Queue10_UInt8_4_io_deq_valid : _T_3785 ? _Queue10_UInt8_3_io_deq_valid : _T_3784 ? _Queue10_UInt8_2_io_deq_valid : _T_3783 ? _Queue10_UInt8_1_io_deq_valid : _T_3782 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_17 = _remapindex_T + 7'h11; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_106 = _remapindex_T_17 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_17 = _GEN_106[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3814 = remapindex_17 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3815 = remapindex_17 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3816 = remapindex_17 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3817 = remapindex_17 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3818 = remapindex_17 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3819 = remapindex_17 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3820 = remapindex_17 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3821 = remapindex_17 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3822 = remapindex_17 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3823 = remapindex_17 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3824 = remapindex_17 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3825 = remapindex_17 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3826 = remapindex_17 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3827 = remapindex_17 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3828 = remapindex_17 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3829 = remapindex_17 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3830 = remapindex_17 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3831 = remapindex_17 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3832 = remapindex_17 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3833 = remapindex_17 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3834 = remapindex_17 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3835 = remapindex_17 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3836 = remapindex_17 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3837 = remapindex_17 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3838 = remapindex_17 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3839 = remapindex_17 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3840 = remapindex_17 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3841 = remapindex_17 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3842 = remapindex_17 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3843 = remapindex_17 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3844 = remapindex_17 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3845 = remapindex_17 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_17 = _T_3845 ? _Queue10_UInt8_31_io_deq_bits : _T_3844 ? _Queue10_UInt8_30_io_deq_bits : _T_3843 ? _Queue10_UInt8_29_io_deq_bits : _T_3842 ? _Queue10_UInt8_28_io_deq_bits : _T_3841 ? _Queue10_UInt8_27_io_deq_bits : _T_3840 ? _Queue10_UInt8_26_io_deq_bits : _T_3839 ? _Queue10_UInt8_25_io_deq_bits : _T_3838 ? _Queue10_UInt8_24_io_deq_bits : _T_3837 ? _Queue10_UInt8_23_io_deq_bits : _T_3836 ? _Queue10_UInt8_22_io_deq_bits : _T_3835 ? _Queue10_UInt8_21_io_deq_bits : _T_3834 ? _Queue10_UInt8_20_io_deq_bits : _T_3833 ? _Queue10_UInt8_19_io_deq_bits : _T_3832 ? _Queue10_UInt8_18_io_deq_bits : _T_3831 ? _Queue10_UInt8_17_io_deq_bits : _T_3830 ? _Queue10_UInt8_16_io_deq_bits : _T_3829 ? _Queue10_UInt8_15_io_deq_bits : _T_3828 ? _Queue10_UInt8_14_io_deq_bits : _T_3827 ? _Queue10_UInt8_13_io_deq_bits : _T_3826 ? _Queue10_UInt8_12_io_deq_bits : _T_3825 ? _Queue10_UInt8_11_io_deq_bits : _T_3824 ? _Queue10_UInt8_10_io_deq_bits : _T_3823 ? _Queue10_UInt8_9_io_deq_bits : _T_3822 ? _Queue10_UInt8_8_io_deq_bits : _T_3821 ? _Queue10_UInt8_7_io_deq_bits : _T_3820 ? _Queue10_UInt8_6_io_deq_bits : _T_3819 ? _Queue10_UInt8_5_io_deq_bits : _T_3818 ? _Queue10_UInt8_4_io_deq_bits : _T_3817 ? _Queue10_UInt8_3_io_deq_bits : _T_3816 ? _Queue10_UInt8_2_io_deq_bits : _T_3815 ? _Queue10_UInt8_1_io_deq_bits : _T_3814 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_17 = _T_3845 ? _Queue10_UInt8_31_io_deq_valid : _T_3844 ? _Queue10_UInt8_30_io_deq_valid : _T_3843 ? _Queue10_UInt8_29_io_deq_valid : _T_3842 ? _Queue10_UInt8_28_io_deq_valid : _T_3841 ? _Queue10_UInt8_27_io_deq_valid : _T_3840 ? _Queue10_UInt8_26_io_deq_valid : _T_3839 ? _Queue10_UInt8_25_io_deq_valid : _T_3838 ? _Queue10_UInt8_24_io_deq_valid : _T_3837 ? _Queue10_UInt8_23_io_deq_valid : _T_3836 ? _Queue10_UInt8_22_io_deq_valid : _T_3835 ? _Queue10_UInt8_21_io_deq_valid : _T_3834 ? _Queue10_UInt8_20_io_deq_valid : _T_3833 ? _Queue10_UInt8_19_io_deq_valid : _T_3832 ? _Queue10_UInt8_18_io_deq_valid : _T_3831 ? _Queue10_UInt8_17_io_deq_valid : _T_3830 ? _Queue10_UInt8_16_io_deq_valid : _T_3829 ? _Queue10_UInt8_15_io_deq_valid : _T_3828 ? _Queue10_UInt8_14_io_deq_valid : _T_3827 ? _Queue10_UInt8_13_io_deq_valid : _T_3826 ? _Queue10_UInt8_12_io_deq_valid : _T_3825 ? _Queue10_UInt8_11_io_deq_valid : _T_3824 ? _Queue10_UInt8_10_io_deq_valid : _T_3823 ? _Queue10_UInt8_9_io_deq_valid : _T_3822 ? _Queue10_UInt8_8_io_deq_valid : _T_3821 ? _Queue10_UInt8_7_io_deq_valid : _T_3820 ? _Queue10_UInt8_6_io_deq_valid : _T_3819 ? _Queue10_UInt8_5_io_deq_valid : _T_3818 ? _Queue10_UInt8_4_io_deq_valid : _T_3817 ? _Queue10_UInt8_3_io_deq_valid : _T_3816 ? _Queue10_UInt8_2_io_deq_valid : _T_3815 ? _Queue10_UInt8_1_io_deq_valid : _T_3814 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_18 = _remapindex_T + 7'h12; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_107 = _remapindex_T_18 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_18 = _GEN_107[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3846 = remapindex_18 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3847 = remapindex_18 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3848 = remapindex_18 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3849 = remapindex_18 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3850 = remapindex_18 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3851 = remapindex_18 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3852 = remapindex_18 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3853 = remapindex_18 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3854 = remapindex_18 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3855 = remapindex_18 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3856 = remapindex_18 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3857 = remapindex_18 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3858 = remapindex_18 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3859 = remapindex_18 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3860 = remapindex_18 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3861 = remapindex_18 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3862 = remapindex_18 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3863 = remapindex_18 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3864 = remapindex_18 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3865 = remapindex_18 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3866 = remapindex_18 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3867 = remapindex_18 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3868 = remapindex_18 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3869 = remapindex_18 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3870 = remapindex_18 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3871 = remapindex_18 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3872 = remapindex_18 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3873 = remapindex_18 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3874 = remapindex_18 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3875 = remapindex_18 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3876 = remapindex_18 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3877 = remapindex_18 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_18 = _T_3877 ? _Queue10_UInt8_31_io_deq_bits : _T_3876 ? _Queue10_UInt8_30_io_deq_bits : _T_3875 ? _Queue10_UInt8_29_io_deq_bits : _T_3874 ? _Queue10_UInt8_28_io_deq_bits : _T_3873 ? _Queue10_UInt8_27_io_deq_bits : _T_3872 ? _Queue10_UInt8_26_io_deq_bits : _T_3871 ? _Queue10_UInt8_25_io_deq_bits : _T_3870 ? _Queue10_UInt8_24_io_deq_bits : _T_3869 ? _Queue10_UInt8_23_io_deq_bits : _T_3868 ? _Queue10_UInt8_22_io_deq_bits : _T_3867 ? _Queue10_UInt8_21_io_deq_bits : _T_3866 ? _Queue10_UInt8_20_io_deq_bits : _T_3865 ? _Queue10_UInt8_19_io_deq_bits : _T_3864 ? _Queue10_UInt8_18_io_deq_bits : _T_3863 ? _Queue10_UInt8_17_io_deq_bits : _T_3862 ? _Queue10_UInt8_16_io_deq_bits : _T_3861 ? _Queue10_UInt8_15_io_deq_bits : _T_3860 ? _Queue10_UInt8_14_io_deq_bits : _T_3859 ? _Queue10_UInt8_13_io_deq_bits : _T_3858 ? _Queue10_UInt8_12_io_deq_bits : _T_3857 ? _Queue10_UInt8_11_io_deq_bits : _T_3856 ? _Queue10_UInt8_10_io_deq_bits : _T_3855 ? _Queue10_UInt8_9_io_deq_bits : _T_3854 ? _Queue10_UInt8_8_io_deq_bits : _T_3853 ? _Queue10_UInt8_7_io_deq_bits : _T_3852 ? _Queue10_UInt8_6_io_deq_bits : _T_3851 ? _Queue10_UInt8_5_io_deq_bits : _T_3850 ? _Queue10_UInt8_4_io_deq_bits : _T_3849 ? _Queue10_UInt8_3_io_deq_bits : _T_3848 ? _Queue10_UInt8_2_io_deq_bits : _T_3847 ? _Queue10_UInt8_1_io_deq_bits : _T_3846 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_18 = _T_3877 ? _Queue10_UInt8_31_io_deq_valid : _T_3876 ? _Queue10_UInt8_30_io_deq_valid : _T_3875 ? _Queue10_UInt8_29_io_deq_valid : _T_3874 ? _Queue10_UInt8_28_io_deq_valid : _T_3873 ? _Queue10_UInt8_27_io_deq_valid : _T_3872 ? _Queue10_UInt8_26_io_deq_valid : _T_3871 ? _Queue10_UInt8_25_io_deq_valid : _T_3870 ? _Queue10_UInt8_24_io_deq_valid : _T_3869 ? _Queue10_UInt8_23_io_deq_valid : _T_3868 ? _Queue10_UInt8_22_io_deq_valid : _T_3867 ? _Queue10_UInt8_21_io_deq_valid : _T_3866 ? _Queue10_UInt8_20_io_deq_valid : _T_3865 ? _Queue10_UInt8_19_io_deq_valid : _T_3864 ? _Queue10_UInt8_18_io_deq_valid : _T_3863 ? _Queue10_UInt8_17_io_deq_valid : _T_3862 ? _Queue10_UInt8_16_io_deq_valid : _T_3861 ? _Queue10_UInt8_15_io_deq_valid : _T_3860 ? _Queue10_UInt8_14_io_deq_valid : _T_3859 ? _Queue10_UInt8_13_io_deq_valid : _T_3858 ? _Queue10_UInt8_12_io_deq_valid : _T_3857 ? _Queue10_UInt8_11_io_deq_valid : _T_3856 ? _Queue10_UInt8_10_io_deq_valid : _T_3855 ? _Queue10_UInt8_9_io_deq_valid : _T_3854 ? _Queue10_UInt8_8_io_deq_valid : _T_3853 ? _Queue10_UInt8_7_io_deq_valid : _T_3852 ? _Queue10_UInt8_6_io_deq_valid : _T_3851 ? _Queue10_UInt8_5_io_deq_valid : _T_3850 ? _Queue10_UInt8_4_io_deq_valid : _T_3849 ? _Queue10_UInt8_3_io_deq_valid : _T_3848 ? _Queue10_UInt8_2_io_deq_valid : _T_3847 ? _Queue10_UInt8_1_io_deq_valid : _T_3846 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_19 = _remapindex_T + 7'h13; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_108 = _remapindex_T_19 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_19 = _GEN_108[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3878 = remapindex_19 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3879 = remapindex_19 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3880 = remapindex_19 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3881 = remapindex_19 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3882 = remapindex_19 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3883 = remapindex_19 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3884 = remapindex_19 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3885 = remapindex_19 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3886 = remapindex_19 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3887 = remapindex_19 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3888 = remapindex_19 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3889 = remapindex_19 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3890 = remapindex_19 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3891 = remapindex_19 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3892 = remapindex_19 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3893 = remapindex_19 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3894 = remapindex_19 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3895 = remapindex_19 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3896 = remapindex_19 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3897 = remapindex_19 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3898 = remapindex_19 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3899 = remapindex_19 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3900 = remapindex_19 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3901 = remapindex_19 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3902 = remapindex_19 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3903 = remapindex_19 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3904 = remapindex_19 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3905 = remapindex_19 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3906 = remapindex_19 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3907 = remapindex_19 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3908 = remapindex_19 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3909 = remapindex_19 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_19 = _T_3909 ? _Queue10_UInt8_31_io_deq_bits : _T_3908 ? _Queue10_UInt8_30_io_deq_bits : _T_3907 ? _Queue10_UInt8_29_io_deq_bits : _T_3906 ? _Queue10_UInt8_28_io_deq_bits : _T_3905 ? _Queue10_UInt8_27_io_deq_bits : _T_3904 ? _Queue10_UInt8_26_io_deq_bits : _T_3903 ? _Queue10_UInt8_25_io_deq_bits : _T_3902 ? _Queue10_UInt8_24_io_deq_bits : _T_3901 ? _Queue10_UInt8_23_io_deq_bits : _T_3900 ? _Queue10_UInt8_22_io_deq_bits : _T_3899 ? _Queue10_UInt8_21_io_deq_bits : _T_3898 ? _Queue10_UInt8_20_io_deq_bits : _T_3897 ? _Queue10_UInt8_19_io_deq_bits : _T_3896 ? _Queue10_UInt8_18_io_deq_bits : _T_3895 ? _Queue10_UInt8_17_io_deq_bits : _T_3894 ? _Queue10_UInt8_16_io_deq_bits : _T_3893 ? _Queue10_UInt8_15_io_deq_bits : _T_3892 ? _Queue10_UInt8_14_io_deq_bits : _T_3891 ? _Queue10_UInt8_13_io_deq_bits : _T_3890 ? _Queue10_UInt8_12_io_deq_bits : _T_3889 ? _Queue10_UInt8_11_io_deq_bits : _T_3888 ? _Queue10_UInt8_10_io_deq_bits : _T_3887 ? _Queue10_UInt8_9_io_deq_bits : _T_3886 ? _Queue10_UInt8_8_io_deq_bits : _T_3885 ? _Queue10_UInt8_7_io_deq_bits : _T_3884 ? _Queue10_UInt8_6_io_deq_bits : _T_3883 ? _Queue10_UInt8_5_io_deq_bits : _T_3882 ? _Queue10_UInt8_4_io_deq_bits : _T_3881 ? _Queue10_UInt8_3_io_deq_bits : _T_3880 ? _Queue10_UInt8_2_io_deq_bits : _T_3879 ? _Queue10_UInt8_1_io_deq_bits : _T_3878 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_19 = _T_3909 ? _Queue10_UInt8_31_io_deq_valid : _T_3908 ? _Queue10_UInt8_30_io_deq_valid : _T_3907 ? _Queue10_UInt8_29_io_deq_valid : _T_3906 ? _Queue10_UInt8_28_io_deq_valid : _T_3905 ? _Queue10_UInt8_27_io_deq_valid : _T_3904 ? _Queue10_UInt8_26_io_deq_valid : _T_3903 ? _Queue10_UInt8_25_io_deq_valid : _T_3902 ? _Queue10_UInt8_24_io_deq_valid : _T_3901 ? _Queue10_UInt8_23_io_deq_valid : _T_3900 ? _Queue10_UInt8_22_io_deq_valid : _T_3899 ? _Queue10_UInt8_21_io_deq_valid : _T_3898 ? _Queue10_UInt8_20_io_deq_valid : _T_3897 ? _Queue10_UInt8_19_io_deq_valid : _T_3896 ? _Queue10_UInt8_18_io_deq_valid : _T_3895 ? _Queue10_UInt8_17_io_deq_valid : _T_3894 ? _Queue10_UInt8_16_io_deq_valid : _T_3893 ? _Queue10_UInt8_15_io_deq_valid : _T_3892 ? _Queue10_UInt8_14_io_deq_valid : _T_3891 ? _Queue10_UInt8_13_io_deq_valid : _T_3890 ? _Queue10_UInt8_12_io_deq_valid : _T_3889 ? _Queue10_UInt8_11_io_deq_valid : _T_3888 ? _Queue10_UInt8_10_io_deq_valid : _T_3887 ? _Queue10_UInt8_9_io_deq_valid : _T_3886 ? _Queue10_UInt8_8_io_deq_valid : _T_3885 ? _Queue10_UInt8_7_io_deq_valid : _T_3884 ? _Queue10_UInt8_6_io_deq_valid : _T_3883 ? _Queue10_UInt8_5_io_deq_valid : _T_3882 ? _Queue10_UInt8_4_io_deq_valid : _T_3881 ? _Queue10_UInt8_3_io_deq_valid : _T_3880 ? _Queue10_UInt8_2_io_deq_valid : _T_3879 ? _Queue10_UInt8_1_io_deq_valid : _T_3878 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_20 = _remapindex_T + 7'h14; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_109 = _remapindex_T_20 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_20 = _GEN_109[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3910 = remapindex_20 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3911 = remapindex_20 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3912 = remapindex_20 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3913 = remapindex_20 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3914 = remapindex_20 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3915 = remapindex_20 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3916 = remapindex_20 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3917 = remapindex_20 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3918 = remapindex_20 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3919 = remapindex_20 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3920 = remapindex_20 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3921 = remapindex_20 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3922 = remapindex_20 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3923 = remapindex_20 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3924 = remapindex_20 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3925 = remapindex_20 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3926 = remapindex_20 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3927 = remapindex_20 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3928 = remapindex_20 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3929 = remapindex_20 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3930 = remapindex_20 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3931 = remapindex_20 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3932 = remapindex_20 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3933 = remapindex_20 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3934 = remapindex_20 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3935 = remapindex_20 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3936 = remapindex_20 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3937 = remapindex_20 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3938 = remapindex_20 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3939 = remapindex_20 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3940 = remapindex_20 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3941 = remapindex_20 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_20 = _T_3941 ? _Queue10_UInt8_31_io_deq_bits : _T_3940 ? _Queue10_UInt8_30_io_deq_bits : _T_3939 ? _Queue10_UInt8_29_io_deq_bits : _T_3938 ? _Queue10_UInt8_28_io_deq_bits : _T_3937 ? _Queue10_UInt8_27_io_deq_bits : _T_3936 ? _Queue10_UInt8_26_io_deq_bits : _T_3935 ? _Queue10_UInt8_25_io_deq_bits : _T_3934 ? _Queue10_UInt8_24_io_deq_bits : _T_3933 ? _Queue10_UInt8_23_io_deq_bits : _T_3932 ? _Queue10_UInt8_22_io_deq_bits : _T_3931 ? _Queue10_UInt8_21_io_deq_bits : _T_3930 ? _Queue10_UInt8_20_io_deq_bits : _T_3929 ? _Queue10_UInt8_19_io_deq_bits : _T_3928 ? _Queue10_UInt8_18_io_deq_bits : _T_3927 ? _Queue10_UInt8_17_io_deq_bits : _T_3926 ? _Queue10_UInt8_16_io_deq_bits : _T_3925 ? _Queue10_UInt8_15_io_deq_bits : _T_3924 ? _Queue10_UInt8_14_io_deq_bits : _T_3923 ? _Queue10_UInt8_13_io_deq_bits : _T_3922 ? _Queue10_UInt8_12_io_deq_bits : _T_3921 ? _Queue10_UInt8_11_io_deq_bits : _T_3920 ? _Queue10_UInt8_10_io_deq_bits : _T_3919 ? _Queue10_UInt8_9_io_deq_bits : _T_3918 ? _Queue10_UInt8_8_io_deq_bits : _T_3917 ? _Queue10_UInt8_7_io_deq_bits : _T_3916 ? _Queue10_UInt8_6_io_deq_bits : _T_3915 ? _Queue10_UInt8_5_io_deq_bits : _T_3914 ? _Queue10_UInt8_4_io_deq_bits : _T_3913 ? _Queue10_UInt8_3_io_deq_bits : _T_3912 ? _Queue10_UInt8_2_io_deq_bits : _T_3911 ? _Queue10_UInt8_1_io_deq_bits : _T_3910 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_20 = _T_3941 ? _Queue10_UInt8_31_io_deq_valid : _T_3940 ? _Queue10_UInt8_30_io_deq_valid : _T_3939 ? _Queue10_UInt8_29_io_deq_valid : _T_3938 ? _Queue10_UInt8_28_io_deq_valid : _T_3937 ? _Queue10_UInt8_27_io_deq_valid : _T_3936 ? _Queue10_UInt8_26_io_deq_valid : _T_3935 ? _Queue10_UInt8_25_io_deq_valid : _T_3934 ? _Queue10_UInt8_24_io_deq_valid : _T_3933 ? _Queue10_UInt8_23_io_deq_valid : _T_3932 ? _Queue10_UInt8_22_io_deq_valid : _T_3931 ? _Queue10_UInt8_21_io_deq_valid : _T_3930 ? _Queue10_UInt8_20_io_deq_valid : _T_3929 ? _Queue10_UInt8_19_io_deq_valid : _T_3928 ? _Queue10_UInt8_18_io_deq_valid : _T_3927 ? _Queue10_UInt8_17_io_deq_valid : _T_3926 ? _Queue10_UInt8_16_io_deq_valid : _T_3925 ? _Queue10_UInt8_15_io_deq_valid : _T_3924 ? _Queue10_UInt8_14_io_deq_valid : _T_3923 ? _Queue10_UInt8_13_io_deq_valid : _T_3922 ? _Queue10_UInt8_12_io_deq_valid : _T_3921 ? _Queue10_UInt8_11_io_deq_valid : _T_3920 ? _Queue10_UInt8_10_io_deq_valid : _T_3919 ? _Queue10_UInt8_9_io_deq_valid : _T_3918 ? _Queue10_UInt8_8_io_deq_valid : _T_3917 ? _Queue10_UInt8_7_io_deq_valid : _T_3916 ? _Queue10_UInt8_6_io_deq_valid : _T_3915 ? _Queue10_UInt8_5_io_deq_valid : _T_3914 ? _Queue10_UInt8_4_io_deq_valid : _T_3913 ? _Queue10_UInt8_3_io_deq_valid : _T_3912 ? _Queue10_UInt8_2_io_deq_valid : _T_3911 ? _Queue10_UInt8_1_io_deq_valid : _T_3910 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_21 = _remapindex_T + 7'h15; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_110 = _remapindex_T_21 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_21 = _GEN_110[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3942 = remapindex_21 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3943 = remapindex_21 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3944 = remapindex_21 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3945 = remapindex_21 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3946 = remapindex_21 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3947 = remapindex_21 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3948 = remapindex_21 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3949 = remapindex_21 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3950 = remapindex_21 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3951 = remapindex_21 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3952 = remapindex_21 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3953 = remapindex_21 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3954 = remapindex_21 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3955 = remapindex_21 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3956 = remapindex_21 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3957 = remapindex_21 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3958 = remapindex_21 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3959 = remapindex_21 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3960 = remapindex_21 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3961 = remapindex_21 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3962 = remapindex_21 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3963 = remapindex_21 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3964 = remapindex_21 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3965 = remapindex_21 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3966 = remapindex_21 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3967 = remapindex_21 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3968 = remapindex_21 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3969 = remapindex_21 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3970 = remapindex_21 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3971 = remapindex_21 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3972 = remapindex_21 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3973 = remapindex_21 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_21 = _T_3973 ? _Queue10_UInt8_31_io_deq_bits : _T_3972 ? _Queue10_UInt8_30_io_deq_bits : _T_3971 ? _Queue10_UInt8_29_io_deq_bits : _T_3970 ? _Queue10_UInt8_28_io_deq_bits : _T_3969 ? _Queue10_UInt8_27_io_deq_bits : _T_3968 ? _Queue10_UInt8_26_io_deq_bits : _T_3967 ? _Queue10_UInt8_25_io_deq_bits : _T_3966 ? _Queue10_UInt8_24_io_deq_bits : _T_3965 ? _Queue10_UInt8_23_io_deq_bits : _T_3964 ? _Queue10_UInt8_22_io_deq_bits : _T_3963 ? _Queue10_UInt8_21_io_deq_bits : _T_3962 ? _Queue10_UInt8_20_io_deq_bits : _T_3961 ? _Queue10_UInt8_19_io_deq_bits : _T_3960 ? _Queue10_UInt8_18_io_deq_bits : _T_3959 ? _Queue10_UInt8_17_io_deq_bits : _T_3958 ? _Queue10_UInt8_16_io_deq_bits : _T_3957 ? _Queue10_UInt8_15_io_deq_bits : _T_3956 ? _Queue10_UInt8_14_io_deq_bits : _T_3955 ? _Queue10_UInt8_13_io_deq_bits : _T_3954 ? _Queue10_UInt8_12_io_deq_bits : _T_3953 ? _Queue10_UInt8_11_io_deq_bits : _T_3952 ? _Queue10_UInt8_10_io_deq_bits : _T_3951 ? _Queue10_UInt8_9_io_deq_bits : _T_3950 ? _Queue10_UInt8_8_io_deq_bits : _T_3949 ? _Queue10_UInt8_7_io_deq_bits : _T_3948 ? _Queue10_UInt8_6_io_deq_bits : _T_3947 ? _Queue10_UInt8_5_io_deq_bits : _T_3946 ? _Queue10_UInt8_4_io_deq_bits : _T_3945 ? _Queue10_UInt8_3_io_deq_bits : _T_3944 ? _Queue10_UInt8_2_io_deq_bits : _T_3943 ? _Queue10_UInt8_1_io_deq_bits : _T_3942 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_21 = _T_3973 ? _Queue10_UInt8_31_io_deq_valid : _T_3972 ? _Queue10_UInt8_30_io_deq_valid : _T_3971 ? _Queue10_UInt8_29_io_deq_valid : _T_3970 ? _Queue10_UInt8_28_io_deq_valid : _T_3969 ? _Queue10_UInt8_27_io_deq_valid : _T_3968 ? _Queue10_UInt8_26_io_deq_valid : _T_3967 ? _Queue10_UInt8_25_io_deq_valid : _T_3966 ? _Queue10_UInt8_24_io_deq_valid : _T_3965 ? _Queue10_UInt8_23_io_deq_valid : _T_3964 ? _Queue10_UInt8_22_io_deq_valid : _T_3963 ? _Queue10_UInt8_21_io_deq_valid : _T_3962 ? _Queue10_UInt8_20_io_deq_valid : _T_3961 ? _Queue10_UInt8_19_io_deq_valid : _T_3960 ? _Queue10_UInt8_18_io_deq_valid : _T_3959 ? _Queue10_UInt8_17_io_deq_valid : _T_3958 ? _Queue10_UInt8_16_io_deq_valid : _T_3957 ? _Queue10_UInt8_15_io_deq_valid : _T_3956 ? _Queue10_UInt8_14_io_deq_valid : _T_3955 ? _Queue10_UInt8_13_io_deq_valid : _T_3954 ? _Queue10_UInt8_12_io_deq_valid : _T_3953 ? _Queue10_UInt8_11_io_deq_valid : _T_3952 ? _Queue10_UInt8_10_io_deq_valid : _T_3951 ? _Queue10_UInt8_9_io_deq_valid : _T_3950 ? _Queue10_UInt8_8_io_deq_valid : _T_3949 ? _Queue10_UInt8_7_io_deq_valid : _T_3948 ? _Queue10_UInt8_6_io_deq_valid : _T_3947 ? _Queue10_UInt8_5_io_deq_valid : _T_3946 ? _Queue10_UInt8_4_io_deq_valid : _T_3945 ? _Queue10_UInt8_3_io_deq_valid : _T_3944 ? _Queue10_UInt8_2_io_deq_valid : _T_3943 ? _Queue10_UInt8_1_io_deq_valid : _T_3942 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_22 = _remapindex_T + 7'h16; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_111 = _remapindex_T_22 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_22 = _GEN_111[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3974 = remapindex_22 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3975 = remapindex_22 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3976 = remapindex_22 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3977 = remapindex_22 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3978 = remapindex_22 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3979 = remapindex_22 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3980 = remapindex_22 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3981 = remapindex_22 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3982 = remapindex_22 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3983 = remapindex_22 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3984 = remapindex_22 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3985 = remapindex_22 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3986 = remapindex_22 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3987 = remapindex_22 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3988 = remapindex_22 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3989 = remapindex_22 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3990 = remapindex_22 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3991 = remapindex_22 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3992 = remapindex_22 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3993 = remapindex_22 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3994 = remapindex_22 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3995 = remapindex_22 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3996 = remapindex_22 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3997 = remapindex_22 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3998 = remapindex_22 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3999 = remapindex_22 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4000 = remapindex_22 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4001 = remapindex_22 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4002 = remapindex_22 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4003 = remapindex_22 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4004 = remapindex_22 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4005 = remapindex_22 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_22 = _T_4005 ? _Queue10_UInt8_31_io_deq_bits : _T_4004 ? _Queue10_UInt8_30_io_deq_bits : _T_4003 ? _Queue10_UInt8_29_io_deq_bits : _T_4002 ? _Queue10_UInt8_28_io_deq_bits : _T_4001 ? _Queue10_UInt8_27_io_deq_bits : _T_4000 ? _Queue10_UInt8_26_io_deq_bits : _T_3999 ? _Queue10_UInt8_25_io_deq_bits : _T_3998 ? _Queue10_UInt8_24_io_deq_bits : _T_3997 ? _Queue10_UInt8_23_io_deq_bits : _T_3996 ? _Queue10_UInt8_22_io_deq_bits : _T_3995 ? _Queue10_UInt8_21_io_deq_bits : _T_3994 ? _Queue10_UInt8_20_io_deq_bits : _T_3993 ? _Queue10_UInt8_19_io_deq_bits : _T_3992 ? _Queue10_UInt8_18_io_deq_bits : _T_3991 ? _Queue10_UInt8_17_io_deq_bits : _T_3990 ? _Queue10_UInt8_16_io_deq_bits : _T_3989 ? _Queue10_UInt8_15_io_deq_bits : _T_3988 ? _Queue10_UInt8_14_io_deq_bits : _T_3987 ? _Queue10_UInt8_13_io_deq_bits : _T_3986 ? _Queue10_UInt8_12_io_deq_bits : _T_3985 ? _Queue10_UInt8_11_io_deq_bits : _T_3984 ? _Queue10_UInt8_10_io_deq_bits : _T_3983 ? _Queue10_UInt8_9_io_deq_bits : _T_3982 ? _Queue10_UInt8_8_io_deq_bits : _T_3981 ? _Queue10_UInt8_7_io_deq_bits : _T_3980 ? _Queue10_UInt8_6_io_deq_bits : _T_3979 ? _Queue10_UInt8_5_io_deq_bits : _T_3978 ? _Queue10_UInt8_4_io_deq_bits : _T_3977 ? _Queue10_UInt8_3_io_deq_bits : _T_3976 ? _Queue10_UInt8_2_io_deq_bits : _T_3975 ? _Queue10_UInt8_1_io_deq_bits : _T_3974 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_22 = _T_4005 ? _Queue10_UInt8_31_io_deq_valid : _T_4004 ? _Queue10_UInt8_30_io_deq_valid : _T_4003 ? _Queue10_UInt8_29_io_deq_valid : _T_4002 ? _Queue10_UInt8_28_io_deq_valid : _T_4001 ? _Queue10_UInt8_27_io_deq_valid : _T_4000 ? _Queue10_UInt8_26_io_deq_valid : _T_3999 ? _Queue10_UInt8_25_io_deq_valid : _T_3998 ? _Queue10_UInt8_24_io_deq_valid : _T_3997 ? _Queue10_UInt8_23_io_deq_valid : _T_3996 ? _Queue10_UInt8_22_io_deq_valid : _T_3995 ? _Queue10_UInt8_21_io_deq_valid : _T_3994 ? _Queue10_UInt8_20_io_deq_valid : _T_3993 ? _Queue10_UInt8_19_io_deq_valid : _T_3992 ? _Queue10_UInt8_18_io_deq_valid : _T_3991 ? _Queue10_UInt8_17_io_deq_valid : _T_3990 ? _Queue10_UInt8_16_io_deq_valid : _T_3989 ? _Queue10_UInt8_15_io_deq_valid : _T_3988 ? _Queue10_UInt8_14_io_deq_valid : _T_3987 ? _Queue10_UInt8_13_io_deq_valid : _T_3986 ? _Queue10_UInt8_12_io_deq_valid : _T_3985 ? _Queue10_UInt8_11_io_deq_valid : _T_3984 ? _Queue10_UInt8_10_io_deq_valid : _T_3983 ? _Queue10_UInt8_9_io_deq_valid : _T_3982 ? _Queue10_UInt8_8_io_deq_valid : _T_3981 ? _Queue10_UInt8_7_io_deq_valid : _T_3980 ? _Queue10_UInt8_6_io_deq_valid : _T_3979 ? _Queue10_UInt8_5_io_deq_valid : _T_3978 ? _Queue10_UInt8_4_io_deq_valid : _T_3977 ? _Queue10_UInt8_3_io_deq_valid : _T_3976 ? _Queue10_UInt8_2_io_deq_valid : _T_3975 ? _Queue10_UInt8_1_io_deq_valid : _T_3974 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_23 = _remapindex_T + 7'h17; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_112 = _remapindex_T_23 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_23 = _GEN_112[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_4006 = remapindex_23 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4007 = remapindex_23 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4008 = remapindex_23 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4009 = remapindex_23 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4010 = remapindex_23 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4011 = remapindex_23 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4012 = remapindex_23 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4013 = remapindex_23 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4014 = remapindex_23 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4015 = remapindex_23 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4016 = remapindex_23 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4017 = remapindex_23 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4018 = remapindex_23 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4019 = remapindex_23 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4020 = remapindex_23 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4021 = remapindex_23 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4022 = remapindex_23 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4023 = remapindex_23 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4024 = remapindex_23 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4025 = remapindex_23 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4026 = remapindex_23 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4027 = remapindex_23 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4028 = remapindex_23 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4029 = remapindex_23 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4030 = remapindex_23 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4031 = remapindex_23 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4032 = remapindex_23 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4033 = remapindex_23 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4034 = remapindex_23 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4035 = remapindex_23 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4036 = remapindex_23 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4037 = remapindex_23 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_23 = _T_4037 ? _Queue10_UInt8_31_io_deq_bits : _T_4036 ? _Queue10_UInt8_30_io_deq_bits : _T_4035 ? _Queue10_UInt8_29_io_deq_bits : _T_4034 ? _Queue10_UInt8_28_io_deq_bits : _T_4033 ? _Queue10_UInt8_27_io_deq_bits : _T_4032 ? _Queue10_UInt8_26_io_deq_bits : _T_4031 ? _Queue10_UInt8_25_io_deq_bits : _T_4030 ? _Queue10_UInt8_24_io_deq_bits : _T_4029 ? _Queue10_UInt8_23_io_deq_bits : _T_4028 ? _Queue10_UInt8_22_io_deq_bits : _T_4027 ? _Queue10_UInt8_21_io_deq_bits : _T_4026 ? _Queue10_UInt8_20_io_deq_bits : _T_4025 ? _Queue10_UInt8_19_io_deq_bits : _T_4024 ? _Queue10_UInt8_18_io_deq_bits : _T_4023 ? _Queue10_UInt8_17_io_deq_bits : _T_4022 ? _Queue10_UInt8_16_io_deq_bits : _T_4021 ? _Queue10_UInt8_15_io_deq_bits : _T_4020 ? _Queue10_UInt8_14_io_deq_bits : _T_4019 ? _Queue10_UInt8_13_io_deq_bits : _T_4018 ? _Queue10_UInt8_12_io_deq_bits : _T_4017 ? _Queue10_UInt8_11_io_deq_bits : _T_4016 ? _Queue10_UInt8_10_io_deq_bits : _T_4015 ? _Queue10_UInt8_9_io_deq_bits : _T_4014 ? _Queue10_UInt8_8_io_deq_bits : _T_4013 ? _Queue10_UInt8_7_io_deq_bits : _T_4012 ? _Queue10_UInt8_6_io_deq_bits : _T_4011 ? _Queue10_UInt8_5_io_deq_bits : _T_4010 ? _Queue10_UInt8_4_io_deq_bits : _T_4009 ? _Queue10_UInt8_3_io_deq_bits : _T_4008 ? _Queue10_UInt8_2_io_deq_bits : _T_4007 ? _Queue10_UInt8_1_io_deq_bits : _T_4006 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_23 = _T_4037 ? _Queue10_UInt8_31_io_deq_valid : _T_4036 ? _Queue10_UInt8_30_io_deq_valid : _T_4035 ? _Queue10_UInt8_29_io_deq_valid : _T_4034 ? _Queue10_UInt8_28_io_deq_valid : _T_4033 ? _Queue10_UInt8_27_io_deq_valid : _T_4032 ? _Queue10_UInt8_26_io_deq_valid : _T_4031 ? _Queue10_UInt8_25_io_deq_valid : _T_4030 ? _Queue10_UInt8_24_io_deq_valid : _T_4029 ? _Queue10_UInt8_23_io_deq_valid : _T_4028 ? _Queue10_UInt8_22_io_deq_valid : _T_4027 ? _Queue10_UInt8_21_io_deq_valid : _T_4026 ? _Queue10_UInt8_20_io_deq_valid : _T_4025 ? _Queue10_UInt8_19_io_deq_valid : _T_4024 ? _Queue10_UInt8_18_io_deq_valid : _T_4023 ? _Queue10_UInt8_17_io_deq_valid : _T_4022 ? _Queue10_UInt8_16_io_deq_valid : _T_4021 ? _Queue10_UInt8_15_io_deq_valid : _T_4020 ? _Queue10_UInt8_14_io_deq_valid : _T_4019 ? _Queue10_UInt8_13_io_deq_valid : _T_4018 ? _Queue10_UInt8_12_io_deq_valid : _T_4017 ? _Queue10_UInt8_11_io_deq_valid : _T_4016 ? _Queue10_UInt8_10_io_deq_valid : _T_4015 ? _Queue10_UInt8_9_io_deq_valid : _T_4014 ? _Queue10_UInt8_8_io_deq_valid : _T_4013 ? _Queue10_UInt8_7_io_deq_valid : _T_4012 ? _Queue10_UInt8_6_io_deq_valid : _T_4011 ? _Queue10_UInt8_5_io_deq_valid : _T_4010 ? _Queue10_UInt8_4_io_deq_valid : _T_4009 ? _Queue10_UInt8_3_io_deq_valid : _T_4008 ? _Queue10_UInt8_2_io_deq_valid : _T_4007 ? _Queue10_UInt8_1_io_deq_valid : _T_4006 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_24 = _remapindex_T + 7'h18; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_113 = _remapindex_T_24 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_24 = _GEN_113[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_4038 = remapindex_24 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4039 = remapindex_24 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4040 = remapindex_24 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4041 = remapindex_24 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4042 = remapindex_24 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4043 = remapindex_24 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4044 = remapindex_24 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4045 = remapindex_24 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4046 = remapindex_24 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4047 = remapindex_24 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4048 = remapindex_24 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4049 = remapindex_24 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4050 = remapindex_24 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4051 = remapindex_24 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4052 = remapindex_24 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4053 = remapindex_24 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4054 = remapindex_24 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4055 = remapindex_24 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4056 = remapindex_24 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4057 = remapindex_24 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4058 = remapindex_24 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4059 = remapindex_24 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4060 = remapindex_24 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4061 = remapindex_24 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4062 = remapindex_24 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4063 = remapindex_24 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4064 = remapindex_24 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4065 = remapindex_24 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4066 = remapindex_24 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4067 = remapindex_24 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4068 = remapindex_24 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4069 = remapindex_24 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_24 = _T_4069 ? _Queue10_UInt8_31_io_deq_bits : _T_4068 ? _Queue10_UInt8_30_io_deq_bits : _T_4067 ? _Queue10_UInt8_29_io_deq_bits : _T_4066 ? _Queue10_UInt8_28_io_deq_bits : _T_4065 ? _Queue10_UInt8_27_io_deq_bits : _T_4064 ? _Queue10_UInt8_26_io_deq_bits : _T_4063 ? _Queue10_UInt8_25_io_deq_bits : _T_4062 ? _Queue10_UInt8_24_io_deq_bits : _T_4061 ? _Queue10_UInt8_23_io_deq_bits : _T_4060 ? _Queue10_UInt8_22_io_deq_bits : _T_4059 ? _Queue10_UInt8_21_io_deq_bits : _T_4058 ? _Queue10_UInt8_20_io_deq_bits : _T_4057 ? _Queue10_UInt8_19_io_deq_bits : _T_4056 ? _Queue10_UInt8_18_io_deq_bits : _T_4055 ? _Queue10_UInt8_17_io_deq_bits : _T_4054 ? _Queue10_UInt8_16_io_deq_bits : _T_4053 ? _Queue10_UInt8_15_io_deq_bits : _T_4052 ? _Queue10_UInt8_14_io_deq_bits : _T_4051 ? _Queue10_UInt8_13_io_deq_bits : _T_4050 ? _Queue10_UInt8_12_io_deq_bits : _T_4049 ? _Queue10_UInt8_11_io_deq_bits : _T_4048 ? _Queue10_UInt8_10_io_deq_bits : _T_4047 ? _Queue10_UInt8_9_io_deq_bits : _T_4046 ? _Queue10_UInt8_8_io_deq_bits : _T_4045 ? _Queue10_UInt8_7_io_deq_bits : _T_4044 ? _Queue10_UInt8_6_io_deq_bits : _T_4043 ? _Queue10_UInt8_5_io_deq_bits : _T_4042 ? _Queue10_UInt8_4_io_deq_bits : _T_4041 ? _Queue10_UInt8_3_io_deq_bits : _T_4040 ? _Queue10_UInt8_2_io_deq_bits : _T_4039 ? _Queue10_UInt8_1_io_deq_bits : _T_4038 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_24 = _T_4069 ? _Queue10_UInt8_31_io_deq_valid : _T_4068 ? _Queue10_UInt8_30_io_deq_valid : _T_4067 ? _Queue10_UInt8_29_io_deq_valid : _T_4066 ? _Queue10_UInt8_28_io_deq_valid : _T_4065 ? _Queue10_UInt8_27_io_deq_valid : _T_4064 ? _Queue10_UInt8_26_io_deq_valid : _T_4063 ? _Queue10_UInt8_25_io_deq_valid : _T_4062 ? _Queue10_UInt8_24_io_deq_valid : _T_4061 ? _Queue10_UInt8_23_io_deq_valid : _T_4060 ? _Queue10_UInt8_22_io_deq_valid : _T_4059 ? _Queue10_UInt8_21_io_deq_valid : _T_4058 ? _Queue10_UInt8_20_io_deq_valid : _T_4057 ? _Queue10_UInt8_19_io_deq_valid : _T_4056 ? _Queue10_UInt8_18_io_deq_valid : _T_4055 ? _Queue10_UInt8_17_io_deq_valid : _T_4054 ? _Queue10_UInt8_16_io_deq_valid : _T_4053 ? _Queue10_UInt8_15_io_deq_valid : _T_4052 ? _Queue10_UInt8_14_io_deq_valid : _T_4051 ? _Queue10_UInt8_13_io_deq_valid : _T_4050 ? _Queue10_UInt8_12_io_deq_valid : _T_4049 ? _Queue10_UInt8_11_io_deq_valid : _T_4048 ? _Queue10_UInt8_10_io_deq_valid : _T_4047 ? _Queue10_UInt8_9_io_deq_valid : _T_4046 ? _Queue10_UInt8_8_io_deq_valid : _T_4045 ? _Queue10_UInt8_7_io_deq_valid : _T_4044 ? _Queue10_UInt8_6_io_deq_valid : _T_4043 ? _Queue10_UInt8_5_io_deq_valid : _T_4042 ? _Queue10_UInt8_4_io_deq_valid : _T_4041 ? _Queue10_UInt8_3_io_deq_valid : _T_4040 ? _Queue10_UInt8_2_io_deq_valid : _T_4039 ? _Queue10_UInt8_1_io_deq_valid : _T_4038 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_25 = _remapindex_T + 7'h19; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_114 = _remapindex_T_25 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_25 = _GEN_114[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_4070 = remapindex_25 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4071 = remapindex_25 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4072 = remapindex_25 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4073 = remapindex_25 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4074 = remapindex_25 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4075 = remapindex_25 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4076 = remapindex_25 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4077 = remapindex_25 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4078 = remapindex_25 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4079 = remapindex_25 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4080 = remapindex_25 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4081 = remapindex_25 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4082 = remapindex_25 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4083 = remapindex_25 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4084 = remapindex_25 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4085 = remapindex_25 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4086 = remapindex_25 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4087 = remapindex_25 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4088 = remapindex_25 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4089 = remapindex_25 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4090 = remapindex_25 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4091 = remapindex_25 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4092 = remapindex_25 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4093 = remapindex_25 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4094 = remapindex_25 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4095 = remapindex_25 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4096 = remapindex_25 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4097 = remapindex_25 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4098 = remapindex_25 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4099 = remapindex_25 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4100 = remapindex_25 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4101 = remapindex_25 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_25 = _T_4101 ? _Queue10_UInt8_31_io_deq_bits : _T_4100 ? _Queue10_UInt8_30_io_deq_bits : _T_4099 ? _Queue10_UInt8_29_io_deq_bits : _T_4098 ? _Queue10_UInt8_28_io_deq_bits : _T_4097 ? _Queue10_UInt8_27_io_deq_bits : _T_4096 ? _Queue10_UInt8_26_io_deq_bits : _T_4095 ? _Queue10_UInt8_25_io_deq_bits : _T_4094 ? _Queue10_UInt8_24_io_deq_bits : _T_4093 ? _Queue10_UInt8_23_io_deq_bits : _T_4092 ? _Queue10_UInt8_22_io_deq_bits : _T_4091 ? _Queue10_UInt8_21_io_deq_bits : _T_4090 ? _Queue10_UInt8_20_io_deq_bits : _T_4089 ? _Queue10_UInt8_19_io_deq_bits : _T_4088 ? _Queue10_UInt8_18_io_deq_bits : _T_4087 ? _Queue10_UInt8_17_io_deq_bits : _T_4086 ? _Queue10_UInt8_16_io_deq_bits : _T_4085 ? _Queue10_UInt8_15_io_deq_bits : _T_4084 ? _Queue10_UInt8_14_io_deq_bits : _T_4083 ? _Queue10_UInt8_13_io_deq_bits : _T_4082 ? _Queue10_UInt8_12_io_deq_bits : _T_4081 ? _Queue10_UInt8_11_io_deq_bits : _T_4080 ? _Queue10_UInt8_10_io_deq_bits : _T_4079 ? _Queue10_UInt8_9_io_deq_bits : _T_4078 ? _Queue10_UInt8_8_io_deq_bits : _T_4077 ? _Queue10_UInt8_7_io_deq_bits : _T_4076 ? _Queue10_UInt8_6_io_deq_bits : _T_4075 ? _Queue10_UInt8_5_io_deq_bits : _T_4074 ? _Queue10_UInt8_4_io_deq_bits : _T_4073 ? _Queue10_UInt8_3_io_deq_bits : _T_4072 ? _Queue10_UInt8_2_io_deq_bits : _T_4071 ? _Queue10_UInt8_1_io_deq_bits : _T_4070 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_25 = _T_4101 ? _Queue10_UInt8_31_io_deq_valid : _T_4100 ? _Queue10_UInt8_30_io_deq_valid : _T_4099 ? _Queue10_UInt8_29_io_deq_valid : _T_4098 ? _Queue10_UInt8_28_io_deq_valid : _T_4097 ? _Queue10_UInt8_27_io_deq_valid : _T_4096 ? _Queue10_UInt8_26_io_deq_valid : _T_4095 ? _Queue10_UInt8_25_io_deq_valid : _T_4094 ? _Queue10_UInt8_24_io_deq_valid : _T_4093 ? _Queue10_UInt8_23_io_deq_valid : _T_4092 ? _Queue10_UInt8_22_io_deq_valid : _T_4091 ? _Queue10_UInt8_21_io_deq_valid : _T_4090 ? _Queue10_UInt8_20_io_deq_valid : _T_4089 ? _Queue10_UInt8_19_io_deq_valid : _T_4088 ? _Queue10_UInt8_18_io_deq_valid : _T_4087 ? _Queue10_UInt8_17_io_deq_valid : _T_4086 ? _Queue10_UInt8_16_io_deq_valid : _T_4085 ? _Queue10_UInt8_15_io_deq_valid : _T_4084 ? _Queue10_UInt8_14_io_deq_valid : _T_4083 ? _Queue10_UInt8_13_io_deq_valid : _T_4082 ? _Queue10_UInt8_12_io_deq_valid : _T_4081 ? _Queue10_UInt8_11_io_deq_valid : _T_4080 ? _Queue10_UInt8_10_io_deq_valid : _T_4079 ? _Queue10_UInt8_9_io_deq_valid : _T_4078 ? _Queue10_UInt8_8_io_deq_valid : _T_4077 ? _Queue10_UInt8_7_io_deq_valid : _T_4076 ? _Queue10_UInt8_6_io_deq_valid : _T_4075 ? _Queue10_UInt8_5_io_deq_valid : _T_4074 ? _Queue10_UInt8_4_io_deq_valid : _T_4073 ? _Queue10_UInt8_3_io_deq_valid : _T_4072 ? _Queue10_UInt8_2_io_deq_valid : _T_4071 ? _Queue10_UInt8_1_io_deq_valid : _T_4070 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_26 = _remapindex_T + 7'h1A; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_115 = _remapindex_T_26 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_26 = _GEN_115[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_4102 = remapindex_26 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4103 = remapindex_26 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4104 = remapindex_26 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4105 = remapindex_26 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4106 = remapindex_26 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4107 = remapindex_26 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4108 = remapindex_26 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4109 = remapindex_26 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4110 = remapindex_26 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4111 = remapindex_26 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4112 = remapindex_26 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4113 = remapindex_26 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4114 = remapindex_26 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4115 = remapindex_26 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4116 = remapindex_26 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4117 = remapindex_26 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4118 = remapindex_26 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4119 = remapindex_26 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4120 = remapindex_26 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4121 = remapindex_26 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4122 = remapindex_26 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4123 = remapindex_26 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4124 = remapindex_26 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4125 = remapindex_26 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4126 = remapindex_26 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4127 = remapindex_26 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4128 = remapindex_26 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4129 = remapindex_26 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4130 = remapindex_26 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4131 = remapindex_26 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4132 = remapindex_26 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4133 = remapindex_26 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_26 = _T_4133 ? _Queue10_UInt8_31_io_deq_bits : _T_4132 ? _Queue10_UInt8_30_io_deq_bits : _T_4131 ? _Queue10_UInt8_29_io_deq_bits : _T_4130 ? _Queue10_UInt8_28_io_deq_bits : _T_4129 ? _Queue10_UInt8_27_io_deq_bits : _T_4128 ? _Queue10_UInt8_26_io_deq_bits : _T_4127 ? _Queue10_UInt8_25_io_deq_bits : _T_4126 ? _Queue10_UInt8_24_io_deq_bits : _T_4125 ? _Queue10_UInt8_23_io_deq_bits : _T_4124 ? _Queue10_UInt8_22_io_deq_bits : _T_4123 ? _Queue10_UInt8_21_io_deq_bits : _T_4122 ? _Queue10_UInt8_20_io_deq_bits : _T_4121 ? _Queue10_UInt8_19_io_deq_bits : _T_4120 ? _Queue10_UInt8_18_io_deq_bits : _T_4119 ? _Queue10_UInt8_17_io_deq_bits : _T_4118 ? _Queue10_UInt8_16_io_deq_bits : _T_4117 ? _Queue10_UInt8_15_io_deq_bits : _T_4116 ? _Queue10_UInt8_14_io_deq_bits : _T_4115 ? _Queue10_UInt8_13_io_deq_bits : _T_4114 ? _Queue10_UInt8_12_io_deq_bits : _T_4113 ? _Queue10_UInt8_11_io_deq_bits : _T_4112 ? _Queue10_UInt8_10_io_deq_bits : _T_4111 ? _Queue10_UInt8_9_io_deq_bits : _T_4110 ? _Queue10_UInt8_8_io_deq_bits : _T_4109 ? _Queue10_UInt8_7_io_deq_bits : _T_4108 ? _Queue10_UInt8_6_io_deq_bits : _T_4107 ? _Queue10_UInt8_5_io_deq_bits : _T_4106 ? _Queue10_UInt8_4_io_deq_bits : _T_4105 ? _Queue10_UInt8_3_io_deq_bits : _T_4104 ? _Queue10_UInt8_2_io_deq_bits : _T_4103 ? _Queue10_UInt8_1_io_deq_bits : _T_4102 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_26 = _T_4133 ? _Queue10_UInt8_31_io_deq_valid : _T_4132 ? _Queue10_UInt8_30_io_deq_valid : _T_4131 ? _Queue10_UInt8_29_io_deq_valid : _T_4130 ? _Queue10_UInt8_28_io_deq_valid : _T_4129 ? _Queue10_UInt8_27_io_deq_valid : _T_4128 ? _Queue10_UInt8_26_io_deq_valid : _T_4127 ? _Queue10_UInt8_25_io_deq_valid : _T_4126 ? _Queue10_UInt8_24_io_deq_valid : _T_4125 ? _Queue10_UInt8_23_io_deq_valid : _T_4124 ? _Queue10_UInt8_22_io_deq_valid : _T_4123 ? _Queue10_UInt8_21_io_deq_valid : _T_4122 ? _Queue10_UInt8_20_io_deq_valid : _T_4121 ? _Queue10_UInt8_19_io_deq_valid : _T_4120 ? _Queue10_UInt8_18_io_deq_valid : _T_4119 ? _Queue10_UInt8_17_io_deq_valid : _T_4118 ? _Queue10_UInt8_16_io_deq_valid : _T_4117 ? _Queue10_UInt8_15_io_deq_valid : _T_4116 ? _Queue10_UInt8_14_io_deq_valid : _T_4115 ? _Queue10_UInt8_13_io_deq_valid : _T_4114 ? _Queue10_UInt8_12_io_deq_valid : _T_4113 ? _Queue10_UInt8_11_io_deq_valid : _T_4112 ? _Queue10_UInt8_10_io_deq_valid : _T_4111 ? _Queue10_UInt8_9_io_deq_valid : _T_4110 ? _Queue10_UInt8_8_io_deq_valid : _T_4109 ? _Queue10_UInt8_7_io_deq_valid : _T_4108 ? _Queue10_UInt8_6_io_deq_valid : _T_4107 ? _Queue10_UInt8_5_io_deq_valid : _T_4106 ? _Queue10_UInt8_4_io_deq_valid : _T_4105 ? _Queue10_UInt8_3_io_deq_valid : _T_4104 ? _Queue10_UInt8_2_io_deq_valid : _T_4103 ? _Queue10_UInt8_1_io_deq_valid : _T_4102 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_27 = _remapindex_T + 7'h1B; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_116 = _remapindex_T_27 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_27 = _GEN_116[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_4134 = remapindex_27 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4135 = remapindex_27 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4136 = remapindex_27 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4137 = remapindex_27 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4138 = remapindex_27 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4139 = remapindex_27 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4140 = remapindex_27 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4141 = remapindex_27 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4142 = remapindex_27 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4143 = remapindex_27 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4144 = remapindex_27 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4145 = remapindex_27 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4146 = remapindex_27 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4147 = remapindex_27 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4148 = remapindex_27 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4149 = remapindex_27 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4150 = remapindex_27 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4151 = remapindex_27 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4152 = remapindex_27 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4153 = remapindex_27 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4154 = remapindex_27 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4155 = remapindex_27 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4156 = remapindex_27 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4157 = remapindex_27 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4158 = remapindex_27 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4159 = remapindex_27 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4160 = remapindex_27 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4161 = remapindex_27 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4162 = remapindex_27 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4163 = remapindex_27 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4164 = remapindex_27 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4165 = remapindex_27 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_27 = _T_4165 ? _Queue10_UInt8_31_io_deq_bits : _T_4164 ? _Queue10_UInt8_30_io_deq_bits : _T_4163 ? _Queue10_UInt8_29_io_deq_bits : _T_4162 ? _Queue10_UInt8_28_io_deq_bits : _T_4161 ? _Queue10_UInt8_27_io_deq_bits : _T_4160 ? _Queue10_UInt8_26_io_deq_bits : _T_4159 ? _Queue10_UInt8_25_io_deq_bits : _T_4158 ? _Queue10_UInt8_24_io_deq_bits : _T_4157 ? _Queue10_UInt8_23_io_deq_bits : _T_4156 ? _Queue10_UInt8_22_io_deq_bits : _T_4155 ? _Queue10_UInt8_21_io_deq_bits : _T_4154 ? _Queue10_UInt8_20_io_deq_bits : _T_4153 ? _Queue10_UInt8_19_io_deq_bits : _T_4152 ? _Queue10_UInt8_18_io_deq_bits : _T_4151 ? _Queue10_UInt8_17_io_deq_bits : _T_4150 ? _Queue10_UInt8_16_io_deq_bits : _T_4149 ? _Queue10_UInt8_15_io_deq_bits : _T_4148 ? _Queue10_UInt8_14_io_deq_bits : _T_4147 ? _Queue10_UInt8_13_io_deq_bits : _T_4146 ? _Queue10_UInt8_12_io_deq_bits : _T_4145 ? _Queue10_UInt8_11_io_deq_bits : _T_4144 ? _Queue10_UInt8_10_io_deq_bits : _T_4143 ? _Queue10_UInt8_9_io_deq_bits : _T_4142 ? _Queue10_UInt8_8_io_deq_bits : _T_4141 ? _Queue10_UInt8_7_io_deq_bits : _T_4140 ? _Queue10_UInt8_6_io_deq_bits : _T_4139 ? _Queue10_UInt8_5_io_deq_bits : _T_4138 ? _Queue10_UInt8_4_io_deq_bits : _T_4137 ? _Queue10_UInt8_3_io_deq_bits : _T_4136 ? _Queue10_UInt8_2_io_deq_bits : _T_4135 ? _Queue10_UInt8_1_io_deq_bits : _T_4134 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_27 = _T_4165 ? _Queue10_UInt8_31_io_deq_valid : _T_4164 ? _Queue10_UInt8_30_io_deq_valid : _T_4163 ? _Queue10_UInt8_29_io_deq_valid : _T_4162 ? _Queue10_UInt8_28_io_deq_valid : _T_4161 ? _Queue10_UInt8_27_io_deq_valid : _T_4160 ? _Queue10_UInt8_26_io_deq_valid : _T_4159 ? _Queue10_UInt8_25_io_deq_valid : _T_4158 ? _Queue10_UInt8_24_io_deq_valid : _T_4157 ? _Queue10_UInt8_23_io_deq_valid : _T_4156 ? _Queue10_UInt8_22_io_deq_valid : _T_4155 ? _Queue10_UInt8_21_io_deq_valid : _T_4154 ? _Queue10_UInt8_20_io_deq_valid : _T_4153 ? _Queue10_UInt8_19_io_deq_valid : _T_4152 ? _Queue10_UInt8_18_io_deq_valid : _T_4151 ? _Queue10_UInt8_17_io_deq_valid : _T_4150 ? _Queue10_UInt8_16_io_deq_valid : _T_4149 ? _Queue10_UInt8_15_io_deq_valid : _T_4148 ? _Queue10_UInt8_14_io_deq_valid : _T_4147 ? _Queue10_UInt8_13_io_deq_valid : _T_4146 ? _Queue10_UInt8_12_io_deq_valid : _T_4145 ? _Queue10_UInt8_11_io_deq_valid : _T_4144 ? _Queue10_UInt8_10_io_deq_valid : _T_4143 ? _Queue10_UInt8_9_io_deq_valid : _T_4142 ? _Queue10_UInt8_8_io_deq_valid : _T_4141 ? _Queue10_UInt8_7_io_deq_valid : _T_4140 ? _Queue10_UInt8_6_io_deq_valid : _T_4139 ? _Queue10_UInt8_5_io_deq_valid : _T_4138 ? _Queue10_UInt8_4_io_deq_valid : _T_4137 ? _Queue10_UInt8_3_io_deq_valid : _T_4136 ? _Queue10_UInt8_2_io_deq_valid : _T_4135 ? _Queue10_UInt8_1_io_deq_valid : _T_4134 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_28 = _remapindex_T + 7'h1C; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_117 = _remapindex_T_28 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_28 = _GEN_117[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_4166 = remapindex_28 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4167 = remapindex_28 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4168 = remapindex_28 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4169 = remapindex_28 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4170 = remapindex_28 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4171 = remapindex_28 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4172 = remapindex_28 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4173 = remapindex_28 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4174 = remapindex_28 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4175 = remapindex_28 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4176 = remapindex_28 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4177 = remapindex_28 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4178 = remapindex_28 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4179 = remapindex_28 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4180 = remapindex_28 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4181 = remapindex_28 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4182 = remapindex_28 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4183 = remapindex_28 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4184 = remapindex_28 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4185 = remapindex_28 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4186 = remapindex_28 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4187 = remapindex_28 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4188 = remapindex_28 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4189 = remapindex_28 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4190 = remapindex_28 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4191 = remapindex_28 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4192 = remapindex_28 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4193 = remapindex_28 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4194 = remapindex_28 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4195 = remapindex_28 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4196 = remapindex_28 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4197 = remapindex_28 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_28 = _T_4197 ? _Queue10_UInt8_31_io_deq_bits : _T_4196 ? _Queue10_UInt8_30_io_deq_bits : _T_4195 ? _Queue10_UInt8_29_io_deq_bits : _T_4194 ? _Queue10_UInt8_28_io_deq_bits : _T_4193 ? _Queue10_UInt8_27_io_deq_bits : _T_4192 ? _Queue10_UInt8_26_io_deq_bits : _T_4191 ? _Queue10_UInt8_25_io_deq_bits : _T_4190 ? _Queue10_UInt8_24_io_deq_bits : _T_4189 ? _Queue10_UInt8_23_io_deq_bits : _T_4188 ? _Queue10_UInt8_22_io_deq_bits : _T_4187 ? _Queue10_UInt8_21_io_deq_bits : _T_4186 ? _Queue10_UInt8_20_io_deq_bits : _T_4185 ? _Queue10_UInt8_19_io_deq_bits : _T_4184 ? _Queue10_UInt8_18_io_deq_bits : _T_4183 ? _Queue10_UInt8_17_io_deq_bits : _T_4182 ? _Queue10_UInt8_16_io_deq_bits : _T_4181 ? _Queue10_UInt8_15_io_deq_bits : _T_4180 ? _Queue10_UInt8_14_io_deq_bits : _T_4179 ? _Queue10_UInt8_13_io_deq_bits : _T_4178 ? _Queue10_UInt8_12_io_deq_bits : _T_4177 ? _Queue10_UInt8_11_io_deq_bits : _T_4176 ? _Queue10_UInt8_10_io_deq_bits : _T_4175 ? _Queue10_UInt8_9_io_deq_bits : _T_4174 ? _Queue10_UInt8_8_io_deq_bits : _T_4173 ? _Queue10_UInt8_7_io_deq_bits : _T_4172 ? _Queue10_UInt8_6_io_deq_bits : _T_4171 ? _Queue10_UInt8_5_io_deq_bits : _T_4170 ? _Queue10_UInt8_4_io_deq_bits : _T_4169 ? _Queue10_UInt8_3_io_deq_bits : _T_4168 ? _Queue10_UInt8_2_io_deq_bits : _T_4167 ? _Queue10_UInt8_1_io_deq_bits : _T_4166 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_28 = _T_4197 ? _Queue10_UInt8_31_io_deq_valid : _T_4196 ? _Queue10_UInt8_30_io_deq_valid : _T_4195 ? _Queue10_UInt8_29_io_deq_valid : _T_4194 ? _Queue10_UInt8_28_io_deq_valid : _T_4193 ? _Queue10_UInt8_27_io_deq_valid : _T_4192 ? _Queue10_UInt8_26_io_deq_valid : _T_4191 ? _Queue10_UInt8_25_io_deq_valid : _T_4190 ? _Queue10_UInt8_24_io_deq_valid : _T_4189 ? _Queue10_UInt8_23_io_deq_valid : _T_4188 ? _Queue10_UInt8_22_io_deq_valid : _T_4187 ? _Queue10_UInt8_21_io_deq_valid : _T_4186 ? _Queue10_UInt8_20_io_deq_valid : _T_4185 ? _Queue10_UInt8_19_io_deq_valid : _T_4184 ? _Queue10_UInt8_18_io_deq_valid : _T_4183 ? _Queue10_UInt8_17_io_deq_valid : _T_4182 ? _Queue10_UInt8_16_io_deq_valid : _T_4181 ? _Queue10_UInt8_15_io_deq_valid : _T_4180 ? _Queue10_UInt8_14_io_deq_valid : _T_4179 ? _Queue10_UInt8_13_io_deq_valid : _T_4178 ? _Queue10_UInt8_12_io_deq_valid : _T_4177 ? _Queue10_UInt8_11_io_deq_valid : _T_4176 ? _Queue10_UInt8_10_io_deq_valid : _T_4175 ? _Queue10_UInt8_9_io_deq_valid : _T_4174 ? _Queue10_UInt8_8_io_deq_valid : _T_4173 ? _Queue10_UInt8_7_io_deq_valid : _T_4172 ? _Queue10_UInt8_6_io_deq_valid : _T_4171 ? _Queue10_UInt8_5_io_deq_valid : _T_4170 ? _Queue10_UInt8_4_io_deq_valid : _T_4169 ? _Queue10_UInt8_3_io_deq_valid : _T_4168 ? _Queue10_UInt8_2_io_deq_valid : _T_4167 ? _Queue10_UInt8_1_io_deq_valid : _T_4166 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_29 = _remapindex_T + 7'h1D; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_118 = _remapindex_T_29 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_29 = _GEN_118[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_4198 = remapindex_29 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4199 = remapindex_29 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4200 = remapindex_29 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4201 = remapindex_29 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4202 = remapindex_29 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4203 = remapindex_29 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4204 = remapindex_29 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4205 = remapindex_29 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4206 = remapindex_29 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4207 = remapindex_29 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4208 = remapindex_29 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4209 = remapindex_29 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4210 = remapindex_29 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4211 = remapindex_29 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4212 = remapindex_29 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4213 = remapindex_29 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4214 = remapindex_29 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4215 = remapindex_29 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4216 = remapindex_29 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4217 = remapindex_29 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4218 = remapindex_29 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4219 = remapindex_29 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4220 = remapindex_29 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4221 = remapindex_29 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4222 = remapindex_29 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4223 = remapindex_29 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4224 = remapindex_29 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4225 = remapindex_29 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4226 = remapindex_29 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4227 = remapindex_29 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4228 = remapindex_29 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4229 = remapindex_29 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_29 = _T_4229 ? _Queue10_UInt8_31_io_deq_bits : _T_4228 ? _Queue10_UInt8_30_io_deq_bits : _T_4227 ? _Queue10_UInt8_29_io_deq_bits : _T_4226 ? _Queue10_UInt8_28_io_deq_bits : _T_4225 ? _Queue10_UInt8_27_io_deq_bits : _T_4224 ? _Queue10_UInt8_26_io_deq_bits : _T_4223 ? _Queue10_UInt8_25_io_deq_bits : _T_4222 ? _Queue10_UInt8_24_io_deq_bits : _T_4221 ? _Queue10_UInt8_23_io_deq_bits : _T_4220 ? _Queue10_UInt8_22_io_deq_bits : _T_4219 ? _Queue10_UInt8_21_io_deq_bits : _T_4218 ? _Queue10_UInt8_20_io_deq_bits : _T_4217 ? _Queue10_UInt8_19_io_deq_bits : _T_4216 ? _Queue10_UInt8_18_io_deq_bits : _T_4215 ? _Queue10_UInt8_17_io_deq_bits : _T_4214 ? _Queue10_UInt8_16_io_deq_bits : _T_4213 ? _Queue10_UInt8_15_io_deq_bits : _T_4212 ? _Queue10_UInt8_14_io_deq_bits : _T_4211 ? _Queue10_UInt8_13_io_deq_bits : _T_4210 ? _Queue10_UInt8_12_io_deq_bits : _T_4209 ? _Queue10_UInt8_11_io_deq_bits : _T_4208 ? _Queue10_UInt8_10_io_deq_bits : _T_4207 ? _Queue10_UInt8_9_io_deq_bits : _T_4206 ? _Queue10_UInt8_8_io_deq_bits : _T_4205 ? _Queue10_UInt8_7_io_deq_bits : _T_4204 ? _Queue10_UInt8_6_io_deq_bits : _T_4203 ? _Queue10_UInt8_5_io_deq_bits : _T_4202 ? _Queue10_UInt8_4_io_deq_bits : _T_4201 ? _Queue10_UInt8_3_io_deq_bits : _T_4200 ? _Queue10_UInt8_2_io_deq_bits : _T_4199 ? _Queue10_UInt8_1_io_deq_bits : _T_4198 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_29 = _T_4229 ? _Queue10_UInt8_31_io_deq_valid : _T_4228 ? _Queue10_UInt8_30_io_deq_valid : _T_4227 ? _Queue10_UInt8_29_io_deq_valid : _T_4226 ? _Queue10_UInt8_28_io_deq_valid : _T_4225 ? _Queue10_UInt8_27_io_deq_valid : _T_4224 ? _Queue10_UInt8_26_io_deq_valid : _T_4223 ? _Queue10_UInt8_25_io_deq_valid : _T_4222 ? _Queue10_UInt8_24_io_deq_valid : _T_4221 ? _Queue10_UInt8_23_io_deq_valid : _T_4220 ? _Queue10_UInt8_22_io_deq_valid : _T_4219 ? _Queue10_UInt8_21_io_deq_valid : _T_4218 ? _Queue10_UInt8_20_io_deq_valid : _T_4217 ? _Queue10_UInt8_19_io_deq_valid : _T_4216 ? _Queue10_UInt8_18_io_deq_valid : _T_4215 ? _Queue10_UInt8_17_io_deq_valid : _T_4214 ? _Queue10_UInt8_16_io_deq_valid : _T_4213 ? _Queue10_UInt8_15_io_deq_valid : _T_4212 ? _Queue10_UInt8_14_io_deq_valid : _T_4211 ? _Queue10_UInt8_13_io_deq_valid : _T_4210 ? _Queue10_UInt8_12_io_deq_valid : _T_4209 ? _Queue10_UInt8_11_io_deq_valid : _T_4208 ? _Queue10_UInt8_10_io_deq_valid : _T_4207 ? _Queue10_UInt8_9_io_deq_valid : _T_4206 ? _Queue10_UInt8_8_io_deq_valid : _T_4205 ? _Queue10_UInt8_7_io_deq_valid : _T_4204 ? _Queue10_UInt8_6_io_deq_valid : _T_4203 ? _Queue10_UInt8_5_io_deq_valid : _T_4202 ? _Queue10_UInt8_4_io_deq_valid : _T_4201 ? _Queue10_UInt8_3_io_deq_valid : _T_4200 ? _Queue10_UInt8_2_io_deq_valid : _T_4199 ? _Queue10_UInt8_1_io_deq_valid : _T_4198 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_30 = _remapindex_T + 7'h1E; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_119 = _remapindex_T_30 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_30 = _GEN_119[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_4230 = remapindex_30 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4231 = remapindex_30 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4232 = remapindex_30 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4233 = remapindex_30 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4234 = remapindex_30 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4235 = remapindex_30 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4236 = remapindex_30 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4237 = remapindex_30 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4238 = remapindex_30 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4239 = remapindex_30 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4240 = remapindex_30 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4241 = remapindex_30 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4242 = remapindex_30 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4243 = remapindex_30 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4244 = remapindex_30 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4245 = remapindex_30 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4246 = remapindex_30 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4247 = remapindex_30 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4248 = remapindex_30 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4249 = remapindex_30 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4250 = remapindex_30 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4251 = remapindex_30 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4252 = remapindex_30 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4253 = remapindex_30 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4254 = remapindex_30 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4255 = remapindex_30 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4256 = remapindex_30 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4257 = remapindex_30 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4258 = remapindex_30 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4259 = remapindex_30 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4260 = remapindex_30 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4261 = remapindex_30 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_30 = _T_4261 ? _Queue10_UInt8_31_io_deq_bits : _T_4260 ? _Queue10_UInt8_30_io_deq_bits : _T_4259 ? _Queue10_UInt8_29_io_deq_bits : _T_4258 ? _Queue10_UInt8_28_io_deq_bits : _T_4257 ? _Queue10_UInt8_27_io_deq_bits : _T_4256 ? _Queue10_UInt8_26_io_deq_bits : _T_4255 ? _Queue10_UInt8_25_io_deq_bits : _T_4254 ? _Queue10_UInt8_24_io_deq_bits : _T_4253 ? _Queue10_UInt8_23_io_deq_bits : _T_4252 ? _Queue10_UInt8_22_io_deq_bits : _T_4251 ? _Queue10_UInt8_21_io_deq_bits : _T_4250 ? _Queue10_UInt8_20_io_deq_bits : _T_4249 ? _Queue10_UInt8_19_io_deq_bits : _T_4248 ? _Queue10_UInt8_18_io_deq_bits : _T_4247 ? _Queue10_UInt8_17_io_deq_bits : _T_4246 ? _Queue10_UInt8_16_io_deq_bits : _T_4245 ? _Queue10_UInt8_15_io_deq_bits : _T_4244 ? _Queue10_UInt8_14_io_deq_bits : _T_4243 ? _Queue10_UInt8_13_io_deq_bits : _T_4242 ? _Queue10_UInt8_12_io_deq_bits : _T_4241 ? _Queue10_UInt8_11_io_deq_bits : _T_4240 ? _Queue10_UInt8_10_io_deq_bits : _T_4239 ? _Queue10_UInt8_9_io_deq_bits : _T_4238 ? _Queue10_UInt8_8_io_deq_bits : _T_4237 ? _Queue10_UInt8_7_io_deq_bits : _T_4236 ? _Queue10_UInt8_6_io_deq_bits : _T_4235 ? _Queue10_UInt8_5_io_deq_bits : _T_4234 ? _Queue10_UInt8_4_io_deq_bits : _T_4233 ? _Queue10_UInt8_3_io_deq_bits : _T_4232 ? _Queue10_UInt8_2_io_deq_bits : _T_4231 ? _Queue10_UInt8_1_io_deq_bits : _T_4230 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_30 = _T_4261 ? _Queue10_UInt8_31_io_deq_valid : _T_4260 ? _Queue10_UInt8_30_io_deq_valid : _T_4259 ? _Queue10_UInt8_29_io_deq_valid : _T_4258 ? _Queue10_UInt8_28_io_deq_valid : _T_4257 ? _Queue10_UInt8_27_io_deq_valid : _T_4256 ? _Queue10_UInt8_26_io_deq_valid : _T_4255 ? _Queue10_UInt8_25_io_deq_valid : _T_4254 ? _Queue10_UInt8_24_io_deq_valid : _T_4253 ? _Queue10_UInt8_23_io_deq_valid : _T_4252 ? _Queue10_UInt8_22_io_deq_valid : _T_4251 ? _Queue10_UInt8_21_io_deq_valid : _T_4250 ? _Queue10_UInt8_20_io_deq_valid : _T_4249 ? _Queue10_UInt8_19_io_deq_valid : _T_4248 ? _Queue10_UInt8_18_io_deq_valid : _T_4247 ? _Queue10_UInt8_17_io_deq_valid : _T_4246 ? _Queue10_UInt8_16_io_deq_valid : _T_4245 ? _Queue10_UInt8_15_io_deq_valid : _T_4244 ? _Queue10_UInt8_14_io_deq_valid : _T_4243 ? _Queue10_UInt8_13_io_deq_valid : _T_4242 ? _Queue10_UInt8_12_io_deq_valid : _T_4241 ? _Queue10_UInt8_11_io_deq_valid : _T_4240 ? _Queue10_UInt8_10_io_deq_valid : _T_4239 ? _Queue10_UInt8_9_io_deq_valid : _T_4238 ? _Queue10_UInt8_8_io_deq_valid : _T_4237 ? _Queue10_UInt8_7_io_deq_valid : _T_4236 ? _Queue10_UInt8_6_io_deq_valid : _T_4235 ? _Queue10_UInt8_5_io_deq_valid : _T_4234 ? _Queue10_UInt8_4_io_deq_valid : _T_4233 ? _Queue10_UInt8_3_io_deq_valid : _T_4232 ? _Queue10_UInt8_2_io_deq_valid : _T_4231 ? _Queue10_UInt8_1_io_deq_valid : _T_4230 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_31 = _remapindex_T + 7'h1F; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_120 = _remapindex_T_31 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_31 = _GEN_120[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_4262 = remapindex_31 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4263 = remapindex_31 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4264 = remapindex_31 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4265 = remapindex_31 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4266 = remapindex_31 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4267 = remapindex_31 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4268 = remapindex_31 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4269 = remapindex_31 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4270 = remapindex_31 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4271 = remapindex_31 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4272 = remapindex_31 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4273 = remapindex_31 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4274 = remapindex_31 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4275 = remapindex_31 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4276 = remapindex_31 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4277 = remapindex_31 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4278 = remapindex_31 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4279 = remapindex_31 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4280 = remapindex_31 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4281 = remapindex_31 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4282 = remapindex_31 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4283 = remapindex_31 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4284 = remapindex_31 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4285 = remapindex_31 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4286 = remapindex_31 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4287 = remapindex_31 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4288 = remapindex_31 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4289 = remapindex_31 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4290 = remapindex_31 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4291 = remapindex_31 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4292 = remapindex_31 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4293 = remapindex_31 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_31 = _T_4293 ? _Queue10_UInt8_31_io_deq_bits : _T_4292 ? _Queue10_UInt8_30_io_deq_bits : _T_4291 ? _Queue10_UInt8_29_io_deq_bits : _T_4290 ? _Queue10_UInt8_28_io_deq_bits : _T_4289 ? _Queue10_UInt8_27_io_deq_bits : _T_4288 ? _Queue10_UInt8_26_io_deq_bits : _T_4287 ? _Queue10_UInt8_25_io_deq_bits : _T_4286 ? _Queue10_UInt8_24_io_deq_bits : _T_4285 ? _Queue10_UInt8_23_io_deq_bits : _T_4284 ? _Queue10_UInt8_22_io_deq_bits : _T_4283 ? _Queue10_UInt8_21_io_deq_bits : _T_4282 ? _Queue10_UInt8_20_io_deq_bits : _T_4281 ? _Queue10_UInt8_19_io_deq_bits : _T_4280 ? _Queue10_UInt8_18_io_deq_bits : _T_4279 ? _Queue10_UInt8_17_io_deq_bits : _T_4278 ? _Queue10_UInt8_16_io_deq_bits : _T_4277 ? _Queue10_UInt8_15_io_deq_bits : _T_4276 ? _Queue10_UInt8_14_io_deq_bits : _T_4275 ? _Queue10_UInt8_13_io_deq_bits : _T_4274 ? _Queue10_UInt8_12_io_deq_bits : _T_4273 ? _Queue10_UInt8_11_io_deq_bits : _T_4272 ? _Queue10_UInt8_10_io_deq_bits : _T_4271 ? _Queue10_UInt8_9_io_deq_bits : _T_4270 ? _Queue10_UInt8_8_io_deq_bits : _T_4269 ? _Queue10_UInt8_7_io_deq_bits : _T_4268 ? _Queue10_UInt8_6_io_deq_bits : _T_4267 ? _Queue10_UInt8_5_io_deq_bits : _T_4266 ? _Queue10_UInt8_4_io_deq_bits : _T_4265 ? _Queue10_UInt8_3_io_deq_bits : _T_4264 ? _Queue10_UInt8_2_io_deq_bits : _T_4263 ? _Queue10_UInt8_1_io_deq_bits : _T_4262 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_31 = _T_4293 ? _Queue10_UInt8_31_io_deq_valid : _T_4292 ? _Queue10_UInt8_30_io_deq_valid : _T_4291 ? _Queue10_UInt8_29_io_deq_valid : _T_4290 ? _Queue10_UInt8_28_io_deq_valid : _T_4289 ? _Queue10_UInt8_27_io_deq_valid : _T_4288 ? _Queue10_UInt8_26_io_deq_valid : _T_4287 ? _Queue10_UInt8_25_io_deq_valid : _T_4286 ? _Queue10_UInt8_24_io_deq_valid : _T_4285 ? _Queue10_UInt8_23_io_deq_valid : _T_4284 ? _Queue10_UInt8_22_io_deq_valid : _T_4283 ? _Queue10_UInt8_21_io_deq_valid : _T_4282 ? _Queue10_UInt8_20_io_deq_valid : _T_4281 ? _Queue10_UInt8_19_io_deq_valid : _T_4280 ? _Queue10_UInt8_18_io_deq_valid : _T_4279 ? _Queue10_UInt8_17_io_deq_valid : _T_4278 ? _Queue10_UInt8_16_io_deq_valid : _T_4277 ? _Queue10_UInt8_15_io_deq_valid : _T_4276 ? _Queue10_UInt8_14_io_deq_valid : _T_4275 ? _Queue10_UInt8_13_io_deq_valid : _T_4274 ? _Queue10_UInt8_12_io_deq_valid : _T_4273 ? _Queue10_UInt8_11_io_deq_valid : _T_4272 ? _Queue10_UInt8_10_io_deq_valid : _T_4271 ? _Queue10_UInt8_9_io_deq_valid : _T_4270 ? _Queue10_UInt8_8_io_deq_valid : _T_4269 ? _Queue10_UInt8_7_io_deq_valid : _T_4268 ? _Queue10_UInt8_6_io_deq_valid : _T_4267 ? _Queue10_UInt8_5_io_deq_valid : _T_4266 ? _Queue10_UInt8_4_io_deq_valid : _T_4265 ? _Queue10_UInt8_3_io_deq_valid : _T_4264 ? _Queue10_UInt8_2_io_deq_valid : _T_4263 ? _Queue10_UInt8_1_io_deq_valid : _T_4262 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [15:0] io_consumer_output_data_lo_lo_lo_lo = {remapVecData_1, remapVecData_0}; // @[ZstdLitRotBuf.scala:225:26, :246:33] wire [15:0] io_consumer_output_data_lo_lo_lo_hi = {remapVecData_3, remapVecData_2}; // @[ZstdLitRotBuf.scala:225:26, :246:33] wire [31:0] io_consumer_output_data_lo_lo_lo = {io_consumer_output_data_lo_lo_lo_hi, io_consumer_output_data_lo_lo_lo_lo}; // @[ZstdLitRotBuf.scala:246:33] wire [15:0] io_consumer_output_data_lo_lo_hi_lo = {remapVecData_5, remapVecData_4}; // @[ZstdLitRotBuf.scala:225:26, :246:33] wire [15:0] io_consumer_output_data_lo_lo_hi_hi = {remapVecData_7, remapVecData_6}; // @[ZstdLitRotBuf.scala:225:26, :246:33] wire [31:0] io_consumer_output_data_lo_lo_hi = {io_consumer_output_data_lo_lo_hi_hi, io_consumer_output_data_lo_lo_hi_lo}; // @[ZstdLitRotBuf.scala:246:33] wire [63:0] io_consumer_output_data_lo_lo = {io_consumer_output_data_lo_lo_hi, io_consumer_output_data_lo_lo_lo}; // @[ZstdLitRotBuf.scala:246:33] wire [15:0] io_consumer_output_data_lo_hi_lo_lo = {remapVecData_9, remapVecData_8}; // @[ZstdLitRotBuf.scala:225:26, :246:33] wire [15:0] io_consumer_output_data_lo_hi_lo_hi = {remapVecData_11, remapVecData_10}; // @[ZstdLitRotBuf.scala:225:26, :246:33] wire [31:0] io_consumer_output_data_lo_hi_lo = {io_consumer_output_data_lo_hi_lo_hi, io_consumer_output_data_lo_hi_lo_lo}; // @[ZstdLitRotBuf.scala:246:33] wire [15:0] io_consumer_output_data_lo_hi_hi_lo = {remapVecData_13, remapVecData_12}; // @[ZstdLitRotBuf.scala:225:26, :246:33] wire [15:0] io_consumer_output_data_lo_hi_hi_hi = {remapVecData_15, remapVecData_14}; // @[ZstdLitRotBuf.scala:225:26, :246:33] wire [31:0] io_consumer_output_data_lo_hi_hi = {io_consumer_output_data_lo_hi_hi_hi, io_consumer_output_data_lo_hi_hi_lo}; // @[ZstdLitRotBuf.scala:246:33] wire [63:0] io_consumer_output_data_lo_hi = {io_consumer_output_data_lo_hi_hi, io_consumer_output_data_lo_hi_lo}; // @[ZstdLitRotBuf.scala:246:33] wire [127:0] io_consumer_output_data_lo = {io_consumer_output_data_lo_hi, io_consumer_output_data_lo_lo}; // @[ZstdLitRotBuf.scala:246:33] wire [15:0] io_consumer_output_data_hi_lo_lo_lo = {remapVecData_17, remapVecData_16}; // @[ZstdLitRotBuf.scala:225:26, :246:33] wire [15:0] io_consumer_output_data_hi_lo_lo_hi = {remapVecData_19, remapVecData_18}; // @[ZstdLitRotBuf.scala:225:26, :246:33] wire [31:0] io_consumer_output_data_hi_lo_lo = {io_consumer_output_data_hi_lo_lo_hi, io_consumer_output_data_hi_lo_lo_lo}; // @[ZstdLitRotBuf.scala:246:33] wire [15:0] io_consumer_output_data_hi_lo_hi_lo = {remapVecData_21, remapVecData_20}; // @[ZstdLitRotBuf.scala:225:26, :246:33] wire [15:0] io_consumer_output_data_hi_lo_hi_hi = {remapVecData_23, remapVecData_22}; // @[ZstdLitRotBuf.scala:225:26, :246:33] wire [31:0] io_consumer_output_data_hi_lo_hi = {io_consumer_output_data_hi_lo_hi_hi, io_consumer_output_data_hi_lo_hi_lo}; // @[ZstdLitRotBuf.scala:246:33] wire [63:0] io_consumer_output_data_hi_lo = {io_consumer_output_data_hi_lo_hi, io_consumer_output_data_hi_lo_lo}; // @[ZstdLitRotBuf.scala:246:33] wire [15:0] io_consumer_output_data_hi_hi_lo_lo = {remapVecData_25, remapVecData_24}; // @[ZstdLitRotBuf.scala:225:26, :246:33] wire [15:0] io_consumer_output_data_hi_hi_lo_hi = {remapVecData_27, remapVecData_26}; // @[ZstdLitRotBuf.scala:225:26, :246:33] wire [31:0] io_consumer_output_data_hi_hi_lo = {io_consumer_output_data_hi_hi_lo_hi, io_consumer_output_data_hi_hi_lo_lo}; // @[ZstdLitRotBuf.scala:246:33] wire [15:0] io_consumer_output_data_hi_hi_hi_lo = {remapVecData_29, remapVecData_28}; // @[ZstdLitRotBuf.scala:225:26, :246:33] wire [15:0] io_consumer_output_data_hi_hi_hi_hi = {remapVecData_31, remapVecData_30}; // @[ZstdLitRotBuf.scala:225:26, :246:33] wire [31:0] io_consumer_output_data_hi_hi_hi = {io_consumer_output_data_hi_hi_hi_hi, io_consumer_output_data_hi_hi_hi_lo}; // @[ZstdLitRotBuf.scala:246:33] wire [63:0] io_consumer_output_data_hi_hi = {io_consumer_output_data_hi_hi_hi, io_consumer_output_data_hi_hi_lo}; // @[ZstdLitRotBuf.scala:246:33] wire [127:0] io_consumer_output_data_hi = {io_consumer_output_data_hi_hi, io_consumer_output_data_hi_lo}; // @[ZstdLitRotBuf.scala:246:33] assign _io_consumer_output_data_T = {io_consumer_output_data_hi, io_consumer_output_data_lo}; // @[ZstdLitRotBuf.scala:246:33] assign io_consumer_output_data_0 = _io_consumer_output_data_T; // @[ZstdLitRotBuf.scala:152:7, :246:33] wire [1:0] _count_valids_T = {1'h0, remapVecValids_0} + {1'h0, remapVecValids_1}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [2:0] _count_valids_T_1 = {1'h0, _count_valids_T} + {2'h0, remapVecValids_2}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [3:0] _count_valids_T_2 = {1'h0, _count_valids_T_1} + {3'h0, remapVecValids_3}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [4:0] _count_valids_T_3 = {1'h0, _count_valids_T_2} + {4'h0, remapVecValids_4}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [5:0] _count_valids_T_4 = {1'h0, _count_valids_T_3} + {5'h0, remapVecValids_5}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [6:0] _count_valids_T_5 = {1'h0, _count_valids_T_4} + {6'h0, remapVecValids_6}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [7:0] _count_valids_T_6 = {1'h0, _count_valids_T_5} + {7'h0, remapVecValids_7}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [8:0] _count_valids_T_7 = {1'h0, _count_valids_T_6} + {8'h0, remapVecValids_8}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [9:0] _count_valids_T_8 = {1'h0, _count_valids_T_7} + {9'h0, remapVecValids_9}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [10:0] _count_valids_T_9 = {1'h0, _count_valids_T_8} + {10'h0, remapVecValids_10}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [11:0] _count_valids_T_10 = {1'h0, _count_valids_T_9} + {11'h0, remapVecValids_11}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [12:0] _count_valids_T_11 = {1'h0, _count_valids_T_10} + {12'h0, remapVecValids_12}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [13:0] _count_valids_T_12 = {1'h0, _count_valids_T_11} + {13'h0, remapVecValids_13}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [14:0] _count_valids_T_13 = {1'h0, _count_valids_T_12} + {14'h0, remapVecValids_14}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [15:0] _count_valids_T_14 = {1'h0, _count_valids_T_13} + {15'h0, remapVecValids_15}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [16:0] _count_valids_T_15 = {1'h0, _count_valids_T_14} + {16'h0, remapVecValids_16}; // @[ZstdLitRotBuf.scala:185:{75,91}, :226:28, :249:60] wire [17:0] _count_valids_T_16 = {1'h0, _count_valids_T_15} + {17'h0, remapVecValids_17}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [18:0] _count_valids_T_17 = {1'h0, _count_valids_T_16} + {18'h0, remapVecValids_18}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [19:0] _count_valids_T_18 = {1'h0, _count_valids_T_17} + {19'h0, remapVecValids_19}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [20:0] _count_valids_T_19 = {1'h0, _count_valids_T_18} + {20'h0, remapVecValids_20}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [21:0] _count_valids_T_20 = {1'h0, _count_valids_T_19} + {21'h0, remapVecValids_21}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [22:0] _count_valids_T_21 = {1'h0, _count_valids_T_20} + {22'h0, remapVecValids_22}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [23:0] _count_valids_T_22 = {1'h0, _count_valids_T_21} + {23'h0, remapVecValids_23}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [24:0] _count_valids_T_23 = {1'h0, _count_valids_T_22} + {24'h0, remapVecValids_24}; // @[ZstdLitRotBuf.scala:185:{75,91}, :226:28, :249:60] wire [25:0] _count_valids_T_24 = {1'h0, _count_valids_T_23} + {25'h0, remapVecValids_25}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [26:0] _count_valids_T_25 = {1'h0, _count_valids_T_24} + {26'h0, remapVecValids_26}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [27:0] _count_valids_T_26 = {1'h0, _count_valids_T_25} + {27'h0, remapVecValids_27}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [28:0] _count_valids_T_27 = {1'h0, _count_valids_T_26} + {28'h0, remapVecValids_28}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [29:0] _count_valids_T_28 = {1'h0, _count_valids_T_27} + {29'h0, remapVecValids_29}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [30:0] _count_valids_T_29 = {1'h0, _count_valids_T_28} + {30'h0, remapVecValids_30}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [31:0] count_valids = {1'h0, _count_valids_T_29} + {31'h0, remapVecValids_31}; // @[ZstdLitRotBuf.scala:226:28, :249:60] assign enough_data = |count_valids; // @[ZstdLitRotBuf.scala:249:60, :251:34] assign io_consumer_output_valid_0 = enough_data; // @[ZstdLitRotBuf.scala:152:7, :251:34] assign io_consumer_available_output_bytes_0 = count_valids[5:0]; // @[ZstdLitRotBuf.scala:152:7, :249:60, :253:38] wire _T_4303 = io_consumer_output_ready_0 & enough_data; // @[Misc.scala:29:18] wire _remapVecReadys_0_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_0_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_1_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_1_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_2_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_2_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_3_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_3_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_4_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_4_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_5_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_5_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_6_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_6_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_7_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_7_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_8_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_8_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_9_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_9_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_10_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_10_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_11_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_11_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_12_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_12_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_13_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_13_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_14_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_14_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_15_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_15_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_16_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_16_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_17_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_17_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_18_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_18_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_19_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_19_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_20_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_20_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_21_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_21_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_22_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_22_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_23_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_23_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_24_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_24_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_25_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_25_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_26_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_26_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_27_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_27_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_28_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_28_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_29_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_29_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_30_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_30_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_31_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_31_T_1 = _T_4303; // @[Misc.scala:29:18] reg [63:0] loginfo_cycles_33; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_66 = {1'h0, loginfo_cycles_33} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_67 = _loginfo_cycles_T_66[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_34; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_68 = {1'h0, loginfo_cycles_34} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_69 = _loginfo_cycles_T_68[63:0]; // @[Util.scala:19:38]
Generate the Verilog code corresponding to the following Chisel files. File Xbar.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressDecoder, AddressSet, RegionType, IdRange, TriStateValue} import freechips.rocketchip.util.BundleField // Trades off slave port proximity against routing resource cost object ForceFanout { def apply[T]( a: TriStateValue = TriStateValue.unset, b: TriStateValue = TriStateValue.unset, c: TriStateValue = TriStateValue.unset, d: TriStateValue = TriStateValue.unset, e: TriStateValue = TriStateValue.unset)(body: Parameters => T)(implicit p: Parameters) = { body(p.alterPartial { case ForceFanoutKey => p(ForceFanoutKey) match { case ForceFanoutParams(pa, pb, pc, pd, pe) => ForceFanoutParams(a.update(pa), b.update(pb), c.update(pc), d.update(pd), e.update(pe)) } }) } } private case class ForceFanoutParams(a: Boolean, b: Boolean, c: Boolean, d: Boolean, e: Boolean) private case object ForceFanoutKey extends Field(ForceFanoutParams(false, false, false, false, false)) class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule { val node = new TLNexusNode( clientFn = { seq => seq(0).v1copy( echoFields = BundleField.union(seq.flatMap(_.echoFields)), requestFields = BundleField.union(seq.flatMap(_.requestFields)), responseKeys = seq.flatMap(_.responseKeys).distinct, minLatency = seq.map(_.minLatency).min, clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) => port.clients map { client => client.v1copy( sourceId = client.sourceId.shift(range.start) )} } ) }, managerFn = { seq => val fifoIdFactory = TLXbar.relabeler() seq(0).v1copy( responseFields = BundleField.union(seq.flatMap(_.responseFields)), requestKeys = seq.flatMap(_.requestKeys).distinct, minLatency = seq.map(_.minLatency).min, endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max, managers = seq.flatMap { port => require (port.beatBytes == seq(0).beatBytes, s"Xbar ($name with parent $parent) data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B") val fifoIdMapper = fifoIdFactory() port.managers map { manager => manager.v1copy( fifoId = manager.fifoId.map(fifoIdMapper(_)) )} } ) } ){ override def circuitIdentity = outputs.size == 1 && inputs.size == 1 } lazy val module = new Impl class Impl extends LazyModuleImp(this) { if ((node.in.size * node.out.size) > (8*32)) { println (s"!!! WARNING !!!") println (s" Your TLXbar ($name with parent $parent) is very large, with ${node.in.size} Masters and ${node.out.size} Slaves.") println (s"!!! WARNING !!!") } val wide_bundle = TLBundleParameters.union((node.in ++ node.out).map(_._2.bundle)) override def desiredName = (Seq("TLXbar") ++ nameSuffix ++ Seq(s"i${node.in.size}_o${node.out.size}_${wide_bundle.shortName}")).mkString("_") TLXbar.circuit(policy, node.in, node.out) } } object TLXbar { def mapInputIds(ports: Seq[TLMasterPortParameters]) = assignRanges(ports.map(_.endSourceId)) def mapOutputIds(ports: Seq[TLSlavePortParameters]) = assignRanges(ports.map(_.endSinkId)) def assignRanges(sizes: Seq[Int]) = { val pow2Sizes = sizes.map { z => if (z == 0) 0 else 1 << log2Ceil(z) } val tuples = pow2Sizes.zipWithIndex.sortBy(_._1) // record old index, then sort by increasing size val starts = tuples.scanRight(0)(_._1 + _).tail // suffix-sum of the sizes = the start positions val ranges = (tuples zip starts) map { case ((sz, i), st) => (if (sz == 0) IdRange(0, 0) else IdRange(st, st + sz), i) } ranges.sortBy(_._2).map(_._1) // Restore orignal order } def relabeler() = { var idFactory = 0 () => { val fifoMap = scala.collection.mutable.HashMap.empty[Int, Int] (x: Int) => { if (fifoMap.contains(x)) fifoMap(x) else { val out = idFactory idFactory = idFactory + 1 fifoMap += (x -> out) out } } } } def circuit(policy: TLArbiter.Policy, seqIn: Seq[(TLBundle, TLEdge)], seqOut: Seq[(TLBundle, TLEdge)]) { val (io_in, edgesIn) = seqIn.unzip val (io_out, edgesOut) = seqOut.unzip // Not every master need connect to every slave on every channel; determine which connections are necessary val reachableIO = edgesIn.map { cp => edgesOut.map { mp => cp.client.clients.exists { c => mp.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma)}}}} }.toVector}.toVector val probeIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.managers.exists(_.regionType >= RegionType.TRACKED) }.toVector}.toVector val releaseIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.anySupportAcquireB }.toVector}.toVector val connectAIO = reachableIO val connectBIO = probeIO val connectCIO = releaseIO val connectDIO = reachableIO val connectEIO = releaseIO def transpose[T](x: Seq[Seq[T]]) = if (x.isEmpty) Nil else Vector.tabulate(x(0).size) { i => Vector.tabulate(x.size) { j => x(j)(i) } } val connectAOI = transpose(connectAIO) val connectBOI = transpose(connectBIO) val connectCOI = transpose(connectCIO) val connectDOI = transpose(connectDIO) val connectEOI = transpose(connectEIO) // Grab the port ID mapping val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager)) // We need an intermediate size of bundle with the widest possible identifiers val wide_bundle = TLBundleParameters.union(io_in.map(_.params) ++ io_out.map(_.params)) // Handle size = 1 gracefully (Chisel3 empty range is broken) def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0) // Transform input bundle sources (sinks use global namespace on both sides) val in = Wire(Vec(io_in.size, TLBundle(wide_bundle))) for (i <- 0 until in.size) { val r = inputIdRanges(i) if (connectAIO(i).exists(x=>x)) { in(i).a.bits.user := DontCare in(i).a.squeezeAll.waiveAll :<>= io_in(i).a.squeezeAll.waiveAll in(i).a.bits.source := io_in(i).a.bits.source | r.start.U } else { in(i).a := DontCare io_in(i).a := DontCare in(i).a.valid := false.B io_in(i).a.ready := true.B } if (connectBIO(i).exists(x=>x)) { io_in(i).b.squeezeAll :<>= in(i).b.squeezeAll io_in(i).b.bits.source := trim(in(i).b.bits.source, r.size) } else { in(i).b := DontCare io_in(i).b := DontCare in(i).b.ready := true.B io_in(i).b.valid := false.B } if (connectCIO(i).exists(x=>x)) { in(i).c.bits.user := DontCare in(i).c.squeezeAll.waiveAll :<>= io_in(i).c.squeezeAll.waiveAll in(i).c.bits.source := io_in(i).c.bits.source | r.start.U } else { in(i).c := DontCare io_in(i).c := DontCare in(i).c.valid := false.B io_in(i).c.ready := true.B } if (connectDIO(i).exists(x=>x)) { io_in(i).d.squeezeAll.waiveAll :<>= in(i).d.squeezeAll.waiveAll io_in(i).d.bits.source := trim(in(i).d.bits.source, r.size) } else { in(i).d := DontCare io_in(i).d := DontCare in(i).d.ready := true.B io_in(i).d.valid := false.B } if (connectEIO(i).exists(x=>x)) { in(i).e.squeezeAll :<>= io_in(i).e.squeezeAll } else { in(i).e := DontCare io_in(i).e := DontCare in(i).e.valid := false.B io_in(i).e.ready := true.B } } // Transform output bundle sinks (sources use global namespace on both sides) val out = Wire(Vec(io_out.size, TLBundle(wide_bundle))) for (o <- 0 until out.size) { val r = outputIdRanges(o) if (connectAOI(o).exists(x=>x)) { out(o).a.bits.user := DontCare io_out(o).a.squeezeAll.waiveAll :<>= out(o).a.squeezeAll.waiveAll } else { out(o).a := DontCare io_out(o).a := DontCare out(o).a.ready := true.B io_out(o).a.valid := false.B } if (connectBOI(o).exists(x=>x)) { out(o).b.squeezeAll :<>= io_out(o).b.squeezeAll } else { out(o).b := DontCare io_out(o).b := DontCare out(o).b.valid := false.B io_out(o).b.ready := true.B } if (connectCOI(o).exists(x=>x)) { out(o).c.bits.user := DontCare io_out(o).c.squeezeAll.waiveAll :<>= out(o).c.squeezeAll.waiveAll } else { out(o).c := DontCare io_out(o).c := DontCare out(o).c.ready := true.B io_out(o).c.valid := false.B } if (connectDOI(o).exists(x=>x)) { out(o).d.squeezeAll :<>= io_out(o).d.squeezeAll out(o).d.bits.sink := io_out(o).d.bits.sink | r.start.U } else { out(o).d := DontCare io_out(o).d := DontCare out(o).d.valid := false.B io_out(o).d.ready := true.B } if (connectEOI(o).exists(x=>x)) { io_out(o).e.squeezeAll :<>= out(o).e.squeezeAll io_out(o).e.bits.sink := trim(out(o).e.bits.sink, r.size) } else { out(o).e := DontCare io_out(o).e := DontCare out(o).e.ready := true.B io_out(o).e.valid := false.B } } // Filter a list to only those elements selected def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1) // Based on input=>output connectivity, create per-input minimal address decode circuits val requiredAC = (connectAIO ++ connectCIO).distinct val outputPortFns: Map[Vector[Boolean], Seq[UInt => Bool]] = requiredAC.map { connectO => val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address)) val routingMask = AddressDecoder(filter(port_addrs, connectO)) val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct)) // Print the address mapping if (false) { println("Xbar mapping:") route_addrs.foreach { p => print(" ") p.foreach { a => print(s" ${a}") } println("") } println("--") } (connectO, route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_ || _))) }.toMap // Print the ID mapping if (false) { println(s"XBar mapping:") (edgesIn zip inputIdRanges).zipWithIndex.foreach { case ((edge, id), i) => println(s"\t$i assigned ${id} for ${edge.client.clients.map(_.name).mkString(", ")}") } println("") } val addressA = (in zip edgesIn) map { case (i, e) => e.address(i.a.bits) } val addressC = (in zip edgesIn) map { case (i, e) => e.address(i.c.bits) } def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B val requestAIO = (connectAIO zip addressA) map { case (c, i) => outputPortFns(c).map { o => unique(c) || o(i) } } val requestCIO = (connectCIO zip addressC) map { case (c, i) => outputPortFns(c).map { o => unique(c) || o(i) } } val requestBOI = out.map { o => inputIdRanges.map { i => i.contains(o.b.bits.source) } } val requestDOI = out.map { o => inputIdRanges.map { i => i.contains(o.d.bits.source) } } val requestEIO = in.map { i => outputIdRanges.map { o => o.contains(i.e.bits.sink) } } val beatsAI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.a.bits) } val beatsBO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.b.bits) } val beatsCI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.c.bits) } val beatsDO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.d.bits) } val beatsEI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.e.bits) } // Fanout the input sources to the output sinks val portsAOI = transpose((in zip requestAIO) map { case (i, r) => TLXbar.fanout(i.a, r, edgesOut.map(_.params(ForceFanoutKey).a)) }) val portsBIO = transpose((out zip requestBOI) map { case (o, r) => TLXbar.fanout(o.b, r, edgesIn .map(_.params(ForceFanoutKey).b)) }) val portsCOI = transpose((in zip requestCIO) map { case (i, r) => TLXbar.fanout(i.c, r, edgesOut.map(_.params(ForceFanoutKey).c)) }) val portsDIO = transpose((out zip requestDOI) map { case (o, r) => TLXbar.fanout(o.d, r, edgesIn .map(_.params(ForceFanoutKey).d)) }) val portsEOI = transpose((in zip requestEIO) map { case (i, r) => TLXbar.fanout(i.e, r, edgesOut.map(_.params(ForceFanoutKey).e)) }) // Arbitrate amongst the sources for (o <- 0 until out.size) { TLArbiter(policy)(out(o).a, filter(beatsAI zip portsAOI(o), connectAOI(o)):_*) TLArbiter(policy)(out(o).c, filter(beatsCI zip portsCOI(o), connectCOI(o)):_*) TLArbiter(policy)(out(o).e, filter(beatsEI zip portsEOI(o), connectEOI(o)):_*) filter(portsAOI(o), connectAOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsCOI(o), connectCOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsEOI(o), connectEOI(o).map(!_)) foreach { r => r.ready := false.B } } for (i <- 0 until in.size) { TLArbiter(policy)(in(i).b, filter(beatsBO zip portsBIO(i), connectBIO(i)):_*) TLArbiter(policy)(in(i).d, filter(beatsDO zip portsDIO(i), connectDIO(i)):_*) filter(portsBIO(i), connectBIO(i).map(!_)) foreach { r => r.ready := false.B } filter(portsDIO(i), connectDIO(i).map(!_)) foreach { r => r.ready := false.B } } } def apply(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { val xbar = LazyModule(new TLXbar(policy, nameSuffix)) xbar.node } // Replicate an input port to each output port def fanout[T <: TLChannel](input: DecoupledIO[T], select: Seq[Bool], force: Seq[Boolean] = Nil): Seq[DecoupledIO[T]] = { val filtered = Wire(Vec(select.size, chiselTypeOf(input))) for (i <- 0 until select.size) { filtered(i).bits := (if (force.lift(i).getOrElse(false)) IdentityModule(input.bits) else input.bits) filtered(i).valid := input.valid && (select(i) || (select.size == 1).B) } input.ready := Mux1H(select, filtered.map(_.ready)) filtered } } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMXbar(nManagers: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("Xbar")) val xbar = LazyModule(new TLXbar) xbar.node := TLDelayer(0.1) := model.node := fuzz.node (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMXbarTest(nManagers: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMXbar(nManagers,txns)).module) dut.io.start := io.start io.finished := dut.io.finished } class TLMulticlientXbar(nManagers: Int, nClients: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val xbar = LazyModule(new TLXbar) val fuzzers = (0 until nClients) map { n => val fuzz = LazyModule(new TLFuzzer(txns)) xbar.node := TLDelayer(0.1) := fuzz.node fuzz } (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzzers.last.module.io.finished } } class TLMulticlientXbarTest(nManagers: Int, nClients: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLMulticlientXbar(nManagers, nClients, txns)).module) dut.io.start := io.start io.finished := dut.io.finished }
module TLXbar_SlaveXbar_BoomTile_i0_o0_a1d8s1k1z1u_1( // @[Xbar.scala:74:9] input clock, // @[Xbar.scala:74:9] input reset // @[Xbar.scala:74:9] ); endmodule
Generate the Verilog code corresponding to the following Chisel files. File InputUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{FlowRoutingBundle} import constellation.noc.{HasNoCParams} class AbstractInputUnitIO( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams], )(implicit val p: Parameters) extends Bundle with HasRouterOutputParams { val nodeId = cParam.destId val router_req = Decoupled(new RouteComputerReq) val router_resp = Input(new RouteComputerResp(outParams, egressParams)) val vcalloc_req = Decoupled(new VCAllocReq(cParam, outParams, egressParams)) val vcalloc_resp = Input(new VCAllocResp(outParams, egressParams)) val out_credit_available = Input(MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) })) val salloc_req = Vec(cParam.destSpeedup, Decoupled(new SwitchAllocReq(outParams, egressParams))) val out = Vec(cParam.destSpeedup, Valid(new SwitchBundle(outParams, egressParams))) val debug = Output(new Bundle { val va_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) val sa_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) }) val block = Input(Bool()) } abstract class AbstractInputUnit( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams] )(implicit val p: Parameters) extends Module with HasRouterOutputParams with HasNoCParams { val nodeId = cParam.destId def io: AbstractInputUnitIO } class InputBuffer(cParam: ChannelParams)(implicit p: Parameters) extends Module { val nVirtualChannels = cParam.nVirtualChannels val io = IO(new Bundle { val enq = Flipped(Vec(cParam.srcSpeedup, Valid(new Flit(cParam.payloadBits)))) val deq = Vec(cParam.nVirtualChannels, Decoupled(new BaseFlit(cParam.payloadBits))) }) val useOutputQueues = cParam.useOutputQueues val delims = if (useOutputQueues) { cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize else 0).scanLeft(0)(_+_) } else { // If no queuing, have to add an additional slot since head == tail implies empty // TODO this should be fixed, should use all slots available cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize + 1 else 0).scanLeft(0)(_+_) } val starts = delims.dropRight(1).zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val ends = delims.tail.zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val fullSize = delims.last // Ugly case. Use multiple queues if ((cParam.srcSpeedup > 1 || cParam.destSpeedup > 1 || fullSize <= 1) || !cParam.unifiedBuffer) { require(useOutputQueues) val qs = cParam.virtualChannelParams.map(v => Module(new Queue(new BaseFlit(cParam.payloadBits), v.bufferSize))) qs.zipWithIndex.foreach { case (q,i) => val sel = io.enq.map(f => f.valid && f.bits.virt_channel_id === i.U) q.io.enq.valid := sel.orR q.io.enq.bits.head := Mux1H(sel, io.enq.map(_.bits.head)) q.io.enq.bits.tail := Mux1H(sel, io.enq.map(_.bits.tail)) q.io.enq.bits.payload := Mux1H(sel, io.enq.map(_.bits.payload)) io.deq(i) <> q.io.deq } } else { val mem = Mem(fullSize, new BaseFlit(cParam.payloadBits)) val heads = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val tails = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val empty = (heads zip tails).map(t => t._1 === t._2) val qs = Seq.fill(nVirtualChannels) { Module(new Queue(new BaseFlit(cParam.payloadBits), 1, pipe=true)) } qs.foreach(_.io.enq.valid := false.B) qs.foreach(_.io.enq.bits := DontCare) val vc_sel = UIntToOH(io.enq(0).bits.virt_channel_id) val flit = Wire(new BaseFlit(cParam.payloadBits)) val direct_to_q = (Mux1H(vc_sel, qs.map(_.io.enq.ready)) && Mux1H(vc_sel, empty)) && useOutputQueues.B flit.head := io.enq(0).bits.head flit.tail := io.enq(0).bits.tail flit.payload := io.enq(0).bits.payload when (io.enq(0).valid && !direct_to_q) { val tail = tails(io.enq(0).bits.virt_channel_id) mem.write(tail, flit) tails(io.enq(0).bits.virt_channel_id) := Mux( tail === Mux1H(vc_sel, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(vc_sel, starts.map(_.U)), tail + 1.U) } .elsewhen (io.enq(0).valid && direct_to_q) { for (i <- 0 until nVirtualChannels) { when (io.enq(0).bits.virt_channel_id === i.U) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := flit } } } if (useOutputQueues) { val can_to_q = (0 until nVirtualChannels).map { i => !empty(i) && qs(i).io.enq.ready } val to_q_oh = PriorityEncoderOH(can_to_q) val to_q = OHToUInt(to_q_oh) when (can_to_q.orR) { val head = Mux1H(to_q_oh, heads) heads(to_q) := Mux( head === Mux1H(to_q_oh, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(to_q_oh, starts.map(_.U)), head + 1.U) for (i <- 0 until nVirtualChannels) { when (to_q_oh(i)) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := mem.read(head) } } } for (i <- 0 until nVirtualChannels) { io.deq(i) <> qs(i).io.deq } } else { qs.map(_.io.deq.ready := false.B) val ready_sel = io.deq.map(_.ready) val fire = io.deq.map(_.fire) assert(PopCount(fire) <= 1.U) val head = Mux1H(fire, heads) when (fire.orR) { val fire_idx = OHToUInt(fire) heads(fire_idx) := Mux( head === Mux1H(fire, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(fire, starts.map(_.U)), head + 1.U) } val read_flit = mem.read(head) for (i <- 0 until nVirtualChannels) { io.deq(i).valid := !empty(i) io.deq(i).bits := read_flit } } } } class InputUnit(cParam: ChannelParams, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams], combineRCVA: Boolean, combineSAST: Boolean ) (implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) { val nVirtualChannels = cParam.nVirtualChannels val virtualChannelParams = cParam.virtualChannelParams class InputUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) { val in = Flipped(new Channel(cParam.asInstanceOf[ChannelParams])) } val io = IO(new InputUnitIO) val g_i :: g_r :: g_v :: g_a :: g_c :: Nil = Enum(5) class InputState extends Bundle { val g = UInt(3.W) val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) val flow = new FlowRoutingBundle val fifo_deps = UInt(nVirtualChannels.W) } val input_buffer = Module(new InputBuffer(cParam)) for (i <- 0 until cParam.srcSpeedup) { input_buffer.io.enq(i) := io.in.flit(i) } input_buffer.io.deq.foreach(_.ready := false.B) val route_arbiter = Module(new Arbiter( new RouteComputerReq, nVirtualChannels )) io.router_req <> route_arbiter.io.out val states = Reg(Vec(nVirtualChannels, new InputState)) val anyFifo = cParam.possibleFlows.map(_.fifo).reduce(_||_) val allFifo = cParam.possibleFlows.map(_.fifo).reduce(_&&_) if (anyFifo) { val idle_mask = VecInit(states.map(_.g === g_i)).asUInt for (s <- states) for (i <- 0 until nVirtualChannels) s.fifo_deps := s.fifo_deps & ~idle_mask } for (i <- 0 until cParam.srcSpeedup) { when (io.in.flit(i).fire && io.in.flit(i).bits.head) { val id = io.in.flit(i).bits.virt_channel_id assert(id < nVirtualChannels.U) assert(states(id).g === g_i) val at_dest = io.in.flit(i).bits.flow.egress_node === nodeId.U states(id).g := Mux(at_dest, g_v, g_r) states(id).vc_sel.foreach(_.foreach(_ := false.B)) for (o <- 0 until nEgress) { when (o.U === io.in.flit(i).bits.flow.egress_node_id) { states(id).vc_sel(o+nOutputs)(0) := true.B } } states(id).flow := io.in.flit(i).bits.flow if (anyFifo) { val fifo = cParam.possibleFlows.filter(_.fifo).map(_.isFlow(io.in.flit(i).bits.flow)).toSeq.orR states(id).fifo_deps := VecInit(states.zipWithIndex.map { case (s, j) => s.g =/= g_i && s.flow.asUInt === io.in.flit(i).bits.flow.asUInt && j.U =/= id }).asUInt } } } (route_arbiter.io.in zip states).zipWithIndex.map { case ((i,s),idx) => if (virtualChannelParams(idx).traversable) { i.valid := s.g === g_r i.bits.flow := s.flow i.bits.src_virt_id := idx.U when (i.fire) { s.g := g_v } } else { i.valid := false.B i.bits := DontCare } } when (io.router_req.fire) { val id = io.router_req.bits.src_virt_id assert(states(id).g === g_r) states(id).g := g_v for (i <- 0 until nVirtualChannels) { when (i.U === id) { states(i).vc_sel := io.router_resp.vc_sel } } } val mask = RegInit(0.U(nVirtualChannels.W)) val vcalloc_reqs = Wire(Vec(nVirtualChannels, new VCAllocReq(cParam, outParams, egressParams))) val vcalloc_vals = Wire(Vec(nVirtualChannels, Bool())) val vcalloc_filter = PriorityEncoderOH(Cat(vcalloc_vals.asUInt, vcalloc_vals.asUInt & ~mask)) val vcalloc_sel = vcalloc_filter(nVirtualChannels-1,0) | (vcalloc_filter >> nVirtualChannels) // Prioritize incoming packetes when (io.router_req.fire) { mask := (1.U << io.router_req.bits.src_virt_id) - 1.U } .elsewhen (vcalloc_vals.orR) { mask := Mux1H(vcalloc_sel, (0 until nVirtualChannels).map { w => ~(0.U((w+1).W)) }) } io.vcalloc_req.valid := vcalloc_vals.orR io.vcalloc_req.bits := Mux1H(vcalloc_sel, vcalloc_reqs) states.zipWithIndex.map { case (s,idx) => if (virtualChannelParams(idx).traversable) { vcalloc_vals(idx) := s.g === g_v && s.fifo_deps === 0.U vcalloc_reqs(idx).in_vc := idx.U vcalloc_reqs(idx).vc_sel := s.vc_sel vcalloc_reqs(idx).flow := s.flow when (vcalloc_vals(idx) && vcalloc_sel(idx) && io.vcalloc_req.ready) { s.g := g_a } if (combineRCVA) { when (route_arbiter.io.in(idx).fire) { vcalloc_vals(idx) := true.B vcalloc_reqs(idx).vc_sel := io.router_resp.vc_sel } } } else { vcalloc_vals(idx) := false.B vcalloc_reqs(idx) := DontCare } } io.debug.va_stall := PopCount(vcalloc_vals) - io.vcalloc_req.ready when (io.vcalloc_req.fire) { for (i <- 0 until nVirtualChannels) { when (vcalloc_sel(i)) { states(i).vc_sel := io.vcalloc_resp.vc_sel states(i).g := g_a if (!combineRCVA) { assert(states(i).g === g_v) } } } } val salloc_arb = Module(new SwitchArbiter( nVirtualChannels, cParam.destSpeedup, outParams, egressParams )) (states zip salloc_arb.io.in).zipWithIndex.map { case ((s,r),i) => if (virtualChannelParams(i).traversable) { val credit_available = (s.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U r.valid := s.g === g_a && credit_available && input_buffer.io.deq(i).valid r.bits.vc_sel := s.vc_sel val deq_tail = input_buffer.io.deq(i).bits.tail r.bits.tail := deq_tail when (r.fire && deq_tail) { s.g := g_i } input_buffer.io.deq(i).ready := r.ready } else { r.valid := false.B r.bits := DontCare } } io.debug.sa_stall := PopCount(salloc_arb.io.in.map(r => r.valid && !r.ready)) io.salloc_req <> salloc_arb.io.out when (io.block) { salloc_arb.io.out.foreach(_.ready := false.B) io.salloc_req.foreach(_.valid := false.B) } class OutBundle extends Bundle { val valid = Bool() val vid = UInt(virtualChannelBits.W) val out_vid = UInt(log2Up(allOutParams.map(_.nVirtualChannels).max).W) val flit = new Flit(cParam.payloadBits) } val salloc_outs = if (combineSAST) { Wire(Vec(cParam.destSpeedup, new OutBundle)) } else { Reg(Vec(cParam.destSpeedup, new OutBundle)) } io.in.credit_return := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire, salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_|_) io.in.vc_free := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire && Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)), salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_|_) for (i <- 0 until cParam.destSpeedup) { val salloc_out = salloc_outs(i) salloc_out.valid := salloc_arb.io.out(i).fire salloc_out.vid := OHToUInt(salloc_arb.io.chosen_oh(i)) val vc_sel = Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.vc_sel)) val channel_oh = vc_sel.map(_.reduce(_||_)).toSeq val virt_channel = Mux1H(channel_oh, vc_sel.map(v => OHToUInt(v)).toSeq) when (salloc_arb.io.out(i).fire) { salloc_out.out_vid := virt_channel salloc_out.flit.payload := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.payload)) salloc_out.flit.head := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.head)) salloc_out.flit.tail := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)) salloc_out.flit.flow := Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.flow)) } .otherwise { salloc_out.out_vid := DontCare salloc_out.flit := DontCare } salloc_out.flit.virt_channel_id := DontCare // this gets set in the switch io.out(i).valid := salloc_out.valid io.out(i).bits.flit := salloc_out.flit io.out(i).bits.out_virt_channel := salloc_out.out_vid } def filterVCSel(sel: MixedVec[Vec[Bool]], srcV: Int) = { if (virtualChannelParams(srcV).traversable) { outParams.zipWithIndex.map { case (oP, oI) => (0 until oP.nVirtualChannels).map { oV => var allow = false virtualChannelParams(srcV).possibleFlows.foreach { pI => allow = allow || routingRelation( cParam.channelRoutingInfos(srcV), oP.channelRoutingInfos(oV), pI ) } if (!allow) sel(oI)(oV) := false.B } } } } (0 until nVirtualChannels).map { i => if (!virtualChannelParams(i).traversable) states(i) := DontCare filterVCSel(states(i).vc_sel, i) } when (reset.asBool) { states.foreach(_.g := g_i) } }
module InputUnit_7( // @[InputUnit.scala:158:7] input clock, // @[InputUnit.scala:158:7] input reset, // @[InputUnit.scala:158:7] output [2:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_3, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_4, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_5, // @[InputUnit.scala:170:14] input io_vcalloc_req_ready, // @[InputUnit.scala:170:14] output io_vcalloc_req_valid, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_3, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_4, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_5, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_3, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_4, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_5, // @[InputUnit.scala:170:14] input io_out_credit_available_1_0, // @[InputUnit.scala:170:14] input io_out_credit_available_0_0, // @[InputUnit.scala:170:14] input io_out_credit_available_0_1, // @[InputUnit.scala:170:14] input io_out_credit_available_0_2, // @[InputUnit.scala:170:14] input io_out_credit_available_0_3, // @[InputUnit.scala:170:14] input io_out_credit_available_0_4, // @[InputUnit.scala:170:14] input io_out_credit_available_0_5, // @[InputUnit.scala:170:14] input io_salloc_req_0_ready, // @[InputUnit.scala:170:14] output io_salloc_req_0_valid, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14] output io_out_0_valid, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14] output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14] output [2:0] io_debug_va_stall, // @[InputUnit.scala:170:14] output [2:0] io_debug_sa_stall, // @[InputUnit.scala:170:14] input io_in_flit_0_valid, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14] input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14] output [5:0] io_in_credit_return, // @[InputUnit.scala:170:14] output [5:0] io_in_vc_free // @[InputUnit.scala:170:14] ); wire vcalloc_vals_5; // @[InputUnit.scala:266:32] wire vcalloc_vals_4; // @[InputUnit.scala:266:32] wire vcalloc_vals_3; // @[InputUnit.scala:266:32] wire vcalloc_vals_2; // @[InputUnit.scala:266:32] wire vcalloc_vals_1; // @[InputUnit.scala:266:32] wire vcalloc_vals_0; // @[InputUnit.scala:266:32] wire _salloc_arb_io_in_0_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_1_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_2_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_3_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_4_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_5_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26] wire [5:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26] wire _route_arbiter_io_in_1_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_2_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_3_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_4_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_5_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29] wire [2:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29] wire _input_buffer_io_deq_0_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_5_bits_payload; // @[InputUnit.scala:181:28] reg [2:0] states_0_g; // @[InputUnit.scala:192:19] reg states_0_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_0_vc_sel_0_0; // @[InputUnit.scala:192:19] reg [1:0] states_0_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_0_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_0_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_0_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_0_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_1_g; // @[InputUnit.scala:192:19] reg states_1_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_0; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_1; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_1_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_1_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_2_g; // @[InputUnit.scala:192:19] reg states_2_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_2; // @[InputUnit.scala:192:19] reg [1:0] states_2_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_2_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_2_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_2_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_2_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_3_g; // @[InputUnit.scala:192:19] reg states_3_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_3; // @[InputUnit.scala:192:19] reg [1:0] states_3_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_3_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_3_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_3_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_3_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_4_g; // @[InputUnit.scala:192:19] reg states_4_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_4; // @[InputUnit.scala:192:19] reg [1:0] states_4_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_4_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_4_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_4_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_4_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_5_g; // @[InputUnit.scala:192:19] reg states_5_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_5; // @[InputUnit.scala:192:19] reg [1:0] states_5_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_5_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_5_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_5_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_5_flow_egress_node_id; // @[InputUnit.scala:192:19] wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30] wire route_arbiter_io_in_0_valid = states_0_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_1_valid = states_1_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_2_valid = states_2_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_3_valid = states_3_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_4_valid = states_4_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_5_valid = states_5_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] reg [5:0] mask; // @[InputUnit.scala:250:21] wire [5:0] _vcalloc_filter_T_3 = {vcalloc_vals_5, vcalloc_vals_4, vcalloc_vals_3, vcalloc_vals_2, vcalloc_vals_1, vcalloc_vals_0} & ~mask; // @[InputUnit.scala:250:21, :253:{80,87,89}, :266:32] wire [11:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 12'h1 : _vcalloc_filter_T_3[1] ? 12'h2 : _vcalloc_filter_T_3[2] ? 12'h4 : _vcalloc_filter_T_3[3] ? 12'h8 : _vcalloc_filter_T_3[4] ? 12'h10 : _vcalloc_filter_T_3[5] ? 12'h20 : vcalloc_vals_0 ? 12'h40 : vcalloc_vals_1 ? 12'h80 : vcalloc_vals_2 ? 12'h100 : vcalloc_vals_3 ? 12'h200 : vcalloc_vals_4 ? 12'h400 : {vcalloc_vals_5, 11'h0}; // @[OneHot.scala:85:71] wire [5:0] vcalloc_sel = vcalloc_filter[5:0] | vcalloc_filter[11:6]; // @[Mux.scala:50:70] wire io_vcalloc_req_valid_0 = vcalloc_vals_0 | vcalloc_vals_1 | vcalloc_vals_2 | vcalloc_vals_3 | vcalloc_vals_4 | vcalloc_vals_5; // @[package.scala:81:59] assign vcalloc_vals_0 = states_0_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_1 = states_1_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_2 = states_2_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_3 = states_3_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_4 = states_4_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_5 = states_5_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] wire _GEN_0 = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35] wire _GEN_1 = _GEN_0 & vcalloc_sel[0]; // @[Mux.scala:32:36] wire _GEN_2 = _GEN_0 & vcalloc_sel[1]; // @[Mux.scala:32:36] wire _GEN_3 = _GEN_0 & vcalloc_sel[2]; // @[Mux.scala:32:36] wire _GEN_4 = _GEN_0 & vcalloc_sel[3]; // @[Mux.scala:32:36] wire _GEN_5 = _GEN_0 & vcalloc_sel[4]; // @[Mux.scala:32:36] wire _GEN_6 = _GEN_0 & vcalloc_sel[5]; // @[Mux.scala:32:36]
Generate the Verilog code corresponding to the following Chisel files. File RecFNToRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import consts._ class RecFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val in = Input(Bits((inExpWidth + inSigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawIn = rawFloatFromRecFN(inExpWidth, inSigWidth, io.in); if ((inExpWidth == outExpWidth) && (inSigWidth <= outSigWidth)) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- io.out := io.in<<(outSigWidth - inSigWidth) io.exceptionFlags := isSigNaNRawFloat(rawIn) ## 0.U(4.W) } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( inExpWidth, inSigWidth, outExpWidth, outSigWidth, flRoundOpt_sigMSBitAlwaysZero )) roundAnyRawFNToRecFN.io.invalidExc := isSigNaNRawFloat(rawIn) roundAnyRawFNToRecFN.io.infiniteExc := false.B roundAnyRawFNToRecFN.io.in := rawIn roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags } } File rawFloatFromRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ /*---------------------------------------------------------------------------- | In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be | set. *----------------------------------------------------------------------------*/ object rawFloatFromRecFN { def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat = { val exp = in(expWidth + sigWidth - 1, sigWidth - 1) val isZero = exp(expWidth, expWidth - 2) === 0.U val isSpecial = exp(expWidth, expWidth - 1) === 3.U val out = Wire(new RawFloat(expWidth, sigWidth)) out.isNaN := isSpecial && exp(expWidth - 2) out.isInf := isSpecial && ! exp(expWidth - 2) out.isZero := isZero out.sign := in(expWidth + sigWidth) out.sExp := exp.zext out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0) out } }
module RecFNToRecFN_178( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands */ class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def *(t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def *(t: UInt) = self * t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros | ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def *(t: SInt) = self * t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros | ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid || output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def *(t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def *(t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }
module MacUnit_247( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Fragmenter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, BufferParams, IdRange, TransferSizes} import freechips.rocketchip.util.{Repeater, OH1ToUInt, UIntToOH1} import scala.math.min import freechips.rocketchip.util.DataToAugmentedData object EarlyAck { sealed trait T case object AllPuts extends T case object PutFulls extends T case object None extends T } // minSize: minimum size of transfers supported by all outward managers // maxSize: maximum size of transfers supported after the Fragmenter is applied // alwaysMin: fragment all requests down to minSize (else fragment to maximum supported by manager) // earlyAck: should a multibeat Put should be acknowledged on the first beat or last beat // holdFirstDeny: allow the Fragmenter to unsafely combine multibeat Gets by taking the first denied for the whole burst // nameSuffix: appends a suffix to the module name // Fragmenter modifies: PutFull, PutPartial, LogicalData, Get, Hint // Fragmenter passes: ArithmeticData (truncated to minSize if alwaysMin) // Fragmenter cannot modify acquire (could livelock); thus it is unsafe to put caches on both sides class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean = false, val earlyAck: EarlyAck.T = EarlyAck.None, val holdFirstDeny: Boolean = false, val nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule { require(isPow2 (maxSize), s"TLFragmenter expects pow2(maxSize), but got $maxSize") require(isPow2 (minSize), s"TLFragmenter expects pow2(minSize), but got $minSize") require(minSize <= maxSize, s"TLFragmenter expects min <= max, but got $minSize > $maxSize") val fragmentBits = log2Ceil(maxSize / minSize) val fullBits = if (earlyAck == EarlyAck.PutFulls) 1 else 0 val toggleBits = 1 val addedBits = fragmentBits + toggleBits + fullBits def expandTransfer(x: TransferSizes, op: String) = if (!x) x else { // validate that we can apply the fragmenter correctly require (x.max >= minSize, s"TLFragmenter (with parent $parent) max transfer size $op(${x.max}) must be >= min transfer size (${minSize})") TransferSizes(x.min, maxSize) } private def noChangeRequired = minSize == maxSize private def shrinkTransfer(x: TransferSizes) = if (!alwaysMin) x else if (x.min <= minSize) TransferSizes(x.min, min(minSize, x.max)) else TransferSizes.none private def mapManager(m: TLSlaveParameters) = m.v1copy( supportsArithmetic = shrinkTransfer(m.supportsArithmetic), supportsLogical = shrinkTransfer(m.supportsLogical), supportsGet = expandTransfer(m.supportsGet, "Get"), supportsPutFull = expandTransfer(m.supportsPutFull, "PutFull"), supportsPutPartial = expandTransfer(m.supportsPutPartial, "PutParital"), supportsHint = expandTransfer(m.supportsHint, "Hint")) val node = new TLAdapterNode( // We require that all the responses are mutually FIFO // Thus we need to compact all of the masters into one big master clientFn = { c => (if (noChangeRequired) c else c.v2copy( masters = Seq(TLMasterParameters.v2( name = "TLFragmenter", sourceId = IdRange(0, if (minSize == maxSize) c.endSourceId else (c.endSourceId << addedBits)), requestFifo = true, emits = TLMasterToSlaveTransferSizes( acquireT = shrinkTransfer(c.masters.map(_.emits.acquireT) .reduce(_ mincover _)), acquireB = shrinkTransfer(c.masters.map(_.emits.acquireB) .reduce(_ mincover _)), arithmetic = shrinkTransfer(c.masters.map(_.emits.arithmetic).reduce(_ mincover _)), logical = shrinkTransfer(c.masters.map(_.emits.logical) .reduce(_ mincover _)), get = shrinkTransfer(c.masters.map(_.emits.get) .reduce(_ mincover _)), putFull = shrinkTransfer(c.masters.map(_.emits.putFull) .reduce(_ mincover _)), putPartial = shrinkTransfer(c.masters.map(_.emits.putPartial).reduce(_ mincover _)), hint = shrinkTransfer(c.masters.map(_.emits.hint) .reduce(_ mincover _)) ) )) ))}, managerFn = { m => if (noChangeRequired) m else m.v2copy(slaves = m.slaves.map(mapManager)) } ) { override def circuitIdentity = noChangeRequired } lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = (Seq("TLFragmenter") ++ nameSuffix).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => if (noChangeRequired) { out <> in } else { // All managers must share a common FIFO domain (responses might end up interleaved) val manager = edgeOut.manager val managers = manager.managers val beatBytes = manager.beatBytes val fifoId = managers(0).fifoId require (fifoId.isDefined && managers.map(_.fifoId == fifoId).reduce(_ && _)) require (!manager.anySupportAcquireB || !edgeOut.client.anySupportProbe, s"TLFragmenter (with parent $parent) can't fragment a caching client's requests into a cacheable region") require (minSize >= beatBytes, s"TLFragmenter (with parent $parent) can't support fragmenting ($minSize) to sub-beat ($beatBytes) accesses") // We can't support devices which are cached on both sides of us require (!edgeOut.manager.anySupportAcquireB || !edgeIn.client.anySupportProbe) // We can't support denied because we reassemble fragments require (!edgeOut.manager.mayDenyGet || holdFirstDeny, s"TLFragmenter (with parent $parent) can't support denials without holdFirstDeny=true") require (!edgeOut.manager.mayDenyPut || earlyAck == EarlyAck.None) /* The Fragmenter is a bit tricky, because there are 5 sizes in play: * max size -- the maximum transfer size possible * orig size -- the original pre-fragmenter size * frag size -- the modified post-fragmenter size * min size -- the threshold below which frag=orig * beat size -- the amount transfered on any given beat * * The relationships are as follows: * max >= orig >= frag * max > min >= beat * It IS possible that orig <= min (then frag=orig; ie: no fragmentation) * * The fragment# (sent via TL.source) is measured in multiples of min size. * Meanwhile, to track the progress, counters measure in multiples of beat size. * * Here is an example of a bus with max=256, min=8, beat=4 and a device supporting 16. * * in.A out.A (frag#) out.D (frag#) in.D gen# ack# * get64 get16 6 ackD16 6 ackD64 12 15 * ackD16 6 ackD64 14 * ackD16 6 ackD64 13 * ackD16 6 ackD64 12 * get16 4 ackD16 4 ackD64 8 11 * ackD16 4 ackD64 10 * ackD16 4 ackD64 9 * ackD16 4 ackD64 8 * get16 2 ackD16 2 ackD64 4 7 * ackD16 2 ackD64 6 * ackD16 2 ackD64 5 * ackD16 2 ackD64 4 * get16 0 ackD16 0 ackD64 0 3 * ackD16 0 ackD64 2 * ackD16 0 ackD64 1 * ackD16 0 ackD64 0 * * get8 get8 0 ackD8 0 ackD8 0 1 * ackD8 0 ackD8 0 * * get4 get4 0 ackD4 0 ackD4 0 0 * get1 get1 0 ackD1 0 ackD1 0 0 * * put64 put16 6 15 * put64 put16 6 14 * put64 put16 6 13 * put64 put16 6 ack16 6 12 12 * put64 put16 4 11 * put64 put16 4 10 * put64 put16 4 9 * put64 put16 4 ack16 4 8 8 * put64 put16 2 7 * put64 put16 2 6 * put64 put16 2 5 * put64 put16 2 ack16 2 4 4 * put64 put16 0 3 * put64 put16 0 2 * put64 put16 0 1 * put64 put16 0 ack16 0 ack64 0 0 * * put8 put8 0 1 * put8 put8 0 ack8 0 ack8 0 0 * * put4 put4 0 ack4 0 ack4 0 0 * put1 put1 0 ack1 0 ack1 0 0 */ val counterBits = log2Up(maxSize/beatBytes) val maxDownSize = if (alwaysMin) minSize else min(manager.maxTransfer, maxSize) // Consider the following waveform for two 4-beat bursts: // ---A----A------------ // -------D-----DDD-DDDD // Under TL rules, the second A can use the same source as the first A, // because the source is released for reuse on the first response beat. // // However, if we fragment the requests, it looks like this: // ---3210-3210--------- // -------3-----210-3210 // ... now we've broken the rules because 210 are twice inflight. // // This phenomenon means we can have essentially 2*maxSize/minSize-1 // fragmented transactions in flight per original transaction source. // // To keep the source unique, we encode the beat counter in the low // bits of the source. To solve the overlap, we use a toggle bit. // Whatever toggle bit the D is reassembling, A will use the opposite. // First, handle the return path val acknum = RegInit(0.U(counterBits.W)) val dOrig = Reg(UInt()) val dToggle = RegInit(false.B) val dFragnum = out.d.bits.source(fragmentBits-1, 0) val dFirst = acknum === 0.U val dLast = dFragnum === 0.U // only for AccessAck (!Data) val dsizeOH = UIntToOH (out.d.bits.size, log2Ceil(maxDownSize)+1) val dsizeOH1 = UIntToOH1(out.d.bits.size, log2Up(maxDownSize)) val dHasData = edgeOut.hasData(out.d.bits) // calculate new acknum val acknum_fragment = dFragnum << log2Ceil(minSize/beatBytes) val acknum_size = dsizeOH1 >> log2Ceil(beatBytes) assert (!out.d.valid || (acknum_fragment & acknum_size) === 0.U) val dFirst_acknum = acknum_fragment | Mux(dHasData, acknum_size, 0.U) val ack_decrement = Mux(dHasData, 1.U, dsizeOH >> log2Ceil(beatBytes)) // calculate the original size val dFirst_size = OH1ToUInt((dFragnum << log2Ceil(minSize)) | dsizeOH1) when (out.d.fire) { acknum := Mux(dFirst, dFirst_acknum, acknum - ack_decrement) when (dFirst) { dOrig := dFirst_size dToggle := out.d.bits.source(fragmentBits) } } // Swallow up non-data ack fragments val doEarlyAck = earlyAck match { case EarlyAck.AllPuts => true.B case EarlyAck.PutFulls => out.d.bits.source(fragmentBits+1) case EarlyAck.None => false.B } val drop = !dHasData && !Mux(doEarlyAck, dFirst, dLast) out.d.ready := in.d.ready || drop in.d.valid := out.d.valid && !drop in.d.bits := out.d.bits // pass most stuff unchanged in.d.bits.source := out.d.bits.source >> addedBits in.d.bits.size := Mux(dFirst, dFirst_size, dOrig) if (edgeOut.manager.mayDenyPut) { val r_denied = Reg(Bool()) val d_denied = (!dFirst && r_denied) || out.d.bits.denied when (out.d.fire) { r_denied := d_denied } in.d.bits.denied := d_denied } if (edgeOut.manager.mayDenyGet) { // Take denied only from the first beat and hold that value val d_denied = out.d.bits.denied holdUnless dFirst when (dHasData) { in.d.bits.denied := d_denied in.d.bits.corrupt := d_denied || out.d.bits.corrupt } } // What maximum transfer sizes do downstream devices support? val maxArithmetics = managers.map(_.supportsArithmetic.max) val maxLogicals = managers.map(_.supportsLogical.max) val maxGets = managers.map(_.supportsGet.max) val maxPutFulls = managers.map(_.supportsPutFull.max) val maxPutPartials = managers.map(_.supportsPutPartial.max) val maxHints = managers.map(m => if (m.supportsHint) maxDownSize else 0) // We assume that the request is valid => size 0 is impossible val lgMinSize = log2Ceil(minSize).U val maxLgArithmetics = maxArithmetics.map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgLogicals = maxLogicals .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgGets = maxGets .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgPutFulls = maxPutFulls .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgPutPartials = maxPutPartials.map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgHints = maxHints .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) // Make the request repeatable val repeater = Module(new Repeater(in.a.bits)) repeater.io.enq <> in.a val in_a = repeater.io.deq // If this is infront of a single manager, these become constants val find = manager.findFast(edgeIn.address(in_a.bits)) val maxLgArithmetic = Mux1H(find, maxLgArithmetics) val maxLgLogical = Mux1H(find, maxLgLogicals) val maxLgGet = Mux1H(find, maxLgGets) val maxLgPutFull = Mux1H(find, maxLgPutFulls) val maxLgPutPartial = Mux1H(find, maxLgPutPartials) val maxLgHint = Mux1H(find, maxLgHints) val limit = if (alwaysMin) lgMinSize else MuxLookup(in_a.bits.opcode, lgMinSize)(Array( TLMessages.PutFullData -> maxLgPutFull, TLMessages.PutPartialData -> maxLgPutPartial, TLMessages.ArithmeticData -> maxLgArithmetic, TLMessages.LogicalData -> maxLgLogical, TLMessages.Get -> maxLgGet, TLMessages.Hint -> maxLgHint)) val aOrig = in_a.bits.size val aFrag = Mux(aOrig > limit, limit, aOrig) val aOrigOH1 = UIntToOH1(aOrig, log2Ceil(maxSize)) val aFragOH1 = UIntToOH1(aFrag, log2Up(maxDownSize)) val aHasData = edgeIn.hasData(in_a.bits) val aMask = Mux(aHasData, 0.U, aFragOH1) val gennum = RegInit(0.U(counterBits.W)) val aFirst = gennum === 0.U val old_gennum1 = Mux(aFirst, aOrigOH1 >> log2Ceil(beatBytes), gennum - 1.U) val new_gennum = ~(~old_gennum1 | (aMask >> log2Ceil(beatBytes))) // ~(~x|y) is width safe val aFragnum = ~(~(old_gennum1 >> log2Ceil(minSize/beatBytes)) | (aFragOH1 >> log2Ceil(minSize))) val aLast = aFragnum === 0.U val aToggle = !Mux(aFirst, dToggle, RegEnable(dToggle, aFirst)) val aFull = if (earlyAck == EarlyAck.PutFulls) Some(in_a.bits.opcode === TLMessages.PutFullData) else None when (out.a.fire) { gennum := new_gennum } repeater.io.repeat := !aHasData && aFragnum =/= 0.U out.a <> in_a out.a.bits.address := in_a.bits.address | ~(old_gennum1 << log2Ceil(beatBytes) | ~aOrigOH1 | aFragOH1 | (minSize-1).U) out.a.bits.source := Cat(Seq(in_a.bits.source) ++ aFull ++ Seq(aToggle.asUInt, aFragnum)) out.a.bits.size := aFrag // Optimize away some of the Repeater's registers assert (!repeater.io.full || !aHasData) out.a.bits.data := in.a.bits.data val fullMask = ((BigInt(1) << beatBytes) - 1).U assert (!repeater.io.full || in_a.bits.mask === fullMask) out.a.bits.mask := Mux(repeater.io.full, fullMask, in.a.bits.mask) out.a.bits.user.waiveAll :<= in.a.bits.user.subset(_.isData) // Tie off unused channels in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLFragmenter { def apply(minSize: Int, maxSize: Int, alwaysMin: Boolean = false, earlyAck: EarlyAck.T = EarlyAck.None, holdFirstDeny: Boolean = false, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { if (minSize <= maxSize) { val fragmenter = LazyModule(new TLFragmenter(minSize, maxSize, alwaysMin, earlyAck, holdFirstDeny, nameSuffix)) fragmenter.node } else { TLEphemeralNode()(ValName("no_fragmenter")) } } def apply(wrapper: TLBusWrapper, nameSuffix: Option[String])(implicit p: Parameters): TLNode = apply(wrapper.beatBytes, wrapper.blockBytes, nameSuffix = nameSuffix) def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper, None) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("Fragmenter")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes)) (ram.node := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLDelayer(0.1) := TLFragmenter(ramBeatBytes, maxSize, earlyAck = EarlyAck.AllPuts) := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLFragmenter(ramBeatBytes, maxSize/2) := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := model.node := fuzz.node) lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMFragmenterTest(ramBeatBytes: Int, maxSize: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMFragmenter(ramBeatBytes,maxSize,txns)).module) io.finished := dut.io.finished dut.io.start := io.start } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} |acquireB = ${acquireB} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT || supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED || supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED || supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB || supportsGet, w = supportsAcquireT || supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} |Slave Address = ${address} |supports = ${supports.infoString} | |""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ || _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_||_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ || _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B || s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_||_) }.foldLeft(false.B)(_||_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} |visibility = ${visibility} |emits = ${emits.infoString} |sourceId = ${sourceId} | |""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ || _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ || _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ || _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ || _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ || _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ || _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ || _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ || _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_||_) }.foldLeft(false.B)(_||_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE || x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps */ class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }
module TLFragmenter_UART( // @[Fragmenter.scala:92:9] input clock, // @[Fragmenter.scala:92:9] input reset, // @[Fragmenter.scala:92:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [11:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [11:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire _repeater_io_full; // @[Fragmenter.scala:274:30] wire [2:0] _repeater_io_deq_bits_opcode; // @[Fragmenter.scala:274:30] wire [2:0] _repeater_io_deq_bits_size; // @[Fragmenter.scala:274:30] wire [7:0] _repeater_io_deq_bits_source; // @[Fragmenter.scala:274:30] wire [28:0] _repeater_io_deq_bits_address; // @[Fragmenter.scala:274:30] wire [7:0] _repeater_io_deq_bits_mask; // @[Fragmenter.scala:274:30] wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_in_a_bits_param_0 = auto_anon_in_a_bits_param; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[Fragmenter.scala:92:9] wire [7:0] auto_anon_in_a_bits_source_0 = auto_anon_in_a_bits_source; // @[Fragmenter.scala:92:9] wire [28:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[Fragmenter.scala:92:9] wire [7:0] auto_anon_in_a_bits_mask_0 = auto_anon_in_a_bits_mask; // @[Fragmenter.scala:92:9] wire [63:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[Fragmenter.scala:92:9] wire auto_anon_in_a_bits_corrupt_0 = auto_anon_in_a_bits_corrupt; // @[Fragmenter.scala:92:9] wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[Fragmenter.scala:92:9] wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[Fragmenter.scala:92:9] wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[Fragmenter.scala:92:9] wire [1:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[Fragmenter.scala:92:9] wire [11:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[Fragmenter.scala:92:9] wire [63:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[Fragmenter.scala:92:9] wire [1:0] auto_anon_in_d_bits_param = 2'h0; // @[Fragmenter.scala:92:9] wire [1:0] auto_anon_out_d_bits_param = 2'h0; // @[Fragmenter.scala:92:9] wire [1:0] anonIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] anonOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire auto_anon_in_d_bits_sink = 1'h0; // @[Fragmenter.scala:92:9] wire auto_anon_in_d_bits_denied = 1'h0; // @[Fragmenter.scala:92:9] wire auto_anon_in_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:92:9] wire auto_anon_out_d_bits_sink = 1'h0; // @[Fragmenter.scala:92:9] wire auto_anon_out_d_bits_denied = 1'h0; // @[Fragmenter.scala:92:9] wire auto_anon_out_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:92:9] wire anonIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire anonOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire anonOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17] wire anonOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire acknum_size = 1'h0; // @[Fragmenter.scala:213:36] wire _dFirst_acknum_T = 1'h0; // @[Fragmenter.scala:215:50] wire _new_gennum_T_1 = 1'h0; // @[Fragmenter.scala:306:50] wire _aFragnum_T_2 = 1'h0; // @[Fragmenter.scala:307:84] wire [1:0] _limit_T_1 = 2'h3; // @[Fragmenter.scala:288:49] wire [1:0] _limit_T_3 = 2'h3; // @[Fragmenter.scala:288:49] wire [1:0] _limit_T_5 = 2'h3; // @[Fragmenter.scala:288:49] wire [1:0] _limit_T_7 = 2'h3; // @[Fragmenter.scala:288:49] wire [1:0] _limit_T_9 = 2'h3; // @[Fragmenter.scala:288:49] wire [1:0] limit = 2'h3; // @[Fragmenter.scala:288:49] wire _find_T_4 = 1'h1; // @[Parameters.scala:137:59] wire find_0 = 1'h1; // @[Parameters.scala:616:12] wire [29:0] _find_T_2 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] _find_T_3 = 30'h0; // @[Parameters.scala:137:46] wire anonIn_a_ready; // @[MixedNode.scala:551:17] wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[Fragmenter.scala:92:9] wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[Fragmenter.scala:92:9] wire [2:0] anonIn_a_bits_param = auto_anon_in_a_bits_param_0; // @[Fragmenter.scala:92:9] wire [2:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[Fragmenter.scala:92:9] wire [7:0] anonIn_a_bits_source = auto_anon_in_a_bits_source_0; // @[Fragmenter.scala:92:9] wire [28:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[Fragmenter.scala:92:9] wire [7:0] anonIn_a_bits_mask = auto_anon_in_a_bits_mask_0; // @[Fragmenter.scala:92:9] wire [63:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[Fragmenter.scala:92:9] wire anonIn_a_bits_corrupt = auto_anon_in_a_bits_corrupt_0; // @[Fragmenter.scala:92:9] wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[Fragmenter.scala:92:9] wire anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [7:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[Fragmenter.scala:92:9] wire anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [1:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [11:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[Fragmenter.scala:92:9] wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[Fragmenter.scala:92:9] wire [1:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[Fragmenter.scala:92:9] wire [11:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[Fragmenter.scala:92:9] wire [63:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[Fragmenter.scala:92:9] wire auto_anon_in_a_ready_0; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_in_d_bits_opcode_0; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_in_d_bits_size_0; // @[Fragmenter.scala:92:9] wire [7:0] auto_anon_in_d_bits_source_0; // @[Fragmenter.scala:92:9] wire [63:0] auto_anon_in_d_bits_data_0; // @[Fragmenter.scala:92:9] wire auto_anon_in_d_valid_0; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_out_a_bits_opcode_0; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_out_a_bits_param_0; // @[Fragmenter.scala:92:9] wire [1:0] auto_anon_out_a_bits_size_0; // @[Fragmenter.scala:92:9] wire [11:0] auto_anon_out_a_bits_source_0; // @[Fragmenter.scala:92:9] wire [28:0] auto_anon_out_a_bits_address_0; // @[Fragmenter.scala:92:9] wire [7:0] auto_anon_out_a_bits_mask_0; // @[Fragmenter.scala:92:9] wire [63:0] auto_anon_out_a_bits_data_0; // @[Fragmenter.scala:92:9] wire auto_anon_out_a_bits_corrupt_0; // @[Fragmenter.scala:92:9] wire auto_anon_out_a_valid_0; // @[Fragmenter.scala:92:9] wire auto_anon_out_d_ready_0; // @[Fragmenter.scala:92:9] assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[Fragmenter.scala:92:9] assign anonOut_a_bits_data = anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] wire _anonIn_d_valid_T_1; // @[Fragmenter.scala:236:36] assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[Fragmenter.scala:92:9] assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[Fragmenter.scala:92:9] wire [2:0] _anonIn_d_bits_size_T; // @[Fragmenter.scala:239:32] assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[Fragmenter.scala:92:9] wire [7:0] _anonIn_d_bits_source_T; // @[Fragmenter.scala:238:47] assign auto_anon_in_d_bits_source_0 = anonIn_d_bits_source; // @[Fragmenter.scala:92:9] assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[Fragmenter.scala:92:9] wire [11:0] _anonOut_a_bits_source_T; // @[Fragmenter.scala:317:33] assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[Fragmenter.scala:92:9] wire [28:0] _anonOut_a_bits_address_T_6; // @[Fragmenter.scala:316:49] assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[Fragmenter.scala:92:9] wire [7:0] _anonOut_a_bits_mask_T; // @[Fragmenter.scala:325:31] assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[Fragmenter.scala:92:9] wire _anonOut_d_ready_T; // @[Fragmenter.scala:235:35] assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[Fragmenter.scala:92:9] assign anonIn_d_bits_opcode = anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] dsizeOH_shiftAmount = anonOut_d_bits_size; // @[OneHot.scala:64:49] assign anonIn_d_bits_data = anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] reg [2:0] acknum; // @[Fragmenter.scala:201:29] reg [2:0] dOrig; // @[Fragmenter.scala:202:24] reg dToggle; // @[Fragmenter.scala:203:30] wire [2:0] dFragnum = anonOut_d_bits_source[2:0]; // @[Fragmenter.scala:204:41] wire [2:0] acknum_fragment = dFragnum; // @[Fragmenter.scala:204:41, :212:40] wire dFirst = acknum == 3'h0; // @[Fragmenter.scala:201:29, :205:29] wire dLast = dFragnum == 3'h0; // @[Fragmenter.scala:204:41, :206:30] wire _drop_T_1 = dLast; // @[Fragmenter.scala:206:30, :234:37] wire [3:0] _dsizeOH_T = 4'h1 << dsizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] dsizeOH = _dsizeOH_T; // @[OneHot.scala:65:{12,27}] wire [5:0] _dsizeOH1_T = 6'h7 << anonOut_d_bits_size; // @[package.scala:243:71] wire [2:0] _dsizeOH1_T_1 = _dsizeOH1_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] dsizeOH1 = ~_dsizeOH1_T_1; // @[package.scala:243:{46,76}] wire dHasData = anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire [2:0] dFirst_acknum = acknum_fragment; // @[Fragmenter.scala:212:40, :215:45] wire _ack_decrement_T = dsizeOH[3]; // @[OneHot.scala:65:27] wire ack_decrement = dHasData | _ack_decrement_T; // @[Fragmenter.scala:216:{32,56}] wire [5:0] _dFirst_size_T = {dFragnum, 3'h0}; // @[Fragmenter.scala:204:41, :218:47] wire [5:0] _dFirst_size_T_1 = {_dFirst_size_T[5:3], _dFirst_size_T[2:0] | dsizeOH1}; // @[package.scala:243:46] wire [6:0] _dFirst_size_T_2 = {_dFirst_size_T_1, 1'h0}; // @[package.scala:241:35] wire [6:0] _dFirst_size_T_3 = {_dFirst_size_T_2[6:1], 1'h1}; // @[package.scala:241:{35,40}] wire [6:0] _dFirst_size_T_4 = {1'h0, _dFirst_size_T_1}; // @[package.scala:241:53] wire [6:0] _dFirst_size_T_5 = ~_dFirst_size_T_4; // @[package.scala:241:{49,53}] wire [6:0] _dFirst_size_T_6 = _dFirst_size_T_3 & _dFirst_size_T_5; // @[package.scala:241:{40,47,49}] wire [2:0] dFirst_size_hi = _dFirst_size_T_6[6:4]; // @[OneHot.scala:30:18] wire [3:0] dFirst_size_lo = _dFirst_size_T_6[3:0]; // @[OneHot.scala:31:18] wire _dFirst_size_T_7 = |dFirst_size_hi; // @[OneHot.scala:30:18, :32:14] wire [3:0] _dFirst_size_T_8 = {1'h0, dFirst_size_hi} | dFirst_size_lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] dFirst_size_hi_1 = _dFirst_size_T_8[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] dFirst_size_lo_1 = _dFirst_size_T_8[1:0]; // @[OneHot.scala:31:18, :32:28] wire _dFirst_size_T_9 = |dFirst_size_hi_1; // @[OneHot.scala:30:18, :32:14] wire [1:0] _dFirst_size_T_10 = dFirst_size_hi_1 | dFirst_size_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire _dFirst_size_T_11 = _dFirst_size_T_10[1]; // @[OneHot.scala:32:28] wire [1:0] _dFirst_size_T_12 = {_dFirst_size_T_9, _dFirst_size_T_11}; // @[OneHot.scala:32:{10,14}] wire [2:0] dFirst_size = {_dFirst_size_T_7, _dFirst_size_T_12}; // @[OneHot.scala:32:{10,14}] wire [3:0] _acknum_T = {1'h0, acknum} - {3'h0, ack_decrement}; // @[Fragmenter.scala:201:29, :216:32, :221:55] wire [2:0] _acknum_T_1 = _acknum_T[2:0]; // @[Fragmenter.scala:221:55] wire [2:0] _acknum_T_2 = dFirst ? dFirst_acknum : _acknum_T_1; // @[Fragmenter.scala:205:29, :215:45, :221:{24,55}] wire _dToggle_T = anonOut_d_bits_source[3]; // @[Fragmenter.scala:224:41] wire _drop_T = ~dHasData; // @[Fragmenter.scala:234:20] wire _drop_T_2 = ~_drop_T_1; // @[Fragmenter.scala:234:{33,37}] wire drop = _drop_T & _drop_T_2; // @[Fragmenter.scala:234:{20,30,33}] assign _anonOut_d_ready_T = anonIn_d_ready | drop; // @[Fragmenter.scala:234:30, :235:35] assign anonOut_d_ready = _anonOut_d_ready_T; // @[Fragmenter.scala:235:35] wire _anonIn_d_valid_T = ~drop; // @[Fragmenter.scala:234:30, :236:39] assign _anonIn_d_valid_T_1 = anonOut_d_valid & _anonIn_d_valid_T; // @[Fragmenter.scala:236:{36,39}] assign anonIn_d_valid = _anonIn_d_valid_T_1; // @[Fragmenter.scala:236:36] assign _anonIn_d_bits_source_T = anonOut_d_bits_source[11:4]; // @[Fragmenter.scala:238:47] assign anonIn_d_bits_source = _anonIn_d_bits_source_T; // @[Fragmenter.scala:238:47] assign _anonIn_d_bits_size_T = dFirst ? dFirst_size : dOrig; // @[OneHot.scala:32:10] assign anonIn_d_bits_size = _anonIn_d_bits_size_T; // @[Fragmenter.scala:239:32] wire [28:0] _find_T; // @[Parameters.scala:137:31] wire [29:0] _find_T_1 = {1'h0, _find_T}; // @[Parameters.scala:137:{31,41}] wire _limit_T = _repeater_io_deq_bits_opcode == 3'h0; // @[Fragmenter.scala:274:30, :288:49] wire _limit_T_2 = _repeater_io_deq_bits_opcode == 3'h1; // @[Fragmenter.scala:274:30, :288:49] wire _limit_T_4 = _repeater_io_deq_bits_opcode == 3'h2; // @[Fragmenter.scala:274:30, :288:49] wire _limit_T_6 = _repeater_io_deq_bits_opcode == 3'h3; // @[Fragmenter.scala:274:30, :288:49] wire _limit_T_8 = _repeater_io_deq_bits_opcode == 3'h4; // @[Fragmenter.scala:274:30, :288:49] wire _limit_T_10 = _repeater_io_deq_bits_opcode == 3'h5; // @[Fragmenter.scala:274:30, :288:49] wire _aFrag_T = _repeater_io_deq_bits_size[2]; // @[Fragmenter.scala:274:30, :297:31] wire [2:0] aFrag = _aFrag_T ? 3'h3 : _repeater_io_deq_bits_size; // @[Fragmenter.scala:274:30, :297:{24,31}] wire [12:0] _aOrigOH1_T = 13'h3F << _repeater_io_deq_bits_size; // @[package.scala:243:71] wire [5:0] _aOrigOH1_T_1 = _aOrigOH1_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] aOrigOH1 = ~_aOrigOH1_T_1; // @[package.scala:243:{46,76}] wire [9:0] _aFragOH1_T = 10'h7 << aFrag; // @[package.scala:243:71] wire [2:0] _aFragOH1_T_1 = _aFragOH1_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] aFragOH1 = ~_aFragOH1_T_1; // @[package.scala:243:{46,76}] wire _aHasData_opdata_T = _repeater_io_deq_bits_opcode[2]; // @[Fragmenter.scala:274:30] wire aHasData = ~_aHasData_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] aMask = aHasData ? 3'h0 : aFragOH1; // @[package.scala:243:46] reg [2:0] gennum; // @[Fragmenter.scala:303:29] wire aFirst = gennum == 3'h0; // @[Fragmenter.scala:303:29, :304:29] wire [2:0] _old_gennum1_T = aOrigOH1[5:3]; // @[package.scala:243:46] wire [3:0] _old_gennum1_T_1 = {1'h0, gennum} - 4'h1; // @[Fragmenter.scala:303:29, :305:79] wire [2:0] _old_gennum1_T_2 = _old_gennum1_T_1[2:0]; // @[Fragmenter.scala:305:79] wire [2:0] old_gennum1 = aFirst ? _old_gennum1_T : _old_gennum1_T_2; // @[Fragmenter.scala:304:29, :305:{30,48,79}] wire [2:0] _aFragnum_T = old_gennum1; // @[Fragmenter.scala:305:30, :307:40] wire [2:0] _new_gennum_T = ~old_gennum1; // @[Fragmenter.scala:305:30, :306:28] wire [2:0] _new_gennum_T_2 = _new_gennum_T; // @[Fragmenter.scala:306:{28,41}] wire [2:0] new_gennum = ~_new_gennum_T_2; // @[Fragmenter.scala:306:{26,41}] wire [2:0] _aFragnum_T_1 = ~_aFragnum_T; // @[Fragmenter.scala:307:{26,40}] wire [2:0] _aFragnum_T_3 = _aFragnum_T_1; // @[Fragmenter.scala:307:{26,72}] wire [2:0] aFragnum = ~_aFragnum_T_3; // @[Fragmenter.scala:307:{24,72}] wire aLast = ~(|aFragnum); // @[Fragmenter.scala:307:24, :308:30] reg aToggle_r; // @[Fragmenter.scala:309:54] wire _aToggle_T = aFirst ? dToggle : aToggle_r; // @[Fragmenter.scala:203:30, :304:29, :309:{27,54}] wire aToggle = ~_aToggle_T; // @[Fragmenter.scala:309:{23,27}] wire _repeater_io_repeat_T = ~aHasData; // @[Fragmenter.scala:314:31] wire _repeater_io_repeat_T_1 = |aFragnum; // @[Fragmenter.scala:307:24, :308:30, :314:53] wire _repeater_io_repeat_T_2 = _repeater_io_repeat_T & _repeater_io_repeat_T_1; // @[Fragmenter.scala:314:{31,41,53}] wire [5:0] _anonOut_a_bits_address_T = {old_gennum1, 3'h0}; // @[Fragmenter.scala:305:30, :316:65] wire [5:0] _anonOut_a_bits_address_T_1 = ~aOrigOH1; // @[package.scala:243:46] wire [5:0] _anonOut_a_bits_address_T_2 = _anonOut_a_bits_address_T | _anonOut_a_bits_address_T_1; // @[Fragmenter.scala:316:{65,88,90}] wire [5:0] _anonOut_a_bits_address_T_3 = {_anonOut_a_bits_address_T_2[5:3], _anonOut_a_bits_address_T_2[2:0] | aFragOH1}; // @[package.scala:243:46] wire [5:0] _anonOut_a_bits_address_T_4 = {_anonOut_a_bits_address_T_3[5:3], 3'h7}; // @[Fragmenter.scala:316:{100,111}] wire [5:0] _anonOut_a_bits_address_T_5 = ~_anonOut_a_bits_address_T_4; // @[Fragmenter.scala:316:{51,111}] assign _anonOut_a_bits_address_T_6 = {_repeater_io_deq_bits_address[28:6], _repeater_io_deq_bits_address[5:0] | _anonOut_a_bits_address_T_5}; // @[Fragmenter.scala:274:30, :316:{49,51}] assign anonOut_a_bits_address = _anonOut_a_bits_address_T_6; // @[Fragmenter.scala:316:49] wire [8:0] anonOut_a_bits_source_hi = {_repeater_io_deq_bits_source, aToggle}; // @[Fragmenter.scala:274:30, :309:23, :317:33] assign _anonOut_a_bits_source_T = {anonOut_a_bits_source_hi, aFragnum}; // @[Fragmenter.scala:307:24, :317:33] assign anonOut_a_bits_source = _anonOut_a_bits_source_T; // @[Fragmenter.scala:317:33] assign anonOut_a_bits_size = aFrag[1:0]; // @[Fragmenter.scala:297:24, :318:25]
Generate the Verilog code corresponding to the following Chisel files. File SimpleHellaCacheIF.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.{Valid,Decoupled,Queue,log2Up,OHToUInt,UIntToOH,PriorityEncoderOH,Arbiter,RegEnable,Cat} import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ /** * This module buffers requests made by the SimpleHellaCacheIF in case they * are nacked. Nacked requests must be replayed in order, and no other requests * must be allowed to go through until the replayed requests are successfully * completed. */ class SimpleHellaCacheIFReplayQueue(depth: Int) (implicit val p: Parameters) extends Module with HasL1HellaCacheParameters { val io = IO(new Bundle { val req = Flipped(Decoupled(new HellaCacheReq)) val nack = Flipped(Valid(Bits(coreParams.dcacheReqTagBits.W))) val resp = Flipped(Valid(new HellaCacheResp)) val replay = Decoupled(new HellaCacheReq) }) // Registers to store the sent request // When a request is sent the first time, // it is stored in one of the reqs registers // and the corresponding inflight bit is set. // The reqs register will be deallocated once the request is // successfully completed. val inflight = RegInit(0.U(depth.W)) val reqs = Reg(Vec(depth, new HellaCacheReq)) // The nack queue stores the index of nacked requests (in the reqs vector) // in the order that they were nacked. A request is enqueued onto nackq // when it is newly nacked (i.e. not a nack for a previous replay). // The head of the nack queue will be replayed until it is // successfully completed, at which time the request is dequeued. // No new requests will be made or other replays attempted until the head // of the nackq is successfully completed. val nackq = Module(new Queue(UInt(log2Up(depth).W), depth)) val replaying = RegInit(false.B) val next_inflight_onehot = PriorityEncoderOH(~inflight) val next_inflight = OHToUInt(next_inflight_onehot) val next_replay = nackq.io.deq.bits val next_replay_onehot = UIntToOH(next_replay) val next_replay_req = reqs(next_replay) // Keep sending the head of the nack queue until it succeeds io.replay.valid := nackq.io.deq.valid && !replaying io.replay.bits := next_replay_req // Don't allow new requests if there is are replays waiting // or something being nacked. io.req.ready := !inflight.andR && !nackq.io.deq.valid && !io.nack.valid // Match on the tags to determine the index of nacks or responses val nack_onehot = Cat(reqs.map(_.tag === io.nack.bits).reverse) & inflight val resp_onehot = Cat(reqs.map(_.tag === io.resp.bits.tag).reverse) & inflight val replay_complete = io.resp.valid && replaying && io.resp.bits.tag === next_replay_req.tag val nack_head = io.nack.valid && nackq.io.deq.valid && io.nack.bits === next_replay_req.tag // Enqueue to the nack queue if there is a nack that is not in response to // the previous replay nackq.io.enq.valid := io.nack.valid && !nack_head nackq.io.enq.bits := OHToUInt(nack_onehot) assert(!nackq.io.enq.valid || nackq.io.enq.ready, "SimpleHellaCacheIF: ReplayQueue nack queue overflow") // Dequeue from the nack queue if the last replay was successfully completed nackq.io.deq.ready := replay_complete assert(!nackq.io.deq.ready || nackq.io.deq.valid, "SimpleHellaCacheIF: ReplayQueue nack queue underflow") // Set inflight bit when a request is made // Clear it when it is successfully completed inflight := (inflight | Mux(io.req.fire, next_inflight_onehot, 0.U)) & ~Mux(io.resp.valid, resp_onehot, 0.U) when (io.req.fire) { reqs(next_inflight) := io.req.bits } // Only one replay outstanding at a time when (io.replay.fire) { replaying := true.B } when (nack_head || replay_complete) { replaying := false.B } } // exposes a sane decoupled request interface class SimpleHellaCacheIF(implicit p: Parameters) extends Module { val io = IO(new Bundle { val requestor = Flipped(new HellaCacheIO()) val cache = new HellaCacheIO }) io <> DontCare val replayq = Module(new SimpleHellaCacheIFReplayQueue(2)) val req_arb = Module(new Arbiter(new HellaCacheReq, 2)) val req_helper = DecoupledHelper( req_arb.io.in(1).ready, replayq.io.req.ready, io.requestor.req.valid) req_arb.io.in(0) <> replayq.io.replay req_arb.io.in(1).valid := req_helper.fire(req_arb.io.in(1).ready) req_arb.io.in(1).bits := io.requestor.req.bits io.requestor.req.ready := req_helper.fire(io.requestor.req.valid) replayq.io.req.valid := req_helper.fire(replayq.io.req.ready) replayq.io.req.bits := io.requestor.req.bits val s0_req_fire = io.cache.req.fire val s1_req_fire = RegNext(s0_req_fire) val s2_req_fire = RegNext(s1_req_fire) val s1_req_tag = RegNext(io.cache.req.bits.tag) val s2_req_tag = RegNext(s1_req_tag) assert(!RegNext(io.cache.s2_nack) || !s2_req_fire || io.cache.s2_nack) assert(!io.cache.s2_nack || !io.cache.req.ready) io.cache.req <> req_arb.io.out io.cache.s1_kill := false.B io.cache.s1_data := RegEnable(req_arb.io.out.bits, s0_req_fire) io.cache.s2_kill := false.B replayq.io.nack.valid := io.cache.s2_nack && s2_req_fire replayq.io.nack.bits := s2_req_tag replayq.io.resp := io.cache.resp io.requestor.resp := io.cache.resp assert(!s2_req_fire || !io.cache.s2_xcpt.asUInt.orR, "SimpleHellaCacheIF exception") }
module SimpleHellaCacheIF( // @[SimpleHellaCacheIF.scala:95:7] input clock, // @[SimpleHellaCacheIF.scala:95:7] input reset, // @[SimpleHellaCacheIF.scala:95:7] output io_requestor_req_ready, // @[SimpleHellaCacheIF.scala:97:14] input io_requestor_req_valid, // @[SimpleHellaCacheIF.scala:97:14] input [39:0] io_requestor_req_bits_addr, // @[SimpleHellaCacheIF.scala:97:14] input [7:0] io_requestor_req_bits_tag, // @[SimpleHellaCacheIF.scala:97:14] input [4:0] io_requestor_req_bits_cmd, // @[SimpleHellaCacheIF.scala:97:14] input [2:0] io_requestor_req_bits_size, // @[SimpleHellaCacheIF.scala:97:14] input io_requestor_req_bits_signed, // @[SimpleHellaCacheIF.scala:97:14] input [1:0] io_requestor_req_bits_dprv, // @[SimpleHellaCacheIF.scala:97:14] input io_requestor_req_bits_dv, // @[SimpleHellaCacheIF.scala:97:14] input io_requestor_req_bits_phys, // @[SimpleHellaCacheIF.scala:97:14] input io_requestor_req_bits_no_alloc, // @[SimpleHellaCacheIF.scala:97:14] input io_requestor_req_bits_no_xcpt, // @[SimpleHellaCacheIF.scala:97:14] input [127:0] io_requestor_req_bits_data, // @[SimpleHellaCacheIF.scala:97:14] input [15:0] io_requestor_req_bits_mask, // @[SimpleHellaCacheIF.scala:97:14] output io_requestor_resp_valid, // @[SimpleHellaCacheIF.scala:97:14] output [7:0] io_requestor_resp_bits_tag, // @[SimpleHellaCacheIF.scala:97:14] output [127:0] io_requestor_resp_bits_data_raw, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_req_ready, // @[SimpleHellaCacheIF.scala:97:14] output io_cache_req_valid, // @[SimpleHellaCacheIF.scala:97:14] output [39:0] io_cache_req_bits_addr, // @[SimpleHellaCacheIF.scala:97:14] output [7:0] io_cache_req_bits_tag, // @[SimpleHellaCacheIF.scala:97:14] output [4:0] io_cache_req_bits_cmd, // @[SimpleHellaCacheIF.scala:97:14] output [2:0] io_cache_req_bits_size, // @[SimpleHellaCacheIF.scala:97:14] output io_cache_req_bits_signed, // @[SimpleHellaCacheIF.scala:97:14] output [1:0] io_cache_req_bits_dprv, // @[SimpleHellaCacheIF.scala:97:14] output io_cache_req_bits_dv, // @[SimpleHellaCacheIF.scala:97:14] output io_cache_req_bits_phys, // @[SimpleHellaCacheIF.scala:97:14] output io_cache_req_bits_no_alloc, // @[SimpleHellaCacheIF.scala:97:14] output io_cache_req_bits_no_xcpt, // @[SimpleHellaCacheIF.scala:97:14] output [15:0] io_cache_req_bits_mask, // @[SimpleHellaCacheIF.scala:97:14] output [127:0] io_cache_s1_data_data, // @[SimpleHellaCacheIF.scala:97:14] output [15:0] io_cache_s1_data_mask, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_s2_nack, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_resp_valid, // @[SimpleHellaCacheIF.scala:97:14] input [7:0] io_cache_resp_bits_tag, // @[SimpleHellaCacheIF.scala:97:14] input [127:0] io_cache_resp_bits_data_raw, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_s2_xcpt_ma_ld, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_s2_xcpt_ma_st, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_s2_xcpt_pf_ld, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_s2_xcpt_pf_st, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_s2_xcpt_ae_ld, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_s2_xcpt_ae_st // @[SimpleHellaCacheIF.scala:97:14] ); wire _req_arb_io_in_0_ready; // @[SimpleHellaCacheIF.scala:104:23] wire _req_arb_io_in_1_ready; // @[SimpleHellaCacheIF.scala:104:23] wire _req_arb_io_out_valid; // @[SimpleHellaCacheIF.scala:104:23] wire [7:0] _req_arb_io_out_bits_tag; // @[SimpleHellaCacheIF.scala:104:23] wire [127:0] _req_arb_io_out_bits_data; // @[SimpleHellaCacheIF.scala:104:23] wire [15:0] _req_arb_io_out_bits_mask; // @[SimpleHellaCacheIF.scala:104:23] wire _replayq_io_req_ready; // @[SimpleHellaCacheIF.scala:103:23] wire _replayq_io_replay_valid; // @[SimpleHellaCacheIF.scala:103:23] wire [39:0] _replayq_io_replay_bits_addr; // @[SimpleHellaCacheIF.scala:103:23] wire [7:0] _replayq_io_replay_bits_tag; // @[SimpleHellaCacheIF.scala:103:23] wire [4:0] _replayq_io_replay_bits_cmd; // @[SimpleHellaCacheIF.scala:103:23] wire [2:0] _replayq_io_replay_bits_size; // @[SimpleHellaCacheIF.scala:103:23] wire _replayq_io_replay_bits_signed; // @[SimpleHellaCacheIF.scala:103:23] wire [1:0] _replayq_io_replay_bits_dprv; // @[SimpleHellaCacheIF.scala:103:23] wire _replayq_io_replay_bits_dv; // @[SimpleHellaCacheIF.scala:103:23] wire _replayq_io_replay_bits_phys; // @[SimpleHellaCacheIF.scala:103:23] wire _replayq_io_replay_bits_no_alloc; // @[SimpleHellaCacheIF.scala:103:23] wire _replayq_io_replay_bits_no_xcpt; // @[SimpleHellaCacheIF.scala:103:23] wire [127:0] _replayq_io_replay_bits_data; // @[SimpleHellaCacheIF.scala:103:23] wire [15:0] _replayq_io_replay_bits_mask; // @[SimpleHellaCacheIF.scala:103:23] reg s1_req_fire; // @[SimpleHellaCacheIF.scala:119:28] reg s2_req_fire; // @[SimpleHellaCacheIF.scala:120:28] reg [7:0] s1_req_tag; // @[SimpleHellaCacheIF.scala:121:27] reg [7:0] s2_req_tag; // @[SimpleHellaCacheIF.scala:122:27] reg REG; // @[SimpleHellaCacheIF.scala:124:18] reg [127:0] io_cache_s1_data_r_data; // @[SimpleHellaCacheIF.scala:129:32] reg [15:0] io_cache_s1_data_r_mask; // @[SimpleHellaCacheIF.scala:129:32]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_388( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } } File Arbiter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ object TLArbiter { // (valids, select) => readys type Policy = (Integer, UInt, Bool) => UInt val lowestIndexFirst: Policy = (width, valids, select) => ~(leftOR(valids) << 1)(width-1, 0) val highestIndexFirst: Policy = (width, valids, select) => ~((rightOR(valids) >> 1).pad(width)) val roundRobin: Policy = (width, valids, select) => if (width == 1) 1.U(1.W) else { val valid = valids(width-1, 0) assert (valid === valids) val mask = RegInit(((BigInt(1) << width)-1).U(width-1,0)) val filter = Cat(valid & ~mask, valid) val unready = (rightOR(filter, width*2, width) >> 1) | (mask << width) val readys = ~((unready >> width) & unready(width-1, 0)) when (select && valid.orR) { mask := leftOR(readys & valid, width) } readys(width-1, 0) } def lowestFromSeq[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: Seq[DecoupledIO[T]]): Unit = { apply(lowestIndexFirst)(sink, sources.map(s => (edge.numBeats1(s.bits), s)):_*) } def lowest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = { apply(lowestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*) } def highest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = { apply(highestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*) } def robin[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = { apply(roundRobin)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*) } def apply[T <: Data](policy: Policy)(sink: DecoupledIO[T], sources: (UInt, DecoupledIO[T])*): Unit = { if (sources.isEmpty) { sink.bits := DontCare } else if (sources.size == 1) { sink :<>= sources.head._2 } else { val pairs = sources.toList val beatsIn = pairs.map(_._1) val sourcesIn = pairs.map(_._2) // The number of beats which remain to be sent val beatsLeft = RegInit(0.U) val idle = beatsLeft === 0.U val latch = idle && sink.ready // winner (if any) claims sink // Who wants access to the sink? val valids = sourcesIn.map(_.valid) // Arbitrate amongst the requests val readys = VecInit(policy(valids.size, Cat(valids.reverse), latch).asBools) // Which request wins arbitration? val winner = VecInit((readys zip valids) map { case (r,v) => r&&v }) // Confirm the policy works properly require (readys.size == valids.size) // Never two winners val prefixOR = winner.scanLeft(false.B)(_||_).init assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _}) // If there was any request, there is a winner assert (!valids.reduce(_||_) || winner.reduce(_||_)) // Track remaining beats val maskedBeats = (winner zip beatsIn) map { case (w,b) => Mux(w, b, 0.U) } val initBeats = maskedBeats.reduce(_ | _) // no winner => 0 beats beatsLeft := Mux(latch, initBeats, beatsLeft - sink.fire) // The one-hot source granted access in the previous cycle val state = RegInit(VecInit(Seq.fill(sources.size)(false.B))) val muxState = Mux(idle, winner, state) state := muxState val allowed = Mux(idle, readys, state) (sourcesIn zip allowed) foreach { case (s, r) => s.ready := sink.ready && r } sink.valid := Mux(idle, valids.reduce(_||_), Mux1H(state, valids)) sink.bits :<= Mux1H(muxState, sourcesIn.map(_.bits)) } } } // Synthesizable unit tests import freechips.rocketchip.unittest._ abstract class DecoupledArbiterTest( policy: TLArbiter.Policy, txns: Int, timeout: Int, val numSources: Int, beatsLeftFromIdx: Int => UInt) (implicit p: Parameters) extends UnitTest(timeout) { val sources = Wire(Vec(numSources, DecoupledIO(UInt(log2Ceil(numSources).W)))) dontTouch(sources.suggestName("sources")) val sink = Wire(DecoupledIO(UInt(log2Ceil(numSources).W))) dontTouch(sink.suggestName("sink")) val count = RegInit(0.U(log2Ceil(txns).W)) val lfsr = LFSR(16, true.B) sources.zipWithIndex.map { case (z, i) => z.bits := i.U } TLArbiter(policy)(sink, sources.zipWithIndex.map { case (z, i) => (beatsLeftFromIdx(i), z) }:_*) count := count + 1.U io.finished := count >= txns.U } /** This tests that when a specific pattern of source valids are driven, * a new index from amongst that pattern is always selected, * unless one of those sources takes multiple beats, * in which case the same index should be selected until the arbiter goes idle. */ class TLDecoupledArbiterRobinTest(txns: Int = 128, timeout: Int = 500000, print: Boolean = false) (implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.roundRobin, txns, timeout, 6, i => i.U) { val lastWinner = RegInit((numSources+1).U) val beatsLeft = RegInit(0.U(log2Ceil(numSources).W)) val first = lastWinner > numSources.U val valid = lfsr(0) val ready = lfsr(15) sink.ready := ready sources.zipWithIndex.map { // pattern: every even-indexed valid is driven the same random way case (s, i) => s.valid := (if (i % 2 == 1) false.B else valid) } when (sink.fire) { if (print) { printf("TestRobin: %d\n", sink.bits) } when (beatsLeft === 0.U) { assert(lastWinner =/= sink.bits, "Round robin did not pick a new idx despite one being valid.") lastWinner := sink.bits beatsLeft := sink.bits } .otherwise { assert(lastWinner === sink.bits, "Round robin did not pick the same index over multiple beats") beatsLeft := beatsLeft - 1.U } } if (print) { when (!sink.fire) { printf("TestRobin: idle (%d %d)\n", valid, ready) } } } /** This tests that the lowest index is always selected across random single cycle transactions. */ class TLDecoupledArbiterLowestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.lowestIndexFirst, txns, timeout, 15, _ => 0.U) { def assertLowest(id: Int): Unit = { when (sources(id).valid) { assert((numSources-1 until id by -1).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a higher valid source was granted ready.") } } sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) } sink.ready := lfsr(15) when (sink.fire) { (0 until numSources).foreach(assertLowest(_)) } } /** This tests that the highest index is always selected across random single cycle transactions. */ class TLDecoupledArbiterHighestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.highestIndexFirst, txns, timeout, 15, _ => 0.U) { def assertHighest(id: Int): Unit = { when (sources(id).valid) { assert((0 until id).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a lower valid source was granted ready.") } } sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) } sink.ready := lfsr(15) when (sink.fire) { (0 until numSources).foreach(assertHighest(_)) } } File Xbar.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressDecoder, AddressSet, RegionType, IdRange, TriStateValue} import freechips.rocketchip.util.BundleField // Trades off slave port proximity against routing resource cost object ForceFanout { def apply[T]( a: TriStateValue = TriStateValue.unset, b: TriStateValue = TriStateValue.unset, c: TriStateValue = TriStateValue.unset, d: TriStateValue = TriStateValue.unset, e: TriStateValue = TriStateValue.unset)(body: Parameters => T)(implicit p: Parameters) = { body(p.alterPartial { case ForceFanoutKey => p(ForceFanoutKey) match { case ForceFanoutParams(pa, pb, pc, pd, pe) => ForceFanoutParams(a.update(pa), b.update(pb), c.update(pc), d.update(pd), e.update(pe)) } }) } } private case class ForceFanoutParams(a: Boolean, b: Boolean, c: Boolean, d: Boolean, e: Boolean) private case object ForceFanoutKey extends Field(ForceFanoutParams(false, false, false, false, false)) class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule { val node = new TLNexusNode( clientFn = { seq => seq(0).v1copy( echoFields = BundleField.union(seq.flatMap(_.echoFields)), requestFields = BundleField.union(seq.flatMap(_.requestFields)), responseKeys = seq.flatMap(_.responseKeys).distinct, minLatency = seq.map(_.minLatency).min, clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) => port.clients map { client => client.v1copy( sourceId = client.sourceId.shift(range.start) )} } ) }, managerFn = { seq => val fifoIdFactory = TLXbar.relabeler() seq(0).v1copy( responseFields = BundleField.union(seq.flatMap(_.responseFields)), requestKeys = seq.flatMap(_.requestKeys).distinct, minLatency = seq.map(_.minLatency).min, endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max, managers = seq.flatMap { port => require (port.beatBytes == seq(0).beatBytes, s"Xbar ($name with parent $parent) data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B") val fifoIdMapper = fifoIdFactory() port.managers map { manager => manager.v1copy( fifoId = manager.fifoId.map(fifoIdMapper(_)) )} } ) } ){ override def circuitIdentity = outputs.size == 1 && inputs.size == 1 } lazy val module = new Impl class Impl extends LazyModuleImp(this) { if ((node.in.size * node.out.size) > (8*32)) { println (s"!!! WARNING !!!") println (s" Your TLXbar ($name with parent $parent) is very large, with ${node.in.size} Masters and ${node.out.size} Slaves.") println (s"!!! WARNING !!!") } val wide_bundle = TLBundleParameters.union((node.in ++ node.out).map(_._2.bundle)) override def desiredName = (Seq("TLXbar") ++ nameSuffix ++ Seq(s"i${node.in.size}_o${node.out.size}_${wide_bundle.shortName}")).mkString("_") TLXbar.circuit(policy, node.in, node.out) } } object TLXbar { def mapInputIds(ports: Seq[TLMasterPortParameters]) = assignRanges(ports.map(_.endSourceId)) def mapOutputIds(ports: Seq[TLSlavePortParameters]) = assignRanges(ports.map(_.endSinkId)) def assignRanges(sizes: Seq[Int]) = { val pow2Sizes = sizes.map { z => if (z == 0) 0 else 1 << log2Ceil(z) } val tuples = pow2Sizes.zipWithIndex.sortBy(_._1) // record old index, then sort by increasing size val starts = tuples.scanRight(0)(_._1 + _).tail // suffix-sum of the sizes = the start positions val ranges = (tuples zip starts) map { case ((sz, i), st) => (if (sz == 0) IdRange(0, 0) else IdRange(st, st + sz), i) } ranges.sortBy(_._2).map(_._1) // Restore orignal order } def relabeler() = { var idFactory = 0 () => { val fifoMap = scala.collection.mutable.HashMap.empty[Int, Int] (x: Int) => { if (fifoMap.contains(x)) fifoMap(x) else { val out = idFactory idFactory = idFactory + 1 fifoMap += (x -> out) out } } } } def circuit(policy: TLArbiter.Policy, seqIn: Seq[(TLBundle, TLEdge)], seqOut: Seq[(TLBundle, TLEdge)]) { val (io_in, edgesIn) = seqIn.unzip val (io_out, edgesOut) = seqOut.unzip // Not every master need connect to every slave on every channel; determine which connections are necessary val reachableIO = edgesIn.map { cp => edgesOut.map { mp => cp.client.clients.exists { c => mp.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma)}}}} }.toVector}.toVector val probeIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.managers.exists(_.regionType >= RegionType.TRACKED) }.toVector}.toVector val releaseIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.anySupportAcquireB }.toVector}.toVector val connectAIO = reachableIO val connectBIO = probeIO val connectCIO = releaseIO val connectDIO = reachableIO val connectEIO = releaseIO def transpose[T](x: Seq[Seq[T]]) = if (x.isEmpty) Nil else Vector.tabulate(x(0).size) { i => Vector.tabulate(x.size) { j => x(j)(i) } } val connectAOI = transpose(connectAIO) val connectBOI = transpose(connectBIO) val connectCOI = transpose(connectCIO) val connectDOI = transpose(connectDIO) val connectEOI = transpose(connectEIO) // Grab the port ID mapping val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager)) // We need an intermediate size of bundle with the widest possible identifiers val wide_bundle = TLBundleParameters.union(io_in.map(_.params) ++ io_out.map(_.params)) // Handle size = 1 gracefully (Chisel3 empty range is broken) def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0) // Transform input bundle sources (sinks use global namespace on both sides) val in = Wire(Vec(io_in.size, TLBundle(wide_bundle))) for (i <- 0 until in.size) { val r = inputIdRanges(i) if (connectAIO(i).exists(x=>x)) { in(i).a.bits.user := DontCare in(i).a.squeezeAll.waiveAll :<>= io_in(i).a.squeezeAll.waiveAll in(i).a.bits.source := io_in(i).a.bits.source | r.start.U } else { in(i).a := DontCare io_in(i).a := DontCare in(i).a.valid := false.B io_in(i).a.ready := true.B } if (connectBIO(i).exists(x=>x)) { io_in(i).b.squeezeAll :<>= in(i).b.squeezeAll io_in(i).b.bits.source := trim(in(i).b.bits.source, r.size) } else { in(i).b := DontCare io_in(i).b := DontCare in(i).b.ready := true.B io_in(i).b.valid := false.B } if (connectCIO(i).exists(x=>x)) { in(i).c.bits.user := DontCare in(i).c.squeezeAll.waiveAll :<>= io_in(i).c.squeezeAll.waiveAll in(i).c.bits.source := io_in(i).c.bits.source | r.start.U } else { in(i).c := DontCare io_in(i).c := DontCare in(i).c.valid := false.B io_in(i).c.ready := true.B } if (connectDIO(i).exists(x=>x)) { io_in(i).d.squeezeAll.waiveAll :<>= in(i).d.squeezeAll.waiveAll io_in(i).d.bits.source := trim(in(i).d.bits.source, r.size) } else { in(i).d := DontCare io_in(i).d := DontCare in(i).d.ready := true.B io_in(i).d.valid := false.B } if (connectEIO(i).exists(x=>x)) { in(i).e.squeezeAll :<>= io_in(i).e.squeezeAll } else { in(i).e := DontCare io_in(i).e := DontCare in(i).e.valid := false.B io_in(i).e.ready := true.B } } // Transform output bundle sinks (sources use global namespace on both sides) val out = Wire(Vec(io_out.size, TLBundle(wide_bundle))) for (o <- 0 until out.size) { val r = outputIdRanges(o) if (connectAOI(o).exists(x=>x)) { out(o).a.bits.user := DontCare io_out(o).a.squeezeAll.waiveAll :<>= out(o).a.squeezeAll.waiveAll } else { out(o).a := DontCare io_out(o).a := DontCare out(o).a.ready := true.B io_out(o).a.valid := false.B } if (connectBOI(o).exists(x=>x)) { out(o).b.squeezeAll :<>= io_out(o).b.squeezeAll } else { out(o).b := DontCare io_out(o).b := DontCare out(o).b.valid := false.B io_out(o).b.ready := true.B } if (connectCOI(o).exists(x=>x)) { out(o).c.bits.user := DontCare io_out(o).c.squeezeAll.waiveAll :<>= out(o).c.squeezeAll.waiveAll } else { out(o).c := DontCare io_out(o).c := DontCare out(o).c.ready := true.B io_out(o).c.valid := false.B } if (connectDOI(o).exists(x=>x)) { out(o).d.squeezeAll :<>= io_out(o).d.squeezeAll out(o).d.bits.sink := io_out(o).d.bits.sink | r.start.U } else { out(o).d := DontCare io_out(o).d := DontCare out(o).d.valid := false.B io_out(o).d.ready := true.B } if (connectEOI(o).exists(x=>x)) { io_out(o).e.squeezeAll :<>= out(o).e.squeezeAll io_out(o).e.bits.sink := trim(out(o).e.bits.sink, r.size) } else { out(o).e := DontCare io_out(o).e := DontCare out(o).e.ready := true.B io_out(o).e.valid := false.B } } // Filter a list to only those elements selected def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1) // Based on input=>output connectivity, create per-input minimal address decode circuits val requiredAC = (connectAIO ++ connectCIO).distinct val outputPortFns: Map[Vector[Boolean], Seq[UInt => Bool]] = requiredAC.map { connectO => val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address)) val routingMask = AddressDecoder(filter(port_addrs, connectO)) val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct)) // Print the address mapping if (false) { println("Xbar mapping:") route_addrs.foreach { p => print(" ") p.foreach { a => print(s" ${a}") } println("") } println("--") } (connectO, route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_ || _))) }.toMap // Print the ID mapping if (false) { println(s"XBar mapping:") (edgesIn zip inputIdRanges).zipWithIndex.foreach { case ((edge, id), i) => println(s"\t$i assigned ${id} for ${edge.client.clients.map(_.name).mkString(", ")}") } println("") } val addressA = (in zip edgesIn) map { case (i, e) => e.address(i.a.bits) } val addressC = (in zip edgesIn) map { case (i, e) => e.address(i.c.bits) } def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B val requestAIO = (connectAIO zip addressA) map { case (c, i) => outputPortFns(c).map { o => unique(c) || o(i) } } val requestCIO = (connectCIO zip addressC) map { case (c, i) => outputPortFns(c).map { o => unique(c) || o(i) } } val requestBOI = out.map { o => inputIdRanges.map { i => i.contains(o.b.bits.source) } } val requestDOI = out.map { o => inputIdRanges.map { i => i.contains(o.d.bits.source) } } val requestEIO = in.map { i => outputIdRanges.map { o => o.contains(i.e.bits.sink) } } val beatsAI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.a.bits) } val beatsBO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.b.bits) } val beatsCI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.c.bits) } val beatsDO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.d.bits) } val beatsEI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.e.bits) } // Fanout the input sources to the output sinks val portsAOI = transpose((in zip requestAIO) map { case (i, r) => TLXbar.fanout(i.a, r, edgesOut.map(_.params(ForceFanoutKey).a)) }) val portsBIO = transpose((out zip requestBOI) map { case (o, r) => TLXbar.fanout(o.b, r, edgesIn .map(_.params(ForceFanoutKey).b)) }) val portsCOI = transpose((in zip requestCIO) map { case (i, r) => TLXbar.fanout(i.c, r, edgesOut.map(_.params(ForceFanoutKey).c)) }) val portsDIO = transpose((out zip requestDOI) map { case (o, r) => TLXbar.fanout(o.d, r, edgesIn .map(_.params(ForceFanoutKey).d)) }) val portsEOI = transpose((in zip requestEIO) map { case (i, r) => TLXbar.fanout(i.e, r, edgesOut.map(_.params(ForceFanoutKey).e)) }) // Arbitrate amongst the sources for (o <- 0 until out.size) { TLArbiter(policy)(out(o).a, filter(beatsAI zip portsAOI(o), connectAOI(o)):_*) TLArbiter(policy)(out(o).c, filter(beatsCI zip portsCOI(o), connectCOI(o)):_*) TLArbiter(policy)(out(o).e, filter(beatsEI zip portsEOI(o), connectEOI(o)):_*) filter(portsAOI(o), connectAOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsCOI(o), connectCOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsEOI(o), connectEOI(o).map(!_)) foreach { r => r.ready := false.B } } for (i <- 0 until in.size) { TLArbiter(policy)(in(i).b, filter(beatsBO zip portsBIO(i), connectBIO(i)):_*) TLArbiter(policy)(in(i).d, filter(beatsDO zip portsDIO(i), connectDIO(i)):_*) filter(portsBIO(i), connectBIO(i).map(!_)) foreach { r => r.ready := false.B } filter(portsDIO(i), connectDIO(i).map(!_)) foreach { r => r.ready := false.B } } } def apply(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { val xbar = LazyModule(new TLXbar(policy, nameSuffix)) xbar.node } // Replicate an input port to each output port def fanout[T <: TLChannel](input: DecoupledIO[T], select: Seq[Bool], force: Seq[Boolean] = Nil): Seq[DecoupledIO[T]] = { val filtered = Wire(Vec(select.size, chiselTypeOf(input))) for (i <- 0 until select.size) { filtered(i).bits := (if (force.lift(i).getOrElse(false)) IdentityModule(input.bits) else input.bits) filtered(i).valid := input.valid && (select(i) || (select.size == 1).B) } input.ready := Mux1H(select, filtered.map(_.ready)) filtered } } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMXbar(nManagers: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("Xbar")) val xbar = LazyModule(new TLXbar) xbar.node := TLDelayer(0.1) := model.node := fuzz.node (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMXbarTest(nManagers: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMXbar(nManagers,txns)).module) dut.io.start := io.start io.finished := dut.io.finished } class TLMulticlientXbar(nManagers: Int, nClients: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val xbar = LazyModule(new TLXbar) val fuzzers = (0 until nClients) map { n => val fuzz = LazyModule(new TLFuzzer(txns)) xbar.node := TLDelayer(0.1) := fuzz.node fuzz } (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzzers.last.module.io.finished } } class TLMulticlientXbarTest(nManagers: Int, nClients: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLMulticlientXbar(nManagers, nClients, txns)).module) dut.io.start := io.start io.finished := dut.io.finished }
module TLXbar_fbus_i2_o1_a32d64s5k5z4u( // @[Xbar.scala:74:9] input clock, // @[Xbar.scala:74:9] input reset, // @[Xbar.scala:74:9] output auto_anon_in_1_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_1_d_bits_source, // @[LazyModuleImp.scala:107:25] output [4:0] auto_anon_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_0_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_anon_in_0_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [4:0] auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire [4:0] out_0_d_bits_sink; // @[Xbar.scala:216:19] wire [4:0] in_1_a_bits_source; // @[Xbar.scala:159:18] wire auto_anon_in_1_a_valid_0 = auto_anon_in_1_a_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_1_a_bits_opcode_0 = auto_anon_in_1_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_1_a_bits_param_0 = auto_anon_in_1_a_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_1_a_bits_size_0 = auto_anon_in_1_a_bits_size; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_1_a_bits_source_0 = auto_anon_in_1_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_1_a_bits_address_0 = auto_anon_in_1_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] auto_anon_in_1_a_bits_mask_0 = auto_anon_in_1_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_1_a_bits_data_0 = auto_anon_in_1_a_bits_data; // @[Xbar.scala:74:9] wire auto_anon_in_1_a_bits_corrupt_0 = auto_anon_in_1_a_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_ready_0 = auto_anon_in_1_d_ready; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_valid_0 = auto_anon_in_0_a_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_a_bits_opcode_0 = auto_anon_in_0_a_bits_opcode; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_0_a_bits_size_0 = auto_anon_in_0_a_bits_size; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_0_a_bits_address_0 = auto_anon_in_0_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] auto_anon_in_0_a_bits_mask_0 = auto_anon_in_0_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_0_a_bits_data_0 = auto_anon_in_0_a_bits_data; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_bits_corrupt_0 = auto_anon_in_0_a_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_ready_0 = auto_anon_in_0_d_ready; // @[Xbar.scala:74:9] wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[Xbar.scala:74:9] wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_d_bits_param_0 = auto_anon_out_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[Xbar.scala:74:9] wire [4:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[Xbar.scala:74:9] wire [4:0] auto_anon_out_d_bits_sink_0 = auto_anon_out_d_bits_sink; // @[Xbar.scala:74:9] wire auto_anon_out_d_bits_denied_0 = auto_anon_out_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[Xbar.scala:74:9] wire auto_anon_out_d_bits_corrupt_0 = auto_anon_out_d_bits_corrupt; // @[Xbar.scala:74:9] wire _readys_T_2 = reset; // @[Arbiter.scala:22:12] wire [2:0] auto_anon_in_0_a_bits_param = 3'h0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_param = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] in_0_a_bits_param = 3'h0; // @[Xbar.scala:159:18] wire [2:0] _addressC_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _addressC_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _addressC_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _addressC_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _requestBOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestBOI_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _beatsBO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _beatsCI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _beatsCI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _beatsCI_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _beatsCI_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] portsAOI_filtered_0_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _portsBIO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] portsBIO_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsBIO_filtered_1_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _portsCOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _portsCOI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] portsCOI_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_0_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _portsCOI_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _portsCOI_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] portsCOI_filtered_1_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_0_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _out_0_a_bits_T_18 = 3'h0; // @[Mux.scala:30:73] wire auto_anon_in_0_a_bits_source = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_bits_source = 1'h0; // @[Xbar.scala:74:9] wire anonIn_a_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_d_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire _addressC_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _requestBOI_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire requestBOI_0_0 = 1'h0; // @[Parameters.scala:46:9] wire _requestBOI_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_T = 1'h0; // @[Parameters.scala:54:10] wire _requestEIO_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_T = 1'h0; // @[Parameters.scala:54:10] wire _requestEIO_WIRE_2_ready = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_2_valid = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_3_ready = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_3_valid = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_T_5 = 1'h0; // @[Parameters.scala:54:10] wire _beatsBO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_opdata_T = 1'h0; // @[Edges.scala:97:37] wire _beatsCI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire beatsCI_opdata = 1'h0; // @[Edges.scala:102:36] wire _beatsCI_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire beatsCI_opdata_1 = 1'h0; // @[Edges.scala:102:36] wire _beatsEI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_2_ready = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_2_valid = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_3_ready = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_3_valid = 1'h0; // @[Bundles.scala:267:61] wire _portsBIO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire portsBIO_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsBIO_filtered_0_valid_T = 1'h0; // @[Xbar.scala:355:54] wire _portsBIO_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsBIO_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsBIO_T = 1'h0; // @[Mux.scala:30:73] wire _portsBIO_T_1 = 1'h0; // @[Mux.scala:30:73] wire _portsBIO_T_2 = 1'h0; // @[Mux.scala:30:73] wire _portsBIO_WIRE_2 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire portsCOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsCOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire portsCOI_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsCOI_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _portsEOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire portsEOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire _portsEOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_WIRE_2_ready = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_2_valid = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_3_ready = 1'h0; // @[Bundles.scala:267:61] wire _portsEOI_WIRE_3_valid = 1'h0; // @[Bundles.scala:267:61] wire portsEOI_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24] wire _portsEOI_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40] wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34] wire _requestAIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire requestAIO_0_0 = 1'h1; // @[Xbar.scala:307:107] wire _requestAIO_T_9 = 1'h1; // @[Parameters.scala:137:59] wire requestAIO_1_0 = 1'h1; // @[Xbar.scala:307:107] wire _requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107] wire _requestCIO_T_9 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_1_0 = 1'h1; // @[Xbar.scala:308:107] wire _requestBOI_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire requestBOI_0_1 = 1'h1; // @[Parameters.scala:56:48] wire _requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _requestEIO_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _requestEIO_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestEIO_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _requestEIO_T_4 = 1'h1; // @[Parameters.scala:57:20] wire requestEIO_0_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestEIO_T_6 = 1'h1; // @[Parameters.scala:54:32] wire _requestEIO_T_7 = 1'h1; // @[Parameters.scala:56:32] wire _requestEIO_T_8 = 1'h1; // @[Parameters.scala:54:67] wire _requestEIO_T_9 = 1'h1; // @[Parameters.scala:57:20] wire requestEIO_1_0 = 1'h1; // @[Parameters.scala:56:48] wire beatsBO_opdata = 1'h1; // @[Edges.scala:97:28] wire _portsAOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsAOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire _portsBIO_filtered_1_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire _portsEOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsEOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire [4:0] _addressC_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _addressC_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _addressC_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _addressC_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _requestBOI_WIRE_bits_source = 5'h0; // @[Bundles.scala:264:74] wire [4:0] _requestBOI_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:264:61] wire [4:0] _requestBOI_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:264:74] wire [4:0] _requestBOI_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:264:61] wire [4:0] _requestBOI_uncommonBits_T = 5'h0; // @[Parameters.scala:52:29] wire [4:0] _requestEIO_WIRE_bits_sink = 5'h0; // @[Bundles.scala:267:74] wire [4:0] _requestEIO_WIRE_1_bits_sink = 5'h0; // @[Bundles.scala:267:61] wire [4:0] _requestEIO_uncommonBits_T = 5'h0; // @[Parameters.scala:52:29] wire [4:0] requestEIO_uncommonBits = 5'h0; // @[Parameters.scala:52:56] wire [4:0] _requestEIO_WIRE_2_bits_sink = 5'h0; // @[Bundles.scala:267:74] wire [4:0] _requestEIO_WIRE_3_bits_sink = 5'h0; // @[Bundles.scala:267:61] wire [4:0] _requestEIO_uncommonBits_T_1 = 5'h0; // @[Parameters.scala:52:29] wire [4:0] requestEIO_uncommonBits_1 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] _beatsBO_WIRE_bits_source = 5'h0; // @[Bundles.scala:264:74] wire [4:0] _beatsBO_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:264:61] wire [4:0] _beatsCI_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _beatsCI_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _beatsCI_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _beatsCI_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _beatsEI_WIRE_bits_sink = 5'h0; // @[Bundles.scala:267:74] wire [4:0] _beatsEI_WIRE_1_bits_sink = 5'h0; // @[Bundles.scala:267:61] wire [4:0] _beatsEI_WIRE_2_bits_sink = 5'h0; // @[Bundles.scala:267:74] wire [4:0] _beatsEI_WIRE_3_bits_sink = 5'h0; // @[Bundles.scala:267:61] wire [4:0] _portsBIO_WIRE_bits_source = 5'h0; // @[Bundles.scala:264:74] wire [4:0] _portsBIO_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:264:61] wire [4:0] portsBIO_filtered_0_bits_source = 5'h0; // @[Xbar.scala:352:24] wire [4:0] portsBIO_filtered_1_bits_source = 5'h0; // @[Xbar.scala:352:24] wire [4:0] _portsCOI_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _portsCOI_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] portsCOI_filtered_0_bits_source = 5'h0; // @[Xbar.scala:352:24] wire [4:0] _portsCOI_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _portsCOI_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] portsCOI_filtered_1_0_bits_source = 5'h0; // @[Xbar.scala:352:24] wire [4:0] _portsEOI_WIRE_bits_sink = 5'h0; // @[Bundles.scala:267:74] wire [4:0] _portsEOI_WIRE_1_bits_sink = 5'h0; // @[Bundles.scala:267:61] wire [4:0] portsEOI_filtered_0_bits_sink = 5'h0; // @[Xbar.scala:352:24] wire [4:0] _portsEOI_WIRE_2_bits_sink = 5'h0; // @[Bundles.scala:267:74] wire [4:0] _portsEOI_WIRE_3_bits_sink = 5'h0; // @[Bundles.scala:267:61] wire [4:0] portsEOI_filtered_1_0_bits_sink = 5'h0; // @[Xbar.scala:352:24] wire [63:0] _addressC_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _addressC_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _addressC_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _addressC_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _requestBOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _requestBOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _requestBOI_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _requestBOI_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _beatsBO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _beatsBO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _beatsCI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _beatsCI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _beatsCI_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _beatsCI_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _portsBIO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _portsBIO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] portsBIO_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] portsBIO_filtered_1_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] _portsCOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _portsCOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] portsCOI_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] _portsCOI_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _portsCOI_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] portsCOI_filtered_1_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [31:0] _addressC_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _addressC_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _addressC_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _addressC_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _requestCIO_T = 32'h0; // @[Parameters.scala:137:31] wire [31:0] _requestCIO_T_5 = 32'h0; // @[Parameters.scala:137:31] wire [31:0] _requestBOI_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _requestBOI_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _requestBOI_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _requestBOI_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _beatsBO_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _beatsBO_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _beatsCI_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _beatsCI_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _beatsCI_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _beatsCI_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _portsBIO_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _portsBIO_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] portsBIO_filtered_0_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] portsBIO_filtered_1_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] _portsCOI_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _portsCOI_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] portsCOI_filtered_0_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] _portsCOI_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _portsCOI_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] portsCOI_filtered_1_0_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [3:0] _addressC_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _addressC_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _addressC_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _addressC_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _requestBOI_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _requestBOI_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _requestBOI_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _requestBOI_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] requestBOI_uncommonBits = 4'h0; // @[Parameters.scala:52:56] wire [3:0] _beatsBO_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _beatsBO_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _beatsCI_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _beatsCI_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _beatsCI_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _beatsCI_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _portsBIO_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _portsBIO_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] portsBIO_filtered_0_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] portsBIO_filtered_1_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] _portsCOI_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _portsCOI_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] portsCOI_filtered_0_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] _portsCOI_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _portsCOI_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] portsCOI_filtered_1_0_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [7:0] _requestBOI_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _requestBOI_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _requestBOI_WIRE_2_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _requestBOI_WIRE_3_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _beatsBO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _beatsBO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _portsBIO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _portsBIO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] portsBIO_filtered_0_bits_mask = 8'h0; // @[Xbar.scala:352:24] wire [7:0] portsBIO_filtered_1_bits_mask = 8'h0; // @[Xbar.scala:352:24] wire [1:0] _requestBOI_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _requestBOI_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _requestBOI_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _requestBOI_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _beatsBO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _beatsBO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _portsBIO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _portsBIO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] portsBIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] portsBIO_filtered_1_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [4:0] in_0_a_bits_source = 5'h10; // @[Xbar.scala:159:18] wire [4:0] _in_0_a_bits_source_T = 5'h10; // @[Xbar.scala:166:55] wire [4:0] portsAOI_filtered_0_bits_source = 5'h10; // @[Xbar.scala:352:24] wire [8:0] beatsBO_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] beatsBO_0 = 9'h0; // @[Edges.scala:221:14] wire [8:0] beatsCI_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] beatsCI_0 = 9'h0; // @[Edges.scala:221:14] wire [8:0] beatsCI_decode_1 = 9'h0; // @[Edges.scala:220:59] wire [8:0] beatsCI_1 = 9'h0; // @[Edges.scala:221:14] wire [11:0] _beatsBO_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _beatsCI_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _beatsCI_decode_T_5 = 12'h0; // @[package.scala:243:46] wire [11:0] _beatsBO_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [11:0] _beatsCI_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [11:0] _beatsCI_decode_T_4 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _beatsBO_decode_T = 27'hFFF; // @[package.scala:243:71] wire [26:0] _beatsCI_decode_T = 27'hFFF; // @[package.scala:243:71] wire [26:0] _beatsCI_decode_T_3 = 27'hFFF; // @[package.scala:243:71] wire [32:0] _requestAIO_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestAIO_T_3 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestAIO_T_7 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestAIO_T_8 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_1 = 33'h0; // @[Parameters.scala:137:41] wire [32:0] _requestCIO_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_3 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_6 = 33'h0; // @[Parameters.scala:137:41] wire [32:0] _requestCIO_T_7 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_8 = 33'h0; // @[Parameters.scala:137:46] wire anonIn_1_a_ready; // @[MixedNode.scala:551:17] wire anonIn_1_a_valid = auto_anon_in_1_a_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_1_a_bits_opcode = auto_anon_in_1_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_1_a_bits_param = auto_anon_in_1_a_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_1_a_bits_size = auto_anon_in_1_a_bits_size_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_1_a_bits_source = auto_anon_in_1_a_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_1_a_bits_address = auto_anon_in_1_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] anonIn_1_a_bits_mask = auto_anon_in_1_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] anonIn_1_a_bits_data = auto_anon_in_1_a_bits_data_0; // @[Xbar.scala:74:9] wire anonIn_1_a_bits_corrupt = auto_anon_in_1_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonIn_1_d_ready = auto_anon_in_1_d_ready_0; // @[Xbar.scala:74:9] wire anonIn_1_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_1_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_1_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_1_d_bits_size; // @[MixedNode.scala:551:17] wire [3:0] anonIn_1_d_bits_source; // @[MixedNode.scala:551:17] wire [4:0] anonIn_1_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_1_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] anonIn_1_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_1_d_bits_corrupt; // @[MixedNode.scala:551:17] wire anonIn_a_ready; // @[MixedNode.scala:551:17] wire anonIn_a_valid = auto_anon_in_0_a_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_opcode = auto_anon_in_0_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_a_bits_size = auto_anon_in_0_a_bits_size_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_a_bits_address = auto_anon_in_0_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] anonIn_a_bits_mask = auto_anon_in_0_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] anonIn_a_bits_data = auto_anon_in_0_a_bits_data_0; // @[Xbar.scala:74:9] wire anonIn_a_bits_corrupt = auto_anon_in_0_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonIn_d_ready = auto_anon_in_0_d_ready_0; // @[Xbar.scala:74:9] wire anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [4:0] anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[Xbar.scala:74:9] wire anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [4:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] anonOut_d_bits_param = auto_anon_out_d_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[Xbar.scala:74:9] wire [4:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[Xbar.scala:74:9] wire [4:0] anonOut_d_bits_sink = auto_anon_out_d_bits_sink_0; // @[Xbar.scala:74:9] wire anonOut_d_bits_denied = auto_anon_out_d_bits_denied_0; // @[Xbar.scala:74:9] wire [63:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[Xbar.scala:74:9] wire anonOut_d_bits_corrupt = auto_anon_out_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_a_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_1_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_1_d_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_1_d_bits_size_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_1_d_bits_source_0; // @[Xbar.scala:74:9] wire [4:0] auto_anon_in_1_d_bits_sink_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_bits_denied_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_1_d_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_valid_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_0_d_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_0_d_bits_size_0; // @[Xbar.scala:74:9] wire [4:0] auto_anon_in_0_d_bits_sink_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_bits_denied_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_0_d_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_a_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_a_bits_size_0; // @[Xbar.scala:74:9] wire [4:0] auto_anon_out_a_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] auto_anon_out_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] auto_anon_out_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_a_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_out_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_out_a_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_d_ready_0; // @[Xbar.scala:74:9] wire in_0_a_ready; // @[Xbar.scala:159:18] assign auto_anon_in_0_a_ready_0 = anonIn_a_ready; // @[Xbar.scala:74:9] wire in_0_a_valid = anonIn_a_valid; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_opcode = anonIn_a_bits_opcode; // @[Xbar.scala:159:18] wire [3:0] in_0_a_bits_size = anonIn_a_bits_size; // @[Xbar.scala:159:18] wire [31:0] in_0_a_bits_address = anonIn_a_bits_address; // @[Xbar.scala:159:18] wire [7:0] in_0_a_bits_mask = anonIn_a_bits_mask; // @[Xbar.scala:159:18] wire [63:0] in_0_a_bits_data = anonIn_a_bits_data; // @[Xbar.scala:159:18] wire in_0_a_bits_corrupt = anonIn_a_bits_corrupt; // @[Xbar.scala:159:18] wire in_0_d_ready = anonIn_d_ready; // @[Xbar.scala:159:18] wire in_0_d_valid; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_valid_0 = anonIn_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_0_d_bits_opcode; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_0_d_bits_param; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_param_0 = anonIn_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] in_0_d_bits_size; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_size_0 = anonIn_d_bits_size; // @[Xbar.scala:74:9] wire [4:0] in_0_d_bits_sink; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_sink_0 = anonIn_d_bits_sink; // @[Xbar.scala:74:9] wire in_0_d_bits_denied; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_denied_0 = anonIn_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] in_0_d_bits_data; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_data_0 = anonIn_d_bits_data; // @[Xbar.scala:74:9] wire in_0_d_bits_corrupt; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[Xbar.scala:74:9] wire in_1_a_ready; // @[Xbar.scala:159:18] assign auto_anon_in_1_a_ready_0 = anonIn_1_a_ready; // @[Xbar.scala:74:9] wire in_1_a_valid = anonIn_1_a_valid; // @[Xbar.scala:159:18] wire [2:0] in_1_a_bits_opcode = anonIn_1_a_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_1_a_bits_param = anonIn_1_a_bits_param; // @[Xbar.scala:159:18] wire [3:0] in_1_a_bits_size = anonIn_1_a_bits_size; // @[Xbar.scala:159:18] wire [3:0] _in_1_a_bits_source_T = anonIn_1_a_bits_source; // @[Xbar.scala:166:55] wire [31:0] in_1_a_bits_address = anonIn_1_a_bits_address; // @[Xbar.scala:159:18] wire [7:0] in_1_a_bits_mask = anonIn_1_a_bits_mask; // @[Xbar.scala:159:18] wire [63:0] in_1_a_bits_data = anonIn_1_a_bits_data; // @[Xbar.scala:159:18] wire in_1_a_bits_corrupt = anonIn_1_a_bits_corrupt; // @[Xbar.scala:159:18] wire in_1_d_ready = anonIn_1_d_ready; // @[Xbar.scala:159:18] wire in_1_d_valid; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_valid_0 = anonIn_1_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_1_d_bits_opcode; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_opcode_0 = anonIn_1_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_1_d_bits_param; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_param_0 = anonIn_1_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] in_1_d_bits_size; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_size_0 = anonIn_1_d_bits_size; // @[Xbar.scala:74:9] wire [3:0] _anonIn_d_bits_source_T; // @[Xbar.scala:156:69] assign auto_anon_in_1_d_bits_source_0 = anonIn_1_d_bits_source; // @[Xbar.scala:74:9] wire [4:0] in_1_d_bits_sink; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_sink_0 = anonIn_1_d_bits_sink; // @[Xbar.scala:74:9] wire in_1_d_bits_denied; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_denied_0 = anonIn_1_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] in_1_d_bits_data; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_data_0 = anonIn_1_d_bits_data; // @[Xbar.scala:74:9] wire in_1_d_bits_corrupt; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_corrupt_0 = anonIn_1_d_bits_corrupt; // @[Xbar.scala:74:9] wire out_0_a_ready = anonOut_a_ready; // @[Xbar.scala:216:19] wire out_0_a_valid; // @[Xbar.scala:216:19] assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_param; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[Xbar.scala:74:9] wire [3:0] out_0_a_bits_size; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[Xbar.scala:74:9] wire [4:0] out_0_a_bits_source; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] out_0_a_bits_address; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] out_0_a_bits_mask; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] out_0_a_bits_data; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[Xbar.scala:74:9] wire out_0_a_bits_corrupt; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[Xbar.scala:74:9] wire out_0_d_ready; // @[Xbar.scala:216:19] assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[Xbar.scala:74:9] wire out_0_d_valid = anonOut_d_valid; // @[Xbar.scala:216:19] wire [2:0] out_0_d_bits_opcode = anonOut_d_bits_opcode; // @[Xbar.scala:216:19] wire [1:0] out_0_d_bits_param = anonOut_d_bits_param; // @[Xbar.scala:216:19] wire [3:0] out_0_d_bits_size = anonOut_d_bits_size; // @[Xbar.scala:216:19] wire [4:0] out_0_d_bits_source = anonOut_d_bits_source; // @[Xbar.scala:216:19] wire [4:0] _out_0_d_bits_sink_T = anonOut_d_bits_sink; // @[Xbar.scala:251:53] wire out_0_d_bits_denied = anonOut_d_bits_denied; // @[Xbar.scala:216:19] wire [63:0] out_0_d_bits_data = anonOut_d_bits_data; // @[Xbar.scala:216:19] wire out_0_d_bits_corrupt = anonOut_d_bits_corrupt; // @[Xbar.scala:216:19] wire portsAOI_filtered_0_ready; // @[Xbar.scala:352:24] assign anonIn_a_ready = in_0_a_ready; // @[Xbar.scala:159:18] wire _portsAOI_filtered_0_valid_T_1 = in_0_a_valid; // @[Xbar.scala:159:18, :355:40] wire [2:0] portsAOI_filtered_0_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsAOI_filtered_0_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [31:0] _requestAIO_T = in_0_a_bits_address; // @[Xbar.scala:159:18] wire [31:0] portsAOI_filtered_0_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [7:0] portsAOI_filtered_0_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [63:0] portsAOI_filtered_0_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_0_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire portsDIO_filtered_0_ready = in_0_d_ready; // @[Xbar.scala:159:18, :352:24] wire portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] assign anonIn_d_valid = in_0_d_valid; // @[Xbar.scala:159:18] wire [2:0] portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:352:24] assign anonIn_d_bits_opcode = in_0_d_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] portsDIO_filtered_0_bits_param; // @[Xbar.scala:352:24] assign anonIn_d_bits_param = in_0_d_bits_param; // @[Xbar.scala:159:18] wire [3:0] portsDIO_filtered_0_bits_size; // @[Xbar.scala:352:24] assign anonIn_d_bits_size = in_0_d_bits_size; // @[Xbar.scala:159:18] wire [4:0] portsDIO_filtered_0_bits_source; // @[Xbar.scala:352:24] wire [4:0] portsDIO_filtered_0_bits_sink; // @[Xbar.scala:352:24] assign anonIn_d_bits_sink = in_0_d_bits_sink; // @[Xbar.scala:159:18] wire portsDIO_filtered_0_bits_denied; // @[Xbar.scala:352:24] assign anonIn_d_bits_denied = in_0_d_bits_denied; // @[Xbar.scala:159:18] wire [63:0] portsDIO_filtered_0_bits_data; // @[Xbar.scala:352:24] assign anonIn_d_bits_data = in_0_d_bits_data; // @[Xbar.scala:159:18] wire portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:352:24] assign anonIn_d_bits_corrupt = in_0_d_bits_corrupt; // @[Xbar.scala:159:18] wire portsAOI_filtered_1_0_ready; // @[Xbar.scala:352:24] assign anonIn_1_a_ready = in_1_a_ready; // @[Xbar.scala:159:18] wire _portsAOI_filtered_0_valid_T_3 = in_1_a_valid; // @[Xbar.scala:159:18, :355:40] wire [2:0] portsAOI_filtered_1_0_bits_opcode = in_1_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_0_bits_param = in_1_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsAOI_filtered_1_0_bits_size = in_1_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [4:0] portsAOI_filtered_1_0_bits_source = in_1_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [31:0] _requestAIO_T_5 = in_1_a_bits_address; // @[Xbar.scala:159:18] wire [31:0] portsAOI_filtered_1_0_bits_address = in_1_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [7:0] portsAOI_filtered_1_0_bits_mask = in_1_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [63:0] portsAOI_filtered_1_0_bits_data = in_1_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_1_0_bits_corrupt = in_1_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire portsDIO_filtered_1_ready = in_1_d_ready; // @[Xbar.scala:159:18, :352:24] wire portsDIO_filtered_1_valid; // @[Xbar.scala:352:24] assign anonIn_1_d_valid = in_1_d_valid; // @[Xbar.scala:159:18] wire [2:0] portsDIO_filtered_1_bits_opcode; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_opcode = in_1_d_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] portsDIO_filtered_1_bits_param; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_param = in_1_d_bits_param; // @[Xbar.scala:159:18] wire [3:0] portsDIO_filtered_1_bits_size; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_size = in_1_d_bits_size; // @[Xbar.scala:159:18] wire [4:0] portsDIO_filtered_1_bits_source; // @[Xbar.scala:352:24] wire [4:0] portsDIO_filtered_1_bits_sink; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_sink = in_1_d_bits_sink; // @[Xbar.scala:159:18] wire portsDIO_filtered_1_bits_denied; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_denied = in_1_d_bits_denied; // @[Xbar.scala:159:18] wire [63:0] portsDIO_filtered_1_bits_data; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_data = in_1_d_bits_data; // @[Xbar.scala:159:18] wire portsDIO_filtered_1_bits_corrupt; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_corrupt = in_1_d_bits_corrupt; // @[Xbar.scala:159:18] wire [4:0] in_0_d_bits_source; // @[Xbar.scala:159:18] wire [4:0] in_1_d_bits_source; // @[Xbar.scala:159:18] assign in_1_a_bits_source = {1'h0, _in_1_a_bits_source_T}; // @[Xbar.scala:159:18, :166:{29,55}] assign _anonIn_d_bits_source_T = in_1_d_bits_source[3:0]; // @[Xbar.scala:156:69, :159:18] assign anonIn_1_d_bits_source = _anonIn_d_bits_source_T; // @[Xbar.scala:156:69] wire _out_0_a_valid_T_4; // @[Arbiter.scala:96:24] assign anonOut_a_valid = out_0_a_valid; // @[Xbar.scala:216:19] wire [2:0] _out_0_a_bits_WIRE_opcode; // @[Mux.scala:30:73] assign anonOut_a_bits_opcode = out_0_a_bits_opcode; // @[Xbar.scala:216:19] wire [2:0] _out_0_a_bits_WIRE_param; // @[Mux.scala:30:73] assign anonOut_a_bits_param = out_0_a_bits_param; // @[Xbar.scala:216:19] wire [3:0] _out_0_a_bits_WIRE_size; // @[Mux.scala:30:73] assign anonOut_a_bits_size = out_0_a_bits_size; // @[Xbar.scala:216:19] wire [4:0] _out_0_a_bits_WIRE_source; // @[Mux.scala:30:73] assign anonOut_a_bits_source = out_0_a_bits_source; // @[Xbar.scala:216:19] wire [31:0] _out_0_a_bits_WIRE_address; // @[Mux.scala:30:73] assign anonOut_a_bits_address = out_0_a_bits_address; // @[Xbar.scala:216:19] wire [7:0] _out_0_a_bits_WIRE_mask; // @[Mux.scala:30:73] assign anonOut_a_bits_mask = out_0_a_bits_mask; // @[Xbar.scala:216:19] wire [63:0] _out_0_a_bits_WIRE_data; // @[Mux.scala:30:73] assign anonOut_a_bits_data = out_0_a_bits_data; // @[Xbar.scala:216:19] wire _out_0_a_bits_WIRE_corrupt; // @[Mux.scala:30:73] assign anonOut_a_bits_corrupt = out_0_a_bits_corrupt; // @[Xbar.scala:216:19] wire _portsDIO_out_0_d_ready_WIRE; // @[Mux.scala:30:73] assign anonOut_d_ready = out_0_d_ready; // @[Xbar.scala:216:19] assign portsDIO_filtered_0_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [4:0] _requestDOI_uncommonBits_T = out_0_d_bits_source; // @[Xbar.scala:216:19] assign portsDIO_filtered_0_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign out_0_d_bits_sink = _out_0_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53] wire [32:0] _requestAIO_T_1 = {1'h0, _requestAIO_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_6 = {1'h0, _requestAIO_T_5}; // @[Parameters.scala:137:{31,41}] wire requestDOI_0_0 = out_0_d_bits_source == 5'h10; // @[Xbar.scala:216:19] wire _portsDIO_filtered_0_valid_T = requestDOI_0_0; // @[Xbar.scala:355:54] wire [3:0] requestDOI_uncommonBits = _requestDOI_uncommonBits_T[3:0]; // @[Parameters.scala:52:{29,56}] wire _requestDOI_T = out_0_d_bits_source[4]; // @[Xbar.scala:216:19] wire _requestDOI_T_1 = ~_requestDOI_T; // @[Parameters.scala:54:{10,32}] wire _requestDOI_T_3 = _requestDOI_T_1; // @[Parameters.scala:54:{32,67}] wire requestDOI_0_1 = _requestDOI_T_3; // @[Parameters.scala:54:67, :56:48] wire _portsDIO_filtered_1_valid_T = requestDOI_0_1; // @[Xbar.scala:355:54] wire [26:0] _beatsAI_decode_T = 27'hFFF << in_0_a_bits_size; // @[package.scala:243:71] wire [11:0] _beatsAI_decode_T_1 = _beatsAI_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsAI_decode_T_2 = ~_beatsAI_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] beatsAI_decode = _beatsAI_decode_T_2[11:3]; // @[package.scala:243:46] wire _beatsAI_opdata_T = in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18] wire beatsAI_opdata = ~_beatsAI_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] beatsAI_0 = beatsAI_opdata ? beatsAI_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [26:0] _beatsAI_decode_T_3 = 27'hFFF << in_1_a_bits_size; // @[package.scala:243:71] wire [11:0] _beatsAI_decode_T_4 = _beatsAI_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsAI_decode_T_5 = ~_beatsAI_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] beatsAI_decode_1 = _beatsAI_decode_T_5[11:3]; // @[package.scala:243:46] wire _beatsAI_opdata_T_1 = in_1_a_bits_opcode[2]; // @[Xbar.scala:159:18] wire beatsAI_opdata_1 = ~_beatsAI_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] beatsAI_1 = beatsAI_opdata_1 ? beatsAI_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [26:0] _beatsDO_decode_T = 27'hFFF << out_0_d_bits_size; // @[package.scala:243:71] wire [11:0] _beatsDO_decode_T_1 = _beatsDO_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsDO_decode_T_2 = ~_beatsDO_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] beatsDO_decode = _beatsDO_decode_T_2[11:3]; // @[package.scala:243:46] wire beatsDO_opdata = out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [8:0] beatsDO_0 = beatsDO_opdata ? beatsDO_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] wire _filtered_0_ready_T; // @[Arbiter.scala:94:31] assign in_0_a_ready = portsAOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_0_valid; // @[Xbar.scala:352:24] assign portsAOI_filtered_0_valid = _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _filtered_0_ready_T_1; // @[Arbiter.scala:94:31] assign in_1_a_ready = portsAOI_filtered_1_0_ready; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24] assign portsAOI_filtered_1_0_valid = _portsAOI_filtered_0_valid_T_3; // @[Xbar.scala:352:24, :355:40] wire _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:355:40] assign in_0_d_valid = portsDIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_opcode = portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_param = portsDIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_size = portsDIO_filtered_0_bits_size; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_source = portsDIO_filtered_0_bits_source; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_sink = portsDIO_filtered_0_bits_sink; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_denied = portsDIO_filtered_0_bits_denied; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_data = portsDIO_filtered_0_bits_data; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_corrupt = portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire _portsDIO_filtered_1_valid_T_1; // @[Xbar.scala:355:40] assign in_1_d_valid = portsDIO_filtered_1_valid; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_opcode = portsDIO_filtered_1_bits_opcode; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_param = portsDIO_filtered_1_bits_param; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_size = portsDIO_filtered_1_bits_size; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_source = portsDIO_filtered_1_bits_source; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_sink = portsDIO_filtered_1_bits_sink; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_denied = portsDIO_filtered_1_bits_denied; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_data = portsDIO_filtered_1_bits_data; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_corrupt = portsDIO_filtered_1_bits_corrupt; // @[Xbar.scala:159:18, :352:24] assign _portsDIO_filtered_0_valid_T_1 = out_0_d_valid & _portsDIO_filtered_0_valid_T; // @[Xbar.scala:216:19, :355:{40,54}] assign portsDIO_filtered_0_valid = _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign _portsDIO_filtered_1_valid_T_1 = out_0_d_valid & _portsDIO_filtered_1_valid_T; // @[Xbar.scala:216:19, :355:{40,54}] assign portsDIO_filtered_1_valid = _portsDIO_filtered_1_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _portsDIO_out_0_d_ready_T = requestDOI_0_0 & portsDIO_filtered_0_ready; // @[Mux.scala:30:73] wire _portsDIO_out_0_d_ready_T_1 = requestDOI_0_1 & portsDIO_filtered_1_ready; // @[Mux.scala:30:73] wire _portsDIO_out_0_d_ready_T_2 = _portsDIO_out_0_d_ready_T | _portsDIO_out_0_d_ready_T_1; // @[Mux.scala:30:73] assign _portsDIO_out_0_d_ready_WIRE = _portsDIO_out_0_d_ready_T_2; // @[Mux.scala:30:73] assign out_0_d_ready = _portsDIO_out_0_d_ready_WIRE; // @[Mux.scala:30:73] reg [8:0] beatsLeft; // @[Arbiter.scala:60:30] wire idle = beatsLeft == 9'h0; // @[Arbiter.scala:60:30, :61:28] wire latch = idle & out_0_a_ready; // @[Xbar.scala:216:19] wire [1:0] _readys_T = {portsAOI_filtered_1_0_valid, portsAOI_filtered_0_valid}; // @[Xbar.scala:352:24] wire [1:0] readys_valid = _readys_T; // @[Arbiter.scala:21:23, :68:51] wire _readys_T_1 = readys_valid == _readys_T; // @[Arbiter.scala:21:23, :22:19, :68:51] wire _readys_T_3 = ~_readys_T_2; // @[Arbiter.scala:22:12] wire _readys_T_4 = ~_readys_T_1; // @[Arbiter.scala:22:{12,19}] reg [1:0] readys_mask; // @[Arbiter.scala:23:23] wire [1:0] _readys_filter_T = ~readys_mask; // @[Arbiter.scala:23:23, :24:30] wire [1:0] _readys_filter_T_1 = readys_valid & _readys_filter_T; // @[Arbiter.scala:21:23, :24:{28,30}] wire [3:0] readys_filter = {_readys_filter_T_1, readys_valid}; // @[Arbiter.scala:21:23, :24:{21,28}] wire [2:0] _readys_unready_T = readys_filter[3:1]; // @[package.scala:262:48] wire [3:0] _readys_unready_T_1 = {readys_filter[3], readys_filter[2:0] | _readys_unready_T}; // @[package.scala:262:{43,48}] wire [3:0] _readys_unready_T_2 = _readys_unready_T_1; // @[package.scala:262:43, :263:17] wire [2:0] _readys_unready_T_3 = _readys_unready_T_2[3:1]; // @[package.scala:263:17] wire [3:0] _readys_unready_T_4 = {readys_mask, 2'h0}; // @[Arbiter.scala:23:23, :25:66] wire [3:0] readys_unready = {1'h0, _readys_unready_T_3} | _readys_unready_T_4; // @[Arbiter.scala:25:{52,58,66}] wire [1:0] _readys_readys_T = readys_unready[3:2]; // @[Arbiter.scala:25:58, :26:29] wire [1:0] _readys_readys_T_1 = readys_unready[1:0]; // @[Arbiter.scala:25:58, :26:48] wire [1:0] _readys_readys_T_2 = _readys_readys_T & _readys_readys_T_1; // @[Arbiter.scala:26:{29,39,48}] wire [1:0] readys_readys = ~_readys_readys_T_2; // @[Arbiter.scala:26:{18,39}] wire [1:0] _readys_T_7 = readys_readys; // @[Arbiter.scala:26:18, :30:11] wire _readys_T_5 = |readys_valid; // @[Arbiter.scala:21:23, :27:27] wire _readys_T_6 = latch & _readys_T_5; // @[Arbiter.scala:27:{18,27}, :62:24] wire [1:0] _readys_mask_T = readys_readys & readys_valid; // @[Arbiter.scala:21:23, :26:18, :28:29] wire [2:0] _readys_mask_T_1 = {_readys_mask_T, 1'h0}; // @[package.scala:253:48] wire [1:0] _readys_mask_T_2 = _readys_mask_T_1[1:0]; // @[package.scala:253:{48,53}] wire [1:0] _readys_mask_T_3 = _readys_mask_T | _readys_mask_T_2; // @[package.scala:253:{43,53}] wire [1:0] _readys_mask_T_4 = _readys_mask_T_3; // @[package.scala:253:43, :254:17] wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:30:11, :68:76] wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}] wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:30:11, :68:76] wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}] wire _winner_T = readys_0 & portsAOI_filtered_0_valid; // @[Xbar.scala:352:24] wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}] wire _winner_T_1 = readys_1 & portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24] wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T = prefixOR_1 | winner_1; // @[Arbiter.scala:71:27, :76:48] wire _out_0_a_valid_T = portsAOI_filtered_0_valid | portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24]
Generate the Verilog code corresponding to the following Chisel files. File Transposer.scala: package gemmini import chisel3._ import chisel3.util._ import Util._ trait Transposer[T <: Data] extends Module { def dim: Int def dataType: T val io = IO(new Bundle { val inRow = Flipped(Decoupled(Vec(dim, dataType))) val outCol = Decoupled(Vec(dim, dataType)) }) } class PipelinedTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { require(isPow2(dim)) val regArray = Seq.fill(dim, dim)(Reg(dataType)) val regArrayT = regArray.transpose val sMoveUp :: sMoveLeft :: Nil = Enum(2) val state = RegInit(sMoveUp) val leftCounter = RegInit(0.U(log2Ceil(dim+1).W)) //(io.inRow.fire && state === sMoveLeft, dim+1) val upCounter = RegInit(0.U(log2Ceil(dim+1).W)) //Counter(io.inRow.fire && state === sMoveUp, dim+1) io.outCol.valid := 0.U io.inRow.ready := 0.U switch(state) { is(sMoveUp) { io.inRow.ready := upCounter <= dim.U io.outCol.valid := leftCounter > 0.U when(io.inRow.fire) { upCounter := upCounter + 1.U } when(upCounter === (dim-1).U) { state := sMoveLeft leftCounter := 0.U } when(io.outCol.fire) { leftCounter := leftCounter - 1.U } } is(sMoveLeft) { io.inRow.ready := leftCounter <= dim.U // TODO: this is naive io.outCol.valid := upCounter > 0.U when(leftCounter === (dim-1).U) { state := sMoveUp } when(io.inRow.fire) { leftCounter := leftCounter + 1.U upCounter := 0.U } when(io.outCol.fire) { upCounter := upCounter - 1.U } } } // Propagate input from bottom row to top row systolically in the move up phase // TODO: need to iterate over columns to connect Chisel values of type T // Should be able to operate directly on the Vec, but Seq and Vec don't mix (try Array?) for (colIdx <- 0 until dim) { regArray.foldRight(io.inRow.bits(colIdx)) { case (regRow, prevReg) => when (state === sMoveUp) { regRow(colIdx) := prevReg } regRow(colIdx) } } // Propagate input from right side to left side systolically in the move left phase for (rowIdx <- 0 until dim) { regArrayT.foldRight(io.inRow.bits(rowIdx)) { case (regCol, prevReg) => when (state === sMoveLeft) { regCol(rowIdx) := prevReg } regCol(rowIdx) } } // Pull from the left side or the top side based on the state for (idx <- 0 until dim) { when (state === sMoveUp) { io.outCol.bits(idx) := regArray(0)(idx) }.elsewhen(state === sMoveLeft) { io.outCol.bits(idx) := regArrayT(0)(idx) }.otherwise { io.outCol.bits(idx) := DontCare } } } class AlwaysOutTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { require(isPow2(dim)) val LEFT_DIR = 0.U(1.W) val UP_DIR = 1.U(1.W) class PE extends Module { val io = IO(new Bundle { val inR = Input(dataType) val inD = Input(dataType) val outL = Output(dataType) val outU = Output(dataType) val dir = Input(UInt(1.W)) val en = Input(Bool()) }) val reg = RegEnable(Mux(io.dir === LEFT_DIR, io.inR, io.inD), io.en) io.outU := reg io.outL := reg } val pes = Seq.fill(dim,dim)(Module(new PE)) val counter = RegInit(0.U((log2Ceil(dim) max 1).W)) // TODO replace this with a standard Chisel counter val dir = RegInit(LEFT_DIR) // Wire up horizontal signals for (row <- 0 until dim; col <- 0 until dim) { val right_in = if (col == dim-1) io.inRow.bits(row) else pes(row)(col+1).io.outL pes(row)(col).io.inR := right_in } // Wire up vertical signals for (row <- 0 until dim; col <- 0 until dim) { val down_in = if (row == dim-1) io.inRow.bits(col) else pes(row+1)(col).io.outU pes(row)(col).io.inD := down_in } // Wire up global signals pes.flatten.foreach(_.io.dir := dir) pes.flatten.foreach(_.io.en := io.inRow.fire) io.outCol.valid := true.B io.inRow.ready := true.B val left_out = VecInit(pes.transpose.head.map(_.io.outL)) val up_out = VecInit(pes.head.map(_.io.outU)) io.outCol.bits := Mux(dir === LEFT_DIR, left_out, up_out) when (io.inRow.fire) { counter := wrappingAdd(counter, 1.U, dim) } when (counter === (dim-1).U && io.inRow.fire) { dir := ~dir } } class NaiveTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { val regArray = Seq.fill(dim, dim)(Reg(dataType)) val regArrayT = regArray.transpose // state = 0 => filling regArray row-wise, state = 1 => draining regArray column-wise val state = RegInit(0.U(1.W)) val countInc = io.inRow.fire || io.outCol.fire val (countValue, countWrap) = Counter(countInc, dim) io.inRow.ready := state === 0.U io.outCol.valid := state === 1.U for (i <- 0 until dim) { for (j <- 0 until dim) { when(countValue === i.U && io.inRow.fire) { regArray(i)(j) := io.inRow.bits(j) } } } for (i <- 0 until dim) { io.outCol.bits(i) := 0.U for (j <- 0 until dim) { when(countValue === j.U) { io.outCol.bits(i) := regArrayT(j)(i) } } } when (io.inRow.fire && countWrap) { state := 1.U } when (io.outCol.fire && countWrap) { state := 0.U } assert(!(state === 0.U) || !io.outCol.fire) assert(!(state === 1.U) || !io.inRow.fire) }
module PE_224( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_32( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54] wire [258:0] _c_sizes_set_T_1 = 259'h0; // @[Monitor.scala:768:52] wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79] wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35] wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35] wire [79:0] c_opcodes_set = 80'h0; // @[Monitor.scala:740:34] wire [79:0] c_sizes_set = 80'h0; // @[Monitor.scala:741:34] wire [19:0] c_set = 20'h0; // @[Monitor.scala:738:34] wire [19:0] c_set_wo_ready = 20'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 5'h14; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [4:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [4:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 5'h14; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_672; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [4:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [4:0] source_1; // @[Monitor.scala:541:22] reg denied; // @[Monitor.scala:543:22] reg [19:0] inflight; // @[Monitor.scala:614:27] reg [79:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [79:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [19:0] a_set; // @[Monitor.scala:626:34] wire [19:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [79:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [79:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [79:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [79:0] _a_opcode_lookup_T_6 = {76'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [79:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[79:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [79:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [79:0] _a_size_lookup_T_6 = {76'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [79:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[79:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [31:0] _GEN_2 = 32'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [31:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[19:0] : 20'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[19:0] : 20'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [7:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [7:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [7:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[79:0] : 80'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [258:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[79:0] : 80'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [19:0] d_clr; // @[Monitor.scala:664:34] wire [19:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [79:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [79:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [31:0] _GEN_5 = 32'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[19:0] : 20'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[19:0] : 20'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[79:0] : 80'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [270:0] _d_sizes_clr_T_5 = 271'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[79:0] : 80'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [19:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [19:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [19:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [79:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [79:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [79:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [79:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [79:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [79:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [19:0] inflight_1; // @[Monitor.scala:726:35] wire [19:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [79:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [79:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [79:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [79:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [79:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [79:0] _c_opcode_lookup_T_6 = {76'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [79:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[79:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [79:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [79:0] _c_size_lookup_T_6 = {76'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [79:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[79:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [19:0] d_clr_1; // @[Monitor.scala:774:34] wire [19:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [79:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [79:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[19:0] : 20'h0; // @[OneHot.scala:58:35] wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_698 ? _d_clr_T_1[19:0] : 20'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[79:0] : 80'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [270:0] _d_sizes_clr_T_11 = 271'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[79:0] : 80'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113] wire [19:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [19:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [79:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [79:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [79:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [79:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File PermuteSequencer.scala: package saturn.backend import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import saturn.common._ import saturn.insns._ class PermuteSequencer(exu_insns: Seq[VectorInstruction])(implicit p: Parameters) extends PipeSequencer(new PermuteMicroOp)(p) { def accepts(inst: VectorIssueInst) = { val needs_mask = inst.vmu && (!inst.vm && inst.mop =/= mopUnit) val needs_index = inst.vmu && inst.mop(0) val arith = !inst.vmu && new VectorDecoder(inst.funct3, inst.funct6, inst.rs1, inst.rs2, exu_insns.filter(_.props.contains(UsesPermuteSeq.Y)), Nil).matched needs_mask || needs_index || arith } val valid = RegInit(false.B) val inst = Reg(new BackendIssueInst) val eidx = Reg(UInt(log2Ceil(maxVLMax).W)) val rvs2_mask = Reg(UInt(egsTotal.W)) val rvm_mask = Reg(UInt(egsPerVReg.W)) val head = Reg(Bool()) val slide_offset = Reg(UInt((1+log2Ceil(maxVLMax)).W)) val slide = !inst.vmu && inst.funct3 =/= OPIVV val slide_up = !inst.funct6(0) val rs2 = Mux(inst.rs1_is_rs2, inst.rs1, inst.rs2) val gatherei16 = inst.funct3 === OPIVV && inst.opif6 === OPIFunct6.rgatherei16 val renvm = inst.renvm val renv2 = inst.renv2 val incr_eew = Mux(inst.vmu, inst.mem_idx_size, Mux(gatherei16, 1.U, inst.vconfig.vtype.vsew)) val eff_vl = Mux(slide, Mux(slide_up, inst.vconfig.vl - slide_offset, min(inst.vconfig.vtype.vlMax, inst.vconfig.vl + slide_offset)), inst.vconfig.vl )(log2Ceil(maxVLMax),0) val next_eidx = get_next_eidx(eff_vl, eidx, incr_eew, 0.U, false.B, false.B) val tail = next_eidx === eff_vl io.dis.ready := !valid || (tail && io.iss.fire) && !io.dis_stall when (io.dis.fire) { val iss_inst = io.dis.bits val offset = Mux(iss_inst.isOpi, get_max_offset(Mux(iss_inst.funct3(2), iss_inst.rs1_data, iss_inst.imm5)), 1.U) val slide = !iss_inst.vmu && iss_inst.funct3 =/= OPIVV val slide_up = !iss_inst.funct6(0) val slide_start = Mux(slide_up, 0.U, offset) val vlmax = iss_inst.vconfig.vtype.vlMax val slide_no_read = Mux(slide_up, iss_inst.vconfig.vl <= offset, offset >= vlmax) valid := Mux(!slide, true.B, !slide_no_read) inst := iss_inst eidx := Mux(!slide, iss_inst.vstart, slide_start) slide_offset := offset val rs2 = Mux(iss_inst.rs1_is_rs2, iss_inst.rs1, iss_inst.rs2) val renv2_arch_mask = get_arch_mask(rs2, iss_inst.emul) rvs2_mask := Mux(iss_inst.renv2, FillInterleaved(egsPerVReg, renv2_arch_mask), 0.U) rvm_mask := Mux(iss_inst.renvm, ~(0.U(egsPerVReg.W)), 0.U) head := true.B } .elsewhen (io.iss.fire) { valid := !tail head := false.B } io.vat := inst.vat io.seq_hazard.valid := valid io.seq_hazard.bits.rintent := hazardMultiply(rvs2_mask | rvm_mask) io.seq_hazard.bits.wintent := false.B io.seq_hazard.bits.vat := inst.vat val vs2_read_oh = Mux(renv2, UIntToOH(io.rvs2.req.bits.eg), 0.U) val vm_read_oh = Mux(renvm, UIntToOH(io.rvm.req.bits.eg), 0.U) val raw_hazard = ((vm_read_oh | vs2_read_oh) & io.older_writes) =/= 0.U val data_hazard = raw_hazard val oldest = inst.vat === io.vat_head io.rvs2.req.valid := valid && renv2 io.rvs2.req.bits.eg := getEgId(rs2, eidx, incr_eew, false.B) io.rvs2.req.bits.oldest := oldest io.rvm.req.valid := valid && renvm io.rvm.req.bits.eg := getEgId(0.U, eidx, 0.U, true.B) io.rvm.req.bits.oldest := oldest io.iss.valid := valid && !data_hazard && (!renvm || io.rvm.req.ready) && (!renv2 || io.rvs2.req.ready) io.iss.bits.renv2 := renv2 io.iss.bits.renvm := renvm io.iss.bits.rvs2_data := io.rvs2.resp io.iss.bits.rvs2_eew := incr_eew io.iss.bits.eidx := eidx io.iss.bits.vl := eff_vl io.iss.bits.rvm_data := Mux(renvm, io.rvm.resp, ~(0.U(dLen.W))) io.iss.bits.vmu := inst.vmu io.iss.bits.tail := tail when (io.iss.fire && !tail) { when (next_is_new_eg(eidx, next_eidx, incr_eew, false.B) && vParams.enableChaining.B) { rvs2_mask := rvs2_mask & ~vs2_read_oh } when (next_is_new_eg(eidx, next_eidx, 0.U, true.B) && vParams.enableChaining.B) { rvm_mask := rvm_mask & ~UIntToOH(io.rvm.req.bits.eg) } eidx := next_eidx } io.busy := valid io.head := head } File Parameters.scala: package saturn.common import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util._ import freechips.rocketchip.tile._ import freechips.rocketchip.diplomacy.{BufferParams} import saturn.exu._ object VectorParams { // minParams: // For a very small area-efficient vector unit with iterative // and element-wise functional units def minParams = VectorParams() // refParams // For a standard modestly capable small vector unit with // SIMD functional units def refParams = minParams.copy( vlrobEntries = 4, vlissqEntries = 3, vsissqEntries = 3, vxissqEntries = 3, vatSz = 5, useSegmentedIMul = true, doubleBufferSegments = true, useScalarFPFMA = false, vrfBanking = 4, ) // dspParams // For a wide high-performance vector unit with multi-issue def dspParams = refParams.copy( issStructure = VectorIssueStructure.Shared ) // genParams: // For a vector unit that performs better on less-optimized // code sequences def genParams = dspParams.copy( issStructure = VectorIssueStructure.Split, vlifqEntries = 16, vlrobEntries = 16 ) // multiFMAParams: // Provides a second sequencer and set of functional units for FMA operations def multiFMAParams = genParams.copy( issStructure = VectorIssueStructure.MultiFMA ) // multiMACParams: // Provides a second sequencer and set of functional units for integer MAC operations def multiMACParams = genParams.copy( issStructure = VectorIssueStructure.MultiMAC ) // dmaParams: // For a vector unit that only does memcpys, and no arithmetic def dmaParams = VectorParams( vdqEntries = 2, vliqEntries = 4, vsiqEntries = 4, vlifqEntries = 32, vlrobEntries = 4, vsifqEntries = 32, vlissqEntries = 2, vsissqEntries = 1, vrfBanking = 1, useIterativeIMul = true ) // The parameters below are approximations // hwaParams // For a vector unit with limited sequencer slots akin to Hwacha def hwaParams = genParams.copy( vatSz = 3, // 8 mseq Entries vdqEntries = 1, vlissqEntries = 8, vsissqEntries = 8, vxissqEntries = 8, vpissqEntries = 8, hwachaLimiter = Some(8), // sequencer slots ) // lgvParams // For a vector unit with very long vector lengths def lgvParams = VectorParams( vatSz = 5, vlifqEntries = 32, vsifqEntries = 32, vlrobEntries = 32, vlissqEntries = 8, vsissqEntries = 8, vxissqEntries = 8, vpissqEntries = 8, useSegmentedIMul = true, useScalarFPMisc = false, useScalarFPFMA = false, vrfBanking = 4, issStructure = VectorIssueStructure.Split ) } case class VXSequencerParams( name: String, fus: Seq[FunctionalUnitFactory] ) { def insns = fus.map(_.insns).flatten } case class VXIssuePathParams( name: String, depth: Int, seqs: Seq[VXSequencerParams] ) { def insns = seqs.map(_.insns).flatten } object VXFunctionalUnitGroups { def integerFUs(idivDoesImul: Boolean = false) = Seq( IntegerPipeFactory, ShiftPipeFactory, BitwisePipeFactory, IntegerDivideFactory(idivDoesImul), MaskUnitFactory, PermuteUnitFactory ) def integerMAC(pipeDepth: Int, useSegmented: Boolean) = Seq( IntegerMultiplyFactory(pipeDepth, useSegmented) ) def allIntegerFUs(idivDoesImul: Boolean, imaDepth: Int, useSegmentedImul: Boolean) = ( integerFUs(idivDoesImul) ++ integerMAC(imaDepth, useSegmentedImul) ) def sharedFPFMA(pipeDepth: Int) = Seq( FPFMAFactory(pipeDepth, true) ) def sharedFPMisc = Seq( SharedFPMiscFactory ) def fpFMA(pipeDepth: Int) = Seq( FPFMAFactory(pipeDepth, false) ) def fpMisc = Seq( FPDivSqrtFactory, FPCmpFactory, FPConvFactory ) def allFPFUs(fmaPipeDepth: Int, useScalarFPFMA: Boolean, useScalarFPMisc: Boolean) = ( (if (useScalarFPFMA) sharedFPFMA(fmaPipeDepth) else fpFMA(fmaPipeDepth)) ++ (if (useScalarFPMisc) sharedFPMisc else fpMisc) ) } sealed trait VectorIssueStructure { def generate(params: VectorParams): Seq[VXIssuePathParams] } object VectorIssueStructure { import VXFunctionalUnitGroups._ case object Unified extends VectorIssueStructure { def generate(params: VectorParams) = { val fp_int_path = VXIssuePathParams( name = "fp_int", depth = params.vxissqEntries, seqs = Seq( VXSequencerParams("fp_int", ( allIntegerFUs(params.useIterativeIMul, params.imaPipeDepth, params.useSegmentedIMul) ++ allFPFUs(params.fmaPipeDepth, params.useScalarFPFMA, params.useScalarFPMisc) )) ) ) Seq(fp_int_path) } } case object Shared extends VectorIssueStructure { def generate(params: VectorParams) = { val fp_int_path = VXIssuePathParams( name = "fp_int", depth = params.vxissqEntries, seqs = Seq( VXSequencerParams("int", allIntegerFUs(params.useIterativeIMul, params.imaPipeDepth, params.useSegmentedIMul)), VXSequencerParams("fp", allFPFUs(params.fmaPipeDepth, params.useScalarFPFMA, params.useScalarFPMisc)) ) ) Seq(fp_int_path) } } case object Split extends VectorIssueStructure { def generate(params: VectorParams) = { val int_path = VXIssuePathParams( name = "int", depth = params.vxissqEntries, seqs = Seq( VXSequencerParams("int", allIntegerFUs(params.useIterativeIMul, params.imaPipeDepth, params.useSegmentedIMul)), ) ) val fp_path = VXIssuePathParams( name = "fp", depth = params.vxissqEntries, seqs = Seq( VXSequencerParams("fp", allFPFUs(params.fmaPipeDepth, params.useScalarFPFMA, params.useScalarFPMisc)) ) ) Seq(int_path, fp_path) } } case object MultiFMA extends VectorIssueStructure { def generate(params: VectorParams) = { require(!params.useScalarFPFMA) val int_path = VXIssuePathParams( name = "int", depth = params.vxissqEntries, seqs = Seq( VXSequencerParams("int", allIntegerFUs(params.useIterativeIMul, params.imaPipeDepth, params.useSegmentedIMul)), ) ) val fp_path = VXIssuePathParams( name = "fp", depth = params.vxissqEntries, seqs = Seq( VXSequencerParams("fp0", allFPFUs(params.fmaPipeDepth, params.useScalarFPFMA, params.useScalarFPMisc)), VXSequencerParams("fp1", fpFMA(params.fmaPipeDepth)) ) ) Seq(int_path, fp_path) } } case object MultiMAC extends VectorIssueStructure { def generate(params: VectorParams) = { require(!params.useIterativeIMul && params.useSegmentedIMul) val int_path = VXIssuePathParams( name = "int", depth = params.vxissqEntries, seqs = Seq( VXSequencerParams("int0", allIntegerFUs(params.useIterativeIMul, params.imaPipeDepth, params.useSegmentedIMul)), VXSequencerParams("int1", integerMAC(params.imaPipeDepth, params.useSegmentedIMul)) ) ) val fp_path = VXIssuePathParams( name = "fp", depth = params.vxissqEntries, seqs = Seq( VXSequencerParams("fp", allFPFUs(params.fmaPipeDepth, params.useScalarFPFMA, params.useScalarFPMisc)) ) ) Seq(int_path, fp_path) } } } case class VectorParams( // In-order dispatch Queue vdqEntries: Int = 4, // Load store instruction queues (in VLSU) vliqEntries: Int = 4, vsiqEntries: Int = 4, // Load store in-flight queues (in VLSU) vlifqEntries: Int = 8, vsifqEntries: Int = 16, vlrobEntries: Int = 2, // Scatter-gather engine params vsgPorts: Int = 8, vsgifqEntries: Int = 4, vsgBuffers: Int = 3, // Load/store/execute/permute/maskindex issue queues vlissqEntries: Int = 0, vsissqEntries: Int = 0, vxissqEntries: Int = 0, vpissqEntries: Int = 0, dLen: Int = 64, vatSz: Int = 3, useSegmentedIMul: Boolean = false, useScalarFPFMA: Boolean = true, // Use shared scalar FPU all non-FMA FP instructions useScalarFPMisc: Boolean = true, // Use shared scalar FPU all non-FMA FP instructions useIterativeIMul: Boolean = false, fmaPipeDepth: Int = 4, imaPipeDepth: Int = 3, // for comparisons only hazardingMultiplier: Int = 0, hwachaLimiter: Option[Int] = None, enableChaining: Boolean = true, latencyInject: Boolean = false, enableDAE: Boolean = true, enableOOO: Boolean = true, enableScalarVectorAddrDisambiguation: Boolean = true, doubleBufferSegments: Boolean = false, vrfBanking: Int = 2, vrfHiccupBuffer: Boolean = true, issStructure: VectorIssueStructure = VectorIssueStructure.Unified, tlBuffer: BufferParams = BufferParams.default, ) { def supported_ex_insns = issStructure.generate(this).map(_.insns).flatten } case object VectorParamsKey extends Field[VectorParams] trait HasVectorParams extends HasVectorConsts { this: HasCoreParameters => implicit val p: Parameters def vParams: VectorParams = p(VectorParamsKey) def dLen = vParams.dLen def dLenB = dLen / 8 def dLenOffBits = log2Ceil(dLenB) def dmemTagBits = log2Ceil(vParams.vlifqEntries.max(vParams.vsifqEntries)) def sgmemTagBits = log2Ceil(vParams.vsgifqEntries) def egsPerVReg = vLen / dLen def egsTotal = (vLen / dLen) * 32 def vrfBankBits = log2Ceil(vParams.vrfBanking) def lsiqIdBits = log2Ceil(vParams.vliqEntries.max(vParams.vsiqEntries)) val debugIdSz = 16 val nRelease = vParams.issStructure match { case VectorIssueStructure.Unified => 3 case VectorIssueStructure.Shared | VectorIssueStructure.Split => 4 case VectorIssueStructure.MultiFMA | VectorIssueStructure.MultiMAC => 5 } def getEgId(vreg: UInt, eidx: UInt, eew: UInt, bitwise: Bool): UInt = { val base = vreg << log2Ceil(egsPerVReg) val off = eidx >> Mux(bitwise, log2Ceil(dLen).U, (log2Ceil(dLenB).U - eew)) base +& off } def getByteId(vreg: UInt, eidx: UInt, eew: UInt): UInt = { Cat(getEgId(vreg, eidx, eew, false.B), (eidx << eew)(log2Ceil(dLenB)-1,0)) } def eewByteMask(eew: UInt) = (0 until (1+log2Ceil(eLen/8))).map { e => Mux(e.U === eew, ((1 << (1 << e)) - 1).U, 0.U) }.reduce(_|_)((eLen/8)-1,0) def eewBitMask(eew: UInt) = FillInterleaved(8, eewByteMask(eew)) def cqOlder(i0: UInt, i1: UInt, tail: UInt) = (i0 < i1) ^ (i0 < tail) ^ (i1 < tail) def dLenSplat(in: UInt, eew: UInt) = { val v = Wire(UInt(64.W)) v := in Mux1H(UIntToOH(eew), (0 until 4).map { i => Fill(dLenB >> i, v((8<<i)-1,0)) }) } def sextElem(in: UInt, in_eew: UInt): UInt = VecInit.tabulate(4)( { eew => Cat(in((8 << eew)-1), in((8 << eew)-1,0)).asSInt })(in_eew)(64,0) def extractElem(in: UInt, in_eew: UInt, eidx: UInt): UInt = { val bytes = in.asTypeOf(Vec(dLenB, UInt(8.W))) VecInit.tabulate(4) { eew => val elem = if (dLen == 64 && eew == 3) { in } else { VecInit(bytes.grouped(1 << eew).map(g => VecInit(g).asUInt).toSeq)(eidx(log2Ceil(dLenB)-1-eew,0)) } elem((8 << eew)-1,0) }(in_eew) } def maxPosUInt(sew: Int) = Cat(0.U, ~(0.U(((8 << sew)-1).W))) def minNegUInt(sew: Int) = Cat(1.U, 0.U(((8 << sew)-1).W)) def maxPosSInt(sew: Int) = ((1 << ((8 << sew)-1))-1).S def minNegSInt(sew: Int) = (-1 << ((8 << sew)-1)).S def maxPosFPUInt(sew: Int) = { val expBits = Seq(4, 5, 8, 11)(sew) val fracBits = (8 << sew) - expBits - 1 Cat(0.U, ~(0.U(expBits.W)), 0.U(fracBits.W)) } def minNegFPUInt(sew: Int) = { val expBits = Seq(4, 5, 8, 11)(sew) val fracBits = (8 << sew) - expBits - 1 Cat(1.U, ~(0.U(expBits.W)), 0.U(fracBits.W)) } def get_arch_mask(reg: UInt, emul: UInt) = VecInit.tabulate(4)({ lmul => FillInterleaved(1 << lmul, UIntToOH(reg >> lmul)((32>>lmul)-1,0)) })(emul) def log2_up(f: UInt, max: Int) = VecInit.tabulate(max)({nf => log2Ceil(nf+1).U})(f) def hazardMultiply(mask: UInt): UInt = if (vParams.hazardingMultiplier == 0) { mask } else { require((1 << vParams.hazardingMultiplier) <= egsTotal) VecInit(mask.asBools.grouped(1 << vParams.hazardingMultiplier).map { g => Fill(1 << vParams.hazardingMultiplier, g.orR) }.toSeq).asUInt } } File PipeSequencer.scala: package saturn.common import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.tile.{CoreModule} import saturn.common._ abstract class PipeSequencer[T <: Data](issType: T)(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { val io = IO(new Bundle { val dis = Flipped(Decoupled(new BackendIssueInst)) val dis_stall = Input(Bool()) // used to disable OOO val seq_hazard = Output(Valid(new SequencerHazard)) val vat = Output(UInt(vParams.vatSz.W)) val vat_head = Input(UInt(vParams.vatSz.W)) val older_writes = Input(UInt(egsTotal.W)) val older_reads = Input(UInt(egsTotal.W)) val busy = Output(Bool()) val head = Output(Bool()) val rvs1 = new VectorReadIO val rvs2 = new VectorReadIO val rvd = new VectorReadIO val rvm = new VectorReadIO val perm = new Bundle { val req = Decoupled(new CompactorReq(dLenB)) val data = Input(UInt(dLen.W)) } val iss = Decoupled(issType) val acc = Input(Valid(new VectorWrite(dLen))) }) def accepts(inst: VectorIssueInst): Bool def min(a: UInt, b: UInt) = Mux(a > b, b, a) def get_max_offset(offset: UInt): UInt = min(offset, maxVLMax.U)(log2Ceil(maxVLMax),0) def get_head_mask(bit_mask: UInt, eidx: UInt, eew: UInt) = bit_mask << (eidx << eew)(dLenOffBits-1,0) def get_tail_mask(bit_mask: UInt, eidx: UInt, eew: UInt) = bit_mask >> (0.U(dLenOffBits.W) - (eidx << eew)(dLenOffBits-1,0)) def get_vm_mask(mask_resp: UInt, eidx: UInt, eew: UInt) = { val vm_off = ((1 << dLenOffBits) - 1).U(log2Ceil(dLen).W) val vm_eidx = (eidx & ~(vm_off >> eew))(log2Ceil(dLen)-1,0) val vm_resp = (mask_resp >> vm_eidx)(dLenB-1,0) Mux1H(UIntToOH(eew), (0 until 4).map { w => FillInterleaved(1 << w, vm_resp) }) } def get_next_eidx(vl: UInt, eidx: UInt, eew: UInt, sub_dlen: UInt, reads_mask: Bool, elementwise: Bool) = { val next = Wire(UInt((1+log2Ceil(maxVLMax)).W)) next := Mux(elementwise, eidx +& 1.U, Mux(reads_mask, eidx +& dLen.U, (((eidx >> (dLenOffBits.U - eew - sub_dlen)) +& 1.U) << (dLenOffBits.U - eew - sub_dlen)) )) min(vl, next) } def next_is_new_eg(eidx: UInt, next_eidx: UInt, eew: UInt, masked: Bool) = { val offset = Mux(masked, log2Ceil(dLen).U, dLenOffBits.U - eew) (next_eidx >> offset) =/= (eidx >> offset) } io.rvs1.req.valid := false.B io.rvs1.req.bits := DontCare io.rvs2.req.valid := false.B io.rvs2.req.bits := DontCare io.rvd.req.valid := false.B io.rvd.req.bits := DontCare io.rvm.req.valid := false.B io.rvm.req.bits := DontCare io.perm.req.valid := false.B io.perm.req.bits := DontCare }
module PermuteSequencer( // @[PermuteSequencer.scala:9:7] input clock, // @[PermuteSequencer.scala:9:7] input reset, // @[PermuteSequencer.scala:9:7] output io_dis_ready, // @[PipeSequencer.scala:11:14] input io_dis_valid, // @[PipeSequencer.scala:11:14] input [31:0] io_dis_bits_bits, // @[PipeSequencer.scala:11:14] input [7:0] io_dis_bits_vconfig_vl, // @[PipeSequencer.scala:11:14] input [2:0] io_dis_bits_vconfig_vtype_vsew, // @[PipeSequencer.scala:11:14] input io_dis_bits_vconfig_vtype_vlmul_sign, // @[PipeSequencer.scala:11:14] input [1:0] io_dis_bits_vconfig_vtype_vlmul_mag, // @[PipeSequencer.scala:11:14] input [6:0] io_dis_bits_vstart, // @[PipeSequencer.scala:11:14] input [63:0] io_dis_bits_rs1_data, // @[PipeSequencer.scala:11:14] input [4:0] io_dis_bits_vat, // @[PipeSequencer.scala:11:14] input [1:0] io_dis_bits_emul, // @[PipeSequencer.scala:11:14] input io_dis_bits_rs1_is_rs2, // @[PipeSequencer.scala:11:14] input io_dis_bits_renv2, // @[PipeSequencer.scala:11:14] input io_dis_bits_renvm, // @[PipeSequencer.scala:11:14] output io_seq_hazard_valid, // @[PipeSequencer.scala:11:14] output [4:0] io_seq_hazard_bits_vat, // @[PipeSequencer.scala:11:14] output [31:0] io_seq_hazard_bits_rintent, // @[PipeSequencer.scala:11:14] output [4:0] io_vat, // @[PipeSequencer.scala:11:14] input [4:0] io_vat_head, // @[PipeSequencer.scala:11:14] input [31:0] io_older_writes, // @[PipeSequencer.scala:11:14] output io_busy, // @[PipeSequencer.scala:11:14] input io_rvs2_req_ready, // @[PipeSequencer.scala:11:14] output io_rvs2_req_valid, // @[PipeSequencer.scala:11:14] output [4:0] io_rvs2_req_bits_eg, // @[PipeSequencer.scala:11:14] output io_rvs2_req_bits_oldest, // @[PipeSequencer.scala:11:14] input [127:0] io_rvs2_resp, // @[PipeSequencer.scala:11:14] input io_rvm_req_ready, // @[PipeSequencer.scala:11:14] output io_rvm_req_valid, // @[PipeSequencer.scala:11:14] output io_rvm_req_bits_oldest, // @[PipeSequencer.scala:11:14] input [127:0] io_rvm_resp, // @[PipeSequencer.scala:11:14] input io_iss_ready, // @[PipeSequencer.scala:11:14] output io_iss_valid, // @[PipeSequencer.scala:11:14] output io_iss_bits_renv2, // @[PipeSequencer.scala:11:14] output io_iss_bits_renvm, // @[PipeSequencer.scala:11:14] output [127:0] io_iss_bits_rvs2_data, // @[PipeSequencer.scala:11:14] output [6:0] io_iss_bits_eidx, // @[PipeSequencer.scala:11:14] output [1:0] io_iss_bits_rvs2_eew, // @[PipeSequencer.scala:11:14] output [127:0] io_iss_bits_rvm_data, // @[PipeSequencer.scala:11:14] output io_iss_bits_vmu, // @[PipeSequencer.scala:11:14] output [7:0] io_iss_bits_vl, // @[PipeSequencer.scala:11:14] output io_iss_bits_tail // @[PipeSequencer.scala:11:14] ); wire io_iss_valid_0; // @[PermuteSequencer.scala:88:{25,41,73}] wire [4:0] _io_rvs2_req_bits_eg_T; // @[Parameters.scala:344:10] reg valid; // @[PermuteSequencer.scala:17:22] reg [31:0] inst_bits; // @[PermuteSequencer.scala:18:18] reg [7:0] inst_vconfig_vl; // @[PermuteSequencer.scala:18:18] reg [2:0] inst_vconfig_vtype_vsew; // @[PermuteSequencer.scala:18:18] reg inst_vconfig_vtype_vlmul_sign; // @[PermuteSequencer.scala:18:18] reg [1:0] inst_vconfig_vtype_vlmul_mag; // @[PermuteSequencer.scala:18:18] reg [4:0] inst_vat; // @[PermuteSequencer.scala:18:18] reg inst_rs1_is_rs2; // @[PermuteSequencer.scala:18:18] reg inst_renv2; // @[PermuteSequencer.scala:18:18] reg inst_renvm; // @[PermuteSequencer.scala:18:18] reg [6:0] eidx; // @[PermuteSequencer.scala:19:18] reg [31:0] rvs2_mask; // @[PermuteSequencer.scala:20:22] reg rvm_mask; // @[PermuteSequencer.scala:21:21] reg [7:0] slide_offset; // @[PermuteSequencer.scala:23:25] wire [2:0] incr_eew = inst_bits[6:0] == 7'h7 | inst_bits[6:0] == 7'h27 ? {1'h0, inst_bits[13:12]} : ~(|(inst_bits[14:12])) & (~(|(inst_bits[14:12])) | inst_bits[14:12] == 3'h3 | inst_bits[14:12] == 3'h4 ? {1'h0, inst_bits[31:26]} : 7'h40) == 7'hE ? 3'h1 : inst_vconfig_vtype_vsew; // @[Bundles.scala:56:20, :58:26, :72:20, :75:20, :84:{18,35}] wire [7:0] _eff_vl_T_9 = 8'h80 >> {1'h0, inst_vconfig_vtype_vsew} + {1'h0, inst_vconfig_vtype_vlmul_sign, ~inst_vconfig_vtype_vlmul_mag}; // @[PermuteSequencer.scala:18:18] wire [7:0] _eff_vl_T_10 = inst_vconfig_vl + slide_offset; // @[PermuteSequencer.scala:18:18, :23:25, :34:97] wire [7:0] eff_vl = ~(inst_bits[6:0] == 7'h7 | inst_bits[6:0] == 7'h27) & (|(inst_bits[14:12])) ? (inst_bits[26] ? (_eff_vl_T_9 > _eff_vl_T_10 ? _eff_vl_T_10 : _eff_vl_T_9) : inst_vconfig_vl - slide_offset) : inst_vconfig_vl; // @[Bundles.scala:56:20, :72:20, :75:20] wire [2:0] _offset_T_13 = 3'h4 - incr_eew; // @[PipeSequencer.scala:54:33] wire [6:0] _GEN = {4'h0, _offset_T_13}; // @[PipeSequencer.scala:54:{15,33}] wire [14:0] _next_eidx_next_T_14 = {7'h0, {1'h0, eidx >> _GEN} + 8'h1} << _offset_T_13; // @[PipeSequencer.scala:54:{15,33,52,60}] wire [7:0] next_eidx = eff_vl > _next_eidx_next_T_14[7:0] ? _next_eidx_next_T_14[7:0] : eff_vl; // @[PipeSequencer.scala:40:{34,37}, :52:10, :54:60] wire tail = next_eidx == eff_vl; // @[PipeSequencer.scala:40:34] wire _io_dis_ready_T_1 = io_iss_ready & io_iss_valid_0; // @[Decoupled.scala:51:35] wire io_dis_ready_0 = ~valid | tail & _io_dis_ready_T_1; // @[Decoupled.scala:51:35] wire [31:0] vs2_read_oh = inst_renv2 ? 32'h1 << _io_rvs2_req_bits_eg_T : 32'h0; // @[OneHot.scala:58:35] wire oldest = inst_vat == io_vat_head; // @[PermuteSequencer.scala:18:18, :79:25] wire [6:0] io_rvs2_req_bits_eg_off = eidx >> _GEN; // @[Parameters.scala:343:20] assign _io_rvs2_req_bits_eg_T = (inst_rs1_is_rs2 ? inst_bits[19:15] : inst_bits[24:20]) + io_rvs2_req_bits_eg_off[4:0]; // @[Parameters.scala:343:20, :344:10] assign io_iss_valid_0 = valid & (({31'h0, inst_renvm} | vs2_read_oh) & io_older_writes) == 32'h0 & (~inst_renvm | io_rvm_req_ready) & (~inst_renv2 | io_rvs2_req_ready); // @[PermuteSequencer.scala:17:22, :18:18, :73:24, :74:24, :76:{33,48,67}, :88:{25,41,45,52,73,77,84}] wire _GEN_0 = io_dis_ready_0 & io_dis_valid; // @[Decoupled.scala:51:35] wire [63:0] _offset_T_9 = io_dis_bits_bits[14] ? io_dis_bits_rs1_data : {59'h0, io_dis_bits_bits[19:15]}; // @[Bundles.scala:72:20, :73:18] wire [7:0] offset = io_dis_bits_bits[14:12] == 3'h0 | io_dis_bits_bits[14:12] == 3'h3 | io_dis_bits_bits[14:12] == 3'h4 ? (_offset_T_9 > 64'h80 ? 8'h80 : _offset_T_9[7:0]) : 8'h1; // @[Bundles.scala:72:20] wire slide_1 = ~(io_dis_bits_bits[6:0] == 7'h7 | io_dis_bits_bits[6:0] == 7'h27) & (|(io_dis_bits_bits[14:12])); // @[Bundles.scala:56:20, :72:20] wire _GEN_1 = _io_dis_ready_T_1 & next_eidx != eff_vl; // @[Decoupled.scala:51:35] wire [4:0] rs2_1 = io_dis_bits_rs1_is_rs2 ? io_dis_bits_bits[19:15] : io_dis_bits_bits[24:20]; // @[Bundles.scala:69:17, :73:18] wire [3:0][31:0] _GEN_2 = {{{{8{&(rs2_1[4:3])}}, {8{rs2_1[4:3] == 2'h2}}, {8{rs2_1[4:3] == 2'h1}}, {8{rs2_1[4:3] == 2'h0}}}}, {{{4{&(rs2_1[4:2])}}, {4{rs2_1[4:2] == 3'h6}}, {4{rs2_1[4:2] == 3'h5}}, {4{rs2_1[4:2] == 3'h4}}, {4{rs2_1[4:2] == 3'h3}}, {4{rs2_1[4:2] == 3'h2}}, {4{rs2_1[4:2] == 3'h1}}, {4{rs2_1[4:2] == 3'h0}}}}, {{{2{&(rs2_1[4:1])}}, {2{rs2_1[4:1] == 4'hE}}, {2{rs2_1[4:1] == 4'hD}}, {2{rs2_1[4:1] == 4'hC}}, {2{rs2_1[4:1] == 4'hB}}, {2{rs2_1[4:1] == 4'hA}}, {2{rs2_1[4:1] == 4'h9}}, {2{rs2_1[4:1] == 4'h8}}, {2{rs2_1[4:1] == 4'h7}}, {2{rs2_1[4:1] == 4'h6}}, {2{rs2_1[4:1] == 4'h5}}, {2{rs2_1[4:1] == 4'h4}}, {2{rs2_1[4:1] == 4'h3}}, {2{rs2_1[4:1] == 4'h2}}, {2{rs2_1[4:1] == 4'h1}}, {2{rs2_1[4:1] == 4'h0}}}}, {32'h1 << rs2_1}}; // @[OneHot.scala:58:35] always @(posedge clock) begin // @[PermuteSequencer.scala:9:7] if (reset) // @[PermuteSequencer.scala:9:7] valid <= 1'h0; // @[PermuteSequencer.scala:17:22] else if (_GEN_0) // @[Decoupled.scala:51:35] valid <= ~slide_1 | ~(io_dis_bits_bits[26] ? offset >= 8'h80 >> {1'h0, io_dis_bits_vconfig_vtype_vsew} + {1'h0, io_dis_bits_vconfig_vtype_vlmul_sign, ~io_dis_bits_vconfig_vtype_vlmul_mag} : io_dis_bits_vconfig_vl <= offset); // @[Bundles.scala:75:20] else if (_io_dis_ready_T_1) // @[Decoupled.scala:51:35] valid <= next_eidx != eff_vl; // @[PipeSequencer.scala:40:34] if (_GEN_0) begin // @[Decoupled.scala:51:35] inst_bits <= io_dis_bits_bits; // @[PermuteSequencer.scala:18:18] inst_vconfig_vl <= io_dis_bits_vconfig_vl; // @[PermuteSequencer.scala:18:18] inst_vconfig_vtype_vsew <= io_dis_bits_vconfig_vtype_vsew; // @[PermuteSequencer.scala:18:18] inst_vconfig_vtype_vlmul_sign <= io_dis_bits_vconfig_vtype_vlmul_sign; // @[PermuteSequencer.scala:18:18] inst_vconfig_vtype_vlmul_mag <= io_dis_bits_vconfig_vtype_vlmul_mag; // @[PermuteSequencer.scala:18:18] inst_vat <= io_dis_bits_vat; // @[PermuteSequencer.scala:18:18] inst_rs1_is_rs2 <= io_dis_bits_rs1_is_rs2; // @[PermuteSequencer.scala:18:18] inst_renv2 <= io_dis_bits_renv2; // @[PermuteSequencer.scala:18:18] inst_renvm <= io_dis_bits_renvm; // @[PermuteSequencer.scala:18:18] slide_offset <= offset; // @[PermuteSequencer.scala:23:25, :44:21] end if (_GEN_1) // @[PermuteSequencer.scala:99:21] eidx <= next_eidx[6:0]; // @[PipeSequencer.scala:40:34] else if (_GEN_0) // @[Decoupled.scala:51:35] eidx <= slide_1 ? (io_dis_bits_bits[26] ? offset[6:0] : 7'h0) : io_dis_bits_vstart; // @[Bundles.scala:75:20] if (~_GEN_1 | next_eidx >> _offset_T_13 == {1'h0, eidx >> _GEN}) begin // @[PipeSequencer.scala:40:34, :54:{15,33}, :60:{16,27,37}] if (_GEN_0) // @[Decoupled.scala:51:35] rvs2_mask <= io_dis_bits_renv2 ? _GEN_2[io_dis_bits_emul] : 32'h0; // @[PermuteSequencer.scala:20:22, :59:{21,53}] end else // @[PermuteSequencer.scala:42:22, :99:31, :100:91] rvs2_mask <= rvs2_mask & ~vs2_read_oh; // @[PermuteSequencer.scala:20:22, :73:24, :101:{30,32}] rvm_mask <= ~(_GEN_1 & next_eidx[7]) & (_GEN_0 ? io_dis_bits_renvm : rvm_mask); // @[Decoupled.scala:51:35] always @(posedge)
Generate the Verilog code corresponding to the following Chisel files. File AMOALU.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters class StoreGen(typ: UInt, addr: UInt, dat: UInt, maxSize: Int) { val size = Wire(UInt(log2Up(log2Up(maxSize)+1).W)) size := typ val dat_padded = dat.pad(maxSize*8) def misaligned: Bool = (addr & ((1.U << size) - 1.U)(log2Up(maxSize)-1,0)).orR def mask = { var res = 1.U for (i <- 0 until log2Up(maxSize)) { val upper = Mux(addr(i), res, 0.U) | Mux(size >= (i+1).U, ((BigInt(1) << (1 << i))-1).U, 0.U) val lower = Mux(addr(i), 0.U, res) res = Cat(upper, lower) } res } protected def genData(i: Int): UInt = if (i >= log2Up(maxSize)) dat_padded else Mux(size === i.U, Fill(1 << (log2Up(maxSize)-i), dat_padded((8 << i)-1,0)), genData(i+1)) def data = genData(0) def wordData = genData(2) } class LoadGen(typ: UInt, signed: Bool, addr: UInt, dat: UInt, zero: Bool, maxSize: Int) { private val size = new StoreGen(typ, addr, dat, maxSize).size private def genData(logMinSize: Int): UInt = { var res = dat for (i <- log2Up(maxSize)-1 to logMinSize by -1) { val pos = 8 << i val shifted = Mux(addr(i), res(2*pos-1,pos), res(pos-1,0)) val doZero = (i == 0).B && zero val zeroed = Mux(doZero, 0.U, shifted) res = Cat(Mux(size === i.U || doZero, Fill(8*maxSize-pos, signed && zeroed(pos-1)), res(8*maxSize-1,pos)), zeroed) } res } def wordData = genData(2) def data = genData(0) } class AMOALU(operandBits: Int)(implicit p: Parameters) extends Module { val minXLen = 32 val widths = (0 to log2Ceil(operandBits / minXLen)).map(minXLen << _) val io = IO(new Bundle { val mask = Input(UInt((operandBits / 8).W)) val cmd = Input(UInt(M_SZ.W)) val lhs = Input(UInt(operandBits.W)) val rhs = Input(UInt(operandBits.W)) val out = Output(UInt(operandBits.W)) val out_unmasked = Output(UInt(operandBits.W)) }) val max = io.cmd === M_XA_MAX || io.cmd === M_XA_MAXU val min = io.cmd === M_XA_MIN || io.cmd === M_XA_MINU val add = io.cmd === M_XA_ADD val logic_and = io.cmd === M_XA_OR || io.cmd === M_XA_AND val logic_xor = io.cmd === M_XA_XOR || io.cmd === M_XA_OR val adder_out = { // partition the carry chain to support sub-xLen addition val mask = ~(0.U(operandBits.W) +: widths.init.map(w => !io.mask(w/8-1) << (w-1))).reduce(_|_) (io.lhs & mask) + (io.rhs & mask) } val less = { // break up the comparator so the lower parts will be CSE'd def isLessUnsigned(x: UInt, y: UInt, n: Int): Bool = { if (n == minXLen) x(n-1, 0) < y(n-1, 0) else x(n-1, n/2) < y(n-1, n/2) || x(n-1, n/2) === y(n-1, n/2) && isLessUnsigned(x, y, n/2) } def isLess(x: UInt, y: UInt, n: Int): Bool = { val signed = { val mask = M_XA_MIN ^ M_XA_MINU (io.cmd & mask) === (M_XA_MIN & mask) } Mux(x(n-1) === y(n-1), isLessUnsigned(x, y, n), Mux(signed, x(n-1), y(n-1))) } PriorityMux(widths.reverse.map(w => (io.mask(w/8/2), isLess(io.lhs, io.rhs, w)))) } val minmax = Mux(Mux(less, min, max), io.lhs, io.rhs) val logic = Mux(logic_and, io.lhs & io.rhs, 0.U) | Mux(logic_xor, io.lhs ^ io.rhs, 0.U) val out = Mux(add, adder_out, Mux(logic_and || logic_xor, logic, minmax)) val wmask = FillInterleaved(8, io.mask) io.out := wmask & out | ~wmask & io.lhs io.out_unmasked := out }
module AMOALU_3( // @[AMOALU.scala:54:7] input clock, // @[AMOALU.scala:54:7] input reset, // @[AMOALU.scala:54:7] input [7:0] io_mask, // @[AMOALU.scala:58:14] input [4:0] io_cmd, // @[AMOALU.scala:58:14] input [63:0] io_lhs, // @[AMOALU.scala:58:14] input [63:0] io_rhs, // @[AMOALU.scala:58:14] output [63:0] io_out // @[AMOALU.scala:58:14] ); wire [7:0] io_mask_0 = io_mask; // @[AMOALU.scala:54:7] wire [4:0] io_cmd_0 = io_cmd; // @[AMOALU.scala:54:7] wire [63:0] io_lhs_0 = io_lhs; // @[AMOALU.scala:54:7] wire [63:0] io_rhs_0 = io_rhs; // @[AMOALU.scala:54:7] wire [3:0] less_signed_mask = 4'h2; // @[AMOALU.scala:88:29] wire [3:0] less_signed_mask_1 = 4'h2; // @[AMOALU.scala:88:29] wire [3:0] _less_signed_T_1 = 4'h0; // @[AMOALU.scala:89:39] wire [3:0] _less_signed_T_3 = 4'h0; // @[AMOALU.scala:89:39] wire [63:0] _io_out_T_3; // @[AMOALU.scala:107:25] wire [63:0] out; // @[AMOALU.scala:102:8] wire [63:0] io_out_0; // @[AMOALU.scala:54:7] wire [63:0] io_out_unmasked; // @[AMOALU.scala:54:7] wire _max_T = io_cmd_0 == 5'hD; // @[AMOALU.scala:54:7, :67:20] wire _max_T_1 = io_cmd_0 == 5'hF; // @[AMOALU.scala:54:7, :67:43] wire max = _max_T | _max_T_1; // @[AMOALU.scala:67:{20,33,43}] wire _min_T = io_cmd_0 == 5'hC; // @[AMOALU.scala:54:7, :68:20] wire _min_T_1 = io_cmd_0 == 5'hE; // @[AMOALU.scala:54:7, :68:43] wire min = _min_T | _min_T_1; // @[AMOALU.scala:68:{20,33,43}] wire add = io_cmd_0 == 5'h8; // @[AMOALU.scala:54:7, :69:20] wire _GEN = io_cmd_0 == 5'hA; // @[AMOALU.scala:54:7, :70:26] wire _logic_and_T; // @[AMOALU.scala:70:26] assign _logic_and_T = _GEN; // @[AMOALU.scala:70:26] wire _logic_xor_T_1; // @[AMOALU.scala:71:49] assign _logic_xor_T_1 = _GEN; // @[AMOALU.scala:70:26, :71:49] wire _logic_and_T_1 = io_cmd_0 == 5'hB; // @[AMOALU.scala:54:7, :70:48] wire logic_and = _logic_and_T | _logic_and_T_1; // @[AMOALU.scala:70:{26,38,48}] wire _logic_xor_T = io_cmd_0 == 5'h9; // @[AMOALU.scala:54:7, :71:26] wire logic_xor = _logic_xor_T | _logic_xor_T_1; // @[AMOALU.scala:71:{26,39,49}] wire _adder_out_mask_T = io_mask_0[3]; // @[AMOALU.scala:54:7, :75:69] wire _wmask_T_3 = io_mask_0[3]; // @[AMOALU.scala:54:7, :75:69, :106:30] wire _adder_out_mask_T_1 = ~_adder_out_mask_T; // @[AMOALU.scala:75:{61,69}] wire [31:0] _adder_out_mask_T_2 = {_adder_out_mask_T_1, 31'h0}; // @[AMOALU.scala:75:{61,77}] wire [63:0] _adder_out_mask_T_3 = {32'h0, _adder_out_mask_T_2}; // @[AMOALU.scala:75:{77,96}] wire [63:0] adder_out_mask = ~_adder_out_mask_T_3; // @[AMOALU.scala:75:{16,96}] wire [63:0] _adder_out_T = io_lhs_0 & adder_out_mask; // @[AMOALU.scala:54:7, :75:16, :76:13] wire [63:0] _adder_out_T_1 = io_rhs_0 & adder_out_mask; // @[AMOALU.scala:54:7, :75:16, :76:31] wire [64:0] _adder_out_T_2 = {1'h0, _adder_out_T} + {1'h0, _adder_out_T_1}; // @[AMOALU.scala:76:{13,21,31}] wire [63:0] adder_out = _adder_out_T_2[63:0]; // @[AMOALU.scala:76:21] wire _less_T = io_mask_0[4]; // @[AMOALU.scala:54:7, :94:49] wire _wmask_T_4 = io_mask_0[4]; // @[AMOALU.scala:54:7, :94:49, :106:30] wire [4:0] _GEN_0 = {3'h0, io_cmd_0[1], 1'h0}; // @[AMOALU.scala:54:7, :89:17] wire [4:0] _less_signed_T; // @[AMOALU.scala:89:17] assign _less_signed_T = _GEN_0; // @[AMOALU.scala:89:17] wire [4:0] _less_signed_T_2; // @[AMOALU.scala:89:17] assign _less_signed_T_2 = _GEN_0; // @[AMOALU.scala:89:17] wire less_signed = _less_signed_T == 5'h0; // @[AMOALU.scala:89:{17,25}] wire _less_T_1 = io_lhs_0[63]; // @[AMOALU.scala:54:7, :91:12] wire _less_T_15 = io_lhs_0[63]; // @[AMOALU.scala:54:7, :91:{12,68}] wire _less_T_2 = io_rhs_0[63]; // @[AMOALU.scala:54:7, :91:23] wire _less_T_16 = io_rhs_0[63]; // @[AMOALU.scala:54:7, :91:{23,76}] wire _less_T_3 = _less_T_1 == _less_T_2; // @[AMOALU.scala:91:{12,18,23}] wire [31:0] _less_T_4 = io_lhs_0[63:32]; // @[AMOALU.scala:54:7, :83:13] wire [31:0] _less_T_7 = io_lhs_0[63:32]; // @[AMOALU.scala:54:7, :83:{13,42}] wire [31:0] _less_T_5 = io_rhs_0[63:32]; // @[AMOALU.scala:54:7, :83:27] wire [31:0] _less_T_8 = io_rhs_0[63:32]; // @[AMOALU.scala:54:7, :83:{27,58}] wire _less_T_6 = _less_T_4 < _less_T_5; // @[AMOALU.scala:83:{13,24,27}] wire _less_T_9 = _less_T_7 == _less_T_8; // @[AMOALU.scala:83:{42,53,58}] wire [31:0] _less_T_10 = io_lhs_0[31:0]; // @[AMOALU.scala:54:7, :82:26] wire [31:0] _less_T_23 = io_lhs_0[31:0]; // @[AMOALU.scala:54:7, :82:26] wire [31:0] _less_T_11 = io_rhs_0[31:0]; // @[AMOALU.scala:54:7, :82:38] wire [31:0] _less_T_24 = io_rhs_0[31:0]; // @[AMOALU.scala:54:7, :82:38] wire _less_T_12 = _less_T_10 < _less_T_11; // @[AMOALU.scala:82:{26,35,38}] wire _less_T_13 = _less_T_9 & _less_T_12; // @[AMOALU.scala:82:35, :83:{53,69}] wire _less_T_14 = _less_T_6 | _less_T_13; // @[AMOALU.scala:83:{24,38,69}] wire _less_T_17 = less_signed ? _less_T_15 : _less_T_16; // @[AMOALU.scala:89:25, :91:{58,68,76}] wire _less_T_18 = _less_T_3 ? _less_T_14 : _less_T_17; // @[AMOALU.scala:83:38, :91:{10,18,58}] wire _less_T_19 = io_mask_0[2]; // @[AMOALU.scala:54:7, :94:49] wire _wmask_T_2 = io_mask_0[2]; // @[AMOALU.scala:54:7, :94:49, :106:30] wire less_signed_1 = _less_signed_T_2 == 5'h0; // @[AMOALU.scala:89:{17,25}] wire _less_T_20 = io_lhs_0[31]; // @[AMOALU.scala:54:7, :91:12] wire _less_T_26 = io_lhs_0[31]; // @[AMOALU.scala:54:7, :91:{12,68}] wire _less_T_21 = io_rhs_0[31]; // @[AMOALU.scala:54:7, :91:23] wire _less_T_27 = io_rhs_0[31]; // @[AMOALU.scala:54:7, :91:{23,76}] wire _less_T_22 = _less_T_20 == _less_T_21; // @[AMOALU.scala:91:{12,18,23}] wire _less_T_25 = _less_T_23 < _less_T_24; // @[AMOALU.scala:82:{26,35,38}] wire _less_T_28 = less_signed_1 ? _less_T_26 : _less_T_27; // @[AMOALU.scala:89:25, :91:{58,68,76}] wire _less_T_29 = _less_T_22 ? _less_T_25 : _less_T_28; // @[AMOALU.scala:82:35, :91:{10,18,58}] wire less = _less_T ? _less_T_18 : _less_T_29; // @[Mux.scala:50:70] wire _minmax_T = less ? min : max; // @[Mux.scala:50:70] wire [63:0] minmax = _minmax_T ? io_lhs_0 : io_rhs_0; // @[AMOALU.scala:54:7, :97:{19,23}] wire [63:0] _logic_T = io_lhs_0 & io_rhs_0; // @[AMOALU.scala:54:7, :99:27] wire [63:0] _logic_T_1 = logic_and ? _logic_T : 64'h0; // @[AMOALU.scala:70:38, :99:{8,27}] wire [63:0] _logic_T_2 = io_lhs_0 ^ io_rhs_0; // @[AMOALU.scala:54:7, :100:27] wire [63:0] _logic_T_3 = logic_xor ? _logic_T_2 : 64'h0; // @[AMOALU.scala:71:39, :100:{8,27}] wire [63:0] logic_0 = _logic_T_1 | _logic_T_3; // @[AMOALU.scala:99:{8,42}, :100:8] wire _out_T = logic_and | logic_xor; // @[AMOALU.scala:70:38, :71:39, :103:19] wire [63:0] _out_T_1 = _out_T ? logic_0 : minmax; // @[AMOALU.scala:97:19, :99:42, :103:{8,19}] assign out = add ? adder_out : _out_T_1; // @[AMOALU.scala:69:20, :76:21, :102:8, :103:8] assign io_out_unmasked = out; // @[AMOALU.scala:54:7, :102:8] wire _wmask_T = io_mask_0[0]; // @[AMOALU.scala:54:7, :106:30] wire _wmask_T_1 = io_mask_0[1]; // @[AMOALU.scala:54:7, :106:30] wire _wmask_T_5 = io_mask_0[5]; // @[AMOALU.scala:54:7, :106:30] wire _wmask_T_6 = io_mask_0[6]; // @[AMOALU.scala:54:7, :106:30] wire _wmask_T_7 = io_mask_0[7]; // @[AMOALU.scala:54:7, :106:30] wire [7:0] _wmask_T_8 = {8{_wmask_T}}; // @[AMOALU.scala:106:30] wire [7:0] _wmask_T_9 = {8{_wmask_T_1}}; // @[AMOALU.scala:106:30] wire [7:0] _wmask_T_10 = {8{_wmask_T_2}}; // @[AMOALU.scala:106:30] wire [7:0] _wmask_T_11 = {8{_wmask_T_3}}; // @[AMOALU.scala:106:30] wire [7:0] _wmask_T_12 = {8{_wmask_T_4}}; // @[AMOALU.scala:106:30] wire [7:0] _wmask_T_13 = {8{_wmask_T_5}}; // @[AMOALU.scala:106:30] wire [7:0] _wmask_T_14 = {8{_wmask_T_6}}; // @[AMOALU.scala:106:30] wire [7:0] _wmask_T_15 = {8{_wmask_T_7}}; // @[AMOALU.scala:106:30] wire [15:0] wmask_lo_lo = {_wmask_T_9, _wmask_T_8}; // @[AMOALU.scala:106:30] wire [15:0] wmask_lo_hi = {_wmask_T_11, _wmask_T_10}; // @[AMOALU.scala:106:30] wire [31:0] wmask_lo = {wmask_lo_hi, wmask_lo_lo}; // @[AMOALU.scala:106:30] wire [15:0] wmask_hi_lo = {_wmask_T_13, _wmask_T_12}; // @[AMOALU.scala:106:30] wire [15:0] wmask_hi_hi = {_wmask_T_15, _wmask_T_14}; // @[AMOALU.scala:106:30] wire [31:0] wmask_hi = {wmask_hi_hi, wmask_hi_lo}; // @[AMOALU.scala:106:30] wire [63:0] wmask = {wmask_hi, wmask_lo}; // @[AMOALU.scala:106:30] wire [63:0] _io_out_T = wmask & out; // @[AMOALU.scala:102:8, :106:30, :107:19] wire [63:0] _io_out_T_1 = ~wmask; // @[AMOALU.scala:106:30, :107:27] wire [63:0] _io_out_T_2 = _io_out_T_1 & io_lhs_0; // @[AMOALU.scala:54:7, :107:{27,34}] assign _io_out_T_3 = _io_out_T | _io_out_T_2; // @[AMOALU.scala:107:{19,25,34}] assign io_out_0 = _io_out_T_3; // @[AMOALU.scala:54:7, :107:25] assign io_out = io_out_0; // @[AMOALU.scala:54:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_51( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input io_in_c_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire [12:0] _GEN_0 = {10'h0, io_in_c_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [2:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [2:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _d_first_T_3 = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala:51:35] reg [2:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [2:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _c_first_T_1 = io_in_c_ready & io_in_c_valid; // @[Decoupled.scala:51:35] reg [2:0] c_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [2:0] size_3; // @[Monitor.scala:517:22] reg [2:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [4:0] inflight; // @[Monitor.scala:614:27] reg [19:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [19:0] inflight_sizes; // @[Monitor.scala:618:33] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire [7:0] _GEN_1 = {5'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_2 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_3 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [7:0] _GEN_4 = {5'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [4:0] inflight_1; // @[Monitor.scala:726:35] reg [19:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [2:0] c_first_counter_1; // @[Edges.scala:229:27] wire c_first_1 = c_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_5 = io_in_c_bits_opcode[2] & io_in_c_bits_opcode[1]; // @[Edges.scala:68:{36,40,51}] wire [7:0] _GEN_6 = {5'h0, io_in_c_bits_source}; // @[OneHot.scala:58:35] wire _GEN_7 = _c_first_T_1 & c_first_1 & _GEN_5; // @[Decoupled.scala:51:35] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] reg [7:0] inflight_2; // @[Monitor.scala:828:27] reg [2:0] d_first_counter_3; // @[Edges.scala:229:27] wire d_first_3 = d_first_counter_3 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_8 = _d_first_T_3 & d_first_3 & io_in_d_bits_opcode[2] & ~(io_in_d_bits_opcode[1]); // @[Decoupled.scala:51:35] wire [7:0] _GEN_9 = {5'h0, io_in_d_bits_sink}; // @[OneHot.scala:58:35] wire [7:0] d_set = _GEN_8 ? 8'h1 << _GEN_9 : 8'h0; // @[OneHot.scala:58:35] wire [7:0] _GEN_10 = {5'h0, io_in_e_bits_sink}; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: package constellation.channel import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy._ import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.util._ import constellation.noc.{HasNoCParams} class NoCMonitor(val cParam: ChannelParams)(implicit val p: Parameters) extends Module with HasNoCParams { val io = IO(new Bundle { val in = Input(new Channel(cParam)) }) val in_flight = RegInit(VecInit(Seq.fill(cParam.nVirtualChannels) { false.B })) for (i <- 0 until cParam.srcSpeedup) { val flit = io.in.flit(i) when (flit.valid) { when (flit.bits.head) { in_flight(flit.bits.virt_channel_id) := true.B assert (!in_flight(flit.bits.virt_channel_id), "Flit head/tail sequencing is broken") } when (flit.bits.tail) { in_flight(flit.bits.virt_channel_id) := false.B } } val possibleFlows = cParam.possibleFlows when (flit.valid && flit.bits.head) { cParam match { case n: ChannelParams => n.virtualChannelParams.zipWithIndex.foreach { case (v,i) => assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR) } case _ => assert(cParam.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR) } } } } File Types.scala: package constellation.routing import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Parameters} import constellation.noc.{HasNoCParams} import constellation.channel.{Flit} /** A representation for 1 specific virtual channel in wormhole routing * * @param src the source node * @param vc ID for the virtual channel * @param dst the destination node * @param n_vc the number of virtual channels */ // BEGIN: ChannelRoutingInfo case class ChannelRoutingInfo( src: Int, dst: Int, vc: Int, n_vc: Int ) { // END: ChannelRoutingInfo require (src >= -1 && dst >= -1 && vc >= 0, s"Illegal $this") require (!(src == -1 && dst == -1), s"Illegal $this") require (vc < n_vc, s"Illegal $this") val isIngress = src == -1 val isEgress = dst == -1 } /** Represents the properties of a packet that are relevant for routing * ingressId and egressId uniquely identify a flow, but vnet and dst are used here * to simplify the implementation of routingrelations * * @param ingressId packet's source ingress point * @param egressId packet's destination egress point * @param vNet virtual subnetwork identifier * @param dst packet's destination node ID */ // BEGIN: FlowRoutingInfo case class FlowRoutingInfo( ingressId: Int, egressId: Int, vNetId: Int, ingressNode: Int, ingressNodeId: Int, egressNode: Int, egressNodeId: Int, fifo: Boolean ) { // END: FlowRoutingInfo def isFlow(f: FlowRoutingBundle): Bool = { (f.ingress_node === ingressNode.U && f.egress_node === egressNode.U && f.ingress_node_id === ingressNodeId.U && f.egress_node_id === egressNodeId.U) } def asLiteral(b: FlowRoutingBundle): BigInt = { Seq( (vNetId , b.vnet_id), (ingressNode , b.ingress_node), (ingressNodeId , b.ingress_node_id), (egressNode , b.egress_node), (egressNodeId , b.egress_node_id) ).foldLeft(0)((l, t) => { (l << t._2.getWidth) | t._1 }) } } class FlowRoutingBundle(implicit val p: Parameters) extends Bundle with HasNoCParams { // Instead of tracking ingress/egress ID, track the physical destination id and the offset at the destination // This simplifies the routing tables val vnet_id = UInt(log2Ceil(nVirtualNetworks).W) val ingress_node = UInt(log2Ceil(nNodes).W) val ingress_node_id = UInt(log2Ceil(maxIngressesAtNode).W) val egress_node = UInt(log2Ceil(nNodes).W) val egress_node_id = UInt(log2Ceil(maxEgressesAtNode).W) }
module NoCMonitor_11( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [2:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26] reg in_flight_2; // @[Monitor.scala:16:26] wire _GEN = io_in_flit_0_bits_virt_channel_id == 2'h1; // @[Monitor.scala:21:46]
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File IBuf.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.{Decoupled,log2Ceil,Cat,UIntToOH,Fill} import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.tile._ import freechips.rocketchip.util._ class Instruction(implicit val p: Parameters) extends ParameterizedBundle with HasCoreParameters { val xcpt0 = new FrontendExceptions // exceptions on first half of instruction val xcpt1 = new FrontendExceptions // exceptions on second half of instruction val replay = Bool() val rvc = Bool() val inst = new ExpandedInstruction val raw = UInt(32.W) require(coreInstBits == (if (usingCompressed) 16 else 32)) } class IBuf(implicit p: Parameters) extends CoreModule { val io = IO(new Bundle { val imem = Flipped(Decoupled(new FrontendResp)) val kill = Input(Bool()) val pc = Output(UInt(vaddrBitsExtended.W)) val btb_resp = Output(new BTBResp()) val inst = Vec(retireWidth, Decoupled(new Instruction)) }) // This module is meant to be more general, but it's not there yet require(decodeWidth == 1) val n = fetchWidth - 1 val nBufValid = if (n == 0) 0.U else RegInit(init=0.U(log2Ceil(fetchWidth).W)) val buf = Reg(chiselTypeOf(io.imem.bits)) val ibufBTBResp = Reg(new BTBResp) val pcWordMask = (coreInstBytes*fetchWidth-1).U(vaddrBitsExtended.W) val pcWordBits = io.imem.bits.pc.extract(log2Ceil(fetchWidth*coreInstBytes)-1, log2Ceil(coreInstBytes)) val nReady = WireDefault(0.U(log2Ceil(fetchWidth+1).W)) val nIC = Mux(io.imem.bits.btb.taken, io.imem.bits.btb.bridx +& 1.U, fetchWidth.U) - pcWordBits val nICReady = nReady - nBufValid val nValid = Mux(io.imem.valid, nIC, 0.U) + nBufValid io.imem.ready := io.inst(0).ready && nReady >= nBufValid && (nICReady >= nIC || n.U >= nIC - nICReady) if (n > 0) { when (io.inst(0).ready) { nBufValid := Mux(nReady >== nBufValid, 0.U, nBufValid - nReady) if (n > 1) when (nReady > 0.U && nReady < nBufValid) { val shiftedBuf = shiftInsnRight(buf.data(n*coreInstBits-1, coreInstBits), (nReady-1.U)(log2Ceil(n-1)-1,0)) buf.data := Cat(buf.data(n*coreInstBits-1, (n-1)*coreInstBits), shiftedBuf((n-1)*coreInstBits-1, 0)) buf.pc := buf.pc & ~pcWordMask | (buf.pc + (nReady << log2Ceil(coreInstBytes))) & pcWordMask } when (io.imem.valid && nReady >= nBufValid && nICReady < nIC && n.U >= nIC - nICReady) { val shamt = pcWordBits + nICReady nBufValid := nIC - nICReady buf := io.imem.bits buf.data := shiftInsnRight(io.imem.bits.data, shamt)(n*coreInstBits-1,0) buf.pc := io.imem.bits.pc & ~pcWordMask | (io.imem.bits.pc + (nICReady << log2Ceil(coreInstBytes))) & pcWordMask ibufBTBResp := io.imem.bits.btb } } when (io.kill) { nBufValid := 0.U } } val icShiftAmt = (fetchWidth.U + nBufValid - pcWordBits)(log2Ceil(fetchWidth), 0) val icData = shiftInsnLeft(Cat(io.imem.bits.data, Fill(fetchWidth, io.imem.bits.data(coreInstBits-1, 0))), icShiftAmt) .extract(3*fetchWidth*coreInstBits-1, 2*fetchWidth*coreInstBits) val icMask = (~0.U((fetchWidth*coreInstBits).W) << (nBufValid << log2Ceil(coreInstBits)))(fetchWidth*coreInstBits-1,0) val inst = icData & icMask | buf.data & ~icMask val valid = (UIntToOH(nValid) - 1.U)(fetchWidth-1, 0) val bufMask = UIntToOH(nBufValid) - 1.U val xcpt = (0 until bufMask.getWidth).map(i => Mux(bufMask(i), buf.xcpt, io.imem.bits.xcpt)) val buf_replay = Mux(buf.replay, bufMask, 0.U) val ic_replay = buf_replay | Mux(io.imem.bits.replay, valid & ~bufMask, 0.U) assert(!io.imem.valid || !io.imem.bits.btb.taken || io.imem.bits.btb.bridx >= pcWordBits) io.btb_resp := io.imem.bits.btb io.pc := Mux(nBufValid > 0.U, buf.pc, io.imem.bits.pc) expand(0, 0.U, inst) def expand(i: Int, j: UInt, curInst: UInt): Unit = if (i < retireWidth) { val exp = Module(new RVCExpander) exp.io.in := curInst io.inst(i).bits.inst := exp.io.out io.inst(i).bits.raw := curInst if (usingCompressed) { val replay = ic_replay(j) || (!exp.io.rvc && ic_replay(j+1.U)) val full_insn = exp.io.rvc || valid(j+1.U) || buf_replay(j) io.inst(i).valid := valid(j) && full_insn io.inst(i).bits.xcpt0 := xcpt(j) io.inst(i).bits.xcpt1 := Mux(exp.io.rvc, 0.U, xcpt(j+1.U).asUInt).asTypeOf(new FrontendExceptions) io.inst(i).bits.replay := replay io.inst(i).bits.rvc := exp.io.rvc when ((bufMask(j) && exp.io.rvc) || bufMask(j+1.U)) { io.btb_resp := ibufBTBResp } when (full_insn && ((i == 0).B || io.inst(i).ready)) { nReady := Mux(exp.io.rvc, j+1.U, j+2.U) } expand(i+1, Mux(exp.io.rvc, j+1.U, j+2.U), Mux(exp.io.rvc, curInst >> 16, curInst >> 32)) } else { when ((i == 0).B || io.inst(i).ready) { nReady := (i+1).U } io.inst(i).valid := valid(i) io.inst(i).bits.xcpt0 := xcpt(i) io.inst(i).bits.xcpt1 := 0.U.asTypeOf(new FrontendExceptions) io.inst(i).bits.replay := ic_replay(i) io.inst(i).bits.rvc := false.B expand(i+1, null, curInst >> 32) } } def shiftInsnLeft(in: UInt, dist: UInt) = { val r = in.getWidth/coreInstBits require(in.getWidth % coreInstBits == 0) val data = Cat(Fill((1 << (log2Ceil(r) + 1)) - r, in >> (r-1)*coreInstBits), in) data << (dist << log2Ceil(coreInstBits)) } def shiftInsnRight(in: UInt, dist: UInt) = { val r = in.getWidth/coreInstBits require(in.getWidth % coreInstBits == 0) val data = Cat(Fill((1 << (log2Ceil(r) + 1)) - r, in >> (r-1)*coreInstBits), in) data >> (dist << log2Ceil(coreInstBits)) } }
module IBuf_7( // @[IBuf.scala:21:7] input clock, // @[IBuf.scala:21:7] input reset, // @[IBuf.scala:21:7] output io_imem_ready, // @[IBuf.scala:22:14] input io_imem_valid, // @[IBuf.scala:22:14] input [1:0] io_imem_bits_btb_cfiType, // @[IBuf.scala:22:14] input io_imem_bits_btb_taken, // @[IBuf.scala:22:14] input [1:0] io_imem_bits_btb_mask, // @[IBuf.scala:22:14] input io_imem_bits_btb_bridx, // @[IBuf.scala:22:14] input [38:0] io_imem_bits_btb_target, // @[IBuf.scala:22:14] input [4:0] io_imem_bits_btb_entry, // @[IBuf.scala:22:14] input [7:0] io_imem_bits_btb_bht_history, // @[IBuf.scala:22:14] input io_imem_bits_btb_bht_value, // @[IBuf.scala:22:14] input [39:0] io_imem_bits_pc, // @[IBuf.scala:22:14] input [31:0] io_imem_bits_data, // @[IBuf.scala:22:14] input [1:0] io_imem_bits_mask, // @[IBuf.scala:22:14] input io_imem_bits_xcpt_pf_inst, // @[IBuf.scala:22:14] input io_imem_bits_xcpt_gf_inst, // @[IBuf.scala:22:14] input io_imem_bits_xcpt_ae_inst, // @[IBuf.scala:22:14] input io_imem_bits_replay, // @[IBuf.scala:22:14] input io_kill, // @[IBuf.scala:22:14] output [39:0] io_pc, // @[IBuf.scala:22:14] output [1:0] io_btb_resp_cfiType, // @[IBuf.scala:22:14] output io_btb_resp_taken, // @[IBuf.scala:22:14] output [1:0] io_btb_resp_mask, // @[IBuf.scala:22:14] output io_btb_resp_bridx, // @[IBuf.scala:22:14] output [38:0] io_btb_resp_target, // @[IBuf.scala:22:14] output [4:0] io_btb_resp_entry, // @[IBuf.scala:22:14] output [7:0] io_btb_resp_bht_history, // @[IBuf.scala:22:14] output io_btb_resp_bht_value, // @[IBuf.scala:22:14] input io_inst_0_ready, // @[IBuf.scala:22:14] output io_inst_0_valid, // @[IBuf.scala:22:14] output io_inst_0_bits_xcpt0_pf_inst, // @[IBuf.scala:22:14] output io_inst_0_bits_xcpt0_gf_inst, // @[IBuf.scala:22:14] output io_inst_0_bits_xcpt0_ae_inst, // @[IBuf.scala:22:14] output io_inst_0_bits_xcpt1_pf_inst, // @[IBuf.scala:22:14] output io_inst_0_bits_xcpt1_gf_inst, // @[IBuf.scala:22:14] output io_inst_0_bits_xcpt1_ae_inst, // @[IBuf.scala:22:14] output io_inst_0_bits_replay, // @[IBuf.scala:22:14] output io_inst_0_bits_rvc, // @[IBuf.scala:22:14] output [31:0] io_inst_0_bits_inst_bits, // @[IBuf.scala:22:14] output [4:0] io_inst_0_bits_inst_rd, // @[IBuf.scala:22:14] output [4:0] io_inst_0_bits_inst_rs1, // @[IBuf.scala:22:14] output [4:0] io_inst_0_bits_inst_rs2, // @[IBuf.scala:22:14] output [4:0] io_inst_0_bits_inst_rs3, // @[IBuf.scala:22:14] output [31:0] io_inst_0_bits_raw // @[IBuf.scala:22:14] ); wire _exp_io_rvc; // @[IBuf.scala:86:21] wire io_imem_valid_0 = io_imem_valid; // @[IBuf.scala:21:7] wire [1:0] io_imem_bits_btb_cfiType_0 = io_imem_bits_btb_cfiType; // @[IBuf.scala:21:7] wire io_imem_bits_btb_taken_0 = io_imem_bits_btb_taken; // @[IBuf.scala:21:7] wire [1:0] io_imem_bits_btb_mask_0 = io_imem_bits_btb_mask; // @[IBuf.scala:21:7] wire io_imem_bits_btb_bridx_0 = io_imem_bits_btb_bridx; // @[IBuf.scala:21:7] wire [38:0] io_imem_bits_btb_target_0 = io_imem_bits_btb_target; // @[IBuf.scala:21:7] wire [4:0] io_imem_bits_btb_entry_0 = io_imem_bits_btb_entry; // @[IBuf.scala:21:7] wire [7:0] io_imem_bits_btb_bht_history_0 = io_imem_bits_btb_bht_history; // @[IBuf.scala:21:7] wire io_imem_bits_btb_bht_value_0 = io_imem_bits_btb_bht_value; // @[IBuf.scala:21:7] wire [39:0] io_imem_bits_pc_0 = io_imem_bits_pc; // @[IBuf.scala:21:7] wire [31:0] io_imem_bits_data_0 = io_imem_bits_data; // @[IBuf.scala:21:7] wire [1:0] io_imem_bits_mask_0 = io_imem_bits_mask; // @[IBuf.scala:21:7] wire io_imem_bits_xcpt_pf_inst_0 = io_imem_bits_xcpt_pf_inst; // @[IBuf.scala:21:7] wire io_imem_bits_xcpt_gf_inst_0 = io_imem_bits_xcpt_gf_inst; // @[IBuf.scala:21:7] wire io_imem_bits_xcpt_ae_inst_0 = io_imem_bits_xcpt_ae_inst; // @[IBuf.scala:21:7] wire io_imem_bits_replay_0 = io_imem_bits_replay; // @[IBuf.scala:21:7] wire io_kill_0 = io_kill; // @[IBuf.scala:21:7] wire io_inst_0_ready_0 = io_inst_0_ready; // @[IBuf.scala:21:7] wire [1:0] _replay_T_3 = 2'h1; // @[IBuf.scala:92:63] wire [1:0] _full_insn_T = 2'h1; // @[IBuf.scala:93:44] wire [1:0] _io_inst_0_bits_xcpt1_T = 2'h1; // @[IBuf.scala:96:59] wire [1:0] _nReady_T = 2'h1; // @[IBuf.scala:102:89] wire [1:0] _nReady_T_3 = 2'h2; // @[IBuf.scala:102:96] wire _replay_T_4 = 1'h1; // @[IBuf.scala:92:63] wire _full_insn_T_1 = 1'h1; // @[IBuf.scala:93:44] wire _io_inst_0_bits_xcpt1_T_1 = 1'h1; // @[IBuf.scala:96:59] wire _io_inst_0_bits_xcpt1_T_2 = 1'h1; // @[package.scala:39:86] wire _nReady_T_1 = 1'h1; // @[IBuf.scala:102:89] wire _io_inst_0_bits_xcpt0_T = 1'h0; // @[package.scala:39:86] wire [31:0] _icMask_T = 32'hFFFFFFFF; // @[IBuf.scala:71:17] wire [39:0] _buf_pc_T = 40'hFFFFFFFFFC; // @[IBuf.scala:59:37] wire [2:0] _nReady_T_2 = 3'h2; // @[IBuf.scala:102:96] wire _io_imem_ready_T_7; // @[IBuf.scala:44:60] wire [39:0] _io_pc_T_1; // @[IBuf.scala:82:15] wire _io_inst_0_valid_T_2; // @[IBuf.scala:94:36] wire _io_inst_0_bits_xcpt0_T_1_pf_inst; // @[package.scala:39:76] wire _io_inst_0_bits_xcpt0_T_1_gf_inst; // @[package.scala:39:76] wire _io_inst_0_bits_xcpt0_T_1_ae_inst; // @[package.scala:39:76] wire _io_inst_0_bits_xcpt1_WIRE_pf_inst; // @[IBuf.scala:96:81] wire _io_inst_0_bits_xcpt1_WIRE_gf_inst; // @[IBuf.scala:96:81] wire _io_inst_0_bits_xcpt1_WIRE_ae_inst; // @[IBuf.scala:96:81] wire replay; // @[IBuf.scala:92:33] wire [31:0] inst; // @[IBuf.scala:72:30] wire io_imem_ready_0; // @[IBuf.scala:21:7] wire [7:0] io_btb_resp_bht_history_0; // @[IBuf.scala:21:7] wire io_btb_resp_bht_value_0; // @[IBuf.scala:21:7] wire [1:0] io_btb_resp_cfiType_0; // @[IBuf.scala:21:7] wire io_btb_resp_taken_0; // @[IBuf.scala:21:7] wire [1:0] io_btb_resp_mask_0; // @[IBuf.scala:21:7] wire io_btb_resp_bridx_0; // @[IBuf.scala:21:7] wire [38:0] io_btb_resp_target_0; // @[IBuf.scala:21:7] wire [4:0] io_btb_resp_entry_0; // @[IBuf.scala:21:7] wire io_inst_0_bits_xcpt0_pf_inst_0; // @[IBuf.scala:21:7] wire io_inst_0_bits_xcpt0_gf_inst_0; // @[IBuf.scala:21:7] wire io_inst_0_bits_xcpt0_ae_inst_0; // @[IBuf.scala:21:7] wire io_inst_0_bits_xcpt1_pf_inst_0; // @[IBuf.scala:21:7] wire io_inst_0_bits_xcpt1_gf_inst_0; // @[IBuf.scala:21:7] wire io_inst_0_bits_xcpt1_ae_inst_0; // @[IBuf.scala:21:7] wire [31:0] io_inst_0_bits_inst_bits_0; // @[IBuf.scala:21:7] wire [4:0] io_inst_0_bits_inst_rd_0; // @[IBuf.scala:21:7] wire [4:0] io_inst_0_bits_inst_rs1_0; // @[IBuf.scala:21:7] wire [4:0] io_inst_0_bits_inst_rs2_0; // @[IBuf.scala:21:7] wire [4:0] io_inst_0_bits_inst_rs3_0; // @[IBuf.scala:21:7] wire io_inst_0_bits_replay_0; // @[IBuf.scala:21:7] wire io_inst_0_bits_rvc_0; // @[IBuf.scala:21:7] wire [31:0] io_inst_0_bits_raw_0; // @[IBuf.scala:21:7] wire io_inst_0_valid_0; // @[IBuf.scala:21:7] wire [39:0] io_pc_0; // @[IBuf.scala:21:7] reg nBufValid; // @[IBuf.scala:34:47] wire _io_pc_T = nBufValid; // @[IBuf.scala:34:47, :82:26] reg [1:0] buf_btb_cfiType; // @[IBuf.scala:35:16] reg buf_btb_taken; // @[IBuf.scala:35:16] reg [1:0] buf_btb_mask; // @[IBuf.scala:35:16] reg buf_btb_bridx; // @[IBuf.scala:35:16] reg [38:0] buf_btb_target; // @[IBuf.scala:35:16] reg [4:0] buf_btb_entry; // @[IBuf.scala:35:16] reg [7:0] buf_btb_bht_history; // @[IBuf.scala:35:16] reg buf_btb_bht_value; // @[IBuf.scala:35:16] reg [39:0] buf_pc; // @[IBuf.scala:35:16] reg [31:0] buf_data; // @[IBuf.scala:35:16] reg [1:0] buf_mask; // @[IBuf.scala:35:16] reg buf_xcpt_pf_inst; // @[IBuf.scala:35:16] reg buf_xcpt_gf_inst; // @[IBuf.scala:35:16] reg buf_xcpt_ae_inst; // @[IBuf.scala:35:16] reg buf_replay; // @[IBuf.scala:35:16] reg [1:0] ibufBTBResp_cfiType; // @[IBuf.scala:36:24] reg ibufBTBResp_taken; // @[IBuf.scala:36:24] reg [1:0] ibufBTBResp_mask; // @[IBuf.scala:36:24] reg ibufBTBResp_bridx; // @[IBuf.scala:36:24] reg [38:0] ibufBTBResp_target; // @[IBuf.scala:36:24] reg [4:0] ibufBTBResp_entry; // @[IBuf.scala:36:24] reg [7:0] ibufBTBResp_bht_history; // @[IBuf.scala:36:24] reg ibufBTBResp_bht_value; // @[IBuf.scala:36:24] wire pcWordBits = io_imem_bits_pc_0[1]; // @[package.scala:163:13] wire [1:0] nReady; // @[IBuf.scala:40:27] wire [1:0] _nIC_T = {1'h0, io_imem_bits_btb_bridx_0} + 2'h1; // @[IBuf.scala:21:7, :41:64] wire [1:0] _nIC_T_1 = io_imem_bits_btb_taken_0 ? _nIC_T : 2'h2; // @[IBuf.scala:21:7, :41:{16,64}] wire [2:0] _GEN = {2'h0, pcWordBits}; // @[package.scala:163:13] wire [2:0] _nIC_T_2 = {1'h0, _nIC_T_1} - _GEN; // @[IBuf.scala:41:{16,86}] wire [1:0] nIC = _nIC_T_2[1:0]; // @[IBuf.scala:41:86] wire [2:0] _GEN_0 = {1'h0, nReady}; // @[IBuf.scala:40:27, :42:25] wire [2:0] _GEN_1 = {2'h0, nBufValid}; // @[IBuf.scala:34:47, :42:25] wire [2:0] _nICReady_T = _GEN_0 - _GEN_1; // @[IBuf.scala:42:25] wire [1:0] nICReady = _nICReady_T[1:0]; // @[IBuf.scala:42:25] wire [1:0] _nValid_T = io_imem_valid_0 ? nIC : 2'h0; // @[IBuf.scala:21:7, :41:86, :43:19] wire [2:0] _nValid_T_1 = {1'h0, _nValid_T} + _GEN_1; // @[IBuf.scala:42:25, :43:{19,45}] wire [1:0] nValid = _nValid_T_1[1:0]; // @[IBuf.scala:43:45] wire [1:0] _GEN_2 = {1'h0, nBufValid}; // @[IBuf.scala:34:47, :44:47] wire _T = nReady >= _GEN_2; // @[IBuf.scala:40:27, :44:47] wire _io_imem_ready_T; // @[IBuf.scala:44:47] assign _io_imem_ready_T = _T; // @[IBuf.scala:44:47] wire _nBufValid_T; // @[package.scala:218:33] assign _nBufValid_T = _T; // @[package.scala:218:33] wire _io_imem_ready_T_1 = io_inst_0_ready_0 & _io_imem_ready_T; // @[IBuf.scala:21:7, :44:{37,47}] wire _io_imem_ready_T_2 = nICReady >= nIC; // @[IBuf.scala:41:86, :42:25, :44:73] wire [2:0] _GEN_3 = {1'h0, nICReady}; // @[IBuf.scala:42:25, :44:94] wire [2:0] _T_4 = {1'h0, nIC} - _GEN_3; // @[IBuf.scala:41:86, :44:94] wire [2:0] _io_imem_ready_T_3; // @[IBuf.scala:44:94] assign _io_imem_ready_T_3 = _T_4; // @[IBuf.scala:44:94] wire [2:0] _nBufValid_T_6; // @[IBuf.scala:56:26] assign _nBufValid_T_6 = _T_4; // @[IBuf.scala:44:94, :56:26] wire [1:0] _io_imem_ready_T_4 = _io_imem_ready_T_3[1:0]; // @[IBuf.scala:44:94] wire _io_imem_ready_T_5 = ~(_io_imem_ready_T_4[1]); // @[IBuf.scala:44:{87,94}] wire _io_imem_ready_T_6 = _io_imem_ready_T_2 | _io_imem_ready_T_5; // @[IBuf.scala:44:{73,80,87}] assign _io_imem_ready_T_7 = _io_imem_ready_T_1 & _io_imem_ready_T_6; // @[IBuf.scala:44:{37,60,80}] assign io_imem_ready_0 = _io_imem_ready_T_7; // @[IBuf.scala:21:7, :44:60] wire _nBufValid_T_1 = ~nBufValid; // @[package.scala:218:43] wire _nBufValid_T_2 = _nBufValid_T | _nBufValid_T_1; // @[package.scala:218:{33,38,43}] wire [2:0] _nBufValid_T_3 = _GEN_1 - _GEN_0; // @[IBuf.scala:42:25, :48:61] wire [1:0] _nBufValid_T_4 = _nBufValid_T_3[1:0]; // @[IBuf.scala:48:61] wire [1:0] _nBufValid_T_5 = _nBufValid_T_2 ? 2'h0 : _nBufValid_T_4; // @[package.scala:218:38] wire [2:0] _shamt_T = _GEN + _GEN_3; // @[IBuf.scala:41:86, :44:94, :55:32] wire [1:0] shamt = _shamt_T[1:0]; // @[IBuf.scala:55:32] wire [1:0] _nBufValid_T_7 = _nBufValid_T_6[1:0]; // @[IBuf.scala:56:26] wire [15:0] _buf_data_data_T = io_imem_bits_data_0[31:16]; // @[IBuf.scala:21:7, :127:58] wire [31:0] _buf_data_data_T_1 = {2{_buf_data_data_T}}; // @[IBuf.scala:127:{24,58}] wire [63:0] buf_data_data = {_buf_data_data_T_1, io_imem_bits_data_0}; // @[IBuf.scala:21:7, :127:{19,24}] wire [5:0] _buf_data_T = {shamt, 4'h0}; // @[IBuf.scala:55:32, :128:19] wire [63:0] _buf_data_T_1 = buf_data_data >> _buf_data_T; // @[IBuf.scala:127:19, :128:{10,19}] wire [15:0] _buf_data_T_2 = _buf_data_T_1[15:0]; // @[IBuf.scala:58:61, :128:10] wire [39:0] _buf_pc_T_1 = io_imem_bits_pc_0 & 40'hFFFFFFFFFC; // @[IBuf.scala:21:7, :59:35] wire [2:0] _buf_pc_T_2 = {nICReady, 1'h0}; // @[IBuf.scala:42:25, :59:80] wire [40:0] _buf_pc_T_3 = {1'h0, io_imem_bits_pc_0} + {38'h0, _buf_pc_T_2}; // @[IBuf.scala:21:7, :59:{68,80}] wire [39:0] _buf_pc_T_4 = _buf_pc_T_3[39:0]; // @[IBuf.scala:59:68] wire [39:0] _buf_pc_T_5 = _buf_pc_T_4 & 40'h3; // @[IBuf.scala:59:{68,109}] wire [39:0] _buf_pc_T_6 = _buf_pc_T_1 | _buf_pc_T_5; // @[IBuf.scala:59:{35,49,109}] wire [2:0] _icShiftAmt_T = _GEN_1 + 3'h2; // @[IBuf.scala:42:25, :68:34] wire [1:0] _icShiftAmt_T_1 = _icShiftAmt_T[1:0]; // @[IBuf.scala:68:34] wire [2:0] _icShiftAmt_T_2 = {1'h0, _icShiftAmt_T_1} - _GEN; // @[IBuf.scala:41:86, :68:{34,46}] wire [1:0] _icShiftAmt_T_3 = _icShiftAmt_T_2[1:0]; // @[IBuf.scala:68:46] wire [1:0] icShiftAmt = _icShiftAmt_T_3; // @[IBuf.scala:68:{46,59}] wire [15:0] _icData_T = io_imem_bits_data_0[15:0]; // @[IBuf.scala:21:7, :69:87] wire [31:0] _icData_T_1 = {2{_icData_T}}; // @[IBuf.scala:69:{57,87}] wire [63:0] _icData_T_2 = {io_imem_bits_data_0, _icData_T_1}; // @[IBuf.scala:21:7, :69:{33,57}] wire [15:0] _icData_data_T = _icData_T_2[63:48]; // @[IBuf.scala:69:33, :120:58] wire [31:0] _icData_data_T_1 = {2{_icData_data_T}}; // @[IBuf.scala:120:{24,58}] wire [63:0] _icData_data_T_2 = {2{_icData_data_T_1}}; // @[IBuf.scala:120:24] wire [127:0] icData_data = {_icData_data_T_2, _icData_T_2}; // @[IBuf.scala:69:33, :120:{19,24}] wire [5:0] _icData_T_3 = {icShiftAmt, 4'h0}; // @[IBuf.scala:68:59, :121:19] wire [190:0] _icData_T_4 = {63'h0, icData_data} << _icData_T_3; // @[IBuf.scala:120:19, :121:{10,19}] wire [31:0] icData = _icData_T_4[95:64]; // @[package.scala:163:13] wire [4:0] _icMask_T_1 = {nBufValid, 4'h0}; // @[IBuf.scala:34:47, :71:65] wire [62:0] _icMask_T_2 = 63'hFFFFFFFF << _icMask_T_1; // @[IBuf.scala:71:{51,65}] wire [31:0] icMask = _icMask_T_2[31:0]; // @[IBuf.scala:71:{51,92}] wire [31:0] _inst_T = icData & icMask; // @[package.scala:163:13] wire [31:0] _inst_T_1 = ~icMask; // @[IBuf.scala:71:92, :72:43] wire [31:0] _inst_T_2 = buf_data & _inst_T_1; // @[IBuf.scala:35:16, :72:{41,43}] assign inst = _inst_T | _inst_T_2; // @[IBuf.scala:72:{21,30,41}] assign io_inst_0_bits_raw_0 = inst; // @[IBuf.scala:21:7, :72:30] wire [3:0] _valid_T = 4'h1 << nValid; // @[OneHot.scala:58:35] wire [4:0] _valid_T_1 = {1'h0, _valid_T} - 5'h1; // @[OneHot.scala:58:35] wire [3:0] _valid_T_2 = _valid_T_1[3:0]; // @[IBuf.scala:74:33] wire [1:0] valid = _valid_T_2[1:0]; // @[IBuf.scala:74:{33,39}] wire [1:0] _io_inst_0_valid_T = valid; // @[IBuf.scala:74:39, :94:32] wire [1:0] _bufMask_T = 2'h1 << _GEN_2; // @[OneHot.scala:58:35] wire [2:0] _bufMask_T_1 = {1'h0, _bufMask_T} - 3'h1; // @[OneHot.scala:58:35] wire [1:0] bufMask = _bufMask_T_1[1:0]; // @[IBuf.scala:75:37] wire _xcpt_T = bufMask[0]; // @[IBuf.scala:75:37, :76:61] wire xcpt_0_pf_inst = _xcpt_T ? buf_xcpt_pf_inst : io_imem_bits_xcpt_pf_inst_0; // @[IBuf.scala:21:7, :35:16, :76:{53,61}] wire xcpt_0_gf_inst = _xcpt_T ? buf_xcpt_gf_inst : io_imem_bits_xcpt_gf_inst_0; // @[IBuf.scala:21:7, :35:16, :76:{53,61}] wire xcpt_0_ae_inst = _xcpt_T ? buf_xcpt_ae_inst : io_imem_bits_xcpt_ae_inst_0; // @[IBuf.scala:21:7, :35:16, :76:{53,61}] assign _io_inst_0_bits_xcpt0_T_1_pf_inst = xcpt_0_pf_inst; // @[package.scala:39:76] assign _io_inst_0_bits_xcpt0_T_1_gf_inst = xcpt_0_gf_inst; // @[package.scala:39:76] assign _io_inst_0_bits_xcpt0_T_1_ae_inst = xcpt_0_ae_inst; // @[package.scala:39:76] wire _xcpt_T_1 = bufMask[1]; // @[IBuf.scala:75:37, :76:61] wire xcpt_1_pf_inst = _xcpt_T_1 ? buf_xcpt_pf_inst : io_imem_bits_xcpt_pf_inst_0; // @[IBuf.scala:21:7, :35:16, :76:{53,61}] wire xcpt_1_gf_inst = _xcpt_T_1 ? buf_xcpt_gf_inst : io_imem_bits_xcpt_gf_inst_0; // @[IBuf.scala:21:7, :35:16, :76:{53,61}] wire xcpt_1_ae_inst = _xcpt_T_1 ? buf_xcpt_ae_inst : io_imem_bits_xcpt_ae_inst_0; // @[IBuf.scala:21:7, :35:16, :76:{53,61}] wire _io_inst_0_bits_xcpt1_T_3_pf_inst = xcpt_1_pf_inst; // @[package.scala:39:76] wire _io_inst_0_bits_xcpt1_T_3_gf_inst = xcpt_1_gf_inst; // @[package.scala:39:76] wire _io_inst_0_bits_xcpt1_T_3_ae_inst = xcpt_1_ae_inst; // @[package.scala:39:76] wire [1:0] buf_replay_0 = buf_replay ? bufMask : 2'h0; // @[IBuf.scala:35:16, :75:37, :77:23] wire [1:0] _full_insn_T_5 = buf_replay_0; // @[IBuf.scala:77:23, :93:63] wire [1:0] _ic_replay_T = ~bufMask; // @[IBuf.scala:75:37, :78:65] wire [1:0] _ic_replay_T_1 = valid & _ic_replay_T; // @[IBuf.scala:74:39, :78:{63,65}] wire [1:0] _ic_replay_T_2 = io_imem_bits_replay_0 ? _ic_replay_T_1 : 2'h0; // @[IBuf.scala:21:7, :78:{35,63}] wire [1:0] ic_replay = buf_replay_0 | _ic_replay_T_2; // @[IBuf.scala:77:23, :78:{30,35}] wire [1:0] _replay_T = ic_replay; // @[IBuf.scala:78:30, :92:29]
Generate the Verilog code corresponding to the following Chisel files. File MSHR.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import freechips.rocketchip.tilelink._ import TLPermissions._ import TLMessages._ import MetaData._ import chisel3.PrintableHelper import chisel3.experimental.dataview._ class ScheduleRequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val a = Valid(new SourceARequest(params)) val b = Valid(new SourceBRequest(params)) val c = Valid(new SourceCRequest(params)) val d = Valid(new SourceDRequest(params)) val e = Valid(new SourceERequest(params)) val x = Valid(new SourceXRequest(params)) val dir = Valid(new DirectoryWrite(params)) val reload = Bool() // get next request via allocate (if any) } class MSHRStatus(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val set = UInt(params.setBits.W) val tag = UInt(params.tagBits.W) val way = UInt(params.wayBits.W) val blockB = Bool() val nestB = Bool() val blockC = Bool() val nestC = Bool() } class NestedWriteback(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val set = UInt(params.setBits.W) val tag = UInt(params.tagBits.W) val b_toN = Bool() // nested Probes may unhit us val b_toB = Bool() // nested Probes may demote us val b_clr_dirty = Bool() // nested Probes clear dirty val c_set_dirty = Bool() // nested Releases MAY set dirty } sealed trait CacheState { val code = CacheState.index.U CacheState.index = CacheState.index + 1 } object CacheState { var index = 0 } case object S_INVALID extends CacheState case object S_BRANCH extends CacheState case object S_BRANCH_C extends CacheState case object S_TIP extends CacheState case object S_TIP_C extends CacheState case object S_TIP_CD extends CacheState case object S_TIP_D extends CacheState case object S_TRUNK_C extends CacheState case object S_TRUNK_CD extends CacheState class MSHR(params: InclusiveCacheParameters) extends Module { val io = IO(new Bundle { val allocate = Flipped(Valid(new AllocateRequest(params))) // refills MSHR for next cycle val directory = Flipped(Valid(new DirectoryResult(params))) // triggers schedule setup val status = Valid(new MSHRStatus(params)) val schedule = Decoupled(new ScheduleRequest(params)) val sinkc = Flipped(Valid(new SinkCResponse(params))) val sinkd = Flipped(Valid(new SinkDResponse(params))) val sinke = Flipped(Valid(new SinkEResponse(params))) val nestedwb = Flipped(new NestedWriteback(params)) }) val request_valid = RegInit(false.B) val request = Reg(new FullRequest(params)) val meta_valid = RegInit(false.B) val meta = Reg(new DirectoryResult(params)) // Define which states are valid when (meta_valid) { when (meta.state === INVALID) { assert (!meta.clients.orR) assert (!meta.dirty) } when (meta.state === BRANCH) { assert (!meta.dirty) } when (meta.state === TRUNK) { assert (meta.clients.orR) assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one } when (meta.state === TIP) { // noop } } // Completed transitions (s_ = scheduled), (w_ = waiting) val s_rprobe = RegInit(true.B) // B val w_rprobeackfirst = RegInit(true.B) val w_rprobeacklast = RegInit(true.B) val s_release = RegInit(true.B) // CW w_rprobeackfirst val w_releaseack = RegInit(true.B) val s_pprobe = RegInit(true.B) // B val s_acquire = RegInit(true.B) // A s_release, s_pprobe [1] val s_flush = RegInit(true.B) // X w_releaseack val w_grantfirst = RegInit(true.B) val w_grantlast = RegInit(true.B) val w_grant = RegInit(true.B) // first | last depending on wormhole val w_pprobeackfirst = RegInit(true.B) val w_pprobeacklast = RegInit(true.B) val w_pprobeack = RegInit(true.B) // first | last depending on wormhole val s_probeack = RegInit(true.B) // C w_pprobeackfirst (mutually exclusive with next two s_*) val s_grantack = RegInit(true.B) // E w_grantfirst ... CAN require both outE&inD to service outD val s_execute = RegInit(true.B) // D w_pprobeack, w_grant val w_grantack = RegInit(true.B) val s_writeback = RegInit(true.B) // W w_* // [1]: We cannot issue outer Acquire while holding blockB (=> outA can stall) // However, inB and outC are higher priority than outB, so s_release and s_pprobe // may be safely issued while blockB. Thus we must NOT try to schedule the // potentially stuck s_acquire with either of them (scheduler is all or none). // Meta-data that we discover underway val sink = Reg(UInt(params.outer.bundle.sinkBits.W)) val gotT = Reg(Bool()) val bad_grant = Reg(Bool()) val probes_done = Reg(UInt(params.clientBits.W)) val probes_toN = Reg(UInt(params.clientBits.W)) val probes_noT = Reg(Bool()) // When a nested transaction completes, update our meta data when (meta_valid && meta.state =/= INVALID && io.nestedwb.set === request.set && io.nestedwb.tag === meta.tag) { when (io.nestedwb.b_clr_dirty) { meta.dirty := false.B } when (io.nestedwb.c_set_dirty) { meta.dirty := true.B } when (io.nestedwb.b_toB) { meta.state := BRANCH } when (io.nestedwb.b_toN) { meta.hit := false.B } } // Scheduler status io.status.valid := request_valid io.status.bits.set := request.set io.status.bits.tag := request.tag io.status.bits.way := meta.way io.status.bits.blockB := !meta_valid || ((!w_releaseack || !w_rprobeacklast || !w_pprobeacklast) && !w_grantfirst) io.status.bits.nestB := meta_valid && w_releaseack && w_rprobeacklast && w_pprobeacklast && !w_grantfirst // The above rules ensure we will block and not nest an outer probe while still doing our // own inner probes. Thus every probe wakes exactly one MSHR. io.status.bits.blockC := !meta_valid io.status.bits.nestC := meta_valid && (!w_rprobeackfirst || !w_pprobeackfirst || !w_grantfirst) // The w_grantfirst in nestC is necessary to deal with: // acquire waiting for grant, inner release gets queued, outer probe -> inner probe -> deadlock // ... this is possible because the release+probe can be for same set, but different tag // We can only demand: block, nest, or queue assert (!io.status.bits.nestB || !io.status.bits.blockB) assert (!io.status.bits.nestC || !io.status.bits.blockC) // Scheduler requests val no_wait = w_rprobeacklast && w_releaseack && w_grantlast && w_pprobeacklast && w_grantack io.schedule.bits.a.valid := !s_acquire && s_release && s_pprobe io.schedule.bits.b.valid := !s_rprobe || !s_pprobe io.schedule.bits.c.valid := (!s_release && w_rprobeackfirst) || (!s_probeack && w_pprobeackfirst) io.schedule.bits.d.valid := !s_execute && w_pprobeack && w_grant io.schedule.bits.e.valid := !s_grantack && w_grantfirst io.schedule.bits.x.valid := !s_flush && w_releaseack io.schedule.bits.dir.valid := (!s_release && w_rprobeackfirst) || (!s_writeback && no_wait) io.schedule.bits.reload := no_wait io.schedule.valid := io.schedule.bits.a.valid || io.schedule.bits.b.valid || io.schedule.bits.c.valid || io.schedule.bits.d.valid || io.schedule.bits.e.valid || io.schedule.bits.x.valid || io.schedule.bits.dir.valid // Schedule completions when (io.schedule.ready) { s_rprobe := true.B when (w_rprobeackfirst) { s_release := true.B } s_pprobe := true.B when (s_release && s_pprobe) { s_acquire := true.B } when (w_releaseack) { s_flush := true.B } when (w_pprobeackfirst) { s_probeack := true.B } when (w_grantfirst) { s_grantack := true.B } when (w_pprobeack && w_grant) { s_execute := true.B } when (no_wait) { s_writeback := true.B } // Await the next operation when (no_wait) { request_valid := false.B meta_valid := false.B } } // Resulting meta-data val final_meta_writeback = WireInit(meta) val req_clientBit = params.clientBit(request.source) val req_needT = needT(request.opcode, request.param) val req_acquire = request.opcode === AcquireBlock || request.opcode === AcquirePerm val meta_no_clients = !meta.clients.orR val req_promoteT = req_acquire && Mux(meta.hit, meta_no_clients && meta.state === TIP, gotT) when (request.prio(2) && (!params.firstLevel).B) { // always a hit final_meta_writeback.dirty := meta.dirty || request.opcode(0) final_meta_writeback.state := Mux(request.param =/= TtoT && meta.state === TRUNK, TIP, meta.state) final_meta_writeback.clients := meta.clients & ~Mux(isToN(request.param), req_clientBit, 0.U) final_meta_writeback.hit := true.B // chained requests are hits } .elsewhen (request.control && params.control.B) { // request.prio(0) when (meta.hit) { final_meta_writeback.dirty := false.B final_meta_writeback.state := INVALID final_meta_writeback.clients := meta.clients & ~probes_toN } final_meta_writeback.hit := false.B } .otherwise { final_meta_writeback.dirty := (meta.hit && meta.dirty) || !request.opcode(2) final_meta_writeback.state := Mux(req_needT, Mux(req_acquire, TRUNK, TIP), Mux(!meta.hit, Mux(gotT, Mux(req_acquire, TRUNK, TIP), BRANCH), MuxLookup(meta.state, 0.U(2.W))(Seq( INVALID -> BRANCH, BRANCH -> BRANCH, TRUNK -> TIP, TIP -> Mux(meta_no_clients && req_acquire, TRUNK, TIP))))) final_meta_writeback.clients := Mux(meta.hit, meta.clients & ~probes_toN, 0.U) | Mux(req_acquire, req_clientBit, 0.U) final_meta_writeback.tag := request.tag final_meta_writeback.hit := true.B } when (bad_grant) { when (meta.hit) { // upgrade failed (B -> T) assert (!meta_valid || meta.state === BRANCH) final_meta_writeback.hit := true.B final_meta_writeback.dirty := false.B final_meta_writeback.state := BRANCH final_meta_writeback.clients := meta.clients & ~probes_toN } .otherwise { // failed N -> (T or B) final_meta_writeback.hit := false.B final_meta_writeback.dirty := false.B final_meta_writeback.state := INVALID final_meta_writeback.clients := 0.U } } val invalid = Wire(new DirectoryEntry(params)) invalid.dirty := false.B invalid.state := INVALID invalid.clients := 0.U invalid.tag := 0.U // Just because a client says BtoT, by the time we process the request he may be N. // Therefore, we must consult our own meta-data state to confirm he owns the line still. val honour_BtoT = meta.hit && (meta.clients & req_clientBit).orR // The client asking us to act is proof they don't have permissions. val excluded_client = Mux(meta.hit && request.prio(0) && skipProbeN(request.opcode, params.cache.hintsSkipProbe), req_clientBit, 0.U) io.schedule.bits.a.bits.tag := request.tag io.schedule.bits.a.bits.set := request.set io.schedule.bits.a.bits.param := Mux(req_needT, Mux(meta.hit, BtoT, NtoT), NtoB) io.schedule.bits.a.bits.block := request.size =/= log2Ceil(params.cache.blockBytes).U || !(request.opcode === PutFullData || request.opcode === AcquirePerm) io.schedule.bits.a.bits.source := 0.U io.schedule.bits.b.bits.param := Mux(!s_rprobe, toN, Mux(request.prio(1), request.param, Mux(req_needT, toN, toB))) io.schedule.bits.b.bits.tag := Mux(!s_rprobe, meta.tag, request.tag) io.schedule.bits.b.bits.set := request.set io.schedule.bits.b.bits.clients := meta.clients & ~excluded_client io.schedule.bits.c.bits.opcode := Mux(meta.dirty, ReleaseData, Release) io.schedule.bits.c.bits.param := Mux(meta.state === BRANCH, BtoN, TtoN) io.schedule.bits.c.bits.source := 0.U io.schedule.bits.c.bits.tag := meta.tag io.schedule.bits.c.bits.set := request.set io.schedule.bits.c.bits.way := meta.way io.schedule.bits.c.bits.dirty := meta.dirty io.schedule.bits.d.bits.viewAsSupertype(chiselTypeOf(request)) := request io.schedule.bits.d.bits.param := Mux(!req_acquire, request.param, MuxLookup(request.param, request.param)(Seq( NtoB -> Mux(req_promoteT, NtoT, NtoB), BtoT -> Mux(honour_BtoT, BtoT, NtoT), NtoT -> NtoT))) io.schedule.bits.d.bits.sink := 0.U io.schedule.bits.d.bits.way := meta.way io.schedule.bits.d.bits.bad := bad_grant io.schedule.bits.e.bits.sink := sink io.schedule.bits.x.bits.fail := false.B io.schedule.bits.dir.bits.set := request.set io.schedule.bits.dir.bits.way := meta.way io.schedule.bits.dir.bits.data := Mux(!s_release, invalid, WireInit(new DirectoryEntry(params), init = final_meta_writeback)) // Coverage of state transitions def cacheState(entry: DirectoryEntry, hit: Bool) = { val out = WireDefault(0.U) val c = entry.clients.orR val d = entry.dirty switch (entry.state) { is (BRANCH) { out := Mux(c, S_BRANCH_C.code, S_BRANCH.code) } is (TRUNK) { out := Mux(d, S_TRUNK_CD.code, S_TRUNK_C.code) } is (TIP) { out := Mux(c, Mux(d, S_TIP_CD.code, S_TIP_C.code), Mux(d, S_TIP_D.code, S_TIP.code)) } is (INVALID) { out := S_INVALID.code } } when (!hit) { out := S_INVALID.code } out } val p = !params.lastLevel // can be probed val c = !params.firstLevel // can be acquired val m = params.inner.client.clients.exists(!_.supports.probe) // can be written (or read) val r = params.outer.manager.managers.exists(!_.alwaysGrantsT) // read-only devices exist val f = params.control // flush control register exists val cfg = (p, c, m, r, f) val b = r || p // can reach branch state (via probe downgrade or read-only device) // The cache must be used for something or we would not be here require(c || m) val evict = cacheState(meta, !meta.hit) val before = cacheState(meta, meta.hit) val after = cacheState(final_meta_writeback, true.B) def eviction(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(evict === from.code, s"MSHR_${from}_EVICT", s"State transition from ${from} to evicted ${cfg}") } else { assert(!(evict === from.code), cf"State transition from ${from} to evicted should be impossible ${cfg}") } if (cover && f) { params.ccover(before === from.code, s"MSHR_${from}_FLUSH", s"State transition from ${from} to flushed ${cfg}") } else { assert(!(before === from.code), cf"State transition from ${from} to flushed should be impossible ${cfg}") } } def transition(from: CacheState, to: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(before === from.code && after === to.code, s"MSHR_${from}_${to}", s"State transition from ${from} to ${to} ${cfg}") } else { assert(!(before === from.code && after === to.code), cf"State transition from ${from} to ${to} should be impossible ${cfg}") } } when ((!s_release && w_rprobeackfirst) && io.schedule.ready) { eviction(S_BRANCH, b) // MMIO read to read-only device eviction(S_BRANCH_C, b && c) // you need children to become C eviction(S_TIP, true) // MMIO read || clean release can lead to this state eviction(S_TIP_C, c) // needs two clients || client + mmio || downgrading client eviction(S_TIP_CD, c) // needs two clients || client + mmio || downgrading client eviction(S_TIP_D, true) // MMIO write || dirty release lead here eviction(S_TRUNK_C, c) // acquire for write eviction(S_TRUNK_CD, c) // dirty release then reacquire } when ((!s_writeback && no_wait) && io.schedule.ready) { transition(S_INVALID, S_BRANCH, b && m) // only MMIO can bring us to BRANCH state transition(S_INVALID, S_BRANCH_C, b && c) // C state is only possible if there are inner caches transition(S_INVALID, S_TIP, m) // MMIO read transition(S_INVALID, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_INVALID, S_TIP_CD, false) // acquire does not cause dirty immediately transition(S_INVALID, S_TIP_D, m) // MMIO write transition(S_INVALID, S_TRUNK_C, c) // acquire transition(S_INVALID, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH, S_INVALID, b && p) // probe can do this (flushes run as evictions) transition(S_BRANCH, S_BRANCH_C, b && c) // acquire transition(S_BRANCH, S_TIP, b && m) // prefetch write transition(S_BRANCH, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_BRANCH, S_TIP_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH, S_TIP_D, b && m) // MMIO write transition(S_BRANCH, S_TRUNK_C, b && c) // acquire transition(S_BRANCH, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH_C, S_INVALID, b && c && p) transition(S_BRANCH_C, S_BRANCH, b && c) // clean release (optional) transition(S_BRANCH_C, S_TIP, b && c && m) // prefetch write transition(S_BRANCH_C, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_BRANCH_C, S_TIP_D, b && c && m) // MMIO write transition(S_BRANCH_C, S_TIP_CD, false) // going dirty means we must shoot down clients transition(S_BRANCH_C, S_TRUNK_C, b && c) // acquire transition(S_BRANCH_C, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_TIP, S_INVALID, p) transition(S_TIP, S_BRANCH, p) // losing TIP only possible via probe transition(S_TIP, S_BRANCH_C, false) // we would go S_TRUNK_C instead transition(S_TIP, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP, S_TIP_D, m) // direct dirty only via MMIO write transition(S_TIP, S_TIP_CD, false) // acquire does not make us dirty immediately transition(S_TIP, S_TRUNK_C, c) // acquire transition(S_TIP, S_TRUNK_CD, false) // acquire does not make us dirty immediately transition(S_TIP_C, S_INVALID, c && p) transition(S_TIP_C, S_BRANCH, c && p) // losing TIP only possible via probe transition(S_TIP_C, S_BRANCH_C, c && p) // losing TIP only possible via probe transition(S_TIP_C, S_TIP, c) // probed while MMIO read || clean release (optional) transition(S_TIP_C, S_TIP_D, c && m) // direct dirty only via MMIO write transition(S_TIP_C, S_TIP_CD, false) // going dirty means we must shoot down clients transition(S_TIP_C, S_TRUNK_C, c) // acquire transition(S_TIP_C, S_TRUNK_CD, false) // acquire does not make us immediately dirty transition(S_TIP_D, S_INVALID, p) transition(S_TIP_D, S_BRANCH, p) // losing D is only possible via probe transition(S_TIP_D, S_BRANCH_C, p && c) // probed while acquire shared transition(S_TIP_D, S_TIP, p) // probed while MMIO read || outer probe.toT (optional) transition(S_TIP_D, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP_D, S_TIP_CD, false) // we would go S_TRUNK_CD instead transition(S_TIP_D, S_TRUNK_C, p && c) // probed while acquired transition(S_TIP_D, S_TRUNK_CD, c) // acquire transition(S_TIP_CD, S_INVALID, c && p) transition(S_TIP_CD, S_BRANCH, c && p) // losing D is only possible via probe transition(S_TIP_CD, S_BRANCH_C, c && p) // losing D is only possible via probe transition(S_TIP_CD, S_TIP, c && p) // probed while MMIO read || outer probe.toT (optional) transition(S_TIP_CD, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP_CD, S_TIP_D, c) // MMIO write || clean release (optional) transition(S_TIP_CD, S_TRUNK_C, c && p) // probed while acquire transition(S_TIP_CD, S_TRUNK_CD, c) // acquire transition(S_TRUNK_C, S_INVALID, c && p) transition(S_TRUNK_C, S_BRANCH, c && p) // losing TIP only possible via probe transition(S_TRUNK_C, S_BRANCH_C, c && p) // losing TIP only possible via probe transition(S_TRUNK_C, S_TIP, c) // MMIO read || clean release (optional) transition(S_TRUNK_C, S_TIP_C, c) // bounce shared transition(S_TRUNK_C, S_TIP_D, c) // dirty release transition(S_TRUNK_C, S_TIP_CD, c) // dirty bounce shared transition(S_TRUNK_C, S_TRUNK_CD, c) // dirty bounce transition(S_TRUNK_CD, S_INVALID, c && p) transition(S_TRUNK_CD, S_BRANCH, c && p) // losing D only possible via probe transition(S_TRUNK_CD, S_BRANCH_C, c && p) // losing D only possible via probe transition(S_TRUNK_CD, S_TIP, c && p) // probed while MMIO read || outer probe.toT (optional) transition(S_TRUNK_CD, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TRUNK_CD, S_TIP_D, c) // dirty release transition(S_TRUNK_CD, S_TIP_CD, c) // bounce shared transition(S_TRUNK_CD, S_TRUNK_C, c && p) // probed while acquire } // Handle response messages val probe_bit = params.clientBit(io.sinkc.bits.source) val last_probe = (probes_done | probe_bit) === (meta.clients & ~excluded_client) val probe_toN = isToN(io.sinkc.bits.param) if (!params.firstLevel) when (io.sinkc.valid) { params.ccover( probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_FULL", "Client downgraded to N when asked only to do B") params.ccover(!probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_HALF", "Client downgraded to B when asked only to do B") // Caution: the probe matches us only in set. // We would never allow an outer probe to nest until both w_[rp]probeack complete, so // it is safe to just unguardedly update the probe FSM. probes_done := probes_done | probe_bit probes_toN := probes_toN | Mux(probe_toN, probe_bit, 0.U) probes_noT := probes_noT || io.sinkc.bits.param =/= TtoT w_rprobeackfirst := w_rprobeackfirst || last_probe w_rprobeacklast := w_rprobeacklast || (last_probe && io.sinkc.bits.last) w_pprobeackfirst := w_pprobeackfirst || last_probe w_pprobeacklast := w_pprobeacklast || (last_probe && io.sinkc.bits.last) // Allow wormhole routing from sinkC if the first request beat has offset 0 val set_pprobeack = last_probe && (io.sinkc.bits.last || request.offset === 0.U) w_pprobeack := w_pprobeack || set_pprobeack params.ccover(!set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_SERIAL", "Sequential routing of probe response data") params.ccover( set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_WORMHOLE", "Wormhole routing of probe response data") // However, meta-data updates need to be done more cautiously when (meta.state =/= INVALID && io.sinkc.bits.tag === meta.tag && io.sinkc.bits.data) { meta.dirty := true.B } // !!! } when (io.sinkd.valid) { when (io.sinkd.bits.opcode === Grant || io.sinkd.bits.opcode === GrantData) { sink := io.sinkd.bits.sink w_grantfirst := true.B w_grantlast := io.sinkd.bits.last // Record if we need to prevent taking ownership bad_grant := io.sinkd.bits.denied // Allow wormhole routing for requests whose first beat has offset 0 w_grant := request.offset === 0.U || io.sinkd.bits.last params.ccover(io.sinkd.bits.opcode === GrantData && request.offset === 0.U, "MSHR_GRANT_WORMHOLE", "Wormhole routing of grant response data") params.ccover(io.sinkd.bits.opcode === GrantData && request.offset =/= 0.U, "MSHR_GRANT_SERIAL", "Sequential routing of grant response data") gotT := io.sinkd.bits.param === toT } .elsewhen (io.sinkd.bits.opcode === ReleaseAck) { w_releaseack := true.B } } when (io.sinke.valid) { w_grantack := true.B } // Bootstrap new requests val allocate_as_full = WireInit(new FullRequest(params), init = io.allocate.bits) val new_meta = Mux(io.allocate.valid && io.allocate.bits.repeat, final_meta_writeback, io.directory.bits) val new_request = Mux(io.allocate.valid, allocate_as_full, request) val new_needT = needT(new_request.opcode, new_request.param) val new_clientBit = params.clientBit(new_request.source) val new_skipProbe = Mux(skipProbeN(new_request.opcode, params.cache.hintsSkipProbe), new_clientBit, 0.U) val prior = cacheState(final_meta_writeback, true.B) def bypass(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(prior === from.code, s"MSHR_${from}_BYPASS", s"State bypass transition from ${from} ${cfg}") } else { assert(!(prior === from.code), cf"State bypass from ${from} should be impossible ${cfg}") } } when (io.allocate.valid && io.allocate.bits.repeat) { bypass(S_INVALID, f || p) // Can lose permissions (probe/flush) bypass(S_BRANCH, b) // MMIO read to read-only device bypass(S_BRANCH_C, b && c) // you need children to become C bypass(S_TIP, true) // MMIO read || clean release can lead to this state bypass(S_TIP_C, c) // needs two clients || client + mmio || downgrading client bypass(S_TIP_CD, c) // needs two clients || client + mmio || downgrading client bypass(S_TIP_D, true) // MMIO write || dirty release lead here bypass(S_TRUNK_C, c) // acquire for write bypass(S_TRUNK_CD, c) // dirty release then reacquire } when (io.allocate.valid) { assert (!request_valid || (no_wait && io.schedule.fire)) request_valid := true.B request := io.allocate.bits } // Create execution plan when (io.directory.valid || (io.allocate.valid && io.allocate.bits.repeat)) { meta_valid := true.B meta := new_meta probes_done := 0.U probes_toN := 0.U probes_noT := false.B gotT := false.B bad_grant := false.B // These should already be either true or turning true // We clear them here explicitly to simplify the mux tree s_rprobe := true.B w_rprobeackfirst := true.B w_rprobeacklast := true.B s_release := true.B w_releaseack := true.B s_pprobe := true.B s_acquire := true.B s_flush := true.B w_grantfirst := true.B w_grantlast := true.B w_grant := true.B w_pprobeackfirst := true.B w_pprobeacklast := true.B w_pprobeack := true.B s_probeack := true.B s_grantack := true.B s_execute := true.B w_grantack := true.B s_writeback := true.B // For C channel requests (ie: Release[Data]) when (new_request.prio(2) && (!params.firstLevel).B) { s_execute := false.B // Do we need to go dirty? when (new_request.opcode(0) && !new_meta.dirty) { s_writeback := false.B } // Does our state change? when (isToB(new_request.param) && new_meta.state === TRUNK) { s_writeback := false.B } // Do our clients change? when (isToN(new_request.param) && (new_meta.clients & new_clientBit) =/= 0.U) { s_writeback := false.B } assert (new_meta.hit) } // For X channel requests (ie: flush) .elsewhen (new_request.control && params.control.B) { // new_request.prio(0) s_flush := false.B // Do we need to actually do something? when (new_meta.hit) { s_release := false.B w_releaseack := false.B // Do we need to shoot-down inner caches? when ((!params.firstLevel).B && (new_meta.clients =/= 0.U)) { s_rprobe := false.B w_rprobeackfirst := false.B w_rprobeacklast := false.B } } } // For A channel requests .otherwise { // new_request.prio(0) && !new_request.control s_execute := false.B // Do we need an eviction? when (!new_meta.hit && new_meta.state =/= INVALID) { s_release := false.B w_releaseack := false.B // Do we need to shoot-down inner caches? when ((!params.firstLevel).B & (new_meta.clients =/= 0.U)) { s_rprobe := false.B w_rprobeackfirst := false.B w_rprobeacklast := false.B } } // Do we need an acquire? when (!new_meta.hit || (new_meta.state === BRANCH && new_needT)) { s_acquire := false.B w_grantfirst := false.B w_grantlast := false.B w_grant := false.B s_grantack := false.B s_writeback := false.B } // Do we need a probe? when ((!params.firstLevel).B && (new_meta.hit && (new_needT || new_meta.state === TRUNK) && (new_meta.clients & ~new_skipProbe) =/= 0.U)) { s_pprobe := false.B w_pprobeackfirst := false.B w_pprobeacklast := false.B w_pprobeack := false.B s_writeback := false.B } // Do we need a grantack? when (new_request.opcode === AcquireBlock || new_request.opcode === AcquirePerm) { w_grantack := false.B s_writeback := false.B } // Becomes dirty? when (!new_request.opcode(2) && new_meta.hit && !new_meta.dirty) { s_writeback := false.B } } } } File Parameters.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property.cover import scala.math.{min,max} case class CacheParameters( level: Int, ways: Int, sets: Int, blockBytes: Int, beatBytes: Int, // inner hintsSkipProbe: Boolean) { require (ways > 0) require (sets > 0) require (blockBytes > 0 && isPow2(blockBytes)) require (beatBytes > 0 && isPow2(beatBytes)) require (blockBytes >= beatBytes) val blocks = ways * sets val sizeBytes = blocks * blockBytes val blockBeats = blockBytes/beatBytes } case class InclusiveCachePortParameters( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams) { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new TLBuffer(a, b, c, d, e)) } object InclusiveCachePortParameters { val none = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.none) val full = InclusiveCachePortParameters( a = BufferParams.default, b = BufferParams.default, c = BufferParams.default, d = BufferParams.default, e = BufferParams.default) // This removes feed-through paths from C=>A and A=>C val fullC = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.default, d = BufferParams.none, e = BufferParams.none) val flowAD = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.flow, e = BufferParams.none) val flowAE = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.flow) // For innerBuf: // SinkA: no restrictions, flows into scheduler+putbuffer // SourceB: no restrictions, flows out of scheduler // sinkC: no restrictions, flows into scheduler+putbuffer & buffered to bankedStore // SourceD: no restrictions, flows out of bankedStore/regout // SinkE: no restrictions, flows into scheduler // // ... so while none is possible, you probably want at least flowAC to cut ready // from the scheduler delay and flowD to ease SourceD back-pressure // For outerBufer: // SourceA: must not be pipe, flows out of scheduler // SinkB: no restrictions, flows into scheduler // SourceC: pipe is useless, flows out of bankedStore/regout, parameter depth ignored // SinkD: no restrictions, flows into scheduler & bankedStore // SourceE: must not be pipe, flows out of scheduler // // ... AE take the channel ready into the scheduler, so you need at least flowAE } case class InclusiveCacheMicroParameters( writeBytes: Int, // backing store update granularity memCycles: Int = 40, // # of L2 clock cycles for a memory round-trip (50ns @ 800MHz) portFactor: Int = 4, // numSubBanks = (widest TL port * portFactor) / writeBytes dirReg: Boolean = false, innerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.fullC, // or none outerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.full) // or flowAE { require (writeBytes > 0 && isPow2(writeBytes)) require (memCycles > 0) require (portFactor >= 2) // for inner RMW and concurrent outer Relase + Grant } case class InclusiveCacheControlParameters( address: BigInt, beatBytes: Int, bankedControl: Boolean) case class InclusiveCacheParameters( cache: CacheParameters, micro: InclusiveCacheMicroParameters, control: Boolean, inner: TLEdgeIn, outer: TLEdgeOut)(implicit val p: Parameters) { require (cache.ways > 1) require (cache.sets > 1 && isPow2(cache.sets)) require (micro.writeBytes <= inner.manager.beatBytes) require (micro.writeBytes <= outer.manager.beatBytes) require (inner.manager.beatBytes <= cache.blockBytes) require (outer.manager.beatBytes <= cache.blockBytes) // Require that all cached address ranges have contiguous blocks outer.manager.managers.flatMap(_.address).foreach { a => require (a.alignment >= cache.blockBytes) } // If we are the first level cache, we do not need to support inner-BCE val firstLevel = !inner.client.clients.exists(_.supports.probe) // If we are the last level cache, we do not need to support outer-B val lastLevel = !outer.manager.managers.exists(_.regionType > RegionType.UNCACHED) require (lastLevel) // Provision enough resources to achieve full throughput with missing single-beat accesses val mshrs = InclusiveCacheParameters.all_mshrs(cache, micro) val secondary = max(mshrs, micro.memCycles - mshrs) val putLists = micro.memCycles // allow every request to be single beat val putBeats = max(2*cache.blockBeats, micro.memCycles) val relLists = 2 val relBeats = relLists*cache.blockBeats val flatAddresses = AddressSet.unify(outer.manager.managers.flatMap(_.address)) val pickMask = AddressDecoder(flatAddresses.map(Seq(_)), flatAddresses.map(_.mask).reduce(_|_)) def bitOffsets(x: BigInt, offset: Int = 0, tail: List[Int] = List.empty[Int]): List[Int] = if (x == 0) tail.reverse else bitOffsets(x >> 1, offset + 1, if ((x & 1) == 1) offset :: tail else tail) val addressMapping = bitOffsets(pickMask) val addressBits = addressMapping.size // println(s"addresses: ${flatAddresses} => ${pickMask} => ${addressBits}") val allClients = inner.client.clients.size val clientBitsRaw = inner.client.clients.filter(_.supports.probe).size val clientBits = max(1, clientBitsRaw) val stateBits = 2 val wayBits = log2Ceil(cache.ways) val setBits = log2Ceil(cache.sets) val offsetBits = log2Ceil(cache.blockBytes) val tagBits = addressBits - setBits - offsetBits val putBits = log2Ceil(max(putLists, relLists)) require (tagBits > 0) require (offsetBits > 0) val innerBeatBits = (offsetBits - log2Ceil(inner.manager.beatBytes)) max 1 val outerBeatBits = (offsetBits - log2Ceil(outer.manager.beatBytes)) max 1 val innerMaskBits = inner.manager.beatBytes / micro.writeBytes val outerMaskBits = outer.manager.beatBytes / micro.writeBytes def clientBit(source: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Cat(inner.client.clients.filter(_.supports.probe).map(_.sourceId.contains(source)).reverse) } } def clientSource(bit: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Mux1H(bit, inner.client.clients.filter(_.supports.probe).map(c => c.sourceId.start.U)) } } def parseAddress(x: UInt): (UInt, UInt, UInt) = { val offset = Cat(addressMapping.map(o => x(o,o)).reverse) val set = offset >> offsetBits val tag = set >> setBits (tag(tagBits-1, 0), set(setBits-1, 0), offset(offsetBits-1, 0)) } def widen(x: UInt, width: Int): UInt = { val y = x | 0.U(width.W) assert (y >> width === 0.U) y(width-1, 0) } def expandAddress(tag: UInt, set: UInt, offset: UInt): UInt = { val base = Cat(widen(tag, tagBits), widen(set, setBits), widen(offset, offsetBits)) val bits = Array.fill(outer.bundle.addressBits) { 0.U(1.W) } addressMapping.zipWithIndex.foreach { case (a, i) => bits(a) = base(i,i) } Cat(bits.reverse) } def restoreAddress(expanded: UInt): UInt = { val missingBits = flatAddresses .map { a => (a.widen(pickMask).base, a.widen(~pickMask)) } // key is the bits to restore on match .groupBy(_._1) .view .mapValues(_.map(_._2)) val muxMask = AddressDecoder(missingBits.values.toList) val mux = missingBits.toList.map { case (bits, addrs) => val widen = addrs.map(_.widen(~muxMask)) val matches = AddressSet .unify(widen.distinct) .map(_.contains(expanded)) .reduce(_ || _) (matches, bits.U) } expanded | Mux1H(mux) } def dirReg[T <: Data](x: T, en: Bool = true.B): T = { if (micro.dirReg) RegEnable(x, en) else x } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = cover(cond, "CCACHE_L" + cache.level + "_" + label, "MemorySystem;;" + desc) } object MetaData { val stateBits = 2 def INVALID: UInt = 0.U(stateBits.W) // way is empty def BRANCH: UInt = 1.U(stateBits.W) // outer slave cache is trunk def TRUNK: UInt = 2.U(stateBits.W) // unique inner master cache is trunk def TIP: UInt = 3.U(stateBits.W) // we are trunk, inner masters are branch // Does a request need trunk? def needT(opcode: UInt, param: UInt): Bool = { !opcode(2) || (opcode === TLMessages.Hint && param === TLHints.PREFETCH_WRITE) || ((opcode === TLMessages.AcquireBlock || opcode === TLMessages.AcquirePerm) && param =/= TLPermissions.NtoB) } // Does a request prove the client need not be probed? def skipProbeN(opcode: UInt, hintsSkipProbe: Boolean): Bool = { // Acquire(toB) and Get => is N, so no probe // Acquire(*toT) => is N or B, but need T, so no probe // Hint => could be anything, so probe IS needed, if hintsSkipProbe is enabled, skip probe the same client // Put* => is N or B, so probe IS needed opcode === TLMessages.AcquireBlock || opcode === TLMessages.AcquirePerm || opcode === TLMessages.Get || (opcode === TLMessages.Hint && hintsSkipProbe.B) } def isToN(param: UInt): Bool = { param === TLPermissions.TtoN || param === TLPermissions.BtoN || param === TLPermissions.NtoN } def isToB(param: UInt): Bool = { param === TLPermissions.TtoB || param === TLPermissions.BtoB } } object InclusiveCacheParameters { val lfsrBits = 10 val L2ControlAddress = 0x2010000 val L2ControlSize = 0x1000 def out_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = { // We need 2-3 normal MSHRs to cover the Directory latency // To fully exploit memory bandwidth-delay-product, we need memCyles/blockBeats MSHRs max(if (micro.dirReg) 3 else 2, (micro.memCycles + cache.blockBeats - 1) / cache.blockBeats) } def all_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = // We need a dedicated MSHR for B+C each 2 + out_mshrs(cache, micro) } class InclusiveCacheBundle(params: InclusiveCacheParameters) extends Bundle
module MSHR_4( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_0, // @[MSHR.scala:86:14] input io_allocate_bits_prio_1, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [12:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input io_directory_bits_clients, // @[MSHR.scala:86:14] input [12:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [9:0] io_status_bits_set, // @[MSHR.scala:86:14] output [12:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [2:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [12:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [2:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [12:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [12:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [12:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [12:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [12:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [2:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [12:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_sink = 3'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire invalid_clients = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire [12:0] invalid_tag = 13'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [12:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [12:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [12:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [12:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_0; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20] reg request_prio_1; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] reg [12:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [9:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg meta_clients; // @[MSHR.scala:100:17] wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39] wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27] wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27] reg [12:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [2:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg probes_done; // @[MSHR.scala:150:24] reg probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire [12:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire req_clientBit = request_source == 6'h21; // @[Parameters.scala:46:9] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}] wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:46:9] wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106] wire excluded_client = _excluded_client_T_9 & req_clientBit; // @[Parameters.scala:46:9] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] wire _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 13'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire probe_bit = io_sinkc_bits_source_0 == 6'h21; // @[Parameters.scala:46:9] wire _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:46:9] wire _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66] wire _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:46:9] wire _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [12:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [12:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire new_clientBit = new_request_source == 6'h21; // @[Parameters.scala:46:9] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:46:9] wire [3:0] prior; // @[MSHR.scala:314:26] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }
module AsyncResetSynchronizerShiftReg_w1_d3_i0_86( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_174 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File BankBinder.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes} case class BankBinderNode(mask: BigInt)(implicit valName: ValName) extends TLCustomNode { private val bit = mask & -mask val maxXfer = TransferSizes(1, if (bit == 0 || bit > 4096) 4096 else bit.toInt) val ids = AddressSet.enumerateMask(mask) def resolveStar(iKnown: Int, oKnown: Int, iStars: Int, oStars: Int): (Int, Int) = { val ports = ids.size val oStar = if (oStars == 0) 0 else (ports - oKnown) / oStars val iStar = if (iStars == 0) 0 else (ports - iKnown) / iStars require (ports == iKnown + iStar*iStars, s"${name} must have ${ports} inputs, but has ${iKnown} + ${iStar}*${iStars} (at ${lazyModule.line})") require (ports == oKnown + oStar*oStars, s"${name} must have ${ports} outputs, but has ${oKnown} + ${oStar}*${oStars} (at ${lazyModule.line})") (iStar, oStar) } def mapParamsD(n: Int, p: Seq[TLMasterPortParameters]): Seq[TLMasterPortParameters] = (p zip ids) map { case (cp, id) => cp.v1copy(clients = cp.clients.map { c => c.v1copy( visibility = c.visibility.flatMap { a => a.intersect(AddressSet(id, ~mask))}, supportsProbe = c.supports.probe intersect maxXfer, supportsArithmetic = c.supports.arithmetic intersect maxXfer, supportsLogical = c.supports.logical intersect maxXfer, supportsGet = c.supports.get intersect maxXfer, supportsPutFull = c.supports.putFull intersect maxXfer, supportsPutPartial = c.supports.putPartial intersect maxXfer, supportsHint = c.supports.hint intersect maxXfer)})} def mapParamsU(n: Int, p: Seq[TLSlavePortParameters]): Seq[TLSlavePortParameters] = (p zip ids) map { case (mp, id) => mp.v1copy(managers = mp.managers.flatMap { m => val addresses = m.address.flatMap(a => a.intersect(AddressSet(id, ~mask))) if (addresses.nonEmpty) Some(m.v1copy( address = addresses, supportsAcquireT = m.supportsAcquireT intersect maxXfer, supportsAcquireB = m.supportsAcquireB intersect maxXfer, supportsArithmetic = m.supportsArithmetic intersect maxXfer, supportsLogical = m.supportsLogical intersect maxXfer, supportsGet = m.supportsGet intersect maxXfer, supportsPutFull = m.supportsPutFull intersect maxXfer, supportsPutPartial = m.supportsPutPartial intersect maxXfer, supportsHint = m.supportsHint intersect maxXfer)) else None })} } /* A BankBinder is used to divide contiguous memory regions into banks, suitable for a cache */ class BankBinder(mask: BigInt)(implicit p: Parameters) extends LazyModule { val node = BankBinderNode(mask) lazy val module = new Impl class Impl extends LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out <> in } } } object BankBinder { def apply(mask: BigInt)(implicit p: Parameters): TLNode = { val binder = LazyModule(new BankBinder(mask)) binder.node } def apply(nBanks: Int, granularity: Int)(implicit p: Parameters): TLNode = { if (nBanks > 0) apply(granularity * (nBanks-1)) else TLTempNode() } } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } }
module BankBinder( // @[BankBinder.scala:61:9] input clock, // @[BankBinder.scala:61:9] input reset, // @[BankBinder.scala:61:9] output auto_in_3_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_3_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_3_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_3_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_3_a_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_in_3_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_3_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_3_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_3_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_3_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_3_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_3_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_3_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_3_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_3_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_in_3_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_3_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_3_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_3_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_2_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_2_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_2_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_2_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_2_a_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_in_2_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_2_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_2_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_2_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_2_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_2_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_2_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_2_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_2_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_2_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_in_2_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_2_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_2_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_2_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_1_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_1_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_1_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_1_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_in_1_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_0_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_0_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_in_0_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_0_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_0_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_0_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_in_0_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_3_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_3_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_3_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_3_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_3_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_out_3_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_3_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_3_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_3_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_3_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_3_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_3_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_3_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_3_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_3_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_out_3_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_out_3_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_3_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_3_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_3_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_2_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_2_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_2_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_2_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_2_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_out_2_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_2_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_2_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_2_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_2_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_2_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_2_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_2_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_2_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_2_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_out_2_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_out_2_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_2_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_2_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_2_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_1_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_1_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_1_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_0_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_0_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_0_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_0_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_0_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_out_0_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_0_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_0_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); TLMonitor_62 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (auto_out_0_a_ready), .io_in_a_valid (auto_in_0_a_valid), .io_in_a_bits_opcode (auto_in_0_a_bits_opcode), .io_in_a_bits_param (auto_in_0_a_bits_param), .io_in_a_bits_size (auto_in_0_a_bits_size), .io_in_a_bits_source (auto_in_0_a_bits_source), .io_in_a_bits_address (auto_in_0_a_bits_address), .io_in_a_bits_mask (auto_in_0_a_bits_mask), .io_in_a_bits_corrupt (auto_in_0_a_bits_corrupt), .io_in_d_ready (auto_in_0_d_ready), .io_in_d_valid (auto_out_0_d_valid), .io_in_d_bits_opcode (auto_out_0_d_bits_opcode), .io_in_d_bits_param (auto_out_0_d_bits_param), .io_in_d_bits_size (auto_out_0_d_bits_size), .io_in_d_bits_source (auto_out_0_d_bits_source), .io_in_d_bits_sink (auto_out_0_d_bits_sink), .io_in_d_bits_denied (auto_out_0_d_bits_denied), .io_in_d_bits_corrupt (auto_out_0_d_bits_corrupt) ); // @[Nodes.scala:27:25] TLMonitor_63 monitor_1 ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (auto_out_1_a_ready), .io_in_a_valid (auto_in_1_a_valid), .io_in_a_bits_opcode (auto_in_1_a_bits_opcode), .io_in_a_bits_param (auto_in_1_a_bits_param), .io_in_a_bits_size (auto_in_1_a_bits_size), .io_in_a_bits_source (auto_in_1_a_bits_source), .io_in_a_bits_address (auto_in_1_a_bits_address), .io_in_a_bits_mask (auto_in_1_a_bits_mask), .io_in_a_bits_corrupt (auto_in_1_a_bits_corrupt), .io_in_d_ready (auto_in_1_d_ready), .io_in_d_valid (auto_out_1_d_valid), .io_in_d_bits_opcode (auto_out_1_d_bits_opcode), .io_in_d_bits_param (auto_out_1_d_bits_param), .io_in_d_bits_size (auto_out_1_d_bits_size), .io_in_d_bits_source (auto_out_1_d_bits_source), .io_in_d_bits_sink (auto_out_1_d_bits_sink), .io_in_d_bits_denied (auto_out_1_d_bits_denied), .io_in_d_bits_corrupt (auto_out_1_d_bits_corrupt) ); // @[Nodes.scala:27:25] TLMonitor_64 monitor_2 ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (auto_out_2_a_ready), .io_in_a_valid (auto_in_2_a_valid), .io_in_a_bits_opcode (auto_in_2_a_bits_opcode), .io_in_a_bits_param (auto_in_2_a_bits_param), .io_in_a_bits_size (auto_in_2_a_bits_size), .io_in_a_bits_source (auto_in_2_a_bits_source), .io_in_a_bits_address (auto_in_2_a_bits_address), .io_in_a_bits_mask (auto_in_2_a_bits_mask), .io_in_a_bits_corrupt (auto_in_2_a_bits_corrupt), .io_in_d_ready (auto_in_2_d_ready), .io_in_d_valid (auto_out_2_d_valid), .io_in_d_bits_opcode (auto_out_2_d_bits_opcode), .io_in_d_bits_param (auto_out_2_d_bits_param), .io_in_d_bits_size (auto_out_2_d_bits_size), .io_in_d_bits_source (auto_out_2_d_bits_source), .io_in_d_bits_sink (auto_out_2_d_bits_sink), .io_in_d_bits_denied (auto_out_2_d_bits_denied), .io_in_d_bits_corrupt (auto_out_2_d_bits_corrupt) ); // @[Nodes.scala:27:25] TLMonitor_65 monitor_3 ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (auto_out_3_a_ready), .io_in_a_valid (auto_in_3_a_valid), .io_in_a_bits_opcode (auto_in_3_a_bits_opcode), .io_in_a_bits_param (auto_in_3_a_bits_param), .io_in_a_bits_size (auto_in_3_a_bits_size), .io_in_a_bits_source (auto_in_3_a_bits_source), .io_in_a_bits_address (auto_in_3_a_bits_address), .io_in_a_bits_mask (auto_in_3_a_bits_mask), .io_in_a_bits_corrupt (auto_in_3_a_bits_corrupt), .io_in_d_ready (auto_in_3_d_ready), .io_in_d_valid (auto_out_3_d_valid), .io_in_d_bits_opcode (auto_out_3_d_bits_opcode), .io_in_d_bits_param (auto_out_3_d_bits_param), .io_in_d_bits_size (auto_out_3_d_bits_size), .io_in_d_bits_source (auto_out_3_d_bits_source), .io_in_d_bits_sink (auto_out_3_d_bits_sink), .io_in_d_bits_denied (auto_out_3_d_bits_denied), .io_in_d_bits_corrupt (auto_out_3_d_bits_corrupt) ); // @[Nodes.scala:27:25] assign auto_in_3_a_ready = auto_out_3_a_ready; // @[BankBinder.scala:61:9] assign auto_in_3_d_valid = auto_out_3_d_valid; // @[BankBinder.scala:61:9] assign auto_in_3_d_bits_opcode = auto_out_3_d_bits_opcode; // @[BankBinder.scala:61:9] assign auto_in_3_d_bits_param = auto_out_3_d_bits_param; // @[BankBinder.scala:61:9] assign auto_in_3_d_bits_size = auto_out_3_d_bits_size; // @[BankBinder.scala:61:9] assign auto_in_3_d_bits_source = auto_out_3_d_bits_source; // @[BankBinder.scala:61:9] assign auto_in_3_d_bits_denied = auto_out_3_d_bits_denied; // @[BankBinder.scala:61:9] assign auto_in_3_d_bits_data = auto_out_3_d_bits_data; // @[BankBinder.scala:61:9] assign auto_in_3_d_bits_corrupt = auto_out_3_d_bits_corrupt; // @[BankBinder.scala:61:9] assign auto_in_2_a_ready = auto_out_2_a_ready; // @[BankBinder.scala:61:9] assign auto_in_2_d_valid = auto_out_2_d_valid; // @[BankBinder.scala:61:9] assign auto_in_2_d_bits_opcode = auto_out_2_d_bits_opcode; // @[BankBinder.scala:61:9] assign auto_in_2_d_bits_param = auto_out_2_d_bits_param; // @[BankBinder.scala:61:9] assign auto_in_2_d_bits_size = auto_out_2_d_bits_size; // @[BankBinder.scala:61:9] assign auto_in_2_d_bits_source = auto_out_2_d_bits_source; // @[BankBinder.scala:61:9] assign auto_in_2_d_bits_denied = auto_out_2_d_bits_denied; // @[BankBinder.scala:61:9] assign auto_in_2_d_bits_data = auto_out_2_d_bits_data; // @[BankBinder.scala:61:9] assign auto_in_2_d_bits_corrupt = auto_out_2_d_bits_corrupt; // @[BankBinder.scala:61:9] assign auto_in_1_a_ready = auto_out_1_a_ready; // @[BankBinder.scala:61:9] assign auto_in_1_d_valid = auto_out_1_d_valid; // @[BankBinder.scala:61:9] assign auto_in_1_d_bits_opcode = auto_out_1_d_bits_opcode; // @[BankBinder.scala:61:9] assign auto_in_1_d_bits_param = auto_out_1_d_bits_param; // @[BankBinder.scala:61:9] assign auto_in_1_d_bits_size = auto_out_1_d_bits_size; // @[BankBinder.scala:61:9] assign auto_in_1_d_bits_source = auto_out_1_d_bits_source; // @[BankBinder.scala:61:9] assign auto_in_1_d_bits_denied = auto_out_1_d_bits_denied; // @[BankBinder.scala:61:9] assign auto_in_1_d_bits_data = auto_out_1_d_bits_data; // @[BankBinder.scala:61:9] assign auto_in_1_d_bits_corrupt = auto_out_1_d_bits_corrupt; // @[BankBinder.scala:61:9] assign auto_in_0_a_ready = auto_out_0_a_ready; // @[BankBinder.scala:61:9] assign auto_in_0_d_valid = auto_out_0_d_valid; // @[BankBinder.scala:61:9] assign auto_in_0_d_bits_opcode = auto_out_0_d_bits_opcode; // @[BankBinder.scala:61:9] assign auto_in_0_d_bits_param = auto_out_0_d_bits_param; // @[BankBinder.scala:61:9] assign auto_in_0_d_bits_size = auto_out_0_d_bits_size; // @[BankBinder.scala:61:9] assign auto_in_0_d_bits_source = auto_out_0_d_bits_source; // @[BankBinder.scala:61:9] assign auto_in_0_d_bits_denied = auto_out_0_d_bits_denied; // @[BankBinder.scala:61:9] assign auto_in_0_d_bits_data = auto_out_0_d_bits_data; // @[BankBinder.scala:61:9] assign auto_in_0_d_bits_corrupt = auto_out_0_d_bits_corrupt; // @[BankBinder.scala:61:9] assign auto_out_3_a_valid = auto_in_3_a_valid; // @[BankBinder.scala:61:9] assign auto_out_3_a_bits_opcode = auto_in_3_a_bits_opcode; // @[BankBinder.scala:61:9] assign auto_out_3_a_bits_param = auto_in_3_a_bits_param; // @[BankBinder.scala:61:9] assign auto_out_3_a_bits_size = auto_in_3_a_bits_size; // @[BankBinder.scala:61:9] assign auto_out_3_a_bits_source = auto_in_3_a_bits_source; // @[BankBinder.scala:61:9] assign auto_out_3_a_bits_address = auto_in_3_a_bits_address; // @[BankBinder.scala:61:9] assign auto_out_3_a_bits_mask = auto_in_3_a_bits_mask; // @[BankBinder.scala:61:9] assign auto_out_3_a_bits_data = auto_in_3_a_bits_data; // @[BankBinder.scala:61:9] assign auto_out_3_a_bits_corrupt = auto_in_3_a_bits_corrupt; // @[BankBinder.scala:61:9] assign auto_out_3_d_ready = auto_in_3_d_ready; // @[BankBinder.scala:61:9] assign auto_out_2_a_valid = auto_in_2_a_valid; // @[BankBinder.scala:61:9] assign auto_out_2_a_bits_opcode = auto_in_2_a_bits_opcode; // @[BankBinder.scala:61:9] assign auto_out_2_a_bits_param = auto_in_2_a_bits_param; // @[BankBinder.scala:61:9] assign auto_out_2_a_bits_size = auto_in_2_a_bits_size; // @[BankBinder.scala:61:9] assign auto_out_2_a_bits_source = auto_in_2_a_bits_source; // @[BankBinder.scala:61:9] assign auto_out_2_a_bits_address = auto_in_2_a_bits_address; // @[BankBinder.scala:61:9] assign auto_out_2_a_bits_mask = auto_in_2_a_bits_mask; // @[BankBinder.scala:61:9] assign auto_out_2_a_bits_data = auto_in_2_a_bits_data; // @[BankBinder.scala:61:9] assign auto_out_2_a_bits_corrupt = auto_in_2_a_bits_corrupt; // @[BankBinder.scala:61:9] assign auto_out_2_d_ready = auto_in_2_d_ready; // @[BankBinder.scala:61:9] assign auto_out_1_a_valid = auto_in_1_a_valid; // @[BankBinder.scala:61:9] assign auto_out_1_a_bits_opcode = auto_in_1_a_bits_opcode; // @[BankBinder.scala:61:9] assign auto_out_1_a_bits_param = auto_in_1_a_bits_param; // @[BankBinder.scala:61:9] assign auto_out_1_a_bits_size = auto_in_1_a_bits_size; // @[BankBinder.scala:61:9] assign auto_out_1_a_bits_source = auto_in_1_a_bits_source; // @[BankBinder.scala:61:9] assign auto_out_1_a_bits_address = auto_in_1_a_bits_address; // @[BankBinder.scala:61:9] assign auto_out_1_a_bits_mask = auto_in_1_a_bits_mask; // @[BankBinder.scala:61:9] assign auto_out_1_a_bits_data = auto_in_1_a_bits_data; // @[BankBinder.scala:61:9] assign auto_out_1_a_bits_corrupt = auto_in_1_a_bits_corrupt; // @[BankBinder.scala:61:9] assign auto_out_1_d_ready = auto_in_1_d_ready; // @[BankBinder.scala:61:9] assign auto_out_0_a_valid = auto_in_0_a_valid; // @[BankBinder.scala:61:9] assign auto_out_0_a_bits_opcode = auto_in_0_a_bits_opcode; // @[BankBinder.scala:61:9] assign auto_out_0_a_bits_param = auto_in_0_a_bits_param; // @[BankBinder.scala:61:9] assign auto_out_0_a_bits_size = auto_in_0_a_bits_size; // @[BankBinder.scala:61:9] assign auto_out_0_a_bits_source = auto_in_0_a_bits_source; // @[BankBinder.scala:61:9] assign auto_out_0_a_bits_address = auto_in_0_a_bits_address; // @[BankBinder.scala:61:9] assign auto_out_0_a_bits_mask = auto_in_0_a_bits_mask; // @[BankBinder.scala:61:9] assign auto_out_0_a_bits_data = auto_in_0_a_bits_data; // @[BankBinder.scala:61:9] assign auto_out_0_a_bits_corrupt = auto_in_0_a_bits_corrupt; // @[BankBinder.scala:61:9] assign auto_out_0_d_ready = auto_in_0_d_ready; // @[BankBinder.scala:61:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_302( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File Tile.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ import Util._ /** * A Tile is a purely combinational 2D array of passThrough PEs. * a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs * @param width The data width of each PE in bits * @param rows Number of PEs on each row * @param columns Number of PEs on each column */ class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module { val io = IO(new Bundle { val in_a = Input(Vec(rows, inputType)) val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it val in_d = Input(Vec(columns, outputType)) val in_control = Input(Vec(columns, new PEControl(accType))) val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val in_last = Input(Vec(columns, Bool())) val out_a = Output(Vec(rows, inputType)) val out_c = Output(Vec(columns, outputType)) val out_b = Output(Vec(columns, outputType)) val out_control = Output(Vec(columns, new PEControl(accType))) val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val out_last = Output(Vec(columns, Bool())) val in_valid = Input(Vec(columns, Bool())) val out_valid = Output(Vec(columns, Bool())) val bad_dataflow = Output(Bool()) }) import ev._ val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls))) val tileT = tile.transpose // TODO: abstract hori/vert broadcast, all these connections look the same // Broadcast 'a' horizontally across the Tile for (r <- 0 until rows) { tile(r).foldLeft(io.in_a(r)) { case (in_a, pe) => pe.io.in_a := in_a pe.io.out_a } } // Broadcast 'b' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_b(c)) { case (in_b, pe) => pe.io.in_b := (if (tree_reduction) in_b.zero else in_b) pe.io.out_b } } // Broadcast 'd' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_d(c)) { case (in_d, pe) => pe.io.in_d := in_d pe.io.out_c } } // Broadcast 'control' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_control(c)) { case (in_ctrl, pe) => pe.io.in_control := in_ctrl pe.io.out_control } } // Broadcast 'garbage' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_valid(c)) { case (v, pe) => pe.io.in_valid := v pe.io.out_valid } } // Broadcast 'id' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_id(c)) { case (id, pe) => pe.io.in_id := id pe.io.out_id } } // Broadcast 'last' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_last(c)) { case (last, pe) => pe.io.in_last := last pe.io.out_last } } // Drive the Tile's bottom IO for (c <- 0 until columns) { io.out_c(c) := tile(rows-1)(c).io.out_c io.out_control(c) := tile(rows-1)(c).io.out_control io.out_id(c) := tile(rows-1)(c).io.out_id io.out_last(c) := tile(rows-1)(c).io.out_last io.out_valid(c) := tile(rows-1)(c).io.out_valid io.out_b(c) := { if (tree_reduction) { val prods = tileT(c).map(_.io.out_b) accumulateTree(prods :+ io.in_b(c)) } else { tile(rows - 1)(c).io.out_b } } } io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_||_)).reduce(_||_) // Drive the Tile's right IO for (r <- 0 until rows) { io.out_a(r) := tile(r)(columns-1).io.out_a } }
module Tile_222( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_478 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }
module AsyncResetSynchronizerShiftReg_w1_d3_i0_16( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] output io_q // @[ShiftReg.scala:36:14] ); wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_36 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File HellaCacheArbiter.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.{Cat,log2Up} import org.chipsalliance.cde.config.Parameters class HellaCacheArbiter(n: Int)(implicit p: Parameters) extends Module { val io = IO(new Bundle { val requestor = Flipped(Vec(n, new HellaCacheIO)) val mem = new HellaCacheIO }) if (n == 1) { io.mem <> io.requestor.head } else { val s1_id = Reg(UInt()) val s2_id = RegNext(s1_id) io.mem.keep_clock_enabled := io.requestor.map(_.keep_clock_enabled).reduce(_||_) io.mem.req.valid := io.requestor.map(_.req.valid).reduce(_||_) io.requestor(0).req.ready := io.mem.req.ready for (i <- 1 until n) io.requestor(i).req.ready := io.requestor(i-1).req.ready && !io.requestor(i-1).req.valid for (i <- n-1 to 0 by -1) { val req = io.requestor(i).req def connect_s0() = { io.mem.req.bits := req.bits io.mem.req.bits.tag := Cat(req.bits.tag, i.U(log2Up(n).W)) s1_id := i.U } def connect_s1() = { io.mem.s1_kill := io.requestor(i).s1_kill io.mem.s1_data := io.requestor(i).s1_data } def connect_s2() = { io.mem.s2_kill := io.requestor(i).s2_kill } if (i == n-1) { connect_s0() connect_s1() connect_s2() } else { when (req.valid) { connect_s0() } when (s1_id === i.U) { connect_s1() } when (s2_id === i.U) { connect_s2() } } } io.mem.uncached_resp.foreach(_.ready := false.B) for (i <- 0 until n) { val resp = io.requestor(i).resp val tag_hit = io.mem.resp.bits.tag(log2Up(n)-1,0) === i.U resp.valid := io.mem.resp.valid && tag_hit io.requestor(i).s2_xcpt := io.mem.s2_xcpt io.requestor(i).s2_gpa := io.mem.s2_gpa io.requestor(i).s2_gpa_is_pte := io.mem.s2_gpa_is_pte io.requestor(i).ordered := io.mem.ordered io.requestor(i).store_pending := io.mem.store_pending io.requestor(i).perf := io.mem.perf io.requestor(i).s2_nack := io.mem.s2_nack && s2_id === i.U io.requestor(i).s2_nack_cause_raw := io.mem.s2_nack_cause_raw io.requestor(i).s2_uncached := io.mem.s2_uncached io.requestor(i).s2_paddr := io.mem.s2_paddr io.requestor(i).clock_enabled := io.mem.clock_enabled resp.bits := io.mem.resp.bits resp.bits.tag := io.mem.resp.bits.tag >> log2Up(n) io.requestor(i).replay_next := io.mem.replay_next io.requestor(i).uncached_resp.map { uncached_resp => val uncached_tag_hit = io.mem.uncached_resp.get.bits.tag(log2Up(n)-1,0) === i.U uncached_resp.valid := io.mem.uncached_resp.get.valid && uncached_tag_hit when (uncached_resp.ready && uncached_tag_hit) { io.mem.uncached_resp.get.ready := true.B } uncached_resp.bits := io.mem.uncached_resp.get.bits uncached_resp.bits.tag := io.mem.uncached_resp.get.bits.tag >> log2Up(n) } } } }
module HellaCacheArbiter_1( // @[HellaCacheArbiter.scala:10:7] input clock, // @[HellaCacheArbiter.scala:10:7] input reset, // @[HellaCacheArbiter.scala:10:7] output io_requestor_0_req_ready, // @[HellaCacheArbiter.scala:12:14] input io_requestor_0_req_valid, // @[HellaCacheArbiter.scala:12:14] input [39:0] io_requestor_0_req_bits_addr, // @[HellaCacheArbiter.scala:12:14] input io_requestor_0_req_bits_dv, // @[HellaCacheArbiter.scala:12:14] input io_requestor_0_s1_kill, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_nack, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_resp_valid, // @[HellaCacheArbiter.scala:12:14] output [39:0] io_requestor_0_resp_bits_addr, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_0_resp_bits_data, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_xcpt_ma_ld, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_xcpt_ma_st, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_xcpt_pf_ld, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_xcpt_pf_st, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_xcpt_gf_ld, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_xcpt_gf_st, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_xcpt_ae_ld, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_xcpt_ae_st, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_store_pending, // @[HellaCacheArbiter.scala:12:14] input io_mem_req_ready, // @[HellaCacheArbiter.scala:12:14] output io_mem_req_valid, // @[HellaCacheArbiter.scala:12:14] output [39:0] io_mem_req_bits_addr, // @[HellaCacheArbiter.scala:12:14] output io_mem_req_bits_dv, // @[HellaCacheArbiter.scala:12:14] output io_mem_s1_kill, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_nack, // @[HellaCacheArbiter.scala:12:14] input io_mem_resp_valid, // @[HellaCacheArbiter.scala:12:14] input [39:0] io_mem_resp_bits_addr, // @[HellaCacheArbiter.scala:12:14] input [63:0] io_mem_resp_bits_data, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_xcpt_ma_ld, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_xcpt_ma_st, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_xcpt_pf_ld, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_xcpt_pf_st, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_xcpt_gf_ld, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_xcpt_gf_st, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_xcpt_ae_ld, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_xcpt_ae_st, // @[HellaCacheArbiter.scala:12:14] input io_mem_store_pending // @[HellaCacheArbiter.scala:12:14] ); wire io_requestor_0_req_valid_0 = io_requestor_0_req_valid; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_requestor_0_req_bits_addr_0 = io_requestor_0_req_bits_addr; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_req_bits_dv_0 = io_requestor_0_req_bits_dv; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s1_kill_0 = io_requestor_0_s1_kill; // @[HellaCacheArbiter.scala:10:7] wire io_mem_req_ready_0 = io_mem_req_ready; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_nack_0 = io_mem_s2_nack; // @[HellaCacheArbiter.scala:10:7] wire io_mem_resp_valid_0 = io_mem_resp_valid; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_mem_resp_bits_addr_0 = io_mem_resp_bits_addr; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_mem_resp_bits_data_0 = io_mem_resp_bits_data; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_ma_ld_0 = io_mem_s2_xcpt_ma_ld; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_ma_st_0 = io_mem_s2_xcpt_ma_st; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_pf_ld_0 = io_mem_s2_xcpt_pf_ld; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_pf_st_0 = io_mem_s2_xcpt_pf_st; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_gf_ld_0 = io_mem_s2_xcpt_gf_ld; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_gf_st_0 = io_mem_s2_xcpt_gf_st; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_ae_ld_0 = io_mem_s2_xcpt_ae_ld; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_ae_st_0 = io_mem_s2_xcpt_ae_st; // @[HellaCacheArbiter.scala:10:7] wire io_mem_store_pending_0 = io_mem_store_pending; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_requestor_0_s2_gpa = 40'h0; // @[HellaCacheArbiter.scala:10:7, :12:14] wire [39:0] io_mem_s2_gpa = 40'h0; // @[HellaCacheArbiter.scala:10:7, :12:14] wire [1:0] io_requestor_0_resp_bits_dprv = 2'h0; // @[HellaCacheArbiter.scala:10:7, :12:14] wire [1:0] io_mem_resp_bits_dprv = 2'h0; // @[HellaCacheArbiter.scala:10:7, :12:14] wire [31:0] io_requestor_0_s2_paddr = 32'h0; // @[HellaCacheArbiter.scala:10:7, :12:14] wire [31:0] io_mem_s2_paddr = 32'h0; // @[HellaCacheArbiter.scala:10:7, :12:14] wire [7:0] io_requestor_0_req_bits_mask = 8'h0; // @[HellaCacheArbiter.scala:10:7, :12:14] wire [7:0] io_requestor_0_s1_data_mask = 8'h0; // @[HellaCacheArbiter.scala:10:7, :12:14] wire [7:0] io_requestor_0_resp_bits_mask = 8'h0; // @[HellaCacheArbiter.scala:10:7, :12:14] wire [7:0] io_mem_req_bits_mask = 8'h0; // @[HellaCacheArbiter.scala:10:7, :12:14] wire [7:0] io_mem_s1_data_mask = 8'h0; // @[HellaCacheArbiter.scala:10:7, :12:14] wire [7:0] io_mem_resp_bits_mask = 8'h0; // @[HellaCacheArbiter.scala:10:7, :12:14] wire [63:0] io_requestor_0_req_bits_data = 64'h0; // @[HellaCacheArbiter.scala:10:7, :12:14] wire [63:0] io_requestor_0_s1_data_data = 64'h0; // @[HellaCacheArbiter.scala:10:7, :12:14] wire [63:0] io_requestor_0_resp_bits_data_word_bypass = 64'h0; // @[HellaCacheArbiter.scala:10:7, :12:14] wire [63:0] io_requestor_0_resp_bits_data_raw = 64'h0; // @[HellaCacheArbiter.scala:10:7, :12:14] wire [63:0] io_requestor_0_resp_bits_store_data = 64'h0; // @[HellaCacheArbiter.scala:10:7, :12:14] wire [63:0] io_mem_req_bits_data = 64'h0; // @[HellaCacheArbiter.scala:10:7, :12:14] wire [63:0] io_mem_s1_data_data = 64'h0; // @[HellaCacheArbiter.scala:10:7, :12:14] wire [63:0] io_mem_resp_bits_data_word_bypass = 64'h0; // @[HellaCacheArbiter.scala:10:7, :12:14] wire [63:0] io_mem_resp_bits_data_raw = 64'h0; // @[HellaCacheArbiter.scala:10:7, :12:14] wire [63:0] io_mem_resp_bits_store_data = 64'h0; // @[HellaCacheArbiter.scala:10:7, :12:14] wire io_requestor_0_req_bits_phys = 1'h1; // @[HellaCacheArbiter.scala:10:7, :12:14] wire io_mem_req_bits_phys = 1'h1; // @[HellaCacheArbiter.scala:10:7, :12:14] wire [1:0] io_requestor_0_req_bits_dprv = 2'h1; // @[HellaCacheArbiter.scala:10:7, :12:14] wire [1:0] io_mem_req_bits_dprv = 2'h1; // @[HellaCacheArbiter.scala:10:7, :12:14] wire io_requestor_0_req_bits_signed = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_req_bits_no_resp = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_req_bits_no_alloc = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_req_bits_no_xcpt = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_nack_cause_raw = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_kill = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_uncached = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_resp_bits_signed = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_resp_bits_dv = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_resp_bits_replay = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_resp_bits_has_data = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_replay_next = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_gpa_is_pte = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_ordered = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_acquire = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_release = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_grant = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_tlbMiss = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_blocked = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_canAcceptStoreThenLoad = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_canAcceptStoreThenRMW = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_canAcceptLoadThenLoad = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_storeBufferEmptyAfterLoad = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_storeBufferEmptyAfterStore = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_keep_clock_enabled = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_clock_enabled = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_req_bits_signed = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_req_bits_no_resp = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_req_bits_no_alloc = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_req_bits_no_xcpt = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_nack_cause_raw = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_kill = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_uncached = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_resp_bits_signed = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_resp_bits_dv = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_resp_bits_replay = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_resp_bits_has_data = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_replay_next = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_gpa_is_pte = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_ordered = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_acquire = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_release = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_grant = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_tlbMiss = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_blocked = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_canAcceptStoreThenLoad = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_canAcceptStoreThenRMW = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_canAcceptLoadThenLoad = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_storeBufferEmptyAfterLoad = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_storeBufferEmptyAfterStore = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_keep_clock_enabled = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_clock_enabled = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_requestor_0_req_bits_size = 2'h3; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_requestor_0_resp_bits_size = 2'h3; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_mem_req_bits_size = 2'h3; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_mem_resp_bits_size = 2'h3; // @[HellaCacheArbiter.scala:10:7] wire [4:0] io_requestor_0_req_bits_cmd = 5'h0; // @[HellaCacheArbiter.scala:10:7] wire [4:0] io_requestor_0_resp_bits_cmd = 5'h0; // @[HellaCacheArbiter.scala:10:7] wire [4:0] io_mem_req_bits_cmd = 5'h0; // @[HellaCacheArbiter.scala:10:7] wire [4:0] io_mem_resp_bits_cmd = 5'h0; // @[HellaCacheArbiter.scala:10:7] wire [6:0] io_requestor_0_req_bits_tag = 7'h0; // @[HellaCacheArbiter.scala:10:7] wire [6:0] io_requestor_0_resp_bits_tag = 7'h0; // @[HellaCacheArbiter.scala:10:7] wire [6:0] io_mem_req_bits_tag = 7'h0; // @[HellaCacheArbiter.scala:10:7] wire [6:0] io_mem_resp_bits_tag = 7'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_req_valid_0 = io_requestor_0_req_valid_0; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_mem_req_bits_addr_0 = io_requestor_0_req_bits_addr_0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_req_bits_dv_0 = io_requestor_0_req_bits_dv_0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s1_kill_0 = io_requestor_0_s1_kill_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_req_ready_0 = io_mem_req_ready_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_nack_0 = io_mem_s2_nack_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_resp_valid_0 = io_mem_resp_valid_0; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_requestor_0_resp_bits_addr_0 = io_mem_resp_bits_addr_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_0_resp_bits_data_0 = io_mem_resp_bits_data_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_ma_ld_0 = io_mem_s2_xcpt_ma_ld_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_ma_st_0 = io_mem_s2_xcpt_ma_st_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_pf_ld_0 = io_mem_s2_xcpt_pf_ld_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_pf_st_0 = io_mem_s2_xcpt_pf_st_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_gf_ld_0 = io_mem_s2_xcpt_gf_ld_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_gf_st_0 = io_mem_s2_xcpt_gf_st_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_ae_ld_0 = io_mem_s2_xcpt_ae_ld_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_ae_st_0 = io_mem_s2_xcpt_ae_st_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_store_pending_0 = io_mem_store_pending_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_req_ready = io_requestor_0_req_ready_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_nack = io_requestor_0_s2_nack_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_valid = io_requestor_0_resp_valid_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_addr = io_requestor_0_resp_bits_addr_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_data = io_requestor_0_resp_bits_data_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_xcpt_ma_ld = io_requestor_0_s2_xcpt_ma_ld_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_xcpt_ma_st = io_requestor_0_s2_xcpt_ma_st_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_xcpt_pf_ld = io_requestor_0_s2_xcpt_pf_ld_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_xcpt_pf_st = io_requestor_0_s2_xcpt_pf_st_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_xcpt_gf_ld = io_requestor_0_s2_xcpt_gf_ld_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_xcpt_gf_st = io_requestor_0_s2_xcpt_gf_st_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_xcpt_ae_ld = io_requestor_0_s2_xcpt_ae_ld_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_xcpt_ae_st = io_requestor_0_s2_xcpt_ae_st_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_store_pending = io_requestor_0_store_pending_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_valid = io_mem_req_valid_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_addr = io_mem_req_bits_addr_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_dv = io_mem_req_bits_dv_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_s1_kill = io_mem_s1_kill_0; // @[HellaCacheArbiter.scala:10:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands */ class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def *(t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def *(t: UInt) = self * t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros | ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def *(t: SInt) = self * t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros | ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid || output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def *(t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def *(t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }
module PE_276( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_20 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands */ class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def *(t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def *(t: UInt) = self * t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros | ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def *(t: SInt) = self * t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros | ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid || output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def *(t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def *(t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }
module PE_359( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_103 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File RoundAnyRawFNToRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util.Fill import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundAnyRawFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int, options: Int ) extends RawModule { override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(inExpWidth, inSigWidth)) // (allowed exponent range has limits) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0) val effectiveInSigWidth = if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1 val neverUnderflows = ((options & (flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact) ) != 0) || (inExpWidth < outExpWidth) val neverOverflows = ((options & flRoundOpt_neverOverflows) != 0) || (inExpWidth < outExpWidth) val outNaNExp = BigInt(7)<<(outExpWidth - 2) val outInfExp = BigInt(6)<<(outExpWidth - 2) val outMaxFiniteExp = outInfExp - 1 val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2 val outMinNonzeroExp = outMinNormExp - outSigWidth + 1 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_near_even = (io.roundingMode === round_near_even) val roundingMode_minMag = (io.roundingMode === round_minMag) val roundingMode_min = (io.roundingMode === round_min) val roundingMode_max = (io.roundingMode === round_max) val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag) val roundingMode_odd = (io.roundingMode === round_odd) val roundMagUp = (roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sAdjustedExp = if (inExpWidth < outExpWidth) (io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S )(outExpWidth, 0).zext else if (inExpWidth == outExpWidth) io.in.sExp else io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S val adjustedSig = if (inSigWidth <= outSigWidth + 2) io.in.sig<<(outSigWidth - inSigWidth + 2) else (io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ## io.in.sig(inSigWidth - outSigWidth - 2, 0).orR ) val doShiftSigDown1 = if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2) val common_expOut = Wire(UInt((outExpWidth + 1).W)) val common_fractOut = Wire(UInt((outSigWidth - 1).W)) val common_overflow = Wire(Bool()) val common_totalUnderflow = Wire(Bool()) val common_underflow = Wire(Bool()) val common_inexact = Wire(Bool()) if ( neverOverflows && neverUnderflows && (effectiveInSigWidth <= outSigWidth) ) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1 common_fractOut := Mux(doShiftSigDown1, adjustedSig(outSigWidth + 1, 3), adjustedSig(outSigWidth, 2) ) common_overflow := false.B common_totalUnderflow := false.B common_underflow := false.B common_inexact := false.B } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundMask = if (neverUnderflows) 0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W) else (lowMask( sAdjustedExp(outExpWidth, 0), outMinNormExp - outSigWidth - 1, outMinNormExp ) | doShiftSigDown1) ## 3.U(2.W) val shiftedRoundMask = 0.U(1.W) ## roundMask>>1 val roundPosMask = ~shiftedRoundMask & roundMask val roundPosBit = (adjustedSig & roundPosMask).orR val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR val anyRound = roundPosBit || anyRoundExtra val roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && roundPosBit) || (roundMagUp && anyRound) val roundedSig: Bits = Mux(roundIncr, (((adjustedSig | roundMask)>>2) +& 1.U) & ~Mux(roundingMode_near_even && roundPosBit && ! anyRoundExtra, roundMask>>1, 0.U((outSigWidth + 2).W) ), (adjustedSig & ~roundMask)>>2 | Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U) ) //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext common_expOut := sRoundedExp(outExpWidth, 0) common_fractOut := Mux(doShiftSigDown1, roundedSig(outSigWidth - 1, 1), roundedSig(outSigWidth - 2, 0) ) common_overflow := (if (neverOverflows) false.B else //*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?: (sRoundedExp>>(outExpWidth - 1) >= 3.S)) common_totalUnderflow := (if (neverUnderflows) false.B else //*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?: (sRoundedExp < outMinNonzeroExp.S)) val unboundedRange_roundPosBit = Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1)) val unboundedRange_anyRound = (doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR val unboundedRange_roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && unboundedRange_roundPosBit) || (roundMagUp && unboundedRange_anyRound) val roundCarry = Mux(doShiftSigDown1, roundedSig(outSigWidth + 1), roundedSig(outSigWidth) ) common_underflow := (if (neverUnderflows) false.B else common_totalUnderflow || //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) && Mux(doShiftSigDown1, roundMask(3), roundMask(2)) && ! ((io.detectTininess === tininess_afterRounding) && ! Mux(doShiftSigDown1, roundMask(4), roundMask(3) ) && roundCarry && roundPosBit && unboundedRange_roundIncr))) common_inexact := common_totalUnderflow || anyRound } //------------------------------------------------------------------------ //------------------------------------------------------------------------ val isNaNOut = io.invalidExc || io.in.isNaN val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero val overflow = commonCase && common_overflow val underflow = commonCase && common_underflow val inexact = overflow || (commonCase && common_inexact) val overflow_roundMagUp = roundingMode_near_even || roundingMode_near_maxMag || roundMagUp val pegMinNonzeroMagOut = commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd) val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp val notNaN_isInfOut = notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp) val signOut = Mux(isNaNOut, false.B, io.in.sign) val expOut = (common_expOut & ~Mux(io.in.isZero || common_totalUnderflow, (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMinNonzeroMagOut, ~outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMaxFiniteMagOut, (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W), 0.U ) & ~Mux(notNaN_isInfOut, (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U )) | Mux(pegMinNonzeroMagOut, outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) | Mux(pegMaxFiniteMagOut, outMaxFiniteExp.U((outExpWidth + 1).W), 0.U ) | Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) | Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U) val fractOut = Mux(isNaNOut || io.in.isZero || common_totalUnderflow, Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U), common_fractOut ) | Fill(outSigWidth - 1, pegMaxFiniteMagOut) io.out := signOut ## expOut ## fractOut io.exceptionFlags := io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int) extends RawModule { override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(expWidth, sigWidth + 2)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( expWidth, sigWidth + 2, expWidth, sigWidth, options)) roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc roundAnyRawFNToRecFN.io.in := io.in roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags }
module RoundRawFNToRecFN_e8_s24_90( // @[RoundAnyRawFNToRecFN.scala:295:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_90 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15] .io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[RoundAnyRawFNToRecFN.scala:310:15] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] endmodule
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag }
module OptimizationBarrier_TLBEntryData_24( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule